Deformation control of manufacturing equipment using frontal irradiation

Abstract

The disclosed systems and techniques are intended to improve semiconductor manufacturing. In one disclosed embodiment, the disclosed systems and techniques include depositing one or more films on the front surface of a substrate, forming a stress compensation layer (SCL) on one or more of the deposited films, irradiating the SCL with a stress relaxation beam to reduce substrate deformation, and adding one or more features to at least one of the one or more deposited films.

Description

Technical Field

[0001]

[0001] This disclosure relates to semiconductor manufacturing, including the processing of wafers and devices fabricated thereon.

Background Art

[0002]

[0002] Modern semiconductor devices, such as devices incorporating processing units, memory devices, photodetectors, solar cells, light-emitting semiconductor devices, complementary metal-oxide-semiconductor (CMOS) structures, etc., are often fabricated on silicon wafers (or other suitable substrates). The wafers may undergo a number of processing operations, such as physical vapor deposition, chemical vapor deposition, etching, photomasking, polishing, and / or various other operations. In a continuing effort to reduce the cost of semiconductor devices, multi-layer stacks of dies, insulating films, patterned and / or doped semiconductor films, and / or other features are often deposited on a single wafer, resulting in, for example, high aspect ratio devices used in 3D flash memory devices and other applications. Deposition, patterning, etching, polishing, etc. of multi-layer stacks of structures often apply significant stress to underlying wafers. Such stress results in both out-of-plane and in-plane distortion of features supported by the wafer. These distortions can cause misalignment of the deposited features and can significantly degrade the quality of the fabricated devices.

Summary of the Invention

[0003]

[0003] In one embodiment, a method of manufacturing a semiconductor device is disclosed that includes depositing one or more films on a front surface of a substrate and forming a stress compensation layer (SCL) on the one or more deposited films, the SCL changing the stress in the substrate. The method further includes applying a stress relaxation beam to the SCL to reduce deformation of the substrate and adding one or more features to at least one of the one or more deposited films.

[0004]

[0004] In another embodiment, a system is disclosed that includes a memory and a processing device communicatively coupled to the memory. The processing device is made to perform operations including depositing one or more films on the front surface of a substrate and forming SCLs on one or more deposited films, the SCLs changing the stress on the substrate. The operations further include irradiating the SCLs with a stress-relaxing beam to reduce deformation of the substrate and adding one or more features to at least one of the one or more deposited films.

[0005]

[0005] In another embodiment, the semiconductor manufacturing system includes one or more processing chambers for depositing one or more films on the front surface of a substrate and forming SCLs on one or more deposited films, the SCLs changing the stress on the substrate. The one or more processing chambers further irradiate the SCLs with a stress relaxation beam to reduce deformation of the substrate and add one or more features to at least one of the one or more deposited films.

[0006]

[0006] This disclosure will be better understood from the detailed description given below and the accompanying drawings of various embodiments of this disclosure. [Brief explanation of the drawing]

[0007] [Figure 1A-1B] A schematic diagram illustrates a process for manufacturing a high aspect ratio structure, including irradiation of a mask with a stress-relaxing beam, according to at least one embodiment. [Figure 2A-2F] Figure 1A-1B shows an overall substrate diagram of a semiconductor manufacturing process, including irradiation of a mask with a stress-relaxing beam, according to at least one embodiment. [Figure 3A-3E] A schematic diagram illustrates a process for correcting substrate deformation using a stress relaxation beam applied to the front surface of a wafer, according to at least one embodiment. [Figure 4]An exemplary Zernike polynomial decomposition of one actual deformation of a substrate (top left) according to at least one embodiment is shown in arbitrary units for parabolic curvature (top right), saddle deformation (bottom left), and residual deformation (bottom right). [Figure 5] This flowchart shows an example of a method for relieving stress and deformation of a substrate using front-side irradiation, according to at least one embodiment. [Figure 6] This flowchart illustrates an exemplary method for determining front-lighting parameters according to at least one embodiment. [Figures 7A-7H] An exemplary process for manufacturing a logic device that uses a stress-relaxing beam to irradiate a front-facing deposited layer, according to at least one embodiment nt, is schematically shown. [Figures 8A-8B] A schematic diagram of an irradiation system capable of irradiating a stress compensation layer, according to at least one embodiment, is shown. [Figure 9] A block diagram of an exemplary computer system capable of supporting the operation of the present disclosure according to at least one embodiment is shown. [Modes for carrying out the invention]

[0008]

[0016] Modern technology often aims to maximize chip area utilization by manufacturing three-dimensional devices with vertical stacks of multiple layers of semiconductor structures. For example, in NAND flash memory devices, the lateral relative arrangement (CMOS near array, or CnA) of memory cells (e.g., floating-gate transistors) and peripheral transistors (e.g., CMOS circuits used to support write / read operations on memory cells) is almost always superseded by the vertical arrangement (CMOS under array, or CuA) where the peripheral CMOS circuits are located beneath the array of memory cells. In some cases, stacks of memory cell layers can be manufactured on top of other stacks, forming structures where the precise alignment of various features within the layers is crucial for the proper functioning of the manufactured device. In one embodiment, a stack of multiple (e.g., 100 or more) alternating oxide (O) and nitride (N) layers (e.g., silicon oxide and silicon nitride layers in one embodiment) may be deposited on a silicon wafer and then covered with a mask layer (e.g., a carbon hard mask). Throughout this disclosure, O and N layers are referred to, but many other layers / films, including but not limited to polycrystalline silicon layers, can be deposited on the wafer. For example, in the fabrication of three-dimensional (3D) dynamic random access memory (DRAM), alternating Si 1-x Ge xA stack of (SiGe) alloy layers and silicon (e.g., epitaxial silicon) layers can be formed by depositing them onto a silicon substrate. A photoresist layer may be deposited on a mask layer with a defined pattern of holes (channel holes), slits, and / or various other openings that are transferred to the stack of ON layers or SiGe layers via the mask. Photolithography can then be performed to open the mask according to the defined pattern (the photoresist material protects the unexposed areas of the mask), allowing access to the stack of ON layers or SiGe layers. An etching process can be performed to etch the regions of the ON layer or silicon germanium layer located below the openings in the mask, forming deep vertical channels and / or slits that can extend all the way through the stack to the wafer. The channels / slits can then be used to supply target material across various ON layers or SiGe layers, for example, to replace the N layer or silicon germanium layer with a conductive material (tungsten, molybdenum, etc.), and / or to form a multilayer transistor array within the vertical channels.

[0009]

[0017] Arrays of transistors and / or other features deposited in a layer stack may need to be precisely aligned with matching structures deposited on the upper surface of the wafer (e.g., source lines of conductive circuits supporting the electronic operation of the transistor arrays). Furthermore, one or more additional layer stacks may be deposited on top of previously deposited stacks, for example, to increase the vertical number of memory cells / transistors and thereby increase the cell density per unit area of ​​the NAND or 3D DRAM device, respectively. Processing such additional stacks can be done as described above, for example, by placing another mask on top of the additional stack, opening the mask, and etching vertical channels / slits through the additional stack. Channels etched through one or more upper stacks must be aligned with corresponding channels etched into one or more bottom stacks so as to ensure that good electrical contacts are formed between the corresponding arrays of memory cells.

[0010]

[0018] However, the alignment of channels, slits, and / or various other features across a vertical stack of multiple layers / films can be hindered by substrate deformation, such as in-plane and / or out-of-plane deformation. Such deformation can be caused by contact between the substrate and the layer stack, stresses between layers in individual stacks, and stresses arising from the patterning of features within the layers. This can result in non-operational and / or suboptimal devices, as well as a corresponding decrease in the yield of the manufacturing process.

[0011]

[0019] Existing technologies include many methods for addressing substrate deformation. For example, a deformed (warped) substrate with various films and features deposited on one side (also called the front, top, or main surface) can be coated on the back side (also called the bottom surface) with a film that applies compressive or tensile stress to the substrate. Such back-side deposited deformation-correcting films, also referred to herein as stress-compensating layers, can impart uniform (or global) stress to the entire substrate, thereby reducing the amount of substrate deformation. Additional stress relaxation can be achieved by implanting ions into the stress-compensating layer, for example, by using an ion beam that impacts the stress-compensating layer, thereby adjusting the stress in the stress-compensating layer and consequently further correcting the deformation of the underlying substrate. Ion implantation can be performed globally or locally (e.g., in a specific selected area of ​​the substrate). The use of back-side stress relaxation techniques involves using unrelated materials and films that do not functionally contribute to the device but add extra complexity and introduce an additional risk of sample heterogeneity.

[0012]

[0020] The aspects and embodiments of this disclosure address these and other challenges of modern semiconductor manufacturing technology by providing systems and techniques for relieving substrate stress and deformation in high aspect ratio devices and improving feature alignment without introducing additional materials and complexity. In some embodiments, a hard mask deposited on a stack of layers / films can be used as a stress compensation layer. More specifically, the hard mask can be exposed to irradiation with a stress relaxation beam before being covered with photoresist and / or other lithography-related materials. The stress relaxation beam may include particles (e.g., ions, electrons), electromagnetic waves (e.g., UV light, far UV light, extreme UV light, visible light, infrared light, etc.), and / or appropriate combinations thereof. The stress relaxation beam collides with the hard mask and alters the coupling network of the hard mask. For example, a low-energy stress relaxation beam can interact with surface atoms of the hard mask, for example, removing some of the surface atoms and effectively performing etching of surface areas of the hard mask. The effectiveness of such etching can be controlled by the selection of ionic species / radicals / ambient gases. In another example, a high-energy stress-relaxation beam can deposit ions inside a hard mask. The ions and / or photons in the beam can disrupt the bonding network (or crystal lattice) of the hard mask, forming vacancies within it, which can further induce annealing through localized heating, UV curing, and / or other effects. The substitution defects and / or vacancies created by the particles of the stress-relaxation beam correct (e.g., reduce) the stress within the hard mask and, through the mask, reduce the stress in the wafer or other substrate. The intensity and / or dose (intensity integrated over time) of the stress-relaxation beam can vary depending on its position within the hard mask and can be determined (e.g., by simulation, modeling, etc.) to maximize stress relaxation within the hard mask and even within the substrate. This facilitates the planarization of the substrate, deposited layers / films, and hard mask combination, making it easier to pattern on the substrate, etch one or more stacks of layers, and / or to accurately align similar elements, improving the quality of the manufactured device.The irradiation intensity / dose can be determined, for example, based on the measured deformation of the substrate (on which layers / films / masks are deposited) using various optical measurement techniques. Multiple techniques may be used to determine the optimal intensity and / or dose of the stress-relaxing beam, including Monte Carlo simulations, influence function calculations, and / or other techniques, as disclosed below.

[0013]

[0021] The advantages of the disclosed embodiments include, but are not limited to, a significant reduction in the cost of stress compensation for substrate shape in semiconductor manufacturing, and more precise alignment of features manufactured on the substrate, including high aspect ratio features in vertically grown semiconductor devices.

[0014]

[0022] As used herein, “wafer” or “substrate” refers to any substrate or material surface formed on a substrate on which a film treatment is performed during a manufacturing process. For example, wafer surfaces on which treatment can be performed include, depending on the application, any intrinsic (doped) material such as silicon, silicon oxide, silicon nitride, strained silicon, silicon on an insulator, silicon oxide with carbon, amorphous silicon, germanium, gallium arsenide, glass, sapphire, plastics, and any other material such as metals, metal nitrides, metal alloys, and other conductive materials. Wafers include, but are not limited to, semiconductor wafers. Wafers may be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, electron beam cure, and / or bake the substrate surface. In addition to performing film treatment directly on the surface of the wafer itself, any of the disclosed film treatment steps may also be performed on underlying layers formed on the wafer, which are disclosed in more detail below. The term “wafer surface” is intended to include such underlying layers, as the context indicates. Therefore, for example, if a film / layer or partial film / layer is deposited on the wafer surface, the exposed surface of the newly deposited film / layer becomes the wafer surface. In some embodiments, the wafer has a thickness in the range of 0.25 mm to 1.5 mm, or in the range of 0.5 mm to 1.25 mm, or in the range of 0.75 mm to 1.0 mm, or greater. In some embodiments, the wafer has a diameter of about 10 cm, 20 cm, 30 cm, or greater.

[0015]

[0023] Figures 1A and 1B schematically illustrate a process 100 for manufacturing a high aspect ratio structure, including irradiation of a mask with a stress-relaxing beam, according to at least one embodiment. The evolution of individual structures (marked with arrows) is shown in Figure 1A. More specifically, a first stack 104 of layers / films can be grown (or deposited) on a substrate 102, a portion of which is shown in Figure 1A. The stack 104 can be a stack of alternating O and N layers, or any other suitable stack, and can include any number of regularly repeated layers (e.g., three or more). Figures 1A and 1B may not be to scale, and it should be understood that the wafer thickness may significantly exceed the height of the first stack 104. For example, the wafer height may be around 0.5 to 1 mm, the thickness of individual O or N layers may be around 100 nm, and the height of the first stack 104 may be around 10 m. In some embodiments, the thickness of the O and / or N layers may be 20 to 30 nm, or less than 20 nm. Next, a mask (e.g., a hard mask) 106 can be deposited on the first laminate 104. In some embodiments, one or more additional stress compensation layers may be deposited together with the mask 106. In some embodiments, after deposition, the mask 106 may undergo annealing, for example, to reduce the overall stress of the mask 106 and / or pre-adjusted mask 106, before stress relaxation by exposure to light.

[0016]

[0024] In some embodiments, the stress relaxation beam 108 is then applied to the mask 106 (or one or more additional stress compensation layers) to deliver position-dependent doses of particles and / or photons. TIFF2026516610000002.tif5170 can be supplied. Here, TIFF2026516610000003.tif4170 are in-plane coordinates within the plane of the wafer / mask. Stress relaxation beam 108 can be generated by appropriate collimating and focusing column 110. By applying stress relaxation beam 108, the stress of the structure including substrate 102, first laminate 104, and mask 106 is reduced, resulting in flattening (reduction of deformation) of the structure.

[0017]

[0025] After stress relaxation, one or more additional layers, including but not limited to a dielectric anti-reflective coating (DARC) layer, an ashingable hard mask (AHM, often made from amorphous carbon), and a bottom anti-reflective coating (BARC) layer, can be deposited on the mask 106. The mask 106 can be opened, for example, using any suitable lithography technique, to generate channels 112 extending over the height of the mask 106 or any other target pattern. More specifically, a photoresist layer (illustrated in Figure 1A for simplicity) can be deposited on the mask 106 and the DARC / AHM / BARC layer. Photolithography can then be used to create a target pattern, for example, a pattern of channel holes to be transferred to the mask 106 and the first laminate 104. An etching process, for example, mask-open etching, can be used to transfer the target pattern to the mask 106 facilitated by the PR / BARC / AHM / DARC layer. Mask open etching generates a pattern of channels 112 (and any other features including, but not limited to, slits and / or other openings) on the mask 106. Additional etching processes (channel hole etching, memory hole etching, dielectric etching) can be used to transfer the channels 112 (or other features) to the first laminate 104 to form extended channels 114 that can extend down to the substrate 102. Etching may consume at least a portion of the mask 106, and the unconsumed portion of the mask 106 can be removed (e.g., by dissolving or evaporating). For simplicity, Figure 1A shows the formation of a cylindrical channel 114, but slits or any other vertical features can be etched in a similar manner.

[0018]

[0026] As shown in Figure 1B, the described process can be repeated for one or more additional stacks of layers / films that may be placed on top of the first stack 104. More specifically, a second stack 122 can be deposited on top of the first stack 104, and a mask 126 can be deposited on top of the second stack 122. The mask 126 can be irradiated using a stress relaxation beam 108. Subsequently, DARC, BARC, and photoresist can be placed on the mask 126, and channels 132 can be created in the mask 126 using photolithography. The channels 132 can then be used to etch the second stack 122 to form channels 134 that extend to the length of the second stack 122. By applying the stress-relaxing beam 108 to masks 106 and 126, the channel 134 in the second stack 122 can be precisely aligned with the channel 114 in the first stack 104, essentially forming a continuous path for material deposition across the entire height of two (or more) stacks. These paths can be used, for example, to replace nitrogen in the N layer with a metal (e.g., tungsten) and form a multilayer transistor array within channels 114 and 134. The example in Figures 1A and 1B shows stress relaxation and alignment of two stacks of layers / films, but three or more stacks can be assembled in a similar manner.

[0019]

[0027] Figures 2A through 2F show cross-sectional views of process 100 of FIGS. 1A through 1B of semiconductor manufacturing including irradiation of a mask with a stress-relief beam, according to at least one embodiment. FIG. 2A shows a substrate 102, which can be a bare wafer or a wafer with one or more features patterned thereon. In some embodiments, substrate 102 can further undergo some additional processing, such as annealing, for example, after deposition of mask 106 and before application of stress-relief beam 108. FIG. 2B shows a first stack 104 deposited on substrate 102. At this stage of process 100, first stack 104 can be a stack of a uniform (unpatterned) film. FIG. 2C shows a mask 106 deposited over first stack 104. FIG. 2D shows the application of stress-relief beam 108 generated by collimating and focusing column 110 and directed at mask 106. FIG. 2E schematically shows photolithography of mask 106. More specifically, mask 106 can be covered with one or more DARC layers and / or BARC layers 200 having a photoresist 202 thereon. A target pattern 204 can be generated within photoresist 202. Target pattern 204 can include chip boundaries, area boundaries, slits, channels, and / or any other applicable features. Photolithography can be performed using any suitable radiation 206 (e.g., UV light, visible light, infrared light, etc.). Photolithography transfers pattern 204 to mask 106. Mask 106 is then used during etching of first stack 104 to form pattern 204 in first stack 104. FIG. 2F shows first stack 104 having etched pattern 204 (with mask 106 that is consumed by etching or removed during post-etch processing). Additional stacks of layers can be further added by repeating the operations shown in FIGS. 2B-2E.

[0020]

[0028] Wafer profile before irradiating the mask with the stress-relief beam By measuring TIFF2026516610000004.tif5170, the amount of stress within the wafer (on which the film and mask are deposited) can be determined. Profile TIFF2026516610000005.tif5170 may refer to the vertical coordinates of the top surface of the mask. In some cases, the stress within the wafer may be uniform and isotropic. TIFF2026516610000006.tif4170. In some cases, stress within a wafer can be anisotropic. TIFF2026516610000007.tif5170. A specific feature pattern is unidirectional, for example, Compressed according to TIFF2026516610000008.tif5170, vertically oriented This can result in tensile stress along TIFF2026516610000009.tif5170, potentially leading to the formation of saddle-shaped wafers. Such saddle-shaped features can occur, for example, in stacks of materials with directional patterning (e.g., word line patterning in NAND devices).

[0021]

[0029] In some embodiments, wafer deformation The vertical profile of TIFF2026516610000010.tif5170 can be measured using optical measurement (e.g., optical interferometry) techniques. In some embodiments, wafer deformation occurs after the layer / film stack is deposited on the wafer. TIFF2026516610000011.tif5170 can be measured. Then, the wafer profile TIFF2026516610000012.tif5170 qualitatively and quantitatively characterizes the shape dimensions of wafer deformation using several parameters (e.g., a set of Zernike (or similar sets of Zernike) polynomials). It can be represented via TIFF2026516610000013.tif5170. Continuous coefficients TIFF2026516610000014.tif6170 Corresponding Zernike polynomial The weights of specific geometric features (elemental deformations) of the wafer, as described by TIFF2026516610000015.tif5170, are shown. In some embodiments, the material of the hard mask is the parabolic curvature coefficient. The hard mask thickness may be selected based on the code of TIFF2026516610000016.tif5170. In some embodiments, the hard mask thickness may be selected. The selection of TIFF2026516610000017.tif4170 is the value of the parabolic curvature coefficient. This can be done according to TIFF2026516610000018.tif5170. The hard mask can then also function as a stress relaxation layer. The hard mask can be deposited using any suitable deposition technique, including physical vapor deposition (e.g., sputtering), chemical vapor deposition (e.g., plasma-assisted deposition), epitaxy, and exfoliation. Deposition can be carried out at room temperature or at a temperature different from room temperature (e.g., high temperature). The thickness of the stress compensation layer is as shown in Figures 3A to 3E below. TIFF2026516610000019.tif4170 can be selected to overcompensate for wafer deformation to some extent. Overcompensation can be selected in combination with the type of stress relaxation beam (e.g., ion implantation, photons, electrons, etc.), the type of implantation species, energy, and dose to ensure the maximum effect from stress relaxation. Stress in the composite structure of wafer, film, and hard mask can then be corrected by a stress relaxation beam that impacts the hard mask and alters its crystal structure. Substitution defects and / or vacancies generated by the beam can relax (e.g., reduce) the stress in the stress compensation layer and reduce the degree of stress overcompensation caused by hard mask deposition. This results in planarization of the wafer.

[0022]

[0030] Figures 3A to 3E schematically illustrate a process for correcting substrate deformation using a stress relaxation beam applied to the front surface of a wafer, according to at least one embodiment. Figure 3A shows a substrate 302 with deformation, which has a positive coefficient (as shown in the figure). The parabolic curvature deformation (having TIFF2026516610000020.tif5170) may include other deformations, including saddle deformation, residual deformation, etc. The wafer front surface 304 may include any number of features, e.g., deposited and / or etched patterns, stacks of layers / films, and / or any other structures. Figure 3B shows the deposition of a hard mask 306 on the front surface 304 of the substrate 302. The hard mask 306 may be (or include) a carbon-based mask (e.g., amorphous carbon), a chromium-based mask, or any other type of mask. In some embodiments, the hard mask 306 may include layers of multiple materials. In some embodiments, the materials of the hard mask 306 may have a coefficient sign It can be selected from the perspective of TIFF2026516610000021.tif5170. For example, positive curvature. In the case of TIFF2026516610000022.tif5170, the hard mask 306 may be selected to have tensile stress (as shown in Figures 3B to 3E). Conversely, negative curvature In the case of TIFF2026516610000023.tif5170, the hard mask 306 can be selected to have compressive stress (not shown in Figures 3B to 3E). The hard mask 306 can be deposited using any suitable deposition technique, including physical vapor deposition (e.g., sputtering), chemical vapor deposition (e.g., plasma-assisted deposition), epitaxy, exfoliation, and / or similar. Deposition can be carried out at room temperature or at a temperature different from room temperature (e.g., high temperature). In some embodiments, the thickness of the hard mask 306 TIFF2026516610000024.tif4170 can be selected to overcorrect wafer deformation to some extent, for example, as shown in Figure 3C, where a positive paraboloid is overcorrected for the curvature of a negative paraboloid. Thickness-dependent paraboloid curvature correction According to TIFF2026516610000025.tif5170, wafer deformation is This changes to TIFF2026516610000026.tif5170: TIFF2026516610000027.tif5170

[0023]

[0031] The degree of overcorrection can be selected in relation to the specific type and parameters (e.g., energy and dose) of the stress relaxation beam used on the hard mask 306. This overcorrection allows for further control of stress (and consequently, control of wafer deformation) in the composite structure of the substrate 302 and the hard mask 306. It may become susceptible to the effects of TIFF2026516610000028.tif5170). As shown in Figure 3D, the collimating and focusing column 110 can generate a stress-relaxing beam 108 that collides with the hard mask 306 and alters its elastic properties, for example, by creating vacancies, breaking crystal bonds, depositing ions, and / or through any other applicable mechanism. The stress-relaxing beam 108 can carry photons, electrons, silicon ions, phosphate ions, argon ions, neon ions, xenon ions, krypton ions, etc. In some embodiments, the energy and type of ions in the stress-relaxing beam 108 can be selected to restrict the injected ions to the volume of the hard mask 306 without allowing the ions to reach the substrate 302 (and / or any layer / film deposited on the substrate 302). Ions present in the hard mask 306 create substitution defects within it. In addition, the ions leave a trail of vacancy defects along their propagation path in the hard mask 306. Substitution defects and / or voids can relieve (e.g., reduce) stress within the hard mask 306, thereby reducing the degree of stress overcompensation caused by hard mask deposition. This results in a planar combination of the substrate 302 and the hard mask 306.

[0024]

[0032] In some embodiments, a small area of ​​the substrate 302 Number of ions deposited per TIFF2026516610000029.tif5170 (or the total amount of photon energy applicable to this region) TIFF2026516610000030.tif5170 is a corrected deformation. This can be determined using a simulation based on local values ​​from TIFF2026516610000031.tif5170 (which is performed as described in more detail below). This simulation is overcorrected for saddle deformation, residual deformation, and parabolic curvature deformation due to the deposition of stress compensation layer 108. This may include the portion of TIFF2026516610000032.tif5170. Scanning speed of stress relaxation beam 108. By controlling TIFF2026516610000033.tif3170, the target local density of ions can be controlled. TIFF2026516610000034.tif5170 can be supplied. In some embodiments, the stress relaxation beam 108 is a Gaussian function (e.g., ion flux). It has a profile that can be approximated by TIFF2026516610000035.tif5170), where, TIFF2026516610000036.tif6170 is in Cartesian coordinates, TIFF2026516610000037.tif5170 represents the maximum ion flux at the center of the beam. TIFF2026516610000038.tif5170 Each of them, This is a characteristic beam spread along TIFF2026516610000039.tif5170. Correspondingly, the distance from the beam center path is... The point where TIFF2026516610000040.tif4170 is located receives an ion dose containing the following number of ions. TIFF2026516610000041.tif14170 In response to this, scan speed By reducing TIFF2026516610000042.tif3170, the number of ions received by various regions of the hard mask 306 can be increased, and vice versa. In addition, the stress relaxation beam 108 is a factor that can be averaged out with respect to the target dose at various points on the hard mask 306. Various offsets to accept multiple doses of ions having TIFF2026516610000043.tif5170 Multiple scans with TIFF2026516610000044.tif4170 can be performed. For example, from the center of the beam to a region Different distances to TIFF2026516610000045.tif5170 Each speed is shown in TIFF2026516610000046.tif4170 After the stress relaxation beam 108, fabricated at TIFF2026516610000047.tif4170, has passed through this region n times, the total dose of ions (or amount of electromagnetic radiation) received by this region is: TIFF2026516610000048.tif13170

[0025]

[0033] As shown in Figure 3E, the stress relaxation layer 310 is formed as part of the hard mask 306, resulting in a significant relaxation of the deformation of the substrate 302, including saddle and residual deformation. In some embodiments, for example, an additional stress compensation layer can be deposited on the back side of the substrate 302 (not shown in Figures 3A-3E) to mitigate additional parabolic deformation.

[0026]

[0034] In some embodiments, the intensity and / or total amount of irradiation to different regions of the wafer can be determined using simulations, such as Monte Carlo simulations. Monte Carlo simulations are used for mask deposition and to determine a specific thickness. The Monte Carlo simulation can be performed on films made from actual materials having TIFF2026516610000049.tif4170. The initial Monte Carlo simulation can be performed against specific baseline (default) conditions for particle irradiation (e.g., default settings of an ion implanter). Baseline conditions may include default particle types, default particle energies, default particle doses applied to masks or other stress compensation layers (e.g., default scan rate and default scan pattern). Subsequently, the baseline conditions can be modified (e.g., optimized) using the Monte Carlo simulation. The Monte Carlo simulation can use calibration data collected (measured) for actual particle irradiation performed against various ion / photon / electron energies, ion types, mask / layer types and materials, particle incidence angles on the film, etc.

[0027]

[0035] In some embodiments, injection map TIFF2026516610000050.tif5170 is another point of the wafer Point-like forces applied to the wafer cause point-like forces on TIFF2026516610000051.tif4170 Influence function characterizing the response (e.g., deformation) in TIFF2026516610000052.tif4170 This can be calculated using TIFF2026516610000053.tif5170. In some embodiments, the influence function is also known as the Green's function. TIFF2026516610000054.tif5170 can be determined from computational simulations or analytical calculations. In some embodiments, the influence function may be determined from one or more experiments, which may include performing ion implantation on a film deposited on a reference wafer.

[0028]

[0036] In some embodiments, wafer deformation TIFF2026516610000055.tif5170 is a secondary contribution TIFF2026516610000056.tif5170 and residual (non-secondary contribution) TIFF2026516610000057.tif5170 can be represented (decomposed) as a combination of contributions. The quadratic deformation is a paraboloid (paraboloid) part with perfect axisymmetricity. TIFF2026516610000058.tif5170 and the saddle part May include TIFF2026516610000059.tif5170. Hard mask thickness 306 TIFF2026516610000060.tif4170 allows the mask to be calculated (or empirically determined) to apply a desired target stress to the wafer. To eliminate non-uniform saddle deformation, the hard mask 306 can be of a thickness / material such that the saddle deformation is converted into a cylindrical deformation with a clear sign across the entire region of the wafer. The cylindrical deformation of uniform sign (and residual higher-order non-secondary deformation) can then be relaxed by irradiation with a stress relaxation beam. In some embodiments, the cylindrical resolution is not inherent and can be either positive (upward cylindrical deformation) or negative (downward cylindrical deformation). Both resolutions can be analyzed and a resolution that allows for more effective stress relaxation can be selected. For example, a resolution characterized by a smaller parabolic curvature deformation can be selected. The parabolic curvature deformation can be relaxed using the selection of the mask 306 (e.g., type and thickness), and the remaining cylindrical deformation (and higher-order residual deformation) can be relaxed by a appropriately selected ion dose or photon dose. This can be addressed by TIFF2026516610000061.tif5170.

[0029]

[0037] In some embodiments, the relaxation of cylindrical or saddle deformation may involve identifying the principal axis (direction) and magnitude of the cylinder / saddle deformation and directing a stress relaxation beam to appropriately selected edge regions of the hard mask. For example, each edge region to which the beam is directed may have a width of 30% or less of the wafer diameter. Further irradiation of the mask region can then relax residual higher-order (ripple) deformation.

[0030]

[0038] Some of these techniques will be described in more detail below. In one embodiment, wafer deformation The vertical profile of TIFF2026516610000062.tif5170 can be measured using optical measurement techniques. For example, the profile The interferogram for TIFF2026516610000063.tif5170 can be obtained using optical interferometry measurements. Then, the wafer profile is obtained through several parameters that qualitatively and quantitatively characterize the shape dimensions of the wafer deformation. TIFF2026516610000064.tif5170 can be represented. In some embodiments, a set of Zernike (or a similar set of polynomials) can be used to represent the wafer profile. TIFF2026516610000065.tif11170 Here, the radius vector of the plane TIFF2026516610000066.tif5170 is located in the (average) plane of the wafer. It can be represented as TIFF2026516610000067.tif5170. Continuous coefficients TIFF2026516610000068.tif6170 Corresponding Zernike polynomial Represents the weights of specific geometric features (elemental deformations) of the wafer as described by TIFF2026516610000069.tif5170. (The Noll indexing scheme of Zernike polynomials is referenced here.) The first three coefficients represent the uniform shift of the wafer ( TIFF2026516610000070.tif5170 Coefficients related to polynomials TIFF2026516610000071.tif5170), TIFF2026516610000072.tif4170 Undeformed, equivalent to rotation around the axis TIFF2026516610000073.tif3170 slope (polynomial Coefficients related to TIFF2026516610000074.tif5170 (TIFF2026516610000075.tif5170), and can be eliminated by realigning the coordinate axes. TIFF2026516610000076.tif3170 Undeformed, equivalent to rotation around the axis TIFF2026516610000077.tif3170 slope (polynomial Related to TIFF2026516610000078.tif5170 I will explain the TIFF2026516610000079.tif5170 coefficient, so I'm not very interested. The fourth coefficient TIFF2026516610000080.tif5170 is, Associated with TIFF2026516610000081.tif5170, it characterizes isotropic parabolic deformation ("curvature"). TIFF2026516610000082.tif5170 each This is associated with the polynomial TIFF2026516610000083.tif6170 and characterizes the saddle-type deformation. The coefficient for TIFF2026516610000084.tif5170 is the diagonal. Upward along TIFF2026516610000085.tif4170 ( TIFF2026516610000086.tif5170) or downward ( (TIFF2026516610000087.tif5170) curved, diagonal Downward along TIFF2026516610000088.tif4170 ( TIFF2026516610000089.tif5170) or upward ( It features a curved saddle shape (TIFF2026516610000090.tif5170). The coefficient for TIFF2026516610000091.tif5170 is, TIFF2026516610000092.tif3170 Upward along the axis ( TIFF2026516610000093.tif5170) or downward ( It curves as shown in TIFF2026516610000094.tif5170. TIFF2026516610000095.tif4170 downward along the axis ( TIFF2026516610000096.tif5170) or upward ( Characterized by a curved saddle shape (TIFF2026516610000097.tif5170). Higher coefficient TIFF2026516610000098.tif5170, etc., are examples of wafer deformation along the radial direction, along the azimuthal direction, or both. Characterizing the gradual and faster changes in TIFF2026516610000099.tif5170, and collective residual deformation This represents TIFF2026516610000100.tif6170. Figure 4 shows one actual deformation of a substrate according to at least one embodiment. The example Zernike polynomial decomposition 400 in TIFF2026516610000101.tif5170 (top left) can be transformed into a parabolic curvature in any unit. TIFF2026516610000102.tif5170 (top right), saddle deformation TIFF2026516610000103.tif5170 (bottom left), and residual deformation. See TIFF2026516610000104.tif5170 (bottom right).

[0031]

[0039] Figure 5 is a flowchart illustrating an exemplary method 500 for stress and deformation relief of a substrate using front-side irradiation, according to at least one embodiment. Method 500 can be performed using a semiconductor manufacturing system comprising one or more processing chambers (e.g., one or more deposition chambers, one or more plasma chambers, one or more etching chambers, one or more polishing chambers, one or more film removal chambers, one or more beam irradiation chambers, one or more optical inspection chambers). The processing chambers can be connected to one or more transfer chambers, which may include, for example, robots for handling substrates in and out of the processing chambers. The transfer chambers may be further connected to load lock chambers (front-end interfaces) which can be connected to one or more front-opening unified pod carriers for holding bare substrates, processed substrates, partially processed substrates, etc. Operations performed by a semiconductor manufacturing system, including any, some, or all of the operations of Method 500, can be performed in response to instructions issued by a suitable computing device having processing logic and memory for storing instructions.

[0032]

[0040] In block 510, method 500 may include obtaining a bare substrate, pre-treating the bare substrate, e.g., polishing the substrate, removing dirt and / or residue from the substrate, and / or preparing the substrate, and / or performing any number of similar operations. In block 520, method 500 may continue to deposit one or more films / layers on the substrate. The layers may include layers of conductive features (e.g., source lines) used as part of a memory cell (transistor) circuit. In some embodiments, the layers may include multiple alternating N (nitride) and O (oxide) layers used as a host and isolation between memory cells. In some embodiments, the layers may include alternating silicon and silicon-germanium alloy layers. In block 530, method 500 may include the shape of the substrate, e.g., some in-plane coordinate system (e.g., polar coordinate system). TIFF2026516610000105.tif5170, Cartesian coordinates, The method includes measuring the displacement of the substrate surface (e.g., top surface) as a function of TIFF2026516610000106.tif5170, or any other suitable coordinates. In block 540, the method 500 includes decomposing the determined shape over a suitable set of polynomials (e.g., Zernike polynomials) and a polynomial expansion coefficient where each coefficient in the set characterizes the abundance of a particular elemental geometric shape in the deformation of the substrate. This includes obtaining the set TIFF2026516610000107.tif6170.

[0033]

[0041] In some embodiments, method 500 may include a decision block 545 for selecting the type of mask (which functions as an SCL) to be used with the substrate. The mask can be selected to serve a dual purpose: to facilitate etching of the stack of layers / films deposited in block 520 and to facilitate stress compensation relaxation of the substrate. For example, the decision in block 545 may be a coefficient that determines the degree of parabolic deformation, e.g., a coefficient This can be done based on TIFF2026516610000108.tif5170. If the substrate is curved downward (towards the back of the substrate), a tension mask can be selected for front deposition in block 545. If the substrate is curved upward (towards the front of the substrate), a compression mask can be selected for front deposition. The operation in block 545 depends on the type of material of the mask to be deposited and the thickness of the mask. This may also include determining TIFF2026516610000109.tif4170. In some embodiments, this determination is set TIFF2026516610000110.tif6170 or the complete profile Multiple expansion coefficients (not just the parabolic curvature coefficient) from TIFF2026516610000111.tif5170 This can be done based on TIFF2026516610000112.tif5170). In certain non-limiting examples, thickness TIFF2026516610000113.tif4170 can be determined as follows: Firstly, the target parabolic deformation is sufficient to overcompensate for the measured substrate deformation. TIFF2026516610000114.tif5170 can be determined, for example, For TIFF2026516610000115.tif5170, the following conditions can be met: TIFF2026516610000116.tif6170 In other words, target parabolic deformation TIFF2026516610000117.tif5170 is a parabolic deformation ( TIFF2026516610000118.tif5170), saddle deformation TIFF2026516610000119.tif5170 and residual deformation (( TIFF2026516610000120.tif5170, and can be selected to be large enough to compensate for higher coefficients. In some embodiments, target parabolic deformation TIFF2026516610000121.tif5170 is at least excessively large compared to the minimum value required to overcompensate for substrate deformation. It can be selected in TIFF2026516610000122.tif5170. For example, TIFF2026516610000123.tif5170 Excessive size TIFF2026516610000124.tif5170 can be empirically selected and depend on the specific material used for the deformation compensation film.

[0034]

[0042] Target parabolic deformation Once TIFF2026516610000125.tif5170 is determined, the mask The thickness of TIFF2026516610000126.tif4170 is, It may be selected using calibration data that represents or otherwise defines TIFF2026516610000127.tif5170. In some embodiments, the function TIFF2026516610000128.tif5170 may be a nonlinear function. In some embodiments, the function TIFF2026516610000129.tif5170 is based on mathematical modeling of the elastic equations for a specific mask material (or multiple material), using empirical calibration, or any combination thereof, to determine the proportionality constants. A linear function containing TIFF2026516610000130.tif3170 It can be named TIFF2026516610000131.tif5170.

[0035]

[0043] In some embodiments, the decision block 545 may not exist, for example, in situations where the type (material) and thickness of the mask are fixed by the specifications of the device to be manufactured and / or the manufacturing process. In some embodiments, limited operation of the decision block 545 may be performed. For example, with a mask type (material) fixed by the technical process specifications, the thickness of the mask can still be selected based on the deformation of the substrate measured in block 530.

[0036]

[0044] In block 550, the selected thickness (of a fixed thickness) The mask (which also functions as SCL) of TIFF2026516610000132.tif4170 can be deposited on the front surface of the substrate. In the optional block 555, the shape of the substrate with the deposited mask can be remeasured, and a new expansion coefficient can be obtained. TIFF2026516610000133.tif5170 can be determined. In block 560, method 500 may include determining (e.g., calculating) a local dose map for mask irradiation. In some embodiments, the dose map may include an expansion coefficient (for compensating for saddle deformation). TIFF2026516610000134.tif5170 (for compensating for residual deformation) Calculations may be performed based on TIFF2026516610000135.tif5170. In block 570, method 500 may continue irradiating the mask with a stress-relaxing beam (e.g., according to a calculated irradiation dose) to reduce the amount of stress in the substrate / film / mask structure and flatten the structure. The stress-relaxing beam may include ions, photons, electrons, and / or any combination thereof. In block 580, method 500 may further include adding one or more features to at least a portion of one or more deposited films. For example, the operation in block 580 may include, for example, forming a photoresist layer on the mask, using the photoresist layer to perform one or more lithography operations to generate a pattern of apertures in the mask, and using the mask (SCL) to etch one or more channels over at least a portion of one or more deposited films by etching one or more channels over at least a portion of one or more deposited films through the pattern of apertures in the mask (SCL). In some embodiments, the operation of block 580 may include adding one or more conductive features to one or more deposited films via one or more etched channels. In some embodiments, the operation of block 580 may include attaching a second wafer to a mask (SCL) and adding one or more features via the back surface of the substrate. Adding such features may include thinning the back surface of the substrate to expose a portion of one or more deposited films and forming one or more features that contact at least one of the one or more deposited films. As part of block 580, various additional operations as defined by the manufacturing specification may be performed, such as covering the mask (SCL) with DARC / BARC, opening the mask, and / or performing any other appropriate operations.

[0037]

[0045] In block 590, the operation of method 500 may include removing the mask (or any mask residue remaining after etching).

[0038]

[0046] Figure 6 is a flowchart showing an exemplary method 600 for determining front illumination parameters according to at least one embodiment. Method 600 can be performed as part of blocks 530-650 of Method 500. In block 610, Method 600 uses, for example, profilometry measurements to determine parabolic deformation (e.g., Zernike coefficients). TIFF2026516610000136.tif5170), saddle deformation (for example, Zernike coefficients) TIFF2026516610000137.tif5170), and residual deformation of the substrate (e.g., Zernike coefficient) This may include identifying all or part of TIFF2026516610000138.tif5170).

[0039]

[0047] In block 620, method 600 is the irradiation dose of the mask deposited on the substrate. The calculation of TIFF2026516610000139.tif5170 may follow. The operation in block 620 is: This may include one or more techniques for determining TIFF2026516610000140.tif5170. In some embodiments, the irradiation dose TIFF2026516610000141.tif5170 can be computed using Monte Carlo simulation. In some embodiments, Irradiation dose using cylindrical resolution in TIFF2026516610000142.tif5170 The file TIFF2026516610000143.tif5170 can be calculated.

[0040]

[0048] In some embodiments, the irradiation dose is applied to a selected edge region of the mask. TIFF2026516610000144.tif5170 can be calculated (and then applied in block 570). More specifically, the operation in block 620 is to determine the magnitude of the principal axis (direction) and saddle deformation (for example, This may include identifying the TIFF2026516610000145.tif5170) and further identifying the edge region of the mask as a target for stress-relaxation irradiation in order to achieve efficient planarization of the substrate. Irradiation of a wider area of ​​the mask can achieve a further (finer) reduction of substrate stress, for example, to alleviate residual substrate deformation remaining after edge irradiation.

[0041]

[0049] In some embodiments, the irradiation dose TIFF2026516610000146.tif5170 is an influence function, also known as the Green's function. This can be calculated using TIFF2026516610000147.tif5170, which is a point on the substrate. A point-like force applied to TIFF2026516610000148.tif4170 causes a point on the substrate. Characterizing the substrate response (e.g., deformation) in TIFF2026516610000149.tif4170. In some embodiments, the influence function TIFF2026516610000150.tif5170 can be determined from computational simulations or analytical calculations. In some embodiments, the influence function can be determined from one or more experiments, which may include performing ion implantation on a film deposited on a reference substrate. In some embodiments, the influence function Multiple combinations of techniques can be used to determine TIFF2026516610000151.tif5170.

[0042]

[0050] For example, Monte Carlo simulations of a structure (e.g., a substrate with a film and a mask deposited thereon) can be performed for specific materials of the structure (e.g., silicon substrate, on-layer stack, Si / SiGe layer stack, carbon mask, etc.) and specific thicknesses of the structure. Initial Monte Carlo simulations can be performed for baseline (default) beam irradiation conditions (e.g., default settings for an ion implanter or light emitter). Baseline conditions may include default particle types (ions, photons, electrons), default particle energies, and default doses of particles directed to the mask (e.g., default scanning speed and default scanning pattern).

[0043]

[0051] In some embodiments, various techniques for calculating irradiation dose can use calibration data 622 collected for actual irradiations performed for various types of irradiation beams, irradiation beam energy, type and material of the irradiated structure, beam incidence angle to the structure, etc. In some embodiments, the calibration data 622 may be statistically pre-processed. For example, various measurements can be collected for multiple substrate / film / mask materials, particle types, incidence angle, and / or other parameters. The statistically processed measurements can be stored (e.g., in the memory of a processing device that performs irradiation dose calculations) in the form of probability distributions of various quantities, including but not limited to: • Density distribution of ion implantation with different ion types, ion energies, and angles of incidence; • Distribution of the number of vacancies generated at different depths (per unit of ion migration length) for different types of irradiated particles (ions, photons, electrons), particle energies, and angles of incidence; • The distribution of stress generated by the irradiated beam for various beam intensities and durations, and / or similar.

[0044]

[0052] Performing the irradiation dose calculation in block 620 may include sampling from a stored distribution and identifying the possibility of achieving target stress relaxation with default settings for beam irradiation conditions of a given type and thickness mask. Method 600 may include several verification operations designed to determine whether the target stress can be achieved without adversely affecting the properties of the substrate / film. For example, in block 625, Method 600 may include verifying whether the penetration depth of the selected (e.g., default) type of particles is sufficient. For example, the penetration depth may be at least a specific portion of the mask thickness, e.g., 20%, 30%, 50%, 80%, or more. In some embodiments, the penetration depth may be up to 100% of the thickness. If the energy is insufficient, Method 600 may include checking in block 630 whether the irradiation beam source can output particles of higher energy. If higher energy is available, Method 600 can increase the energy of the particles (block 640) and continue repeating the irradiation dose calculation in block 620 for the increased energy. If the maximum energy of the irradiation beam source has already been reached, method 600 can be repeated by replacing the ions (in block 650) with different types of ions (for example, if an ion beam is used for irradiation), such as replacing silicon ions with ions such as boron, carbon, or fluorine, and performing Monte Carlo simulations of the new types of ions.

[0045]

[0053] In block 655, method 600 may include verifying whether the expected number of formed voids is sufficient. To verify sufficiency, method 600 can evaluate the stress relaxation caused by the formed voids. In one embodiment, method 600 can start with a certain value of stress in the mask, e.g., -3.0 GPa or some other suitable value (a negative sign indicating compressive stress), and use beam irradiation to relax this stress to 0.0 GPa at various locations in the mask toward the neutral point.

[0046]

[0054] If the number of voids is insufficient, method 600 may include increasing the dose of particles (block 660) and repeating the irradiation dose calculation of block 620 for the increased dose.

[0047]

[0055] In block 665, method 600 is such that the vacancies reach a target depth (e.g., the thickness of the film). TIFF2026516610000152.tif4170, or a certain proportion of the film, This may include confirming that the particles are located within TIFF2026516610000153.tif5170 or any other value empirically set to prevent the particles from penetrating the substrate / film and affecting the properties of the substrate / film. If vacancies are formed at a depth beyond the target depth, method 600 may include increasing the incident angle (e.g., by tilting the irradiation beam) (in block 670) to keep the vacancies (and displacement impurities) in a shallower region of the mask.

[0048]

[0056] Blocks 620-670 may be repeated multiple times until the irradiation dose calculation in block 620 is determined to be sufficient to achieve the desired stress relaxation (for example, by reducing the tensile stress of the mask, substrate deformation is eliminated or reduced to at least an acceptable tolerance). The final setting for mask irradiation (block 680) determined from the irradiation dose calculation may then be used for mask irradiation with a stress relaxation beam (in block 570).

[0049]

[0057] Figures 7A to 7H schematically illustrate an exemplary process for manufacturing a logic device that uses a stress-relaxation beam to irradiate a front-side deposited layer, according to at least one embodiment. Figure 7A shows a stack of films 704 deposited on the front surface of a substrate 702. A stress compensation layer 706 is deposited on top of the stack of films 704. The stress compensation layer 706 may include a dielectric / semiconductor material, a metallic material, or a combination of one or more dielectric / semiconductor materials and one or more metallic materials. The stress compensation layer 706 may be a mask (e.g., a hard mask) deposited for use in an etching operation or any other processing operation. In some embodiments, the stress compensation layer 706 may be a film deposited for stress relaxation purposes.

[0050]

[0058] As shown in Figure 7B, by exposing the stress compensation layer 706 to irradiation 708, the stress compensation layer 706 can be subjected to a local stress modification process, for example, as disclosed above in relation to Figures 1 to 6.

[0051]

[0059] Figure 7C shows the preparation of a substrate carrier 710 (e.g., a silicon substrate, glass, plastic web, or some other type of substrate) on which the adhesive layer 712 is deposited.

[0052]

[0060] As shown in Figure 7D, the substrate carrier 710 can be rotated upside down and attached to the stress compensation layer 706 supported by the substrate 702 using the adhesive layer 712.

[0053]

[0061] As shown in Figure 7E, the substrate 702 can undergo partial removal operations (backside thinning) including, but not limited to, rough grinding, fine grinding, CMP, wet etching, dry etching, and / or similar processes.

[0054]

[0062] As shown in Figure 7F, the remaining portion of the substrate 702 can be subjected to lithographic patterning, for example, to form openings for conductive channels.

[0055]

[0063] As shown in Figure 7F, the patterning 714 can be filled with one or more conductive materials 716 and can undergo one or more polishing operations.

[0056]

[0064] As shown in Figure 7H, for example, one or more additional layers 718 of conductive or insulating material can be deposited using a metal interconnect dual damascene treatment operation or other suitable operation.

[0057]

[0065] Figure 8A schematically shows an irradiation system 800 capable of performing irradiation of a stress compensation layer according to at least one embodiment. The irradiation system 800 may include a collimating and focusing column 110 as shown in Figure 1. The irradiation system 800 may further include a beam source 802 for generating a source beam 804. The beam source 802 may include a chamber for generating ions (e.g., a plasma chamber), a light source for generating photons (e.g., a laser, laser diode, lamp, etc.), a heating filament for generating electrons, and / or any other source for particles of the type deployed in the particular stress relaxation techniques of this disclosure. The beam source 802 may be powered by a power element 806 and may include an extraction electrode assembly (not shown). The irradiation system 800 may include a mass spectrometer 808 (e.g., if the beam source 802 generates charged particles such as electrons or ions), and a collimating and focusing column 110. The collimating and focusing column 110 can guide the stress relaxation beam 108 to the substrate 102. The substrate 102 may be supported by a support stage 812. In some embodiments, the support stage 812 and the substrate 102 can remain stationary while the substrate 102 is irradiated with the stress relaxation beam 108, and the components of the irradiation system 800 can be repositioned relative to the substrate 102. In some embodiments, the irradiation system 800 may remain stationary, and the support stage 812 can reposition the substrate 102. In some embodiments, the stress relaxation beam 108 may have an intensity (e.g., light intensity) that is modulated by changing the intensity of the beam source 802 and / or by placing a partially absorbing or partially reflective material at a location between the beam source 802 and the substrate 102. This allows for localized irradiation doses at various locations on the substrate 102. It will be possible to supply TIFF2026516610000154.tif5170. Scanning by the stress relaxation beam 108 is performed along multiple directions according to any suitable predetermined pattern, for example, TIFF2026516610000155.tif3170 along the axis and TIFF2026516610000156.tif4170 Along the axis, for example, in a spiral pattern TIFF2026516610000157.tif3170 can be performed back and forth along the axis. In various embodiments, the stress relaxation beam 108 can be scanned at frequencies of several Hz, tens of Hz, hundreds of Hz, thousands of Hz, or higher.

[0058]

[0066] The operation of the irradiation system 800 may be controlled by a controller 814 which includes any suitable computing device, microcontroller, or processor, such as any other processing device having a central processing device (CPU), field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), etc., and / or memory devices, such as random access memory (RAM), read-only memory (ROM), flash memory, and / or any combination thereof. The controller 814 can control the operation of the power element 806, the support stage 812, and / or various other components and modules of the irradiation system 800. The controller 814 may include a stress relaxation module 816 capable of performing simulations to determine the target intensity of the stress relaxation beam 108 used to alleviate deformation of various wafers. In some embodiments, as shown in Figure 8B, the support stage 812 can tilt the substrate 102 in one or two spatial directions, for example, to change the angle of incidence of the stress relaxation beam 108 to the substrate 102. In some embodiments, instead of tilting the substrate 102, the controller 814 can cause the stress relaxation beam 108 to tilt relative to the substrate 102.

[0059]

[0067] Figure 9 shows a block diagram of an exemplary computer system 900 capable of supporting the operation of the present disclosure according to at least one embodiment. In various exemplary embodiments, the exemplary computer system 900 may be or include the controller 814 in Figure 8. The exemplary computer system 900 may be connected to other computer systems in a LAN, intranet, extranet, and / or internet. The computer system 900 may operate in the role of a server in a client-server network environment. The computer system 900 may be a personal computer (PC), a set-top box (STB), a server, a network router, a switch or bridge, or any device capable of executing a set of instructions (sequentially or otherwise) that specify actions to be performed by such device. Furthermore, although only a single exemplary computer system is shown, the term “computer” should also be interpreted as including any collection of computers that individually or in conjunction execute a set (or set of) instructions to perform any one or more of the methods described herein.

[0060]

[0068] An exemplary computer system 900 may include a processing device 902 (also called a processor or CPU), main memory 904 (e.g., read-only memory (ROM), flash memory, synchronous DRAM (SDRAM), and other dynamic random access memory (DRAM)), static memory 906 (e.g., flash memory, static random access memory (SRAM), etc.), and secondary memory (e.g., data storage device 918) that can communicate with each other via a bus.

[0061]

[0069] The processing device 902 represents one or more general-purpose processing devices, such as a microprocessor or a central processing device. More specifically, the processing device 902 may be a complex instruction set computing (CISC) microsystem processor, a reduced instruction set computing (RISC) microsystem processor, a very long instruction word (VLIW) microsystem processor, a processor that executes other instruction sets, or a processor that executes combinations of instruction sets. The processing device 902 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), or a network processor. In one or more aspects of this disclosure, the processing device 902 may include processing logic 926 configured to execute an instruction (e.g., instruction 922) that implements an example of a wafer stress and deformation relaxation method 500 and / or a method 600 for determining front-illumination parameters, according to at least one embodiment.

[0062]

[0070] The exemplary computer system 900 may further include a network interface device 908 that can be communicatively connected to a network 920. The exemplary computer system 900 may further include a video display 910 (e.g., a liquid crystal display (LCD), a touchscreen, or a cathode ray tube (CRT)), an alphanumeric input device 912 (e.g., a keyboard), a cursor control device 914 (e.g., a mouse), and an acoustic signal generating device 916 (e.g., a speaker).

[0063]

[0071] The data storage device 918 may include a computer-readable storage medium (or more specifically, a non-temporary computer-readable storage medium) 924 in which one or more sets 922 of executable instructions are stored. In one or more aspects of the present disclosure, the executable instructions 922 may include executable instructions that implement an example of a wafer stress and deformation relief method 500 and / or a method 600 for determining front-lighting parameters using front-lighting, according to at least one embodiment.

[0064]

[0072] The executable instruction 922 may reside, all or at least partially, in the main memory 904 and / or processing device 902 while being executed by the exemplary computer system 900, and the main memory 904 and processing device 902 also constitute computer-readable storage media. Furthermore, the executable instruction 922 may be further transmitted or received over a network via the network interface device 908.

[0065]

[0073] In Figure 9, the computer-readable storage medium 924 is shown as a single medium; however, the term “computer-readable storage medium” should be understood to include a single medium or multiple mediums that store one or more sets of operational instructions (e.g., centralized or distributed databases, and / or associated caches and servers). Furthermore, the term “computer-readable storage medium” should be interpreted to include any medium capable of storing or encoding a set of instructions for execution by a machine, causing the machine to perform one or more of the methods described herein. Therefore, the term “computer-readable storage medium” should be interpreted to include, but not be limited to, solid memory, optical media, and magnetic media.

[0066]

[0074] Some parts of the detailed description above are presented in terms of algorithms and representations of operations on data bits in computer memory. Descriptions and representations of these algorithms are means used by those skilled in the field of data processing technology to most effectively convey the content of the invention to others skilled in the art. An algorithm is considered here, and generally, as a consistent sequence of steps leading to a desired result. These steps require the physical handling of quantities. These quantities are usually, though not always, in the form of electrical or magnetic signals that can be stored, transferred, combined, compared, or otherwise manipulated. These signals have proven convenient, primarily for reasons of common use, to be represented as bits, values, elements, symbols, characters, terms, numbers, etc.

[0067]

[0075] However, it should be noted that all these terms and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those physical quantities. Unless otherwise stated, as will be apparent from the following descriptions, throughout this specification, descriptions using terms such as “specify,” “determine,” “save,” “adjust,” “cause,” “return,” “compare,” “create,” “stop,” “load,” “copy,” “throw,” “replace,” and “execute” refer to the operation and processing of a computer system or similar electronic computing device. A computer system or similar electronic computing device manipulates data represented as physical (electronic) quantities in its registers and memory and converts it to other data represented as similar physical quantities. This conversion destination is the computer system’s memory, registers, or other information storage, transmission, and display devices.

[0068]

[0076] Embodiments of this disclosure also relate to apparatus for carrying out the methods described herein. The apparatus may be a general-purpose computer system that can be configured specifically for a desired purpose or selectively programmed by a computer program stored in the computer system. Such computer programs may be stored in computer-readable storage media such as any type of disk including optical disks, CD-ROMs, and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic disk storage media, optical storage media, flash memory devices, other types of machine-accessible storage media, or any type of media suitable for storing electronic instructions, each of which is connected to a computer system bus.

[0069]

[0077] The methods and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used with the program in accordance with the teachings herein, or it may be more convenient to construct a device more specialized to perform the required method steps. The structures of various such systems will become apparent from the description below. Furthermore, the scope of this disclosure is not limited to any particular programming language. It should be understood that the teachings herein can be implemented using a variety of programming languages.

[0070]

[0078] It should be understood that the above description is intended to be illustrative and not limiting. Many other implementation examples will become apparent to those skilled in the art upon reading and understanding the above description. While this disclosure describes specific embodiments, it should be recognized that the systems and methods of this disclosure are not limited to the embodiments described herein and can be implemented with modifications within the scope of the appended claims. Therefore, the specification and drawings should be considered illustrative rather than limiting. Accordingly, the scope of this disclosure should be determined by referring to the appended claims and, together with, the entire scope of equivalents to which the claims are applicable.

Claims

1. A method for manufacturing semiconductor devices, Depositing one or more films on the front surface of the substrate, Forming a stress compensation layer (SCL) on one or more deposited films, wherein the SCL changes the stress of the substrate; In order to reduce the deformation of the substrate, a stress relaxation beam is applied to the SCL, Adding one or more features to at least one of the one or more deposited films Methods that include...

2. The method according to claim 1, wherein the stress relaxation beam includes at least one of an ion beam, a photon beam, or an electron beam.

3. Adding one or more features A method comprising etching one or more channels across at least a portion of the one or more deposited films using the SCL.

4. Etching one or more of the aforementioned channels Forming a photoresist layer on the SCL, Using the photoresist layer, one or more lithography operations are performed to create an aperture pattern in the SCL. Etching the one or more channels over at least a portion of the one or more deposited films through the pattern of the SCL openings. The method according to claim 3, including the method described in claim 3.

5. The method according to claim 4, comprising adding one or more conductive features to the one or more deposited films via the one or more etched channels.

6. The method according to claim 1, comprising removing the SCL after adding the one or more features.

7. Adding the one or more features to at least one of the one or more deposited films is The second wafer is attached to the SCL, Adding one or more features via the back surface of the substrate The method according to claim 1, including the method described in claim 1.

8. Adding one or more features via the back surface of the substrate is Thinning the back surface of the substrate to expose at least one of the one or more deposited films, To form the one or more features so as to be in contact with at least one of the one or more deposited films. The method according to claim 7, including the method described in claim 7.

9. To obtain optical inspection data that characterizes the deformation profile of the substrate, Using the aforementioned optical inspection data, the setting of the stress relaxation beam is determined. The method according to claim 1, including the method described in claim 1.

10. The setting for the stress relaxation beam is The type of particles in the stress relaxation beam, The energy of the particles in the stress relaxation beam, or The incidence angle of the particles in the stress relaxation beam The method according to claim 9, comprising one or more of the above.

11. It is a system, Memory and A processing device that is communicatively connected to the aforementioned memory and The processing device is equipped with, Depositing one or more films on the front surface of the substrate, Forming a stress compensation layer (SCL) on one or more deposited films, wherein the SCL changes the stress of the substrate; In order to reduce the deformation of the substrate, a stress relaxation beam is applied to the SCL, Adding one or more features to at least one of the one or more deposited films A system that causes operations including [specific actions] to be performed.

12. The system according to claim 11, wherein the stress relaxation beam includes at least one of an ion beam, a photon beam, or an electron beam.

13. Adding one or more features The system according to claim 11, comprising etching one or more channels across one or more deposited films using the SCL.

14. A semiconductor manufacturing system, One or more films are deposited on the front surface of the substrate. Forming a stress compensation layer (SCL) on one or more deposited films, wherein the SCL changes the stress of the substrate, In order to reduce the deformation of the substrate, a stress relaxation beam is applied to the SCL. To add one or more features to at least one of the one or more deposited films, A semiconductor manufacturing system comprising one or more processing chambers.

15. To add one or more features, the one or more processing chambers, The semiconductor manufacturing system according to claim 14, wherein the SCL is used to etch one or more channels over at least a portion of the one or more deposited films.

16. To etch the one or more channels, the one or more processing chambers are: A photoresist layer is formed on the SCL, Using the photoresist layer, one or more lithography operations are performed to generate an aperture pattern in the SCL. The semiconductor manufacturing system according to claim 15, wherein the one or more channels are etched over at least a portion of the one or more deposited films via the pattern of openings in the SCL.

17. The one or more processing chambers described above are further: The semiconductor manufacturing system according to claim 16, comprising adding one or more conductive features to the one or more deposited films via the one or more etched channels.

18. The one or more processing chambers described above are further: The semiconductor manufacturing system according to claim 14, wherein the SCL is removed after adding one or more of the features.

19. To add the one or more features to at least one of the one or more deposited films, the one or more processing chambers are: The second wafer is attached to the SCL, The semiconductor manufacturing system according to claim 14, wherein one or more features are added via the back surface of the substrate.

20. To add the one or more features to at least one of the one or more deposited films, the one or more processing chambers further: The back surface of the substrate is thinned to expose at least one of the one or more deposited films. The semiconductor manufacturing system according to claim 19, wherein the one or more features are formed in contact with at least one of the one or more deposited films.

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