Optical communication substrate using glass interposer

Abstract

This specification describes photonic interconnects based on glass interposers. The type of glass interposer described herein is used to photonically interconnect multiple smaller photonic integrated circuits (PICs), as opposed to using a single larger PIC. Typical yields of glass interposers are significantly higher than those of PICs. This is because glass interposers are inherently passive, while PICs contain active photonic elements. Active photonic components tend to be more susceptible to manufacturing defects than passive photonic components because they require additional manufacturing steps. The technique described herein improves performance by allowing the selection and sorting of reticles known to be good, instead of having to slice a large number of connected reticles from the wafer.

Description

Technical Field

[0001] The present invention relates to an optical communication substrate using a glass interposer.

Background Art

[0002] Optical interconnect is a type of communication technology that uses optical signals to transmit data between different components or devices within a system. Such an interconnect replaces conventional electrical connections such as copper wires or wirings on a circuit board with optical fibers or waveguides. In an optical interconnect, data is converted into an optical signal using an optical transmitter, typically a laser or a light-emitting diode (LED). Such an optical signal travels through an optical fiber or waveguide made of a material that can efficiently guide and transmit light with minimal loss. On the receiving side, an optical receiver reconverts the input optical signal back into an electrical signal that can be processed by an electronic device.

Summary of the Invention

[0003] Some embodiments relate to a photonic device comprising a glass interposer including an optical network having one or more glass waveguides, and a plurality of photonic integrated circuits (PICs) attached to the glass interposer, wherein at least one PIC of the plurality of PICs includes an optical transceiver optically coupled to the optical network of the glass interposer, and a plurality of electrical connections configured to couple to one or more electronic chips.

[0004] In some embodiments, the glass interposer further includes a through glass via (TGV), and at least one PIC further includes a through silicon via (TSV) electrically coupled to the TGV.

[0005] In some embodiments, the glass interposer further includes a first redistribution layer (RDL) adjacent to a first surface of the glass interposer and a second RDL adjacent to a second surface opposite to the first surface of the glass interposer, wherein the first RDL is configured to connect to at least one PIC and the second RDL is configured to connect to a substrate.

[0006] In some embodiments, at least one PIC is mounted on a glass interposer on a first surface of the PIC, and electrical connections are formed on a second surface of the PIC opposite to the first surface.

[0007] In some embodiments, the glass interposer defines a recess, the first surface of the PIC is located within the recess, and at least one optical transceiver of the PIC is edge-coupled to the optical network of the glass interposer.

[0008] In some embodiments, the glass interposer defines a recess, the first surface of the PIC is suspended on the recess, and at least one optical transceiver of the PIC is evanescently coupled to the optical network of the glass interposer.

[0009] Some embodiments relate to a system including multiple photonic integrated circuits (PICs) and a multi-reticle glass interposer that enables optical communication between the PICs. In some embodiments, at least one of the PICs is a multi-reticle PIC.

[0010] In some embodiments, the system further includes multiple integrated circuit chips, each chip located on a different reticle of the PIC. In some embodiments, the glass interposer includes a glass waveguide that couples the PICs together.

[0011] In some embodiments, the glass interposer further includes glass through-vias coupled to silicon through-vias formed within the PIC. In some embodiments, each of the multiple PICs is acquired from a common wafer.

[0012] In some embodiments, multiple PICs are acquired from two or more wafers. In some embodiments, each PIC is coupled to a glass interposer via evanescent coupling.

[0013] In some embodiments, the PIC includes an active photonic circuit, while the glass interposer lacks an active photonic circuit. Some embodiments relate to a computing system comprising a glass interposer including an optical network having one or more glass waveguides, a plurality of photonic integrated circuits (PICs) mounted on the glass interposer, each including an optical transceiver optically coupled to the optical network of the glass interposer, and a plurality of electronic chiplets arranged on the plurality of PICs such that the plurality of PICs are positioned between the plurality of electronic chiplets and the glass interposer.

[0014] In some embodiments, the glass interposer further includes through-glass vias (TGVs), and the PIC further includes through-silicon vias (TSVs) electrically coupled to the TGVs. In some embodiments, multiple PICs are acquired from two or more wafers.

[0015] In some embodiments, the glass interposer defines a recess, at least one of several PICs is located within the recess, and the optical transceiver of at least one PIC is edge-coupled to the optical network of the glass interposer.

[0016] In some embodiments, the computing system further includes a voltage regulator (VR) module, and a glass interposer is positioned between the PIC and the VR module.

[0017] Various aspects and embodiments of this application will be described with reference to the following figures. Please note that the drawings are not necessarily drawn to scale. Items appearing in multiple figures are indicated by the same reference numeral in the figures in which they appear. [Brief explanation of the drawing]

[0018] [Figure 1A] This figure shows a semiconductor wafer having multiple reticles, including a 2x4 reticle block, according to several embodiments. [Figure 1B] This figure shows a semiconductor wafer having multiple reticles, including two blocks of 2x2 reticles, according to several embodiments. [Figure 1C] This figure shows two semiconductor wafers, one containing a 2x2 reticle block and the other containing a 2x1 reticle block, according to some embodiments. [Figure 2A] This is a cross-sectional view of a photonic system including a glass interposer according to several embodiments. [Figure 2B] This is a cross-sectional view of another photonic system including a glass interposer, according to several embodiments. [Figure 2C] This is a cross-sectional view of yet another photonic system, including a glass interposer, according to several embodiments. [Figure 2D] This is a cross-sectional view of yet another photonic system, including a glass interposer, according to several embodiments. [Figure 2E] This is a cross-sectional view of a bonding photonic system including an edge coupler, according to several embodiments. [Figure 2F] This is a cross-sectional view of a bonding photonic system including an evanescent coupler according to several embodiments. [Figure 3A] Top view of a photonic system including a glass interposer, according to some embodiments. [Figure 3B] Top view of another photonic system including a glass interposer, according to some embodiments. [Figure 3C] Top view of yet another photonic system including a glass interposer, according to some embodiments. [Figure 4A] Top view of a photonic system including a glass interposer and a pair of 2×2 reticle photonic integrated circuits (PICs), according to some embodiments. [Figure 4B] Top view of a photonic system including a glass interposer, a 2×2 reticle PIC, and a 2×1 reticle PIC, according to some embodiments. [Figure 5A] Top view of a computing system including a plurality of interconnected glass interposers, according to some embodiments. [Figure 5B] Top view of a computing system including a plurality of glass interposers interconnected using optical flow switches, according to some embodiments. [Figure 6] Block diagram of a computing system including a plurality of glass interposers interconnected using optical flow switches, according to some embodiments. [Figure 7] Cross-sectional view of a photonic system including a glass interposer and a plurality of power modules, according to some embodiments. [Figure 8A] Cross-sectional view of a photonic system including a through-hole glass interposer, according to some embodiments. [Figure 8B] Top view of the through-hole glass interposer of FIG. 8A, according to some embodiments. [Figure 9] Cross-sectional view of a photonic system including a flip-chip substrate, according to some embodiments. [Figure 10]This is a cross-sectional view of a photonic system including a glass photonic chiplet according to several embodiments. [Figure 11] This is a cross-sectional view of a photonic system including PICs positioned on both sides of a glass interposer, according to several embodiments. [Figure 12] This is a cross-sectional view of a photonic system including PICs positioned on both sides of a glass interposer, according to several embodiments. [Modes for carrying out the invention]

[0019] Chip-on-optical silicon solutions based on photonic interposers can be used to improve the bandwidth of inter-chiplet die communication within application-specific integrated circuit (ASIC) packages, enabling the close integration of multiple heterogeneous chiplets. Compared to conventional electronic solutions, this approach improves inter-die communication bandwidth and latency by enabling communication anywhere within the die (not just the die edge) without limitations imposed by electromagnetic interference (EMI). Furthermore, this approach improves the yield of electronic dies by allowing large chiplet dies to be divided into smaller chiplet dies. These types of photonic interposers include integrated photonic circuits (e.g., photonic switches, transceivers, couplers, and waveguides) configured to route signals in a programmable manner in the optical domain.

[0020] The inventors recognize and understand that this method has challenges. Firstly, yield is limited. To connect a considerable number of chiplet dies, the photonic interposer must be relatively large. To be large enough to interconnect several chiplets, the photonic interposer is generally formed by combining multiple consecutive reticle slices from an optical wafer. This is obtained using repeating reticle tiles. Yield problems arise because the performance of the photonic interposer depends on whether each of these reticles is good (yield). If at least one of these reticles is not good (e.g., has a manufacturing defect), the performance of the entire photonic interposer is impaired. For example, consider the wafer in Figure 1A containing a grid of reticles. Multiple photonic interposers can be obtained from this wafer by slicing consecutive reticles. In this example, the photonic interposer is obtained by slicing a block of 2x4 reticles. The performance of the resulting photonic interposer depends on whether each of the 2x4 reticles is free of defects. If at least one of these eight reticles is defective, the overall performance of the photonic interposer is impaired. While it is possible to mitigate this yield problem using redundant logic, this approach is limited and does not completely solve the problem.

[0021] Secondly, forming a photonic interposer by repeating wafer reticles limits the flexibility of the chiplet dies that can be placed on top of the interposer. This is because, in most implementations, the wafer reticles are identical to each other, thereby limiting the functionality that can be achieved using the photonic interposer.

[0022] Recognizing the susceptibility of conventional photonic interposers to yield, coupled with their limited flexibility, the inventors developed a glass interposer-based architecture. The type of glass interposer described herein is used to photonically interconnect multiple smaller photonic integrated circuits (PICs), as opposed to using a single larger PIC. The inventors recognize and understand that the typical yield of glass interposers is significantly higher than that of PICs. This is because glass interposers are inherently passive, while PICs contain active photonic elements. Active photonic components (e.g., photonic transceivers and switches) tend to be more susceptible to manufacturing defects than passive photonic components (e.g., waveguides and couplers) because active components require additional manufacturing steps (e.g., ion implantation, sputtering, epitaxial growth, etc.). This method improves performance because, instead of having to slice through a large number of connected reticles (as shown in Figure 1A), it allows for the selection and sorting of reticles that are known to be good. In the example in Figure 1B, instead of a single PIC with eight consecutive reticles, two separate PICs can be obtained by slicing separate blocks of 2x2 reticles. The switching capability of the PIC in Figure 1B is approximately the same as that of the PIC in Figure 1A, but yield performance is improved. This is because the probability of finding eight good reticles in a 4x2 arrangement is generally lower than the probability of finding eight good reticles in two different 2x2 blocks.

[0023] A further advantage is that using a glass interposer in the manner described herein offers greater flexibility than a photonic interposer in that it allows the use of PICs with different patterns. In contrast, in a reticle-stitched photonic interposer, each reticle has the same pattern as the others. This can be seen from Figure 1C, where one PIC is extracted from a first wafer and another PIC is extracted from another wafer. The wafers may be patterned in different layouts. The PICs may be mounted together on a common glass interposer.

[0024] Figure 2A is a cross-sectional view of a photonic system including a glass interposer according to several embodiments. The glass interposer 102 sits on a substrate 100 and hosts one or more PICs 120. Light is supplied to the PICs via optical fibers 112, which are optically coupled to the glass interposer via fiber connectors 114. The electronic integrated circuits are arranged on top of the PICs. For example, a first PIC is shown having a memory chiplet 130 and a compute chiplet 131 arranged on top of it, and another PIC is shown having a switch chiplet 131 arranged on top of it. The package in Figure 2A can connect other types of electronic integrated circuits, including, for example, accelerators, graphics processing units, etc.

[0025] The glass interposer 102 may be made of any suitable type of glass, including, for example, SiO2, fused silica, or borosilicate glass. The glass interposer may include passive optical devices (e.g., waveguides, passive couplers, waveguide crossings, wavelength multiplexers / demultiplexers, etc.) but may be inherently passive in that active optical devices (e.g., modulators, detectors, switches, etc.) may be omitted. The glass waveguide 106 may be used to route light from one part of the glass interposer to another, thereby forming a network that optically couples the PICs to each other. For example, Figure 2A shows a photonic signal 111 traveling from one PIC to another. The waveguide may be made of any suitable material compatible with the technique used to manufacture the glass interposer. The waveguide may be fabricated in situ inside the glass interposer itself by lithography or laser writing. In another embodiment, the waveguide and passive optical components within the glass interposer may be manufactured using an ion exchange process. Different glass compositions may require different manufacturing techniques. Furthermore, the waveguide may be made of a material having a refractive index greater than that of the surrounding material, thus ensuring that the optical signal modes are well contained and guided within the waveguide. For example, the glass interposer may be made of SiO2, and the waveguide may also be made of SiO2, but may be doped to produce a greater refractive index, or may be made of silicon nitride. Silicon nitride may be grown, deposited, or bonded.

[0026] Glass interposers can be manufactured using semiconductor manufacturing techniques. In one example, a glass interposer is patterned according to a reticle-stitched arrangement. In such a configuration, a step-and-repeat process generates multiple reticles as instances of the same set of photomasks. Each reticle can be patterned to have waveguides that optically couple to waveguides formed in adjacent reticles. In Figure 2A, the intersection 108 represents the location where a waveguide crosses the boundary between adjacent reticles in the glass interposer.

[0027] In some embodiments, the glass interposer 102 may be relatively thick along the vertical direction, but the thickness may be limited by the maximum length that can be obtained for the TGV using conventional manufacturing techniques. For example, in some embodiments, the thickness of the glass interposer may be less than 2.54 cm (1 inch) (e.g., 150 μm to 350 μm, or 250 μm to 350 μm). In other embodiments, the thickness is given some examples: 2.54 cm (1 inch) to 50.8 cm (20 inches), 5.08 cm (2 inches) to 50.8 cm (20 inches), 12.7 cm (5 inches) to 50.8 cm (20 inches), 19.1 cm (7.5 inches) to 50.8 cm (20 inches), 25.4 cm (10 inches) to 50.8 cm (20 inches), 31.8 cm (12.5 inches) to 50.8 cm (20 inches), 38.1 cm (15 inches) to 50.8 cm (20 inches), 2.54 cm (1 inch) to 38.1 cm (15 inches), 5.08 cm The dimensions may also be m (2 inches) to 38.1 cm (15 inches), 12.7 cm (5 inches) to 38.1 cm (15 inches), 19.1 cm (7.5 inches) to 38.1 cm (15 inches), 25.4 cm (10 inches) to 38.1 cm (15 inches), 31.8 cm (12.5 inches) to 38.1 cm (15 inches), 2.54 cm (1 inch) to 25.4 cm (10 inches), 5.08 cm (2 inches) to 25.4 cm (10 inches), 12.7 cm (5 inches) to 25.4 cm (10 inches), or 19.1 cm (7.5 inches) to 25.4 cm (10 inches).

[0028] The PIC 120 is located in a recess formed on the upper surface of the glass interposer 120. This arrangement allows the waveguide of the PIC to be aligned (along the same axis) with the glass waveguide of the interposer, thereby forming an edge coupler 137. The edge coupler provides efficient optical coupling to and from the PIC. In contrast to the glass interposer 102, the PIC can be inherently active in that it may include a modulator, a photodetector, and an optical switch. In Figure 2A, for example, one PIC is shown having an optical transmitter (TX) 122, and the other PIC is shown having an optical receiver (RX) 124. In this arrangement, data transmitted by the optical TX 122 is transmitted to the optical RX 124 via the glass waveguide 106. In some embodiments, each PIC may have both a transmitter and a receiver, thus allowing the PIC to process data in both directions. Furthermore, the PIC may include an optical switch (not shown in Figure 2A) for routing data to (and from) any one of the chiplets located on the PIC.

[0029] Optical switching elements can change the topology of how electronic chiplets are interconnected. A specific topology that is most advantageous for one application may be created first, and then modified in response to the demands of performing different applications. Some of the most common topologies include all-to-all, hypertoroid, ring, and tree.

[0030] Optical switching elements also enable the use of redundant photonic elements within a PIC to improve PIC yield. Two photonic devices may be connected to the switch. If one photonic device (e.g., TX, RX, or coupler) is not manufactured as good during production or fails during operation, the switch can be used to modify the system to use another well-manufactured or still-good photonic element.

[0031] The optical TX and optical RX within the PIC can utilize Wavelength Division Multiplexing (WDM), in which multiple wavelengths (for example, at intervals of 50 GHz, 100 GHz, 200 GHz, or 400 GHz in high-density WDM, or at intervals of 10 nm or more in coarse WDM) are carried through the same physical waveguide or optical fiber. Glass waveguides and waveguides within the PIC can be adapted to high-density or coarse WDM.

[0032] In some embodiments, the PIC may further include a vertical grid coupler to couple light directly (perpendicularly) without passing through a glass interposer. These vertical grid couplers may be useful for testing photonic devices within the PIC during the manufacturing process.

[0033] If the PIC is flip-chip mounted in a glass interposer, the vertical grid coupler may be exposed from the bottom (the top is closest to the active silicon layer, and the bottom is where the handle silicon layer is located) by removing or thinning the silicon handle. Removal can be done by either grinding or etching.

[0034] Light sources, such as laser sources, LED sources, vertical cavity surface-emitting laser (VCSEL) sources, or amplified spontaneous emission (ASE) sources, can be integrated into the system in several ways. Firstly, external light sources can be coupled to the system via fibers that can be connected via edge connector assemblies or vertical grating couplers on the PIC. Furthermore, these laser sources can also be directly flip-chip bonded onto at least one PIC. In another embodiment, one of the PICs may be fabricated using a III-V foundry process such that this particular PIC has gain material for laser oscillation or optical amplification operation. Optical circuit switches and light distribution systems within the PIC can be used to distribute light sources from one input point to multiple PICs, and to multiple TX elements within a single PIC.

[0035] In the example in Figure 2A, the compute chiplet 131 includes a serializer / deserializer (SerDes) 132, and the switch chiplet 133 includes a SerDes 134. These SerDes enable the data to be serialized to the optical channels, thereby increasing the overall data rate supported by each optical channel.

[0036] Electronic signals from the compute chiplet can be sent to the PIC using TX SerDes at data rates, for example, 56-64 Gbps NRZ or 112 Gbps PAM-4. A Physical Coding Sublayer (PCS) may also be used. The PCS enables bit scrambling and DC balancing that may be required by several TX components, such as a microring modulator. The SerDes may also include an analog front-end for equalization, including (but not limited to) feed-forward equalization (FFE) and continuous time linear equalization (CTLE) on the TX side (and decision feedback equalization (DFE) on the RX side). Equalization can invert the channel response to significantly reduce inter-symbol interference. The signal can be sent directly to a photonic TX modulator or further amplified (if the photonic transmitter element requires a higher voltage). On the RX side, the signal can then be received by RX SerDes.

[0037] If an electronic chiplet does not use SerDes to communicate with its corresponding PIC, it may use a broadly parallel interface for communication with the PIC, such as a wire bundle, Advanced Interface Bus (AIB), or Universal Chiplet Interconnect Express (UCIe). In some cases, these signals may be sent directly from the TX PIC to the RX PIC. Furthermore, in some protocols such as UCIe, the clock may be transferred from the TX component to the RX component by wavelength multiplexing the signal and clock within the same waveguide. However, in some embodiments, it may be desirable to construct a SerDes shim that serializes the broadly parallel signals (which may generally be slow) into a single signal corresponding to the electrical bandwidth of the photonic TX and photonic RX.

[0038] A glass via (TGV) 103 may be used to provide electrical access from the substrate 100 to the PIC. The TGV includes a conductor extending vertically through an interposer. A bottom redistribution layer (RDL) 104 provides electrical coupling between the TGV and the underlying substrate. An upper RDL 110 provides electrical coupling between the TGV and the PIC. Microbumps (not shown in Figure 2A) connect the upper RDL 110 to the bottom surface of the PIC 120. RDLs can redistribute input / output (I / O) connections in the PIC's native layout to a different layout to suit, for example, the requirements of the underlying substrate. This allows for more efficient signal routing between the PIC and the package. The PIC may include a silicon via (TSV) 126 for providing power and signals to a chip located on the PIC. The electrical connection section (for example, a Ball Grid Array (BGA) or Land Grid Array (LGA)) provides an electrical interface between the PIC and the electronic chip.

[0039] In some embodiments, the number of layers in the upper RDL and the bottom RDL are equal due to manufacturing constraints, such as glass warping. However, in other embodiments, the number of layers between the upper RDL and the bottom RDL are different. For example, the number of layers required in the upper RDL may be minimal because electrical routing already exists within the PIC120. In another example, if the pitch of the substrate 100 is already as fine / tight as the pitch of the glass through-vias 103, it may be desirable to eliminate the bottom RDL entirely.

[0040] The example in Figure 2B differs from the example in Figure 2A in that the PIC is located on the upper surface of the glass interposer (as opposed to being located in a recess). As a result, there is no alignment between the PIC waveguide and the glass waveguide. Instead, the PIC waveguide is coupled to the glass waveguide via the evanescent coupler 129.

[0041] Another useful optical coupling method, distinct from those shown in Figures 2A and 2B, is vertical coupling. In some embodiments, vertical coupling is achieved by using a lattice coupler. In other embodiments, vertical coupling is achieved by depositing microlenses and micromirrors within the PIC and the glass interposer. Both techniques are interchangeable, as long as they are designed to allow the optical modes to enable efficient, low-loss coupling. Importantly, different optical coupling methods can be used within a single system / package. For example, one waveguide may be coupled from the PIC to the glass interposer via edge coupling, while another waveguide may be coupled via evanescent coupling.

[0042] In some other embodiments, the light source may also be directly integrated into the glass interposer without the need for a PIC in between. The coupling of the light source to the glass interposer may use the same coupling methods as those used for coupling between the PIC and the glass interposer (evanescent coupling, edge coupling, vertical coupling). The advantage of this direct coupling is that the polarization of the output light can be retained within the glass (compared to the need to use polarization-retaining fibers). Furthermore, coupling to the waveguide means that the couplers can be packed more tightly than the standard 127 μm or 250 μm for optical fibers.

[0043] The example in Figure 2C differs from the example in Figure 2A in that the PIC is positioned between the substrate 100 and the glass interposer 102. The electronic chip is positioned on the top surface of the glass interposer 102. Optical coupling to and from the PIC is achieved via the evanescent coupler 129, although a solution is also possible in which the PIC is positioned inside a recess formed in the bottom surface of the interposer (similar to Figure 2A). In this example, the glass waveguide is located near the bottom surface of the interposer, in contrast to being near the top surface as in Figure 2A. From an operational standpoint, the package in Figure 2C operates in much the same way as the package in Figure 2A. The glass waveguide provides optical connectivity between the PICs. The TSV of the PIC and the TGV of the interposer provide electrical access to the electronic chip.

[0044] The example in Figure 2D differs from the example in Figure 2C in that both the PIC and the interposer have recesses (140). In this way, the bottom surface of the interposer sits on the recessed area on the top surface of the PIC. This arrangement facilitates evanescent coupling in that the PIC waveguide and the glass waveguide can be brought close to each other.

[0045] The packages shown in Figures 2A to 2D can be manufactured by chip-on-wafer bonding, such as thermocompression bonding. Such a packaging process can produce tolerances of a 1 μm regime that are suitable for microbump (e.g., copper bump) technology. In some embodiments, the same package can be manufactured with tighter tolerances using hybrid bonding. In this case, direct copper-to-copper connections are made without the use of bumps. Hybrid bonding allows for tighter tolerances, closer to a 0.1 μm regime. Tighter tolerances enable more efficient coupling and finer-pitch electrical connections. The package in Figure 2E shows a package manufactured by hybrid bonding, in which optical coupling between the PIC and the glass interposer is created by edge coupling. The finer pitch allows for direct mounting from TGV to PIC (without the need to use microbumps, as in contrast to the package in Figure 2A). Figure 2F shows another package manufactured by hybrid bonding, in which optical coupling is achieved by evanescent coupling. This technology enables wafer-to-wafer bonding (and chip-to-wafer bonding), allowing the chip to be bonded onto the PIC120 before it is packaged with the glass interposer. As shown in Figure 2E, finer pitches can enable direct mounting from the TGV to the PIC. Although the packages in Figures 2E–2F are shown with only one PIC bonded, the illustrated glass interposer may support multiple PICs, as in the arrangements shown in Figures 2A–2D.

[0046] In some embodiments, the PIC120 may be attached to the glass interposer 102 by glass welding, but other techniques are also possible. Nano-welding or micro-welding of glass allows the glass to be attached to other glass, metal, silicon, or other materials. The welding may be performed using laser welding, in which a high-power ultrashort pulse laser is directed to the area to be welded. In some embodiments, the PIC120 may be welded at a location away from or around the available photonic elements. The welding location can allow for precise alignment of the PIC120 with respect to the glass interposer 102.

[0047] Figures 3A, 3B, and 3C provide examples of photonic systems that can be obtained using the photonic interposer described herein. In these examples, the glass has an interposer that can be considered to have four quadrants, although other arrangements are possible. These photonic systems may be arranged according to any of the cross-sections shown in Figures 2A to 2D, as well as other cross-sections not shown herein.

[0048] As can be seen from these examples, the glass interposers described herein enable photonic systems that combine PICs with different layouts. This is in contrast to some conventional reticle-stitched active photonic interposers where all tiles share the same layout. As a result, greater flexibility is achieved from a system architecture perspective. In the example in Figure 3A, the glass interposer 102 hosts three different types of PICs (one PIC1, two PIC2s, and one PIC3). PIC1 hosts one compute chiplet 131 and two memory chiplets 130. PIC2 each hosts one compute chiplet 131. PIC3 hosts four memory chiplets 130. To give different PIC types the ability to connect to different chiplet arrangements, the patterned optical networks within different PIC types may be different from one another. This means that PICs can be obtained from different wafers.

[0049] The system allows electronic signals from each of the compute / switch / memory chiplets to be communicated and transmitted photonically to another compute / switch / memory chiplet in a different glass reticle. In some embodiments, different PICs may be fabricated using different processes (such as not using the same mask set). For example, PIC1 may be a silicon photonic PIC, PIC2 may be a silicon nitride PIC, while PIC3 may be a PIC fabricated using a III-V process (e.g., indium phosphide (InP)). In another embodiment, the size of PIC1-3 may be larger than a single reticle, and a multi-reticle waveguide crossing may be used to connect the photonic elements between two adjacent reticles. It is also possible to fabricate all PICs placed within the multi-reticle glass system using the same mask set. The step of creating the system allows only known good PIC dies to be packaged in the system.

[0050] In some embodiments, the PIC is fabricated using a process involving optical amplification, such as a semiconductor optical amplifier (SOA). The PIC may be fabricated in a silicon photonics foundry, with subsequent deposition of III-V material, or the PIC may be fabricated directly in a III-V foundry. The SOA can amplify the optical signal passing through this glass tile to prevent any optical loss in the system. The SOA can also prevent expected optical loss for signals exiting the system through optical fiber channels where loss is expected, or for signals arriving in the system that must be amplified to the sensitivity of the optical RX component. The SOA can also be used to generate a laser as a light source for the system.

[0051] The system in Figure 3B differs from the system in Figure 3A in that the PIC3 includes four reticles 230 supporting the memory chiplets, in contrast to the system in Figure 3A which has a single reticle shared among all memory chiplets. Furthermore, this demonstrates that the type of glass interposer described herein allows the PIC to form various computer architectures.

[0052] Figure 3C shows yet another architecture based on the glass interposer. The northwest quadrant of the glass interposer hosts two PICs and a compute chiplet. The PICs are located on the electrical RDL. Each PIC may host additional chiplets, such as memory chiplets, compute chiplets, and / or switch chiplets, in the configurations shown in Figures 2A to 2D, for example. In particular, the compute chiplets are located on the electrical RDL. This means that communication with the compute chiplets takes place in the electrical domain via the electrical RDL. To enable this, the PICs can be flip-chip coupled to the upper RDL without having to rely on TSVs. In contrast, the compute chiplet located in the northeast quadrant is located on the PIC. This means that communication to and from the compute chiplet takes place in the optical domain. The configuration in the southwest quadrant is similar to the configuration in the northwest quadrant in that it includes a compute chiplet and PICs on the electrical RDL. The difference is that this quadrant includes eight PICs organized around the electrical RDL. Finally, the southeast quadrant includes a single PIC that extends across the entire reticle of the glass interposer. In this case, the PIC may be flip-chip bonded onto a metal layer on top of the glass. Since the metal layer within the PIC can function as an RDL itself, it may not be necessary to include an RDL layer.

[0053] In some embodiments, the reticle of the glass interposer may include an electronic chiplet without a PIC placed on it. Instead, the chiplet communicates with adjacent chiplets using the substrate 100.

[0054] As described above, using the type of glass interposer described herein improves upon conventional active photonic interposers because these glass interposers can significantly improve the system yield. This can be seen from the examples in Figures 4A and 4B. The example in Figure 4A shows a glass interposer with two PICs, each having a 2x2 reticle. As a result, the system contains a total of eight reticles. This system can be considered good if all reticles are free from critical defects that could otherwise compromise the integrity of the system. To achieve this, at least two 2x2 blocks must be identified on the wafer (as shown in Figure 1B). An equivalent architecture using a conventional active photonic interposer would require a 4x2 reticle block to achieve similar performance. Identifying one good 4x2 block on a wafer is generally less likely than identifying two good 2x2 blocks on the same wafer. This improves the overall yield.

[0055] In the example in Figure 4A, each reticle of each PIC hosts one compute chiplet and two memory chiplets. The PICs are reticle-stitched in such a way that one reticle of the PIC is optically coupled to an adjacent reticle of that PIC (e.g., via a reticle intersection 208). The glass interposer can also be reticle-stitched in such a way that one reticle of the interposer is optically coupled to an adjacent reticle of the interposer (e.g., via a glass tile intersection 108). In this example, one PIC is positioned corresponding to one reticle of the interposer, and the other PIC is positioned corresponding to another reticle of the interposer.

[0056] The example in Figure 4B differs from the example in Figure 4A in that, instead of having two 2x2 PICs, the glass interposer includes one PIC with a 2x2 reticle and one PIC with a 2x1 reticle. In some embodiments, the PICs may be obtained from different wafers (as shown in Figure 1C). As a result, the PICs may be patterned with different photonic network layouts. In this example, the first PIC includes compute chiplets and memory chiplets, while the second PIC includes a dedicated input / output (I / O) chiplet 220.

[0057] Figure 5A shows an example of how multiple glass interposers may be connected to create a large, high-performance computing cluster. Interconnection between glass interposers can be achieved using optical fibers (e.g., single-mode, polarization-retaining, or multimode fibers, or single-core or multi-core fibers) or free-space optical communication (e.g., a PIC can emit and receive light by using either a single or phased array grid coupler). In some embodiments, each glass interposer is identical to the others. In other embodiments, all (or at least some) of the glass interposers are independently positioned relative to the others. Furthermore, electronic switch / router chiplets can be used to redirect signals from one compute chiplet to the correct photonic TX / RX device.

[0058] Optionally, the glass interposer can incorporate the SOA within a single reticle or within a fiber connector assembly to withstand the expected losses from the PIC, glass waveguide, and optical fiber.

[0059] It is also important to note that a photonic signal arriving at a single PIC does not necessarily have to be detected there. The signal may be rerouted to another location on the interposer before being detected using the built-in optical flow switches in one or more PICs.

[0060] In some embodiments, the computing systems of the type described herein may be interconnected by an external optical flow switch (see Figure 5B). The optical flow switch may be fabricated using a micro-electromechanical system (MEMS), a MEMS mirror, a piezoelectric-controlled photonic integrated circuit having a spatial waveguide switch (e.g., a Mach-Zehnder interferometer (MZI)) and / or a wavelength switch (e.g., a resonator-based switch), and a robotic arm for inserting and removing optical fiber cables. In some embodiments, the optical flow switch is fabricated using a multi-reticle PIC that creates a switch having a butterfly topology, Clos topology, hypercube topology, Benes topology, Cantor topology, tree-based topology, or hypertroid topology. In some embodiments, the optical flow switch detects light arriving at the flow switch, performs electronic switching within an electronic switching device, and regenerates a new set of signals based on the detected light to be emitted from the switch. The optical flow switch may be combined with the architecture shown in Figure 5A, in which some connections are made directly between interposers and some connections are mediated by the optical flow switch. The external optical flow switch may also include an SOA to compensate for the losses of the optical flow switch. The switch may also further include a laser light source and wavelength multiplexing / demultiplexing (MUX / DEMUX) functions.

[0061] In some embodiments, the flow switch device may be connected to one or more other flow switches so that a photonic signal originating from one interposer can be rerouted multiple times by multiple optical flow switches before being received by another interposer. This arrangement is shown in Figure 6.

[0062] In some embodiments, the wafer-level package stacked die can be directly bonded to glass. Simultaneously, the electrical connections can be deployed on the back surface using organic or inorganic RDL. An example of this arrangement is shown in Figure 7. In this example, the TGV(103) and RDL(700) can be processed before the die stack (PIC combined with the electronic chiplet) is mounted on the interposer. In this case, instead of bonding the front surfaces of the PIC and the electronic chiplet together, bonding between the front and back surfaces can be performed. As a result, the photonics are inverted. An I / O connector 704 and a voltage regulator (VR) module 706 are located on the bottom surface of the package. The I / O connector 704 supplies signals from the bottom surface of the package. Similarly, the VR module 706 supplies regulated power from the bottom surface of the package.

[0063] In some embodiments, a bundle of connectors passing through an opening formed on the glass interposer may be used instead of the TGV. This alternative arrangement is shown in Figures 8A and 8B. As shown, the opening 800 is defined penetrating the glass interposer. The opening is large enough to allow several connectors (e.g., copper pillars) to pass through it. The connectors electrically couple the bottom RDL to the PIC. Figure 8B shows a cross-section of a glass interposer having such an opening 800. This arrangement has the advantage of being on a relatively flat panel and allowing die bonding to be performed early in the assembly process.

[0064] The arrangement in Figure 9 also relies on an opening that penetrates the glass interposer. However, in this case, the flip-chip substrate 902 is inserted directly into the opening, thereby providing a direct electrical connection to the PIC. The flip-chip substrate 902 may be supported by a larger substrate 900.

[0065] In the arrangement of Figure 10, a glass photonic chiplet 1000 is used instead of the type of glass interposer described herein. The glass chiplet 1000 includes a glass waveguide that provides an optical bridge between adjacent PICs. The coupling between the PIC waveguide and the glass waveguide can be performed evanescently, as shown in the example of Figure 10. The glass chiplet 1000 may share the same characteristics as described above in relation to the glass interposer 102, including its configuration, but may be smaller.

[0066] In the arrangement shown in Figure 11, the PICs of the type described above can be placed on either side of the glass interposer. The advantage is that the overall bandwidth coming out of the package can be significantly increased (e.g., doubled). RDLs can be used to connect to the PICs in the manner described above. Fiber connectors provide access to the PICs on both sides of the interposer. Furthermore, in some embodiments, multiple levels of glass waveguides can be provided, thereby increasing the package's ability to route signals. This can be achieved by fusion splicing, as shown in the example in Figure 12. In this case, two glass panels (1200, 2200) are fused to each other (see fusion splice 2300). Each panel may contain a layer of glass waveguides. The waveguides of the upper panel can be coupled (e.g., evanescently) to the waveguides in the PICs on the top surface of the package. The waveguides of the bottom panel can be coupled (e.g., evanescently) to the waveguides in the PICs on the bottom surface of the package.

[0067] In further embodiments, the glass interposer may include passive optical circuits such as wavelength multiplexers and demultiplexers. These can be manufactured via an array waveguide grid within the interposer or via resonant devices such as optical rings or racetracks. The glass interposer can also expand narrower pitch (<10 μm) waveguides with smaller modes within the PIC to larger pitch (127 μm or 250 μm) waveguides with larger modes that can be adapted to fiber connectors at the edges. Furthermore, the waveguides within the glass interposer can be programmed in a 3D manner so that some waveguides can remain at the same vertical height, while others can move up and down at different vertical heights. This allows adaptation to multi-fiber optical connectors that may have multiple fiber rows at different heights. Additionally, some optical connectors may have pins that help align the fiber with the glass waveguide. Precise holes for these pins can also be manufactured within the glass interposer. In this case, the optical connector functions as the male connector, while the glass interposer functions as the female connector.

[0068] In some embodiments, glass pins can be precisely welded onto the surface of a glass interposer to enable the glass to be used as a male connector. Two glass interposers can be connected to each other, with one having a male connector and the other having a female connector. Optical coupling between one glass interposer and the other can be enabled via the same waveguide that enables coupling between the glass interposer and the optical fiber connector.

[0069] While several aspects and embodiments of the technology described herein have been described, it should be understood that various changes, modifications, and improvements will be readily conceivable to those skilled in the art. Such changes, modifications, and improvements are intended to fall within the spirit and scope of the technology described herein. Accordingly, it should be understood that the embodiments described herein are presented only as examples, and embodiments of the present invention may be practiced in ways different from those specifically described, within the scope of the appended claims and their equivalents. In addition, any combination of two or more features, systems, articles, materials, and / or methods described herein is included within the scope of this disclosure, provided that such features, systems, articles, materials, and / or methods are not contradictory to each other.

[0070] Furthermore, as described, several embodiments may be embodied in one or more methods. The operations performed as part of the method may be ordered in any suitable manner. Thus, embodiments may be constructed in which the operations are performed in an order different from the order described, and may include performing several operations simultaneously, even if they are shown as sequential operations in the exemplary embodiments.

[0071] All definitions defined and used herein should be understood to take precedence over dictionary definitions, definitions in documents incorporated by reference, and / or the ordinary meanings of the terms defined.

[0072] As used herein and in the claims, the indefinite articles "a" and "an" should be understood to mean "at least one" unless explicitly indicated otherwise. As used herein and in the claims, the phrase “and / or” should be understood to mean “either or both” of the elements thus connected, i.e., elements that exist conjugately in some cases and disjunctly in others.

[0073] As used herein and in the claims, the phrase “at least one” referring to a list of one or more elements means at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of every element specifically enumerated in the list of elements, nor excluding any combination of elements in the list of elements. This definition also allows for the presence of elements other than those specifically identified in the list of elements referred to by the phrase “at least one,” whether related to the specifically identified elements or not, at the discretion of the definition.

[0074] The terms "approximately" and "about" may be used in some embodiments to mean within ±20% of the target value, within ±10% of the target value, within ±5% of the target value, and within ±2% of the target value. The terms "approximately" and "about" may include the target value.

Claims

1. A glass interposer including an optical network having one or more glass waveguides, A plurality of photonic integrated circuits (PICs) attached to the glass interposer, wherein at least one of the plurality of PICs includes an optical transceiver optically coupled to the optical network of the glass interposer and a plurality of electrical connections configured to be coupled to one or more electronic chips, A photonic device equipped with the following features.

2. The photonic device according to claim 1, wherein the glass interposer further comprises through-glass vias (TGVs), and the at least one PIC further comprises through-silicon vias (TSVs) electrically coupled to the TGVs.

3. The glass interposer further includes a first redistribution layer (RDL) adjacent to the first surface of the glass interposer, and a second RDL adjacent to the second surface of the glass interposer opposite to the first surface. The first RDL is configured to be connected to at least one PIC, and the second RDL is configured to be connected to a circuit board. The photonic device according to claim 2.

4. The at least one PIC is mounted on the glass interposer on the first surface of the PIC, The electrical connection portion is formed on the second surface of the PIC opposite to the first surface. The photonic device according to claim 1.

5. The glass interposer defines a recess, and the first surface of the PIC is positioned within the recess. The optical transceiver of at least one PIC is edge-coupled to the optical network of the glass interposer. The photonic device according to claim 4.

6. The glass interposer defines a recess, and the first surface of the PIC is suspended on the recess. The optical transceiver of at least one PIC is evanescently coupled to the optical network of the glass interposer. The photonic device according to claim 4.

7. Multiple photonic integrated circuits (PICs), A multi-reticle glass interposer that enables optical communication between the aforementioned PICs, A system equipped with these features.

8. The system according to claim 7, wherein at least one of the PICs is a multi-reticle PIC.

9. The system according to claim 8, further comprising a plurality of integrated circuit chips, each chip located on a different reticle of the PIC.

10. The system according to claim 7, wherein the glass interposer includes a glass waveguide for connecting the PICs.

11. The system according to claim 7, wherein the glass interposer further includes glass through vias coupled to silicon through vias formed in the PIC.

12. The system according to claim 7, wherein each of the plurality of PICs is obtained from a common wafer.

13. The system according to claim 7, wherein the plurality of PICs are obtained from two or more wafers.

14. The system according to claim 7, wherein each PIC is coupled to the glass interposer via an evanescent coupling.

15. The system according to claim 7, wherein the PIC includes an active photonic circuit, and the glass interposer lacks an active photonic circuit.

16. A glass interposer including an optical network having one or more glass waveguides, A plurality of photonic integrated circuits (PICs) attached to the glass interposer, each including an optical transceiver optically coupled to the optical network of the glass interposer, A plurality of electronic chiplets, wherein the plurality of PICs are arranged on the plurality of PICs such that the plurality of PICs are arranged between the plurality of electronic chiplets and the glass interposer, A computing system equipped with [the following features].

17. The computing system according to claim 16, wherein the glass interposer further comprises through-glass vias (TGVs), and the PIC further comprises through-silicon vias (TSVs) electrically coupled to the TGVs.

18. The computing system according to claim 16, wherein the plurality of PICs are obtained from two or more wafers.

19. The glass interposer defines a recess, and at least one of the plurality of PICs is disposed within the recess. The optical transceiver of at least one PIC is edge-coupled to the optical network of the glass interposer. The computing system according to claim 16.

20. Further including a voltage regulator (VR) module, The glass interposer is positioned between the PIC and the VR module. The computing system according to claim 16.

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