Logical-Physical Table-Based Memory Device Fragmentation Analysis

Abstract

This disclosure relates to fragmentation evaluation in a memory system. For example, a method for operating a memory controller includes the step of receiving a request from a host regarding the fragmentation level of a file stored in a memory device. The method further includes the step of determining the read performance level of a file based on a logical-to-physical (L2P) address mapping table corresponding to the file, without reading the file from the memory device. The method further includes the step of determining the fragmentation level based on the read performance level.

Description

Technical Field

[0001] This disclosure generally relates to memory devices and memory systems, and more particularly to systems and methods for defragmenting memory devices.

Background Art

[0002] Data stored in a memory device may become fragmented over time. Fragmentation can potentially slow down the performance of the memory device by reducing its access and processing speeds. In some implementations, fragmentation can further cause unwanted corruption and data loss in the memory device. Defragmentation is a process that reduces the degree of fragmentation by reorganizing the data of the memory device for faster access and better system performance.

Summary of the Invention

Means for Solving the Problems

[0003] This disclosure relates to fragmentation evaluation in a memory system. In one example, a method for operating a memory controller includes receiving, from a host, a request regarding the fragmentation level of a file stored in a memory device. The method further includes determining a read performance level of the file based on a logical-to-physical (L2P) address mapping table corresponding to the file without reading the file from the memory device. The method further includes determining the fragmentation level based on the read performance level.

[0004] While generally described as computer implementation software embodied on a tangible medium that processes and transforms each piece of data, some or all of the embodiments may further be computer implementation methods or each system or other device for carrying out the functionality described herein. Details of these and other embodiments and implementations of the disclosure are described in the accompanying drawings and the following description. Other features, purposes, and advantages of the disclosure will become apparent from the description and drawings, as well as from the claims. [Brief explanation of the drawing]

[0005] [Figure 1] This is a block diagram of an exemplary system having a memory device according to some aspects of the present disclosure. [Figure 2A] This figure shows exemplary storage products according to several aspects of this disclosure. [Figure 2B] This figure shows exemplary storage products according to several aspects of this disclosure. [Figure 3] This is a schematic circuit diagram of an exemplary memory device including peripheral circuits according to some aspects of the present disclosure. [Figure 4] This is a block diagram of an exemplary system including a memory device, a memory controller, and a host, according to some aspects of the present disclosure. [Figure 5A] This figure shows exemplary logical and physical addresses of a file according to several aspects of this disclosure. [Figure 5B] This figure shows exemplary logical and physical addresses of a file according to several aspects of this disclosure. [Figure 5C] This figure shows exemplary logical and physical addresses of a file according to several aspects of this disclosure. [Figure 6] This is a flowchart illustrating exemplary methods for fragmentation evaluation according to some aspects of the present disclosure. [Figure 7] This figure shows exemplary read performance curves for several aspects of the present disclosure. [Modes for carrying out the invention]

[0006] Similar reference numbers and names in various drawings refer to the same elements.

[0007] The defragmentation process can reorganize fragmented files to store data from several files located in adjacent or even contiguous physical locations within a memory device. For example, the Universal Flash Storage (UFS) protocol provides a file-based optimization (FBO) feature. The FBO feature allows the host and the flash memory device (e.g., a NAND device) to cooperate during the defragmentation process. The host can first assess how fragmented the files in the flash memory device are by querying the fragmentation level (also called the degree of fragmentation) of the files from the flash memory device. After the host knows the fragmentation level of the files, it can decide whether to perform defragmentation of the files based on the fragmentation level. If so, the host can instruct the flash memory device to defragment the files in order to improve file access performance.

[0008] The level of file fragmentation can be measured or evaluated in various ways. For example, a controller could read a file from a flash memory device to determine how the file is scattered across various locations on the flash memory device. This may not be an efficient method, as it occupies resources and even processing power on both the flash memory device and the host. Furthermore, frequent memory read operations can degrade the reliability of the flash memory device due to read disturbance. Another fragmentation evaluation method involves estimating the performance of the flash memory device based on the real-time distribution of data between the physical addresses of the flash memory device. This method may require sophisticated algorithms and is therefore difficult to implement when the real-time distribution of data is complex. Thus, an efficient and practical fragmentation evaluation technique is desired.

[0009] This disclosure provides a fragmentation evaluation technique based on a logical-to-physical (L2P) address mapping table (also known as an L2P table or L2P mapping table). In some implementations, a controller may receive a request from a host for the fragmentation level of a file stored in a memory device. The controller may determine the read performance level of a file based on the L2P address mapping table corresponding to the file, without reading the file from the memory device. The controller may then determine the fragmentation level based on the read performance level and return the fragmentation level to the host.

[0010] The techniques described in this disclosure may be implemented to achieve one or more of the following advantages: Firstly, compared to some existing methods, the proposed fragmentation evaluation technique avoids reading actual file data from physical addresses and is therefore more efficient and consumes fewer resources. Secondly, the proposed fragmentation evaluation technique may not degrade the reliability of the memory device. Thirdly, the proposed fragmentation evaluation technique may provide more accurate results because it takes into account the distribution of files across various planes of the memory device.

[0011] The above-mentioned aspects of this disclosure and several other aspects will be discussed in more detail below.

[0012] Figure 1 shows a block diagram of an exemplary system 100 having a memory device according to some aspects of the present disclosure. System 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As shown in Figure 1, system 100 may include a host 108 having a host memory 110 and a host processor 112, and a memory system 102 having one or more memory devices 104 and a memory controller 106.

[0013] The host 108 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 108 may be coupled to a memory controller 106 and configured to send or receive data to and from the memory device 104 through the memory controller 106. For example, the host 108 may send program data in a program operation or receive read data in a read operation. The host processor 112 may be a control unit (CU) or an arithmetic and logic unit (ALU). The host memory 110 may be a memory unit including registers or cache memory. The host 108 is configured to receive and send instructions and commands to and from the memory controller 106 of the memory system 102, and to perform or implement some of the functions and operations provided in this disclosure, which are described later.

[0014] The memory device 104 may be any of the memory devices disclosed in this disclosure, such as a NAND flash memory device. Note that NAND flash is merely an example of a memory device for illustrative purposes. It may also include any suitable solid-state, non-volatile memory, such as NOR flash, ferroelectric RAM (FeRAM), phase-change memory (PCM), magnetoresistive random-access memory (MRAM), spin-transfer torque magnetic random-access memory (STT-RAM), or resistive random-access memory (RRAM). In some implementations, the memory device 104 includes a three-dimensional (3D) NAND flash memory device.

[0015] As shown in Figure 1, the memory device 104 may include one or more dies 114. A die 114 may also be called a memory cell array and may include a plurality of planes 116. Each plane 116 may include a plurality of physical blocks 118.

[0016] The memory controller 106 may be implemented by a microprocessor, microcontroller (also known as a microcontroller unit: MCU), digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), programmable logic device (PLD), state machine, gate logic, discrete hardware circuitry, and other appropriate hardware, firmware, and / or software, configured to perform various functions as described below.

[0017] The memory controller 106, according to several implementations, is coupled to the memory device 104 and the host 108 and configured to control the memory device 104. The memory controller 106 can manage the data stored in the memory device 104 and communicate with the host 108. In some implementations, the memory controller 106 is designed to operate in low duty cycle environments for use in electronic devices such as personal computers, digital cameras, and mobile phones, acting like a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media. In some implementations, the memory controller 106 is designed to operate in high duty cycle environments a solid state drive (SSD) or embedded multimedia card (eMMC) used as data storage for mobile devices such as smartphones, tablets, and laptop computers, or as an enterprise storage array. The memory controller 106 can be configured to control the operation of the memory device 104, such as reading, erasing, and programming, by issuing instructions to the memory device 104, such as read instructions. For example, the memory controller 106 may be configured to issue read instructions to the peripheral circuits of the memory device 104 in order to control read operations. The memory controller 106 can also be configured to manage various functions related to data stored in or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address conversion, and wear leveling.In some implementations, the memory controller 106 is further configured to process an error correction code (ECC) for data read from or written to the memory device 104. Any other suitable functions, such as formatting the memory device 104, may also be performed by the memory controller 106.

[0018] The memory controller 106 can communicate with an external device (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with an external device through at least one of various interface protocols, such as the USB protocol, the MMC protocol, the peripheral component interconnection (PCI) protocol, the PCI express (PCI-E) protocol, the advanced technology attachment (ATA) protocol, the serial ATA protocol, the parallel ATA protocol, the small computer small interface (SCSI) protocol, the enhanced small disk interface (ESDI) protocol, the integrated drive electronics (IDE) protocol, the FireWire protocol, etc. The memory controller 106 is configured to receive and transmit commands to and from the host 108 and to execute or perform a plurality of functions and operations provided in this disclosure, which will be described later.

[0019] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices contained in the same package, such as a Universal Flash Storage (UFS) package or an eMMC package. In other words, the memory system 102 can be implemented and packaged in different types of end electronic products. In one example shown in Figure 2A, the memory controller 106 and a single memory device 104 can be integrated into a memory card 202. The memory card 202 may include PC cards (Personal Computer Memory Card International Association: PCMCIA), CF cards, SmartMedia (SM) cards, Memory Sticks, Multimedia Cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may further include a memory card connector 204 that connects the memory card 202 to a host (for example, the host 108 in Figure 1). In another example shown in Figure 2B, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may further include an SSD connector 208 that connects the SSD 206 to a host (for example, the host 108 in Figure 1). In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than that of the memory card 202.

[0020] Figure 3 shows a schematic circuit diagram of an exemplary memory device 300 including peripheral circuits according to several aspects of the present disclosure. The memory device 300 may be an example of the memory device 104 in Figure 1. Note that the NAND flash disclosed herein is merely an example of a memory device for illustrative purposes. This may also include any suitable solid-state, non-volatile memory, such as NOR flash, FeRAM, PCM, MRAM, STT-RAM, or RRAM. The memory device 300 may include a die or memory cell array 114 and peripheral circuits 302 coupled to the memory cell array 114. The memory cell array 114 may be a NAND flash memory cell array in which memory cells 306 are provided therein in the form of an array of NAND memory strings 308, each extending vertically upwards on a substrate (not shown). In some implementations, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, such as voltage or charge, which depends on the number of electrons trapped within the region of the memory cell 306. Each memory cell 306 may be either a floating-gate type memory cell including a floating-gate transistor or a charge-trap type memory cell including a charge-trap transistor.

[0021] In some implementations, each memory cell 306 is a single-level cell (SLC) that has two possible memory states and can thus store one bit of data. For example, a first memory state "0" can correspond to a first range of voltages, and a second memory state "1" can correspond to a second range of voltages. In some implementations, each memory cell 306 is a multi-level cell (MLC) that can store more than a single bit of data in more than four memory states. For example, an MLC can store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to assume a certain range of possible nominal storage values. In one example, when each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programming levels from an erased state by writing one of three possible nominal storage values to the cell. A fourth nominal storage value can be used for the erased state.

[0022] As shown in Figure 3, each NAND memory string 308 may include a source select gate (SSG) transistor 310 at its source end and a drain select gate (DSG) transistor 312 at its drain end. The SSG transistor 310 and DSG transistor 312 can be configured to activate the selected NAND memory string 308 (a column of the array) during read and program operations. In some implementations, the sources of NAND memory strings 308 in the same physical block 118 are coupled through the same source line (SL) 314, for example, a common SL. In other words, NAND memory strings 308 in the same physical block 118 have an array common source (ACS), according to some implementations. The drain of the DSG transistor 312 of each NAND memory string 308 is coupled, according to some implementations, to a respective bit line 316 from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., above the threshold voltage of the DSG transistor 312) or a deselection voltage (e.g., 0V) to the gate of each DSG transistor 312 through one or more DSG lines 313, and / or by applying a selection voltage (e.g., above the threshold voltage of the SSG transistor 310) or a deselection voltage (e.g., 0V) to the gate of each SSG transistor 310 through one or more SSG lines 315.

[0023] As shown in Figure 3, the NAND memory string 308 can be organized into multiple physical blocks 118, each of which may have a common source line 314 coupled to, for example, ACS. In some implementations, each physical block 118 is the basic data unit for erase operations, i.e., memory cells 306 on the same physical block 118 are erased simultaneously. To erase the memory cells 306 in a selected physical block 118, the source lines 314 coupled to the selected physical block 118 and to the unselected physical blocks 118 on the same plane as the selected physical block 118 can be biased with an erase voltage (Vers), such as a high positive voltage (e.g., 20V or higher). Memory cells 306 in adjacent NAND memory strings 308 can be coupled through word lines 318 that select which rows of memory cells 306 are affected by read and program operations. Peripheral circuits 302 can be coupled to the memory cell array 114 through bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313. The peripheral circuitry 302 may include any suitable analog, digital, and mixed-signal circuits to facilitate the operation of the memory cell array 114 by applying voltage signals and / or current signals to each target memory cell 306 through bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313, and sensing therefrom. The peripheral circuitry 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology.

[0024] Figure 4 shows a block diagram of an exemplary system 400, including a memory device 104, a memory controller 106, and a host 108, according to some aspects of the present disclosure. In some implementations, the memory device 104 may be a NAND device. As shown in Figure 4, the host 108 may include host memory 110 and a host processor 112. The host memory 110 may store logical addresses, for example, the logical block address (LBA) of a file (for example, file 404), and the index node 406 of the file (for example, an i-node). The host processor 112 may include or be coupled to an index node update module 408 (for example, an i-node update module). The index node update module 408 is configured to update the index node 406 of a file. Note that the index node (for example, an i-node) may be a data structure in a Unix-style filesystem that describes a filesystem object such as a file or directory. The node may be a file data structure that stores information about any Linux® file, except for its name and data. The node stores file metadata, including file size, the device on which the file is stored, the user and group IDs associated with the file, or the permissions required to access the file.

[0025] As shown in Figure 4, the memory controller 106 may include a controller processor 410, such as a memory chip controller (MCC) or a memory controller unit (MCU). The controller processor 410 is configured to control modules to execute commands or instructions for performing the functions disclosed herein. The controller processor 410 may be configured to control the operation of each peripheral circuit by generating and sending various control signals, such as read commands for read operations. The controller processor 410 may also send clock signals at desired frequencies, durations, and duty cycles to other peripheral circuits 302 to coordinate the operation of each peripheral circuit 302, for example, to synchronize it.

[0026] The memory controller 106 may further include at least one of the volatile controller memory 412 and the non-volatile controller memory 414. In some implementations, the memory controller 106 may include both the volatile controller memory 412 and the non-volatile controller memory 414. In some implementations, the memory controller 106 may include either the volatile controller memory 412 or the non-volatile controller memory 414. The volatile controller memory 412 may include registers or cache memory that enable faster access and process speeds for reading, writing, or erasing data stored therein, but may not retain the stored information after the power supply is removed. In some implementations, the volatile controller memory 412 may include either dynamic random-access memory (DRAM) or static random-access memory (SRAM). The non-volatile controller memory 414 may retain the stored information even after the power supply is removed. In some implementations, the non-volatile controller memory 414 includes NAND, NOR, FeRAM, PCM, MRAM, STT-RAM, or RRAM. In some implementations, the non-volatile controller memory 414 may not be located within the memory controller 106. For example, the non-volatile controller memory 414 may be located outside the memory controller 106 but coupled to it.

[0027] As shown in Figure 4, the memory controller 106 may include a memory controller interface 416 configured to receive and send commands or instructions to and from the host 108. In some implementations, the memory controller interface 416 is coupled to a controller processor 410 and configured to receive and send commands or instructions causing the controller processor 410 to perform the functions disclosed herein.

[0028] The L2P address mapping table may be stored in various locations within the system 400. The L2P address mapping table 418 may be stored in non-volatile memory such as memory device 104 (e.g., a NAND device) and non-volatile controller memory 414. In this way, the address mapping data in the L2P address mapping table 418 is not erased after power-off. In some implementations, the L2P address mapping table is stored and processed in volatile memory such as volatile controller memory 412. In some implementations, after the system starts up or restarts, the L2P address mapping table may be periodically loaded from memory device 104 or non-volatile controller memory 414 and stored in volatile controller memory 412 for faster access and processing speed. In some implementations, the L2P address mapping table 418 may contain address mapping data corresponding to file 404 in host memory 110.

[0029] The memory controller 106 may include an address mapping table update module (not shown in Figure 4) configured to generate and update the L2P address mapping table 418. The address mapping table update module may be implemented by a firmware program in the firmware of the controller processor 410. In some implementations, the address mapping table update module may reside in the controller processor 410 or be coupled to the controller processor 410 and controlled by the controller processor 410 to execute commands and instructions from the host 108. For example, the address mapping table update module may be configured to execute mapping update commands received from the host 108 and update the L2P address mapping table 418 accordingly.

[0030] Figures 5A to 5C show exemplary logical and physical addresses of file 500 in some aspects of the present disclosure. File 500 is an example of file 404 in Figure 4. As shown in Figure 5A, the inode 502 of file 500 may include a list of LBA segments 504, 506, 508, and 510. Each of the LBA segments 504, 506, 508, and 510 contains one or more consecutive LBAs. The LBA segments 504, 506, 508, and 510 in Figure 5A are for illustrative purposes only, and it should be noted that in a real implementation, the LBA segments may contain more LBAs than the LBA segments in Figure 5A. The data of file 500 is stored at the physical addresses of the memory device. Figure 5B shows an exemplary L2P address mapping table 520, where the logical addresses of file 500 are mapped to the physical addresses of file 500 in the memory device. The L2P address mapping table 520 may be an example of the L2P address mapping table 418 in Figure 4. When the controller reads file 500, the controller first determines the physical address based on the L2P address mapping table 520, and then reads the data from that physical address. As shown in Figure 5B, each LBA in file 500 is mapped to a physical block address (PBA). Even though the L2P address mapping table 520 indicates that file 500 is stored in the PBA indicated by the L2P address mapping table 520, please note that the index number of the PBA for file 500 is for illustrative purposes only and may differ from the PBA in the memory device in a real-world implementation. Figure 5C shows an example where the physical addresses of file 500 are scattered across various planes in two dies 530 and 532 of a memory device. In this example, each of the two dies has four planes. Die 530 includes planes 534, 536, 538, and 540, and die 532 includes planes 542, 544, 546, and 548. The PBA of file 500 is placed on the eight planes of the memory device.

[0031] Figure 6 is a flowchart of an exemplary method 600 for fragmentation evaluation according to several aspects of the present disclosure. Method 600 may be performed by a memory controller (for example, memory controller 106 in Figure 1). The operations shown in Method 600 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some of the operations may be performed simultaneously or in a different order than shown in Figure 6. In some implementations, Method 600 may be performed by a firmware program of a controller processor in the memory controller (for example, controller processor 410 in Figure 4). Programming instructions may be stored in a computer storage medium and executed by the controller processor to perform the operations shown in Method 600. In some implementations, the programming instructions may be stored in volatile memory (such as SRAM). In some implementations, the programming instructions may be stored in non-volatile memory (such as memory device 104 or non-volatile controller memory 414) so ​​as not to be erased after the memory controller is powered off. Programming instructions may be loaded into high-speed memory such as tightly coupled memory (TCM) or volatile memory (for example, volatile controller memory 412 in Figure 4) and executed by the controller processor when the memory controller is activated.

[0032] In 602, the memory controller receives a request from the host. The request may query the fragmentation level of a file stored in the memory device. The request may include the logical address of the file. For example, the request may indicate an inode, which includes one or more LBAs of the file (e.g., LBA1-7, 10, 12-13, and 17-22 in Figure 5B). In some implementations, the request is an FBO request under the UFS 4.0 technical standard.

[0033] In 604, the memory controller reads the L2P address mapping table associated with the file. In some implementations, the memory controller may load the L2P address mapping table from volatile controller memory (e.g., volatile controller memory 412 in Figure 4) or non-volatile controller memory (e.g., non-volatile controller memory 414 in Figure 4). The L2P address mapping table in volatile or non-volatile controller memory may be loaded from a memory device (e.g., memory device 104 in Figure 1).

[0034] In 606, the memory controller determines the average contiguous physical address length of a file. The memory controller may first determine the physical address of a file based on the file's logical address and L2P address mapping table. The physical address of a file can be divided into one or more physical address segments, each physical address segment containing one or more contiguous physical addresses. In some implementations, each physical address is a PBA of a predetermined size (e.g., 4K bytes). In some implementations, the average contiguous physical address length may be determined based on the amount of one or more physical address segments and how many contiguous physical addresses each physical address segment contains.

[0035] For example, a file contains four physical address segments. The first physical address segment has two consecutive PBAs. The second physical address segment has four consecutive PBAs. The third physical address segment has six consecutive PBAs. The fourth physical address segment has eight consecutive PBAs. Therefore, this file has an average of five consecutive PBAs (i.e., the sum of 2, 4, 6, and 8 divided by 4 is 5). In this example, the size of the PBAs is 4 kilobytes (KB). Therefore, the memory controller can determine that the average consecutive physical address length of the file is 20 KB.

[0036] In some implementations, the average contiguous physical address length of a file can be determined using the following algorithm implemented by the memory controller.

[0037] Step 1: Set the initial value of the PBA continuous segment counter to 1. Determine the first LBA of the file based on the file's index node. Determine the PBA mapped to the first LBA based on the file's L2P address mapping table. Set the PBA mapped to the first LBA as the current PBA.

[0038] Step 2: Determine the next LBA in the file and the next PBA mapped to the next LBA. Check if the next PBA is the successor physical address to the current PBA. If it is the successor physical address, leave the PBA contiguous segment counter unchanged (because the contiguous PBA segment is not broken) and update the current PBA to the next PBA. If it is not the successor physical address, increment the PBA contiguous segment counter by 1 (because the contiguous PBA segment is broken) and update the current PBA to the next PBA.

[0039] Step 3: Repeat Step 2 until the last LBA of the file is found. Determine the average contiguous physical address length of the file by dividing the file length by the PBA contiguous segment counter.

[0040] In 608, the memory controller determines the read performance level based on the average contiguous physical address length and the read performance curve. The read performance curve may represent an estimate of the random read performance of the memory device for a given chunk size. In some implementations, the read performance curve is determined by performing random read tests or experiments on the memory device. In the random read experiment, files of various chunk sizes are located at random physical addresses on the memory device, and the read speed of the files is measured. The chunk size may be the proximity storage space occupied by each smallest unit of the file.

[0041] Figure 7 shows a diagram 700 illustrating exemplary read performance curves 702 according to several embodiments of the present disclosure. The horizontal axis of diagram 700 represents the random read chunk size measured in KB units. The vertical axis of diagram 700 represents the read performance measured in megabytes per second (MB / S). The read performance curve 702 is drawn by connecting data points 704. Each data point 704 is determined by performing a read performance test on the memory device. The read performance test may involve reading files of various chunk sizes and measuring the actual read speed. In some implementations, the read performance curve 702 is predetermined. Given an average continuous physical address length, the memory controller may determine the read performance level by finding a point on the read performance curve 702 where the random read chunk size (on the horizontal axis) is equal to the average continuous physical address length, and by determining the read performance at that point on the vertical axis.

[0042] Referring again to method 600 in Figure 6, at 610, the memory controller compares the average contiguous physical address length of the file to a threshold. For example, the threshold may be 16KB. If the average contiguous physical address length is greater than the threshold, method 600 proceeds to 612, where the memory controller returns the read performance level to the host as the file fragmentation level. If the average contiguous physical address length is less than or equal to the threshold, method 600 proceeds to 614.

[0043] In step 614, the memory controller determines the value based on the distribution of the file's physical addresses. In step 616, the memory controller adjusts the read performance level based on that value. In step 618, the memory controller returns the adjusted read performance level to the host as the file fragmentation level.

[0044] When a file is highly fragmented (i.e., has a small average contiguous physical address length), the distribution of the file across various planes of the memory device can also contribute to the file's fragmentation level. In this situation, a file whose physical addresses are relatively uniformly distributed across all planes of the memory device can be considered more fragmented. For example, Figure 5C shows that file 500 (called file A) is distributed across eight planes on two dies of a memory device. Suppose there is another file (called file B) similar to file 500, but with an average contiguous physical address length stored only on planes 534 and 536 of die 530, then file A and file B may have similar read performance levels based on their read performance curves. However, file B is more fragmented because it occupies fewer planes within the memory device. Therefore, when the average contiguous physical address length of a file is below a threshold, the memory controller can more accurately assess the file's fragmentation level by adjusting the read performance level using a value determined based on the distribution of the file's physical addresses.

[0045] In some implementations, the memory controller may use the following algorithms to adjust the read performance level.

[0046] Step 1: Determine the total number of planes (e.g., N) that store one piece of data in the file. Count how many physical addresses in the file are in each plane. P i This indicates the number of physical addresses of files in plane i (1 ≤ i ≤ N). In some implementations, a memory device contains multiple dies, each die containing multiple planes. In this case, it should be considered that all planes within the memory device may belong to different dies.

[0047] Step 2: Average physical address count

[0048]

number

[0049] Calculate.

[0050] Step 3: P i The standard deviation of (1 ≤ i ≤ N), i.e.

[0051]

number

[0052] Calculate.

[0053] Step 4: Value

[0054]

number

[0055] Based on this assessment, the adjusted read performance level was set to read performance level

[0056]

number

[0057] It is assumed that the division was performed by [a certain factor].

[0058] For example, Figure 5C shows that file 500 has PBAs distributed across eight planes. N=8. P1=2. P2=5. P3=1. P4=1. P5=3. P6=3. P7=0. P8=1.

[0059]

number

[0060] S = 1.5. The value for file 500 is 1.5625. The adjusted read performance level for file 500 can be determined by the read performance curve (e.g., read performance curve 702) and then divided by 1.5625.

[0061] Please understand that the algorithm described above for adjusting file read performance levels is merely an illustrative example. The memory controller may use any other appropriate method to adjust file read performance levels based on the distribution of the file's physical addresses.

[0062] In some implementations, the host receives a fragmentation level from the memory controller. If the host determines that the fragmentation level exceeds a fragmentation level threshold, it may send a command to the memory controller. The command instructs the memory controller to perform defragmentation. Method 600 may further include the memory controller receiving the command and performing defragmentation based on the received command.

[0063] This specification includes many specific implementation details, but these should not be interpreted as limiting the scope of what is claimed, but rather as descriptions of features that may be specific to a particular implementation. Some features described herein in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented separately or in any partial combination in multiple implementations. Furthermore, features described previously may be described as working in combination, and may even be initially claimed as such, but one or more features from the claims may, in some cases, be removed from that combination, and the claimed combination may be a partial combination or a variation of a partial combination.

[0064] As used in this disclosure, the words “a,” “an,” or “the” are used to include one or more unless the context explicitly indicates otherwise. The word “or” is used to refer to a non-exclusive “or” unless otherwise specified. The statement “at least one of A and B” is synonymous with “A, B, or A and B.” Furthermore, any expressions or terms used in this disclosure, unless otherwise defined, are for illustrative purposes only and not for limitation. Any use of section headings is intended to aid in the reading of the document and should not be construed as limiting, as information related to a section heading may be found within or outside that particular section.

[0065] To the extent used in this disclosure, the terms “about” or “near” may allow for a percentage change in a value or range of, for example, within 10%, 5%, or 1% of the stated value or the stated range limit.

[0066] As used in this disclosure, the term “substantially” means the majority or most, such as at least about 50%, 60%, 70%, 80%, 90%, 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99%, or at least about 99.999% or more.

[0067] Values ​​expressed in range form should be interpreted flexibly to include not only the numerical limits explicitly stated as the limits of the range, but also the individual numerical values ​​or subranges contained within that range, as if each numerical value and subrange were explicitly stated. For example, the range "0.1% to about 5%" or "0.1% to 5%" should be interpreted to include about 0.1% to about 5% and the individual values ​​within the indicated range (e.g., 1%, 2%, 3%, and 4%) as well as subranges (e.g., 0.1% to 0.5%, 1.1% to 2.2%, 3.3% to 4.4%). A statement "X to Y" is equivalent to "about X to about Y" unless otherwise specified. Similarly, a statement "X, Y, or Z" is equivalent to "about X, about Y, or about Z" unless otherwise specified.

[0068] This document describes specific implementations of the subject matter. Other implementations, modifications, and rearrangements of the described implementations are within the scope of the appended claims, as will be apparent to those skilled in the art. While the operations are shown in a particular order in the drawings or claims, such operations do not necessarily need to be performed in the particular illustrated order or sequentially, nor do they need to be performed all shown operations to achieve a desired result (some operations may be considered optional). In some situations, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be advantageous and may be implemented as appropriate.

[0069] Furthermore, the separation or integration of various system modules and components in the aforementioned implementation forms is not required in all implementation forms; the components and systems described can generally be integrated into one or packaged into multiple products.

[0070] Therefore, the exemplary implementations described above do not define or limit this disclosure. Other modifications, substitutions, and alterations are possible without departing from the intent and scope of this disclosure.

[0071] According to one aspect of this disclosure, a method for operating a memory controller is disclosed. This method includes the step of receiving a request from a host for the fragmentation level of a file stored in a memory device. This method further includes the step of determining the read performance level of a file based on a logical-to-physical (L2P) address mapping table corresponding to the file, without reading the file from the memory device. This method further includes the step of determining the fragmentation level based on the read performance level.

[0072] In some implementations, a request includes multiple logical addresses of a file. The step of determining the read performance level of a file includes reading an L2P address mapping table from a memory device, determining the average contiguous physical address length of a file based on the multiple logical addresses of the file and the L2P address mapping table, and determining the read performance level based on at least the average contiguous physical address length and a predetermined read performance curve.

[0073] In some implementations, the step of determining the average contiguous physical address length of a file includes the step of mapping multiple logical addresses to physical address segments according to an L2P address mapping table. Each physical address segment contains one or more contiguous physical addresses. The step of determining the average contiguous physical address length of a file further includes the step of determining the average contiguous physical address length. The average contiguous physical address length is determined based on the amount of one or more contiguous physical addresses contained in each physical address segment and the total amount of physical address segments.

[0074] In some implementations, each logical address in a set of logical addresses is a logical block address (LBA), and each physical address in a physical address segment is a physical block address (PBA).

[0075] In some implementations, a given read performance curve is determined by performing random read experiments on a memory device using test data of various chunk sizes.

[0076] In some implementations, the step of determining the read performance level includes determining the initial read performance level corresponding to the average continuous physical address length based on a given read performance curve, and determining whether the average continuous physical address length is greater than a threshold.

[0077] In some implementations, the step of determining the read performance level further includes a step of determining the read performance level as the initial read performance level in response to determining that the average continuous physical address length is greater than a threshold.

[0078] In some implementations, the step of determining the read performance level further includes determining the read performance level as an initial read performance level adjusted by a certain value, in response to determining that the average contiguous physical address length is below a threshold. The value is determined based on the distribution of the file's physical addresses across several planes of the memory device.

[0079] In some implementations, the read performance level is determined based on the initial read performance level and value. The value is determined based on how uniformly the file's physical addresses are spread across several planes of the memory device. If the file's physical addresses are uniformly spread across several planes of the memory device, the value will be smaller than .

[0080] In some implementations, the memory device includes a three-dimensional (3D) NAND flash memory device.

[0081] In some implementations, the requirement is a file-based optimization (FBO) requirement under the Universal Flash Storage (UFS) 4.0 technical standard.

[0082] In some implementations, the method further includes the step of returning the fragmentation level to the host. The method further includes the step of receiving a command from the host to perform defragmentation. The host sends a command in response to determining that the fragmentation level exceeds the fragmentation level threshold. The method further includes the step of performing defragmentation based on the received command.

[0083] In another aspect of this disclosure, a memory system is disclosed. The memory system includes a memory device and a memory controller. The memory controller includes one or more processors and a computer storage medium. The computer storage medium is coupled to one or more processors and stores programming instructions for execution by one or more processors to cause the memory controller to perform an operation. The operation includes receiving a request from a host about the fragmentation level of a file stored in the memory device, determining the read performance level of the file based on a logical-to-physical (L2P) address mapping table corresponding to the file without reading the file from the memory device, and determining the fragmentation level based on the read performance level.

[0084] In some implementations, a request includes multiple logical addresses of a file. Determining the read performance level of a file involves reading an L2P address mapping table from a memory device, determining the average contiguous physical address length of the file based on the multiple logical addresses of the file and the L2P address mapping table, and determining the read performance level based on at least the average contiguous physical address length and a given read performance curve.

[0085] In some implementations, determining the average contiguous physical address length of a file involves mapping multiple logical addresses to physical address segments according to an L2P address mapping table. Each physical address segment contains one or more contiguous physical addresses. Determining the average contiguous physical address length of a file further involves determining the average contiguous physical address length. The average contiguous physical address length is determined based on the amount of one or more contiguous physical addresses contained in each physical address segment and the total amount of physical address segments.

[0086] In some implementations, each logical address in a set of logical addresses is a logical block address (LBA), and each physical address in a physical address segment is a physical block address (PBA).

[0087] In some implementations, a given read performance curve is determined by performing random read experiments on a memory device using test data of various chunk sizes.

[0088] In another aspect of this disclosure, a non-temporary computer storage medium is disclosed. The non-temporary computer storage medium is coupled to one or more processors of a memory controller and stores programming instructions for execution by one or more processors to cause the memory controller to perform an operation. The operation includes receiving a request from a host about the fragmentation level of a file stored in the memory device, determining the read performance level of the file based on a logical-to-physical (L2P) address mapping table corresponding to the file without reading the file from the memory device, and determining the fragmentation level based on the read performance level.

[0089] In some implementations, a request includes multiple logical addresses of a file. Determining the read performance level of a file involves reading an L2P address mapping table from a memory device, determining the average contiguous physical address length of the file based on the multiple logical addresses of the file and the L2P address mapping table, and determining the read performance level based on at least the average contiguous physical address length and a given read performance curve.

[0090] In some implementations, determining the average contiguous physical address length of a file involves mapping multiple logical addresses to physical address segments according to an L2P address mapping table. Each physical address segment contains one or more contiguous physical addresses. Determining the average contiguous physical address length of a file further involves determining the average contiguous physical address length. The average contiguous physical address length is determined based on the amount of one or more contiguous physical addresses contained in each physical address segment and the total amount of physical address segments.

[0091] The above description of specific implementation forms can be readily modified and / or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and scope of the equivalent implementation forms disclosed herein, based on the teachings and guidance provided herein.

[0092] The breadth and scope of this disclosure should not be limited by any of the exemplary implementations described above, but should be defined solely in accordance with the subsequent claims and their equivalents. Therefore, other implementations are also within the scope of the claims. [Explanation of Symbols]

[0093] 100 Systems 102 memory systems 104 Memory Devices 106 Memory Controller 108 hosts 110 Host memory 112 host processors 114 dies, memory cell array 116 Plain 118 physical blocks 202 memory card 204 Memory card connector 206 SSD 208 SSD connectors 300 memory devices 302 Peripheral Circuits 306 memory cells 308 NAND memory string 310 Source Select Gate (SSG) Transistor 312 Drain-Selected Gate (DSG) Transistor 313 DSG line 314 Source Line (SL) 315 SSG Line 316-bit line 400 System 404 File 406 Index Nodes 408 Index Node Update Module 410 Controller Processor 412 Volatile controller memory 414 Non-volatile controller memory 416 Memory Controller Interface 418 L2P Address Mapping Table 500 Systems 502 i-nodes 504 LBA segment 506 LBA segment 508 LBA segment 510 LBA segments 520 L2P Address Mapping Table 530 Die 532 Die 534 Plain 536 Plain 538 Plain 540 Plain 702 Read Performance 704 data points

Claims

1. A method for operating a memory controller, The steps include receiving a request from the host regarding the fragmentation level of a file stored in a memory device, Without reading the file from the memory device, the step of determining the read performance level of the file based on the logical-to-physical (L2P) address mapping table corresponding to the file, A step of determining the fragmentation level based on the read performance level. Methods that include...

2. The request includes multiple logical addresses of the file, and the step of determining the read performance level of the file is: The steps include reading the L2P address mapping table from the memory device, The steps include determining the average continuous physical address length of the file based on the plurality of logical addresses of the file and the L2P address mapping table, The steps include determining the read performance level based at least on the average continuous physical address length and a predetermined read performance curve, and The method according to claim 1, including the method described in claim 1.

3. The step of determining the average continuous physical address length of the aforementioned file is: A step of mapping the plurality of logical addresses to physical address segments according to the L2P address mapping table, wherein each of the physical address segments includes one or more consecutive physical addresses; A step of determining the average continuous physical address length, wherein the average continuous physical address length is determined based on the amount of one or more continuous physical addresses included in each of the physical address segments and the sum of the amounts of the physical address segments. The method according to claim 2, including the method described in claim 2.

4. Each of the aforementioned logical addresses is a logical block address (LBA), The method according to claim 3, wherein each physical address in the physical address segment is a physical block address (PBA).

5. The method according to claim 2, wherein the predetermined read performance curve is determined by performing random read experiments on the memory device using test data of various chunk sizes.

6. The step of determining the read performance level is: The steps include determining the initial read performance level corresponding to the average continuous physical address length based on the predetermined read performance curve, The steps include determining whether the average continuous physical address length is greater than a threshold, and The method according to claim 2, including the method described in claim 2.

7. The step of determining the read performance level is: The method according to claim 6, further comprising the step of determining the read performance level as the initial read performance level in response to determining that the average continuous physical address length is greater than the threshold.

8. The step of determining the read performance level is: The method according to claim 6, further comprising the step of determining the read performance level as the initial read performance level adjusted by a certain value determined based on the distribution of the physical addresses of the file among several planes of the memory device, in response to the determination that the average continuous physical address length is less than or equal to the threshold.

9. The read performance level is determined based on the initial read performance level and the value. The value is determined based on how uniformly the physical addresses of the file are spread across the several planes of the memory device. The method according to any one of claims 1 to 8, wherein the value is smaller than the physical address of the file if the physical address of the file is uniformly distributed across the several planes of the memory device.

10. The method according to any one of claims 1 to 9, wherein the memory device includes a three-dimensional (3D) NAND flash memory device.

11. The method according to any one of claims 1 to 10, wherein the requirement is a file-based optimization (FBO) requirement under the Universal Flash Storage (UFS) 4.0 technical standard.

12. The steps include: returning the aforementioned fragmentation level to the host, A step of receiving a command from the host to perform defragmentation, wherein the host sends the command in response to determining that the fragmentation level exceeds a fragmentation level threshold. The steps include: performing the defragmentation based on the received command; The method according to any one of claims 1 to 11, further comprising:

13. Memory devices and, A memory controller comprising one or more processors and computer storage media The computer storage medium is coupled to one or more processors and stores programming instructions for execution by the one or more processors to cause the memory controller to perform an operation, and the operation is Receiving a request from the host regarding the fragmentation level of the files stored in the memory device, Without reading the file from the memory device, the read performance level of the file is determined based on the logical-to-physical (L2P) address mapping table corresponding to the file. The fragmentation level is determined based on the read performance level. A memory system that includes this.

14. The request includes multiple logical addresses of the file, and determining the read performance level of the file is: Reading the L2P address mapping table from the memory device, The average continuous physical address length of the file is determined based on the plurality of logical addresses of the file and the L2P address mapping table, The read performance level is determined based at least on the average continuous physical address length and a predetermined read performance curve. The memory system according to claim 13, including the memory system according to claim 13.

15. Determining the average continuous physical address length of the aforementioned file means that The mapping of the plurality of logical addresses to physical address segments according to the L2P address mapping table, wherein each of the physical address segments includes one or more consecutive physical addresses. The determination of the average continuous physical address length, wherein the average continuous physical address length is determined based on the sum of the amount of one or more continuous physical addresses included in each of the physical address segments and the amount of the physical address segments. The memory system according to claim 14, including the memory system according to claim 14.

16. Each of the aforementioned logical addresses is a logical block address (LBA), The memory system according to any one of claims 13 to 15, wherein each physical address in the physical address segment is a physical block address (PBA).

17. The memory system according to claim 14, wherein the predetermined read performance curve is determined by performing random read experiments on the memory device using test data of various chunk sizes.

18. A non-temporary computer storage medium, wherein the non-temporary computer storage medium is coupled to one or more processors of a memory controller and stores programming instructions for execution by the one or more processors to cause the memory controller to perform an operation, and the operation is Receiving a request from the host regarding the fragmentation level of files stored in the memory device, Without reading the file from the memory device, the read performance level of the file is determined based on the logical-to-physical (L2P) address mapping table corresponding to the file. The fragmentation level is determined based on the read performance level. Non-temporary computer storage media, including [specific type of storage medium].

19. The request includes multiple logical addresses of the file, and determining the read performance level of the file is: Reading the L2P address mapping table from the memory device, The average continuous physical address length of the file is determined based on the plurality of logical addresses of the file and the L2P address mapping table, The read performance level is determined based at least on the average continuous physical address length and a predetermined read performance curve. A non-temporary computer storage medium according to claim 18, including the following:

20. Determining the average continuous physical address length of the aforementioned file means that The mapping of the plurality of logical addresses to physical address segments according to the L2P address mapping table, wherein each of the physical address segments includes one or more consecutive physical addresses. The determination of the average continuous physical address length, wherein the average continuous physical address length is determined based on the sum of the amount of one or more continuous physical addresses included in each of the physical address segments and the amount of the physical address segments. The non-temporary computer storage medium according to claim 18 or 19, including the following:

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