Chips, methods for manufacturing the same, and electronic devices

Abstract

This application provides a chip, a method for manufacturing the same, and an electronic device. When a chemical gold plating layer is manufactured on a nickel-containing adhesive layer using a chemical gold plating method, the chemical gold plating is not affected by electric or magnetic fields, and therefore gold can easily penetrate through holes regardless of the angle of incidence. Gold is deposited on the surface of the adhesive layer through a substitution reaction between nickel and gold, and the gold that has penetrated into the through holes increases the thickness of the chemical gold plating layer inside the through holes, reducing the difference in thickness between the chemical gold plating layer inside and outside the through holes. As a result, the difference in thickness between the conductive plating layer inside and outside the through holes is reduced, the subconformation phenomenon is avoided, the uniformity of the conductive plating layer inside and outside the through holes is improved, and the performance of the conductive plating layer and, furthermore, the chip is improved. In addition, because the adhesive layer is a nickel-containing film layer, gold can be deposited on the surface of the adhesive layer, and not in other locations where there is no adhesive layer. In this way, the amount of gold used is reduced, and the manufacturing cost of the chip is reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly, to chips, methods of manufacturing the same, and electronic devices.

Background Art

[0002] A chip includes a substrate and semiconductor devices disposed on the substrate. The semiconductor devices are, for example, transistors or capacitors. One side of the surface on which the semiconductor devices are disposed may be referred to as the front surface of the substrate, and the other side of the surface may be referred to as the back surface of the substrate. When through holes are provided in the substrate, the through holes may be covered by the power terminals or ground terminals of the semiconductor devices. Therefore, when a conductive plating layer is manufactured on the back surface of the substrate, the conductive plating layer covers not only the back surface, but also the sidewalls of the through holes and the surfaces belonging to the power terminals or ground terminals and exposed from the through holes. As a result, heat generated when the semiconductor devices operate can be conducted from the back surface to the outside, and thus the heat dissipation ability of the chip is improved. In addition, the structural complexity of the front surface of the substrate can be reduced, and the power terminals or ground terminals of the semiconductor devices can be simplified by using the space on the back surface of the substrate.

[0003] However, in the prior art, the thickness of the conductive plating layer manufactured on the back surface of the substrate varies greatly inside and outside the through holes, and the sub-conformal phenomenon effect is likely to occur. In this case, the performance of the conductive plating layer inside and outside the through holes becomes non-uniform, and as a result, the performance of the conductive plating layer deteriorates, affecting the performance of the chip.

Summary of the Invention

[0004] This application provides a chip, a method of manufacturing the same, and an electronic device that reduce the difference in thickness between the conductive plating layers inside and outside the through holes and improve the performance of the conductive plating layer and further the chip.

Means for Solving the Problems

[0005] According to a first aspect, one embodiment of the present application provides a chip. The chip may include a substrate and a conductive structure. The substrate has a first surface and a second surface arranged opposite to each other, and through holes penetrating the first surface and the second surface. The number of through holes provided is based on the actual requirements, so there may be one, two, three, or more through holes, without limiting the number as specified herein. The conductive structure may be arranged on the first surface. One, two, or more conductive structures may be arranged. The function of the conductive structure includes, but is not limited to, transmitting power signals, ground signals, or other signals. The functions of the conductive structures may be the same, partially the same, or all different, and may be specifically defined on the actual requirements. Regardless of the number of conductive structures arranged and the function of each conductive structure, the requirement is satisfied if one conductive structure covers a through hole. In addition, the number of through holes covered by conductive structures is also not limited as specified herein.

[0006] The chip may further include a conductive plating layer. The conductive plating layer may be formed on the second surface, the sidewalls of the through-holes, and the surface belonging to the conductive structure and exposed from the through-holes. Part of the second surface other than the through-holes may be called the non-through-hole region. The sidewalls of the through-holes are sometimes abbreviated as hole walls. Surfaces belonging to the conductive structure and exposed from the through-holes may be considered as the hole bottom. In this way, the conductive plating layer is arranged in the region other than the through-holes, hole walls, and hole bottoms, and the conductive plating layer is connected to the conductive structure, so that heat from the conductive structure can be conducted through the conductive plating layer to the second surface and dissipated through the second surface, and signals transmitted by the conductive structure can be transmitted to the conductive plating layer.

[0007] The conductive plating layer may include an adhesive layer formed on areas other than the through-hole, hole wall, and hole bottom, a chemical gold plating layer formed on the adhesive layer, and a gold electroplating layer formed on the chemical gold plating layer. As a result, the adhesive layer, the chemical gold plating layer, and the gold electroplating layer are sequentially laminated in the direction from the first surface to the second surface. In this way, when a chemical gold plating layer (sometimes called a seed layer) is produced on a nickel-containing adhesive layer using a chemical gold plating method, the chemical plating is not affected by electric or magnetic fields, so there are no problems regarding the angle of incidence of particles, and gold can easily penetrate into the through-hole without being affected by the angle of incidence. Gold is deposited on the surface of the adhesive layer through a substitution reaction between nickel and gold, and the gold that has penetrated into the through-hole can increase the thickness of the seed layer inside the through-hole, reducing the difference in thickness between the seed layer inside and outside the through-hole, and as a result, the difference in thickness between the gold electroplating layer inside and outside the through-hole is reduced. This reduces the difference in thickness between the conductive plating layers inside and outside the through-hole, avoids subconformation, improves the uniformity of the conductive plating layers inside and outside the through-hole, and consequently improves the performance of the conductive plating layer and the chip. In addition, because the adhesive layer is a nickel-containing film layer, a seed layer can be formed on the surface of the adhesive layer, and gold is not deposited in other locations where there is no adhesive layer. This solves the problem of gold waste caused by the deposition of most of the gold on the inner wall of the device cavity in the Physical Vapor Deposition (PVD) method, reduces the amount of gold used, and as a result, lowers the manufacturing cost of the chip.

[0008] In some embodiments, it is shown that when the ratio of the first thickness at any position within the through-hole to the second thickness at any position on the second surface of the chemical gold plating layer is set to 0.5 or more, the difference in thickness between the seed layer inside and outside the through-hole is small, and the resistance of the seed layer inside the through-hole is effectively reduced. Therefore, when a gold electroplating layer is manufactured on a seed layer by using a gold electroplating method, the gold electroplating layer inside the through-hole can be made thicker to further reduce the difference in thickness between the inside and outside of the through-hole during gold electroplating, further improve the thickness uniformity of the conductive plating layer, and further shorten the gold electroplating time. This not only reduces the amount of gold used but also improves the manufacturing efficiency of the conductive plating layer and even the chip.

[0009] For example, any position within the through-hole described above may include a position between 1 / 3 and 2 / 3 of the through-hole's depth, for instance, a position halfway through the through-hole's depth. The thickness of the chemical gold plating layer at these positions is close to the average thickness of the chemical gold plating layer at various positions within the through-hole. By selecting the thickness of the chemical gold plating layer at these positions as the first thickness, it is easy to achieve a ratio of 0.5 or more between the first thickness and the second thickness. This helps to reduce the difference in thickness between the gold electroplating layer inside and outside the through-hole, and thus helps to reduce the gold electroplating time.

[0010] In addition, setting the second thickness to 300 nm or more helps to achieve a specific thickness of the chemical gold plating layer within the through-hole, avoiding excessively high resistance caused by an excessively thin chemical gold plating layer within the through-hole. This helps to reduce the difference in thickness between the gold electroplating layer inside and outside the through-hole, and also helps to reduce the difference in thickness between the conductive plating layer inside and outside the through-hole, especially when the ratio of the first thickness to the second thickness is 0.5 or more, further reducing the difference in thickness between the conductive plating layer inside and outside the through-hole. Furthermore, when the second thickness is 300 nm or more, the internal stress of the chemical gold plating layer can be reduced, and warping of the chemical gold plating layer can be avoided. This helps to reduce the difference in thickness between the conductive plating layer inside and outside the through-hole, and even improves the performance of the conductive plating layer and the chip.

[0011] In some embodiments, the atomic percentage of nickel in the adhesive layer may be set to 80% or more, while the atomic percentage of another corresponding element is 20% or less. In this way, the adhesive layer may contain a relatively large amount of nickel. During chemical gold plating, the surface of the nickel-containing film layer may be plated directly without the use of a catalyst, and the nickel content of the adhesive layer has a specific effect on the gold plating effect. A higher nickel content indicates that gold plating is easier, and a lower nickel content indicates that gold plating is less easy. Therefore, a higher nickel content in the adhesive layer can promote and accelerate gold deposition, and as a result, gold can be easily deposited on the surface of the adhesive layer, improving the production efficiency of the chemical gold plated layer.

[0012] In addition, the adhesive layer may consist of at least one of elemental nickel and a nickel-containing inorganic compound, and may be a single-layer or multi-layer structure. When the adhesive layer is a multi-layer structure, the materials of the layers may be the same or different, and may be specifically determined based on the actual requirements. The nickel-containing inorganic compound may be selected from at least one of nickel-vanadium alloys, nickel phosphide, nickel nitride, nickel boride, nickel-tungsten alloys, nickel-aluminum alloys, nickel-titanium alloys, nickel-thallium alloys, nickel-chromium alloys, etc., resulting in a wide range of material choices and meeting the requirements of various application scenarios.

[0013] In addition, when manufacturing the adhesive layer, the adhesive layer may be produced using the PVD method, and the thickness of the adhesive layer may be controlled to between 0.1 μm and 0.5 μm. In this way, if the adhesive layer is excessively thin, it can be prevented from affecting the gold plating effect in the chemical gold plating, and as a result, the chemical gold plating layer can be easily formed on the adhesive layer, avoiding unnecessary waste caused when the adhesive layer is excessively thick. This helps to reduce manufacturing costs based on reducing the difference in thickness between the chemical gold plating layer inside and outside the through hole.

[0014] In some embodiments, the substrate may be composed of compound materials of Group III and Group V elements. For example, compound materials of Group III and Group V elements include, but are not limited to, GaP, GaAs, AlAs, AlP, AlSb, InP, InSb, InAs, GaInAs, GaInP, GaAlP, and GaAlAs. The conductive structure may be composed of a conductive material. For example, conductive materials include, but are not limited to, conductive metals, conductive metal oxides, conductive metal alloys, and conductive organic compounds.

[0015] According to a second aspect, one embodiment of the present application provides a chip manufacturing method comprising the steps of forming a conductive structure on a substrate, wherein the substrate has a first surface and a second surface arranged opposite to each other, and through holes penetrating the first surface and the second surface, the conductive structure being located on the first surface and covering the through holes, the second surface, the side walls of the through holes, and forming an adhesive layer on a surface belonging to the conductive structure and exposed from the through holes, wherein the adhesive layer contains nickel, forming a chemical gold plating layer on the adhesive layer, and forming a gold electroplating layer on the chemical gold plating layer.

[0016] Thus, when a chemical gold plating layer (sometimes called a seed layer) is produced on a nickel-containing adhesive layer using a chemical gold plating method, the chemical plating is not affected by electric or magnetic fields, so there are no problems regarding the angle of incidence of particles, and gold can easily penetrate the through-holes without being affected by the angle of incidence. Gold is deposited on the surface of the adhesive layer through a substitution reaction between nickel and gold, and the gold that has penetrated the through-holes can increase the thickness of the seed layer inside the through-holes, reducing the difference in thickness between the seed layer inside and outside the through-holes, and as a result the difference in thickness between the gold electroplated layer inside and outside the through-holes is reduced. This reduces the difference in thickness between the conductive plating layer inside and outside the through-holes, avoids the subconformation phenomenon, improves the uniformity of the conductive plating layer inside and outside the through-holes, and improves the performance of the conductive plating layer and, furthermore, the chip. In addition, because the adhesive layer is a nickel-containing film layer, the seed layer can be produced on the surface of the adhesive layer, and gold is not deposited in other locations where there is no adhesive layer. This solves the problem of gold waste caused by the deposition of most of the gold on the inner walls of the device cavity in the PVD method, reducing the amount of gold used and consequently lowering the manufacturing cost of the chip.

[0017] The principle by which the manufacturing method solves the problem is the same as the principle by which the chip described above solves the problem; therefore, for embodiments and technical effects of the manufacturing method, please refer to the embodiments and technical effects of the chip described above. Further details will not be explained again.

[0018] According to a third aspect, one embodiment of the present application provides an electronic device. The electronic device may include a circuit board and a chip as described in the first aspect. The chip is placed on the circuit board. By improving the uniformity of the thickness of the conductive plating layer inside and outside the through-holes, the performance of the conductive plating layer and further the chip can be improved, manufacturing costs can be reduced, and the manufacturing efficiency of the conductive plating layer can be improved. As a result, the electronic device manufactured using the chip can also achieve the objectives of improved performance, reduced manufacturing costs, and improved manufacturing efficiency.

[0019] The principle of solving the problem by using electronic devices is the same as the principle of solving the problem by using the chips described above; therefore, for embodiments and technical effects of electronic devices, please refer to the embodiments and technical effects of the chips described above. Further details will not be explained again. [Brief explanation of the drawing]

[0020] [Figure 1] This is a diagram showing the structure of an electronic device according to one embodiment of this application. [Figure 2] This is a diagram showing the structure of a chip according to one embodiment of this application. [Figure 3] This is a diagram of a chip manufacturing process according to one embodiment of this application. [Figure 4] This is a cross-sectional view of an adhesive layer and a chemical gold plating layer according to one embodiment of this application. [Figure 5] This is a cross-sectional view of the adhesive layer and gold layer in the prior art. [Figure 6] This is a cross-sectional view of a gold electroplating layer manufactured on a chemical gold plating layer. [Figure 7] This is a cross-sectional view of a gold electroplating layer fabricated on a gold layer manufactured using the PVD method. [Modes for carrying out the invention]

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the following will further elaborate on this application in detail with reference to the accompanying drawings.

[0022] Note that the same reference numbers in the accompanying drawings of this application indicate the same or similar structures. Therefore, repeated descriptions will be omitted. The expressions of position and direction in this application are explained by using the accompanying drawings as an example. However, changes can be made as necessary, and all changes fall within the protection scope of this application. The accompanying drawings of this application are only used to show the relative positional relationship and do not represent the actual scale.

[0023] To make it easier to understand the technical solutions provided in the embodiments of this application, the following will first explain the application scenarios.

[0024] The chips provided in the embodiments of this application can be widely used in various electronic devices. The electronic devices can include various terminal devices and electronic components. The terminal devices can include devices such as smartphones, smart TVs, smart TV set-top boxes, smartwatches, personal computers (PCs), wearable devices, and intelligent broadband devices, but are not limited thereto. The electronic components can include telecommunications devices such as wireless networks, fixed networks, and servers, as well as components such as chip modules or memories, but are not limited thereto. Details will not be described in this specification.

[0025] Figure 1 shows a structure in which a chip is applied to an electronic device. As shown in Figure 1, the electronic device includes a housing 100 and a circuit board 200 placed in the housing 100. The chip 300 is placed on the circuit board 200. The chip 300 may include a substrate and a semiconductor device placed on the substrate. The semiconductor device is, for example, a transistor or a capacitor. In a substrate, one side of the surface on which the semiconductor device is placed may be called the surface of the substrate, and the other side of the surface may be called the back surface of the substrate. When through-holes are provided in the substrate, the through-holes may be covered by the power or ground terminals of the semiconductor device. Therefore, when a conductive plating layer is manufactured on the back surface of the substrate, the conductive plating layer covers not only the back surface of the substrate but also the side walls of the through-holes and the surfaces belonging to the power or ground terminals that are exposed from the through-holes, and as a result the conductive plating layer is connected to the power or ground terminals. This allows the heat generated when the semiconductor device is operating to be conducted from the back surface of the substrate to the outside, and as a result the heat dissipation capacity of the chip 300 is improved. In addition, the structural complexity of the substrate surface can be reduced, and the power lines or ground lines required for the circuit can be simplified by using the space on the back surface of the substrate.

[0026] Currently, when a conductive plating layer is manufactured on the back surface of a substrate, a titanium or titanium-tungsten layer may be sputtered first on the back surface of the substrate, the side walls of the through-holes, and the surfaces belonging to the power or ground ends that are exposed from the through-holes, using PVD as an adhesive layer. Then, a gold layer may be sputtered on the surface of the adhesive layer using PVD, and finally, gold may be plated on the surface of the seed layer using electroplating to increase the thickness of the conductive plating layer. In the PVD method, the incident angle of the particles cannot be controlled, so particles with large angles have difficulty entering the through-holes. Consequently, the seed layer is thicker on the outside of the through-holes and thinner inside the through-holes. Based on the principle that thicker layers have lower resistance and thinner layers have higher resistance, the thickness of the gold inside the through-holes during gold plating is much thinner than the thickness of the gold outside the through-holes. This leads to a large difference in the thickness of the conductive plating layer inside and outside the through-holes, ultimately resulting in low performance of the conductive plating layer.

[0027] Therefore, this application provides a chip, a method for manufacturing the same, and an electronic device that reduce the difference in thickness between the conductive plating layer inside and outside the through hole, avoid subconformation, improve the uniformity of the conductive plating layer inside and outside the through hole, and improve the performance of the conductive plating layer and the chip.

[0028] Figure 2 is a diagram of the structure of a chip according to one embodiment of the present application. As shown in Figure 2, the chip may include a substrate 10 and a conductive structure 20. The substrate 10 has a first surface b1 and a second surface b2 arranged opposite to each other, and through holes 11 that penetrate the first surface b1 and the second surface b2. Any number of through holes can be provided, and there may be one, two, three, or more through holes 11, without limiting the quantity as specified herein. The conductive structure 20 may be arranged on the first surface b1. One, two, or more conductive structures 20 may be arranged. The function of the conductive structure 20 includes, but is not limited to, transmitting power signals, ground signals, or other signals. The functions of the conductive structures 20 may be the same, partially the same, or all different, and may be specifically set based on the actual requirements. Regardless of the number of conductive structures 20 arranged and the setting of the function of each conductive structure 20, the requirement is satisfied if one conductive structure 20 covers the through holes 11. In addition, the number of through-holes 11 covered by the conductive structure 20 is not limited herein.

[0029] Please refer to Figure 2. The chip may further include a conductive plating layer 30. The conductive plating layer 30 may be formed on the second surface b2, the side wall of the through hole 11, and the surface of the conductive structure 20 that is exposed from the through hole 11. A portion of the second surface b2 other than the through hole 11 may be called the non-through hole region. The side wall of the through hole 11 may be abbreviated as hole wall b3. The surface of the conductive structure 20 that is exposed from the through hole 11 may be considered the hole bottom. In this way, the conductive plating layer 30 is placed in the region other than the through hole, hole wall b3, and hole bottom, and the conductive plating layer 30 is connected to the conductive structure 20, so that heat from the conductive structure 20 can be conducted through the conductive plating layer 30 to the second surface b2 and dissipated through the second surface b2, and signals transmitted by the conductive structure 20 can be transmitted to the conductive plating layer 30.

[0030] The conductive plating layer 30 may include an adhesive layer 31 formed on areas other than the through-hole, hole wall b3, and hole bottom, a chemical gold plating layer 32 formed on the adhesive layer 31, and a gold electroplating layer 33 formed on the chemical gold plating layer 32. As a result, the adhesive layer 31, the chemical gold plating layer 32, and the gold electroplating layer 33 are sequentially laminated in the direction from the first surface b1 to the second surface b2 (i.e., direction F1 in Figure 2). The manufacturing material of the adhesive layer 31 contains the element nickel. For example, the adhesive layer 31 may be composed of at least one of the element nickel and a nickel-containing inorganic compound. The nickel-containing inorganic compound may be selected from, but is not limited to, at least one of nickel-vanadium alloys, nickel phosphide, nickel nitride, nickel boride, nickel-tungsten alloys, nickel-aluminum alloys, nickel-titanium alloys, nickel-thallium alloys, nickel-chromium alloys, etc. As a result, the range of material selection is broadened, and the requirements in various application scenarios are met. In addition, the adhesive layer 31 may be a single-layer structure or a multi-layer structure. When the adhesive layer 31 is a multi-layer structure, the materials of the layers may be the same or different, and may be specifically determined based on the actual requirements.

[0031] Thus, when a chemical gold plating layer (sometimes called a seed layer) 32 is manufactured on the nickel-containing adhesive layer 31 using a chemical gold plating method, the chemical plating is not affected by electric or magnetic fields, so there are no problems regarding the angle of incidence of the particles, and gold can easily penetrate the through-hole 11 without being affected by the angle of incidence. Gold is deposited on the surface of the adhesive layer 31 through a substitution reaction between nickel and gold, and the gold that has penetrated the through-hole 11 can increase the thickness of the seed layer inside the through-hole 11, reducing the difference in thickness between the seed layer inside and outside the through-hole 11, and as a result the difference in thickness between the gold electroplating layer 33 inside and outside the through-hole 11 is reduced. This reduces the difference in thickness between the conductive plating layer 30 inside and outside the through-hole 11, avoids the subconformation phenomenon, improves the uniformity of the conductive plating layer 30 inside and outside the through-hole 11, and improves the performance of the conductive plating layer 30 and, furthermore, the chip.

[0032] For example, an adhesive layer 31 may be formed by using the PVD method, and the resulting adhesive layer 31 may be a nickel-containing film layer. In this way, a gold layer can be produced on the surface of the adhesive layer 31 by using a chemical gold plating method through a substitution reaction between nickel and gold, thereby obtaining a seed layer, and gold will not be deposited in other locations if the adhesive layer 31 is not present. This solves the problem of gold waste caused by the deposition of most of the gold on the inner wall of the device cavity in the PVD method, reduces the amount of gold used, and consequently lowers the manufacturing cost of the chip.

[0033] Chemical gold plating is a method of depositing gold onto the adhesive layer 31 through a chemical reaction based on the oxidation-reduction principle, and it should be understood that this method does not require the supply of an external electric current. Gold electroplating is a method of forming a gold layer by releasing gold ions under the action of an externally supplied electric current.

[0034] As shown in Figure 2, when the ratio of the first thickness d1 at any position within the through hole 11 to the second thickness d2 at any position on the second surface b2 of the chemical gold plating layer 32 is set to 0.5 or more, the difference in thickness between the seed layer inside and outside the through hole 11 is small, and the resistance of the seed layer inside the through hole 11 is effectively reduced. Therefore, when the gold electroplating layer 33 is manufactured on the seed layer by using the gold electroplating method, the gold electroplating layer 33 inside the through hole 11 can be made thicker to further reduce the difference in thickness between the inside and outside of the through hole 11 during gold electroplating, further improve the thickness uniformity of the conductive plating layer 30, and further shorten the gold electroplating time. This not only reduces the amount of gold used, but also improves the manufacturing efficiency of the conductive plating layer 30 and even the chip.

[0035] As shown in Figure 2, setting the second thickness d2 at any position on the second surface b2 to 300 nm or more helps to achieve a specific thickness of the chemical gold plating layer 32 inside the through hole 11, thereby avoiding excessively large resistance caused by an excessively thin chemical gold plating layer 32 inside the through hole 11. This helps to reduce the difference in thickness between the gold electroplating layer 33 inside and outside the through hole 11, and helps to reduce the difference in thickness between the conductive plating layer 30 inside and outside the through hole 11, and in particular helps to further reduce the difference in thickness between the conductive plating layer 30 inside and outside the through hole 11 when the ratio of the first thickness d1 to the second thickness d2 is 0.5 or more.

[0036] Figure 3 shows an example of a schematic flowchart of a chip manufacturing method according to one embodiment of the present application. As shown in Figure 3, the method may include the following steps.

[0037] Step 1: As shown in Figure 3(a), a through hole 11 is formed in the substrate 10 having a first surface b1 and a second surface b2 that are arranged opposite to each other, and the through hole 11 penetrates the first surface b1 and the second surface b2.

[0038] As shown in Figure 3(a), the first surface b1 and the second surface b2 of the substrate 10 are arranged opposite each other in the thickness direction of the substrate 10, and the through-hole 11 extends in the thickness direction of the substrate 10 and penetrates the first surface b1 and the second surface b2. The size and shape of the through-hole 11 may be determined based on actual requirements. For example, but not limited to, the cross section of the through-hole 11 that is parallel to the first surface b1 may be elliptical, circular, or irregular in shape. Taking an elliptical shape as an example, the shortest diameter may be 30 μm, but not limited to this, and the longest diameter may be 60 μm, but not limited to this. In addition, when manufacturing the through-hole 11, the through-hole 11 may be etched into the substrate 10 by plasma etching, but not limited to this.

[0039] Step 2: As shown in Figure 3(b), a conductive structure 20 covering the through hole 11 is formed on the first surface b1.

[0040] As shown in Figure 3(b), this figure is illustrated by using an example in which one conductive structure 20 covers one through hole 11. If the structure in Figure 3(b) is reversed, the surface belonging to the conductive structure 20 and exposed from the through hole 11 can be considered the bottom of the through hole 11.

[0041] Step 3: A conductive plating layer 30 is formed on the second surface b2, the side wall of the through hole 11, and the surface belonging to the conductive structure 20 that is exposed from the through hole 11. The conductive plating layer 30 includes an adhesive layer 31, a chemical gold plating layer 32, and a gold electroplating layer 33, which are sequentially laminated in the direction from the first surface b1 to the second surface b2. The adhesive layer 31 contains nickel.

[0042] Next, the process for manufacturing the conductive plating layer 30 will be described in detail. This process may include the following steps in particular.

[0043] Step 3.1: As shown in Figure 3(c), a nickel-containing material is used to form an adhesive layer 31 on the second surface b2, the hole wall b3, and the bottom of the hole, based on the PVD method. The thickness d3 of the adhesive layer 31 may be controlled from 0.1 μm to 0.5 μm.

[0044] Step 3.2: Clean the tip on which the adhesive layer 31 has been formed.

[0045] For example, a plasma with a specific power (e.g., 400W, but not limited) is used, and an inert gas (e.g., argon, but not limited) is introduced to clean the chip on which the adhesive layer 31 has formed for a certain period of time (e.g., 90 seconds, but not limited). After that, the cleaned chip is kept under vacuum for a certain period of time (e.g., 5 minutes, but not limited) to remove organic contaminants from the surface of the chip. Subsequently, the chip is cleaned using a sulfuric acid solution (e.g., 5%, but not limited) at a specific concentration at room temperature to remove the oxide film on the surface of the chip.

[0046] Step 3.3: As shown in Figure 3(d), a chemical gold plating layer 32 is formed on the adhesive layer 31 by using a chemical gold plating method.

[0047] The specific manufacturing process for the chemical gold plating layer 32 may include the following two steps: In the first step, a substitution gold plating solution is used to carry out a substitution reaction between nickel and gold on the surface of the adhesive layer 31, resulting in the surface of the adhesive layer 31 containing gold (sometimes called a substitution gold layer). In the second step, a chemical gold plating solution is used to continue gold plating on the surface of the substitution gold layer, increasing the thickness of the gold layer to obtain the chemical gold plating layer 32. Thus, the thickness of the chemical gold plating layer 32 at any position on the second surface b2 is 300 nm or more, and the ratio of the thickness of the chemical gold plating layer 32 at the intermediate position of the through hole 11 to the thickness of the chemical gold plating layer 32 at any position on the second surface b2 is 0.5 or more.

[0048] For example, a substitution gold plating solution typically contains multiple components. Specific volumes of these components are measured and mixed together, and then replenished to a target volume (e.g., 1 L, but not limited to this) to obtain mixture A. The pH value of mixture A is adjusted to a predetermined value (e.g., 7.2, but not limited to this), and the temperature of mixture A is increased to a predetermined temperature (e.g., 74°C, but not limited to this). The chips treated in step 3.2 are then immersed in the heated mixture A, resulting in a nickel-gold substitution reaction on the surface of the adhesive layer 31. After a certain period of time has elapsed (e.g., 12 minutes, but not limited to this), the chips are removed and washed to obtain chips containing a substitution gold layer on the surface of the adhesive layer 31.

[0049] For example, a chemical gold plating solution generally contains multiple components. Specific volumes of components are measured and mixed together, and then replenished to a target volume (e.g., 1 L, but not limited to this) to obtain mixture B. The pH value of mixture B is adjusted to a predetermined value (e.g., 7.2, but not limited to this), and the temperature of mixture B is increased to a predetermined temperature (e.g., 50°C, but not limited to this). Next, a chip with a substituted gold layer formed on it is placed into the heated mixture B, resulting in a reduction reaction with respect to the gold in the chemical gold plating solution, forming a reduced gold layer on the surface of the substituted gold layer and increasing the thickness of the gold layer. After a certain period of time has elapsed (e.g., 3 minutes, but not limited to this), the chip is removed and washed to obtain a chip with a chemical gold plating layer 32 formed on it. The chemical gold plating layer 32 includes the substituted gold layer and the reduced gold layer.

[0050] Of course, the production of the chemical gold plating layer 32 is not limited to the two-step method described above, and other methods that can be used to obtain the chemical gold plating layer 32 may be used as alternatives. This is not limited herein.

[0051] Step 3.4: Clean the chip on which the chemical gold plating layer 32 has been formed.

[0052] Specifically, for details on the particular cleaning process, please refer to the cleaning process described in step 3.2.

[0053] Step 3.5: A gold electroplating layer 33 is formed on the chemical gold plating layer 32, as shown in Figure 3(e).

[0054] When forming the gold electroplating layer 33, the chip processed in step 3.4 is first fastened to the substrate with the chemical gold plating layer 32 facing upwards. Then, the substrate with the chip fastened to it is moved to a fixing jig of an electroplating machine, and electroplating may be performed stepwise using an electroplating gold solution. After the electroplating is complete, the chip is washed using deionized water and dried to obtain the gold electroplating layer 33.

[0055] For example, the currents used in the electroplating steps during stepwise electroplating may differ, and the magnitude of the current used in the electroplating steps may be sequentially increased based on the electroplating sequence. For example, two-step electroplating is used as an example. The current used in the first step of electroplating is smaller than the current used in the second step of electroplating. The advantage of such a setting is that a smaller current is used in the earlier electroplating step, and as a result, the thickness of the gold inside the through-hole 11 can be increased, reducing the difference in thickness between the gold inside and outside the through-hole 11. A larger current is used in the subsequent steps, and as a result, the thickness of the gold can be increased to reach the design thickness of the gold electroplating layer 33. This ensures a small difference in thickness between the gold electroplating layer 33 inside and outside the through-hole 11, and manufacturing efficiency can be further improved. Certainly, stepwise electroplating may be two-step electroplating, but is not limited thereto, and may be specifically determined based on the actual situation, and this is not limited herein.

[0056] The conductive plating layer will be explained below using specific test results.

[0057] Embodiments: As shown in Figures 4 and 5, Figure 4 is a cross-sectional view of the adhesive layer and the chemical gold plating layer at different positions and magnifications according to one embodiment of the present application, and Figure 5 is a cross-sectional view of the adhesive layer and the gold layer at different positions and magnifications in the prior art. The adhesive layer in the prior art is manufactured using the PVD method, and the material used to manufacture the adhesive layer is titanium. The gold layer in the prior art is manufactured using the PVD method. In addition, in Figures 4 and 5, the magnification of (a) is greater than the magnification of (b), and the magnification of (b) is greater than the magnification of (c). By comparing the structures shown in Figures 4 and 5, the following was found, namely,

[0058] 1. The second thickness d2 of the chemical gold plating layer provided on the second surface in this embodiment of the present application is approximately 592 nm to 620 nm. As shown in Figure 4(b), the first thickness d1 of the chemical gold plating layer corresponding to half the depth of the through hole is approximately 324 nm to 374 nm. As shown in Figure 4(c), the ratio of the first thickness d1 to the second thickness d2 is greater than 0.5. Thus, the chemical gold plating layer provided in this embodiment of the present application has a large thickness and a flat surface (as shown in Figure 4(a)).

[0059] 2. The second thickness d2 of the prior art gold layer on the second surface is approximately 128 nm to 256 nm. As shown in Figure 5(b), the first thickness d1 of the gold layer corresponding to half the depth of the through hole is approximately 31 nm to 40 nm. As shown in Figure 5(c), the ratio of the first thickness d1 to the second thickness d2 is less than 0.3. Therefore, the prior art gold layer is thin, island-like, and has a non-uniform surface (as shown in Figure 5(a)).

[0060] Through a comparison between gold layers produced using chemical gold plating and gold layers produced using PVD (Physical Vapor Deposition), analysis revealed that gold layers deposited using PVD have significant internal stress. Increasing the thickness of the gold layer can lead to warping of the gold layer, delamination from the adhesive layer, and even cracking of the wafer. As a result, the obtained gold layer is island-like and has a non-uniform surface. In addition, in PVD, most of the gold is deposited on the inner wall of the device cavity, so the amount of gold deposited on the adhesive layer is limited. Consequently, the gold layer becomes thin. However, gold layers produced using chemical plating (i.e., chemical gold plating layers) can avoid the aforementioned problems, and as a result, the produced chemical gold plating layers have a flat surface and greater thickness.

[0061] Embodiments: As shown in Figures 6 and 7, Figure 6 is a cross-sectional view of a gold electroplated layer manufactured on a chemical gold plated layer at different positions and magnifications, and Figure 7 is a cross-sectional view of a gold electroplated layer manufactured on a gold layer manufactured by using the PVD method at different positions and magnifications. In Figures 6 and 7, the magnification in (a) is greater than the magnification in (b), and the magnification in (b) is greater than the magnification in (c). By comparing the structures shown in Figures 6 and 7, the following was found, namely,

[0062] 1. When a gold layer is produced using the PVD method, the thickness of the gold electroplating layer produced on top of the gold layer is greater than the area of ​​the through-hole, and the bottom of the hole is small, resulting in subconformation, as shown by the solid circle in Figure 7(a). When a gold layer is produced using the PVD method, it is difficult to effectively sputter gold into the through-hole due to problems with the angle of incidence of the particles, and as a result, the gold layer inside the through-hole has a thin thickness and high resistance. Therefore, in the electroplating process, the current inside the through-hole is small, and the thickness of the gold electroplating layer is particularly small at the bottom of the hole. The difference in thickness between the chemical gold plating layer inside and outside the through-hole is small, and the resistance of the chemical gold plating layer inside the through-hole is small. In this case, as shown by the solid circle in Figure 6(a), the current inside the through-hole in the electroplating process is large, the thickness of the gold electroplating layer inside the through-hole is increased, and the subconformation phenomenon is avoided.

[0063] 2. For a gold electroplating layer manufactured on a gold layer produced using the PVD method, the thickness d4 of the gold electroplating layer in areas other than through holes is approximately 8.51 μm, as shown in Figure 7(b), and the thickness d5 of the gold electroplating layer at the bottom of the hole is approximately 3.90 μm, as shown in Figure 7(c), with a ratio of thickness d5 to thickness d4 being 45.9%. For a gold electroplating layer manufactured on a chemical gold plating layer, the thickness d4 of the gold electroplating layer in areas other than through holes is approximately 7.63 μm, as shown in Figure 6(b), and the thickness d5 of the gold electroplating layer at the bottom of the hole is approximately 4.64 μm, as shown in Figure 6(c), with a ratio of thickness d4 to thickness d5 being 60.8%. The smaller the difference in thickness between the gold electroplating layer manufactured on a chemical gold plating layer, both inside and outside the through hole, the thicker the gold electroplating layer inside the through hole is considered to be. If the thickness of the gold electroplating layer at the bottom of the hole is required to be 4 μm, then, based on the above ratio, when the gold electroplating layer is manufactured on a gold layer produced by the PVD method, the gold electroplating layer in areas other than the through-hole needs to be electroplated to 8.87 μm. When the gold electroplating layer is manufactured on a chemical gold plating layer, the gold electroplating layer in areas other than the through-hole needs to be electroplated to only 6.58 μm. Through comparison, by manufacturing the gold electroplating layer on a chemical gold plating layer, 30% of the electroplating gold can be saved, resulting in an effective reduction in the amount of gold used and thus lowering manufacturing costs. From another perspective, manufacturing the gold electroplating layer on a chemical gold plating layer achieves good filling of the through-holes.

[0064] It should be understood that during gold electroplating, the gold in the through-holes is relatively consumed and cannot be replenished in time. Therefore, the thickness of the gold electroplating layer inside and outside the through-holes cannot be made equal in the two processes.

[0065] Clearly, a person skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. In this case, this application is intended to encompass these modifications and variations to the embodiments of this application, provided that they fall within the scope of protection defined by the following claims and their equivalents. [Explanation of symbols]

[0066] 10 circuit boards 11 Through hole 20 Conductive Structures 30 Conductive plating layer 31 Adhesive layer 32 Chemical gold plating layer 33 Gold electroplating layer 100 Housing 200 circuit boards 300 chips b1 First side b2 Second side b3 hole wall

Claims

1. It's a tip, A substrate having a first surface and a second surface arranged opposite to each other, and through holes penetrating the first surface and the second surface, A conductive structure, wherein the conductive structure is located on the first surface and covers the through hole, A conductive plating layer, wherein the conductive plating layer is formed on the second surface, the side wall of the through hole, and the conductive structure and exposed from the through hole, and the conductive plating layer comprises an adhesive layer, a chemical gold plating layer, and a gold electroplating layer sequentially laminated from the first surface toward the second surface, the adhesive layer containing nickel element, and the conductive plating layer A chip equipped with this feature.

2. The chip according to claim 1, wherein the chemical gold plating layer at any position within the through hole has a first thickness, the chemical gold plating layer at any position on the second surface has a second thickness, and the ratio of the first thickness to the second thickness is 0.5 or more.

3. The chip according to claim 2, wherein any position within the through hole includes a position at half the depth of the through hole.

4. The chip according to any one of claims 1 to 3, wherein the thickness of the chemical gold plating layer at any position on the second surface is 300 nm or more.

5. The chip according to any one of claims 1 to 4, wherein the atomic percentage of the nickel element contained in the adhesive layer is 80% or more.

6. The chip according to any one of claims 1 to 5, wherein the adhesive layer comprises at least one of a nickel element and a nickel-containing inorganic compound.

7. The chip according to any one of claims 1 to 6, wherein the thickness of the adhesive layer is in the range of 0.1 μm to 0.5 μm.

8. A method for manufacturing chips, A step of forming a conductive structure on a substrate, wherein the substrate has a first surface and a second surface arranged opposite to each other, and through holes penetrating the first surface and the second surface, and the conductive structure is located on the first surface and covers the through holes, A step of forming an adhesive layer on the second surface, the side wall of the through hole, and the surface belonging to the conductive structure that is exposed from the through hole, wherein the adhesive layer contains nickel. The steps include forming a chemical gold plating layer on the adhesive layer, The steps include forming a gold electroplating layer on the chemical gold plating layer and A manufacturing method that includes this.

9. The step of forming the adhesive layer is, The step of forming the adhesive layer by using a physical vapor deposition method. The manufacturing method according to claim 8, including

10. The manufacturing method according to claim 8 or 9, wherein the chemical gold plating layer formed at any position within the through hole has a first thickness, the chemical gold plating layer formed at any position on the second surface has a second thickness, and the ratio of the first thickness to the second thickness is 0.5 or more.

11. The manufacturing method according to any one of claims 8 to 10, wherein the thickness of the chemical gold plating layer formed at any position on the second surface is 300 nm or more.

12. An electronic device comprising a circuit board and a chip according to any one of claims 1 to 7, wherein the chip is disposed on the circuit board.

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