Light-emitting element and display device containing the same

Abstract

The display device includes a first electrode and a second electrode spaced apart from each other on a substrate. The light-emitting element is positioned between the first electrode and the second electrode. The light-emitting element core of the light-emitting element includes a first semiconductor layer, a second semiconductor layer spaced apart from the first semiconductor layer, and a light-emitting layer positioned between the first and second semiconductor layers. The first element insulating layer surrounds the sides of the light-emitting element core. The first element insulating layer is an oxide insulating film having a single-crystal structure.

Description

Technical Field

[0001] The present invention relates to a light-emitting element and a display device including the same.

Background Art

[0002] Interest in information displays has been increasing, and there has been a growing demand to use portable information media, so the requirements and commercialization of display devices have been emphasized.

[0003] It should be understood that the above background art is provided in part to provide a useful background for understanding the technology. However, the background art may also include ideas, concepts, or recognitions that are not part of what was known or recognized by a person skilled in the relevant technical field before the effective filing date of the corresponding application for the subject matter disclosed herein.

Summary of the Invention

Problems to be Solved by the Invention

[0004] An object of the present invention is to provide a light-emitting element with improved element efficiency and reliability, and a display device including the same.

Means for Solving the Problems

[0005] A light-emitting element according to an embodiment of the present invention includes a light-emitting element core including a first semiconductor layer, a second semiconductor layer separated from the first semiconductor layer, and a light-emitting layer disposed between the first semiconductor layer and the second semiconductor layer; and a first element insulating layer surrounding a side surface of the light-emitting element core. The first element insulating layer is an oxide insulating film having a single crystal structure.

[0006] In a direction perpendicular to a side surface of the light-emitting element core, the thickness of the first element insulating layer may be greater than about 0 nm and less than or equal to about 10 nm.

[0007] The first element insulating layer may include a metal oxide containing two or more metal elements.

[0008] The two or more metallic elements mentioned above may be one or more selected from the group consisting of Ta, Hf, Zr, La, Si, Ti, and Al.

[0009] The first element insulating layer includes a first metal element, and at least a portion of the light-emitting core includes a base element, wherein the binding energy of the oxide to the first metal element can be greater than the binding energy of the base element to the oxide.

[0010] The ionic radius of the first metal element may be larger than the ionic radius of the base element in the oxide.

[0011] The first element insulating layer may be disposed directly on the side surface of the light-emitting element core.

[0012] The light-emitting element may further include a second element insulating layer that surrounds the outer surface of the first element insulating layer.

[0013] The second element insulating layer may be an oxide insulating film having an amorphous or polycrystalline structure.

[0014] The first element insulating layer and the second element insulating layer may contain only the same material as each other.

[0015] The light-emitting element may further include a third element insulating layer surrounding the outer surface of the second element insulating layer.

[0016] The first element insulating layer has a superlattice layer structure in which a first layer and a second layer containing different materials are alternately stacked in multiple layers, and the first layer and the second layer may be stacked in a direction perpendicular to the side surface of the light-emitting core.

[0017] The first and second layers may each be oxide insulating films having a single-crystal structure.

[0018] In a direction perpendicular to the side surface of the light-emitting element core, the thickness of the first layer and the second layer, respectively, may be greater than about 0 nm and less than or equal to about 10 nm.

[0019] An embodiment of the present invention includes a first electrode and a second electrode arranged on a substrate and spaced apart from each other; and a light-emitting element disposed between the first electrode and the second electrode. The light-emitting element includes a light-emitting core comprising a first semiconductor layer, a second semiconductor layer spaced apart from the first semiconductor layer, and a light-emitting layer disposed between the first semiconductor layer and the second semiconductor layer; and a first element insulating layer surrounding the side surface of the light-emitting core. The first element insulating layer is an oxide insulating film having a single-crystal structure.

[0020] In a direction perpendicular to the side surface of the light-emitting element core, the first element insulating layer can have a thickness greater than about 0 nm and less than or equal to about 10 nm.

[0021] The first element insulating layer may include a metal oxide containing two or more metal elements.

[0022] The two or more metallic elements mentioned above may be one or more selected from the group consisting of Ta, Hf, Zr, La, Si, Ti, and Al.

[0023] The light-emitting element further includes a second element insulating layer surrounding the outer surface of the first element insulating layer, and the second element insulating layer may be an oxide insulating film having an amorphous or polycrystalline structure.

[0024] The first element insulating layer has a superlattice layer structure in which a first layer and a second layer containing different materials are alternately stacked in multiple layers, the first layer and the second layer are stacked in a direction perpendicular to the side surface of the light-emitting core, and the first layer and the second layer may each be an oxide insulating film having a single crystal structure. [Effects of the Invention]

[0025] In the light-emitting device according to an embodiment of the present invention, the oxide insulating film having a single-crystal structure can directly surround the side surface of the light-emitting device core including the semiconductor layer. In this case, the light-emitting device core can have the effect of being surface-treated, and the surface defects of the light-emitting device core can be improved. The oxide insulating film can prevent the diffusion of impurities into the light-emitting device core, and thereby, the device efficiency and reliability of the light-emitting device can be improved.

[0026] The above and other features of the present invention will become more apparent by describing the detailed embodiments of the present invention with reference to the accompanying drawings.

Brief Description of the Drawings

[0027] [Figure 1] It is a schematic perspective view of a light-emitting device according to an embodiment. [Figure 2] It is a schematic cross-sectional view showing an embodiment of the light-emitting device of FIG. 1. [Figure 3] It is a schematic cross-sectional view showing an embodiment of the light-emitting device of FIG. 1. [Figure 4] It is a schematic cross-sectional view showing an embodiment of the light-emitting device of FIG. 1. [Figure 5] It is a schematic cross-sectional view showing an embodiment of the light-emitting device of FIG. 1. [Figure 6] It is an enlarged view of the P region of FIG. 5. [Figure 7] It is a schematic cross-sectional view showing an embodiment of the light-emitting device of FIG. 1. [Figure 8] It is a schematic cross-sectional view showing an embodiment of the light-emitting device of FIG. 1. [Figure 9] It is a schematic perspective view of a light-emitting device according to an embodiment. [Figure 10] It is a schematic perspective view of a light-emitting device according to an embodiment. [Figure 11] It is a process cross-sectional view showing the manufacturing method of the light-emitting device of FIG. 1. [Figure 12] It is a process cross-sectional view showing the manufacturing method of the light-emitting device of FIG. 1. [Figure 13] It is a process cross-sectional view showing the manufacturing method of the light-emitting device of FIG. 1. [Figure 14]Figure 1 is a cross-sectional view showing the process for manufacturing a light-emitting element. [Figure 15] Figure 1 is a cross-sectional view showing the process for manufacturing a light-emitting element. [Figure 16] Figure 1 is a cross-sectional view showing the process for manufacturing a light-emitting element. [Figure 17] Figure 1 is a cross-sectional view showing the process for manufacturing a light-emitting element. [Figure 18] This is a schematic plan view of a display device according to one embodiment. [Figure 19] This is a schematic plan view showing one embodiment of pixels included in the display device shown in Figure 18. [Figure 20] Figure 19 is a schematic cross-sectional view showing one embodiment of a pixel cut along the line I-I'. [Figure 21] This is a schematic cross-sectional view showing an enlarged version of the Q region in Figure 20, illustrating one embodiment. [Figure 22] This is a schematic cross-sectional view showing an enlarged version of the Q region in Figure 20, illustrating one embodiment. [Figure 23] This is a schematic cross-sectional view showing an enlarged version of the Q region in Figure 20, illustrating one embodiment. [Figure 24] This is a schematic cross-sectional view showing an enlarged version of the Q region in Figure 20, illustrating one embodiment. [Modes for carrying out the invention]

[0028] Since the present invention can be modified in various ways and may take on various forms, the present invention includes the given embodiments. However, the embodiments are not limited to those disclosed and can be applied to any modifications and equivalents. Exemplary embodiments are described in more detail below with reference to the accompanying drawings. However, the embodiments described herein are not limited and can be embodied in other forms. Rather, these embodiments are provided so as to make the present invention thorough and complete, and the scope of the exemplary embodiments will be fully communicated to those skilled in the art.

[0029] In drawings, dimensions may be exaggerated to clarify the explanation. When a component is described as being "between" two components, understand that it may be the sole component between the two components, or there may be one or more intervening components. Similar reference numbers refer to similar elements overall.

[0030] As used herein, the singular forms ("a", "an", "the") are used when contextually clear. Unless otherwise indicated, it is intended to include the plural form.

[0031] In the specification and claims, the term “and / or” is intended, for the purposes of its meaning and interpretation, to include any combination of the terms “and” and “or.” For example, “A and / or B” can be understood to mean “A, B or A and B.” The terms “and” and “or” may be used in a conjugated or separable sense and can be understood as equivalent to “and / or.”

[0032] In the specification and claims, the expression “at least one of ~” is intended, for the purposes of its meaning and interpretation, to include “at least one selected from the group of ~.” For example, “at least one of A and B” means “A, B, or A It can be understood that this means "and B".

[0033] Terms such as "first," "second," etc., are used to describe various components, but the components should not be limited by such terms. The terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, a "first" component may be called a "second" component, and similarly, a "second" component may be called a "first" component.

[0034] In this application, terms such as “comprises, comprising, and / or including” or “has, have, and / or having” should be understood to indicate the existence of features, figures, stages, operations, components, parts, or combinations thereof as described in the specification, and not to preemptively exclude the possibility of the existence or addition of one or more other features, figures, stages, operations, components, parts, or combinations thereof.

[0035] Furthermore, when we say that a layer, film, region, plate, or other part is "on top of" another part, this includes not only the case where it is "directly on top" of the other part, but also the case where there are other parts in between.

[0036] Furthermore, in this specification, when a part such as a layer, membrane, region, or plate is said to be formed on top of another part, the direction of formation is not limited to the upward direction, but also includes formation in the side or downward direction. Conversely, when a part such as a layer, membrane, region, or plate is said to be "below" another part, this includes not only the case where it is "directly below" the other part, but also the case where there is another part in between.

[0037] The term “overlap” or “overlapped” means that the first object can be on top of, below, or to the side of the second object, and vice versa. Furthermore, the term “overlap” may include layer, stack, face or confront, extend, cover, partially cover, or any other appropriate term that a person skilled in the art would recognize and understand.

[0038] Element does not overlap with other elements (not overlapping or do not Where it is written as 'overlap', this may include any other appropriate term that a person skilled in the art can recognize and understand, meaning that the elements are separated from each other, offset from each other, or apart from each other.

[0039] The terms “face” and “facing” mean that the first component can face the second component directly or indirectly. When a third component is present between the first and second components, the first and second components are still facing each other, but can be understood as facing each other indirectly.

[0040] In the following description, when we say that one part is connected to another part, this includes not only cases where they are directly connected, but also cases where they are electrically connected with other elements in between. In one embodiment of the present invention, “connection” between two components can be used to encompass both electrical and physical connections.

[0041] As used herein, “about” or “approximately” means within an acceptable range of deviation for a particular value, as determined by a person skilled in the art, taking into account the measurement of a particular quantity and the associated error (i.e., the limits of the measuring system), including the stated value. For example, “about” may mean within one or more standard deviations, or within ±30%, 20%, 10%, or 5% of the stated value.

[0042] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as those generally understood by a person of ordinary skill in the art to which this invention pertains. Terms as defined in commonly used dictionaries should be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and it will be understood that they should not be interpreted in an ideal or overly formal sense.

[0043] The following describes a display device according to an embodiment, with reference to the drawings.

[0044] Figure 1 is a schematic perspective view of a light-emitting element according to an embodiment. Figure 2 is a schematic cross-sectional view showing one embodiment of the light-emitting element of Figure 1.

[0045] Referring to Figures 1 and 2, the light-emitting element ED is a particulate element and may be a rod or cylindrical shape having a predetermined aspect ratio. The light-emitting element ED has a shape that extends in one direction X, and the length of the light-emitting element ED in the one direction X is greater than the diameter of the light-emitting element ED, and the aspect ratio may be 1.2:1 to 100:1. However, it is not limited thereto, and for example, the light-emitting element ED may have the shape of a cylinder, rod, wire, tube, etc., or it may have the shape of a cube, rectangular parallelepiped, hexagonal prism, or other polygonal prism, or it may have a shape that extends in one direction and has a partially inclined outer surface.

[0046] The light-emitting element (ED) can have a size on the nanometer scale (approximately 1 nm to less than approximately 1 μm) or the micrometer scale (approximately 1 μm to less than approximately 1 mm). In one embodiment, the light-emitting element (ED) may have a diameter and / or length on the nanometer scale, or both may be on the micrometer scale. In one embodiment, the diameter of the light-emitting element (ED) may be on the nanometer scale, and the length of the light-emitting element (ED) may be on the micrometer scale. According to the embodiment, some light-emitting elements (ED) may have a diameter and / or length on the nanometer scale, while other light-emitting elements (ED) may have a diameter and / or length on the micrometer scale.

[0047] In one embodiment, the light-emitting element ED may be an inorganic light-emitting diode. The inorganic light-emitting diode may include a plurality of semiconductor layers. For example, the inorganic light-emitting diode may include a first conductivity type (e.g., n-type) semiconductor layer, a second conductivity type (e.g., p-type) semiconductor layer, and an active semiconductor layer interposed between them. The active semiconductor layer is supplied with holes and electrons from the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, respectively, and the holes and electrons that reach the active semiconductor layer can combine with each other to emit light.

[0048] The light-emitting element ED may include a light-emitting element core 30, a first element insulating layer 39, and a second element insulating layer 38.

[0049] The light-emitting element core 30 may have a shape that extends in one direction X. The light-emitting element core 30 may be rod-shaped or cylindrical. However, it is not limited to these, and for example, the light-emitting element core 30 may have the shape of a cube, a rectangular parallelepiped, a polygonal prism such as a hexagonal prism, or a shape that extends in one direction X and has a partially inclined outer surface.

[0050] The light-emitting element core 30 may include a first semiconductor layer 31, a second semiconductor layer 32, a light-emitting layer 33, and an element electrode layer 37. The first semiconductor layer 31, the light-emitting layer 33, the second semiconductor layer 32, and the element electrode layer 37 may be stacked sequentially on each other along one direction X.

[0051] The first semiconductor layer 31 may be doped with a first conductivity type dopant. The first conductivity type is n-type, and the first conductivity type dopant may be Si, Ge, Sn, or similar within the scope of the present invention. For example, the first semiconductor layer 31 may be an n-type semiconductor. For example, the first semiconductor layer 31 may be n-GaN doped with n-type Si.

[0052] The second semiconductor layer 32 may be arranged apart from the first semiconductor layer 31, with the light-emitting layer 33 in between. The second semiconductor layer 32 may be doped with a second conductivity type dopant. The second conductivity type is p-type, and the second conductivity type dopant may be Mg, Zn, Ca, Sr, Ba, or similar within the scope of the present invention. For example, the second semiconductor layer 32 may be a p-type semiconductor. For example, the second semiconductor layer 32 may be p-GaN doped with p-type Mg.

[0053] The first semiconductor layer 31 and the second semiconductor layer 32 may each consist of a single layer, but are not limited to this. For example, depending on the material contained in the light-emitting layer 33, at least one of the first semiconductor layer 31 and the second semiconductor layer 32 may consist of more layers, such as a clad layer or TSBR (Tensile Strain Barrier). It may also include a (reducing) layer.

[0054] The light-emitting layer 33 may be placed between the first semiconductor layer 31 and the second semiconductor layer 32. The light-emitting layer 33 may include a single or multiple quantum well structure. The light-emitting layer 33 can emit light through electron-hole pair coupling in response to an electrical signal applied via the first semiconductor layer 31 and the second semiconductor layer 32. For example, if the light-emitting layer 33 emits light in the blue wavelength range, it may include, but is not limited to, materials such as AlGaN and AlGaInN.

[0055] In the embodiment, the light-emitting layer 33 may have a structure in which semiconductor materials of a type with a large bandgap energy and semiconductor materials with a small bandgap energy are alternately stacked, or it may contain different group III to V semiconductor materials depending on the wavelength band of the emitted light. The light emitted by the light-emitting layer 36 is not limited to light in the blue wavelength band, and may optionally emit light in the red or green wavelength band.

[0056] Light emitted from the light-emitting layer 33 can be emitted not only from the end faces of the light-emitting element ED, but also from the sides of the light-emitting element ED. The direction of light emission from the light-emitting layer 33 is not limited to a specific direction.

[0057] To apply an electrical signal to the first semiconductor layer 31 and the second semiconductor layer 32, both ends of the light-emitting element ED are electrically connected to an external electrode, and the element electrode layer 37 can be placed between the second semiconductor layer 32 and the external electrode to reduce resistance. The element electrode layer 37 may include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), and ITZO (Indium Tin-Zinc Oxide). According to the embodiment, the element electrode layer 37 may include an n-type or p-type doped semiconductor material.

[0058] The device electrode layer 37 may, but is not limited to, be located on the second semiconductor layer 32. For example, another device electrode layer may be located further below the first semiconductor layer 31.

[0059] The first element insulating layer 39 may be arranged to surround the side (or outer periphery) of the light-emitting element core 30. The first element insulating layer 39 may be arranged to enclose the side of the semiconductor layer (and element electrode layer 37) included in the light-emitting element core 30. The first element insulating layer 39 may be arranged to surround at least the side of the first semiconductor layer 31, the light-emitting layer 33, and the second semiconductor layer 32, and may extend in one direction X.

[0060] The first element insulating layer 39 surrounds the sides of the light-emitting element core 30, but allows both end faces of the light-emitting element core 30 to be exposed. Because the first element insulating layer 39 is not placed on both end faces of the light-emitting element core 30 (for example, the top and bottom faces of the light-emitting element core 30 in Figure 1), the element electrode layer 37 and the first semiconductor layer 31 of the light-emitting element core 30 can be exposed by the first element insulating layer 39.

[0061] In one embodiment, the first element insulating layer 39 may include an insulating material having a single-crystal structure. For example, the first element insulating layer 39 may be a single-crystal insulating layer. The insulating material included in the first element insulating layer 39 may be a material having a higher dielectric constant than the material included in the semiconductor layer of the light-emitting element core 30. For example, the dielectric constant of the material included in the first element insulating layer 39 may be greater than the dielectric constant of the material included in the semiconductor layer of the light-emitting element core 30. By including an insulating material with a large dielectric constant and a single-crystal structure in the first element insulating layer 39, the first element insulating layer 39 can improve surface defects in the semiconductor layer included in the light-emitting element core 30, which will be described later.

[0062] In exemplary embodiments in which the first semiconductor layer 31, the second semiconductor layer 32, and the light-emitting layer 33 include gallium nitride (GaN), the first element insulating layer 39 may include a single-crystal insulating material having a dielectric constant greater than that of GaN. For example, the first element insulating layer 39 may include aluminum nitride (AlN) having a single-crystal structure, aluminum oxide (AlxOy) having a single-crystal structure, or similar materials within the scope of the present invention.

[0063] The first element insulating layer 39 may be directly positioned on the side surface of the light-emitting element core 30. The first element insulating layer 39 may be positioned so as to be in direct contact with the side surface of the light-emitting element core 30. Therefore, the inner surface of the first element insulating layer 39 can be in contact with the side surface of the light-emitting element core 30. In this case, the first element insulating layer 39 can surface-treat the side surfaces of the first semiconductor layer 31, the second semiconductor layer 32, and the light-emitting layer 33 of the light-emitting element core 30 to improve surface defects that occur on the side surfaces of the semiconductor layers of the light-emitting element core 30. Surface defects formed on the side surface of the light-emitting element core 30 may be defects that occur on the surface of the semiconductor layer exposed to the etchant at the outermost edge during the etching process for forming the light-emitting element core 30 in the manufacturing process of the light-emitting element ED described later. Surface defects can cause leakage of electrons injected into the semiconductor layer or trapping of holes, hindering the coupling of electrons and holes and reducing the optical efficiency of the light-emitting element ED. When the first element insulating layer 39 having a single-crystal structure is directly placed on or formed on the side surface of the light-emitting element core 30, the side surface of the light-emitting element core 30 can have the effect of surface treatment. For example, the dislocation density on the surface of the light-emitting element core 30 can be reduced. Therefore, surface defects formed on the side surface of the light-emitting element core 30 can be improved by the first element insulating layer 39, and the element efficiency and reliability of the light-emitting element ED can be improved.

[0064] Furthermore, the first element insulating layer 39, by being interposed between the light-emitting element core 30 and the second element insulating layer 38, can prevent defects formed inside the second element insulating layer 38 or the diffusion of impurities from the second element insulating layer 38 to the multiple semiconductor layers of the light-emitting element core 30 (for example, the first semiconductor layer 31, the second semiconductor layer 32, and the light-emitting layer 33). For example, the first element insulating layer 39 can be interposed between the light-emitting element core 30 and the second element insulating layer 38, and can physically separate them.

[0065] The first element insulating layer 39 may have a predetermined thickness d1 in a direction perpendicular to the side surface of the light-emitting element core 30. In other words, the first element insulating layer 39 may be formed within a distance corresponding to the thickness d1 from the side surface of the light-emitting element core 30. The first element insulating layer 39 formed on the side surface of the light-emitting element core 30 can be formed by forming a first insulating material layer 390 having a single-crystal structure on the side surface (or outer circumferential surface) of the light-emitting element core 30, as described later, and then removing a portion of it. On the other hand, in order for the first element insulating layer 39 to maintain a single-crystal structure, the thickness d1 of the first element insulating layer 39 must be formed to be less than or equal to a critical thickness. The 'critical thickness' can be defined as the thickness at which the thin film maintains a single-crystal structure in the process of forming a thin film. In one embodiment, the thickness d1 of the first element insulating layer 39 may be within a range less than or equal to the critical thickness of the material contained in the first element insulating layer 39. For example, if the first element insulating layer 39 contains zirconium oxide (ZrOx), the critical thickness may be approximately 10 nm. In this case, the thickness d1 of the first element insulating layer 39 can be greater than approximately 0 nm and less than or equal to approximately 10 nm. For example, the thickness d1 of the first element insulating layer 39 can be approximately 5 nm. For reference, when a thin film is formed on the light-emitting element core 30 to a thickness below the critical thickness, the crystal structure of the thin film becomes similar to the crystal structure of the light-emitting element core 30, and as a result, the thin film can have a single-crystal structure. In contrast, when a thin film is formed to a thickness exceeding the critical thickness, the thin film has its own (or independent) crystal structure, regardless of the crystal structure of the light-emitting element core 30, and for example, the thin film can have an amorphous or polycrystalline structure. For example, in a thin film containing zirconium oxide (ZrOx), when formed to a thickness of approximately 10 nm or less, the thin film has a tetragonal crystal structure, and when the thickness exceeds 10 nm, the thin film can have an amorphous structure.

[0066] In the embodiment, the first element insulating layer 39 may be an oxide insulating film. For reference, the first element insulating layer 39 may be an insulating film containing a group III-V semiconductor compound, for example, a nitride insulating film. However, forming the nitride insulating film may require a high-temperature process and specific reaction gases compared to forming an oxide insulating film. In other words, oxide insulating films can be formed more easily than nitride insulating films (or insulating films containing III-V semiconductor compounds), and oxide The manufacturing cost of the light-emitting element ED, which includes the first element insulating layer 39, can be reduced. Furthermore, if the second element insulating layer 38, described later, contains the same material as the first element insulating layer 39, the manufacturing process of the light-emitting element ED can be further simplified, and the manufacturing cost can be reduced even further.

[0067] In the embodiment, the first element insulating layer 39 may include a metal oxide containing two or more metal elements. For example, the two or more metal elements may be one or more selected from the group consisting of tantalum (Ta), hafnium (Hf), zirconium (Zr), lanthanum (La), silicon (Si), titanium (Ti), and aluminum (Al). For example, the first element insulating layer 39 may include zirconium oxide (ZrxOy) and aluminum oxide (AlxOy). Experimentally, when the first element insulating layer 39 contains two or more metal elements, the stability of the first element insulating layer 39 can be improved compared to when it contains only one metal element.

[0068] In one embodiment, the first element insulating layer 39 may contain a first metallic element. The first metallic element can be selected based on the physical properties of a base element for forming at least a portion of the light-emitting core 30. The base element may refer to the material forming the first semiconductor layer 31, the second semiconductor layer 32, and the light-emitting layer 33.

[0069] For example, if the first semiconductor layer 31 contains n-GaN, the second semiconductor layer 32 contains p-GaN, and / or the light-emitting layer 33 contains a gallium-based material, the base element may be gallium. As another example, if at least one of the first semiconductor layer 31, the second semiconductor layer 32, and the light-emitting layer 33 contains a phosphide-based material (e.g., lnP), the base element may be phosphorus (P).

[0070] In the embodiment, the bond-dissociation energy of the oxide formed by the first metal element may be greater than the bond energy of the base element for forming the light-emitting element core 30.

[0071] Experimentally, if the binding energy of the material forming the first element insulating layer 39 is greater than the binding energy of the material forming the light-emitting element core 30, the impact on the light-emitting element core 30 can be minimized, and the first element insulating layer 39 can be formed more stably. Therefore, according to the embodiment, the risk of the first element insulating layer 39 impairing the luminescence efficiency of the light-emitting element ED can be prevented.

[0072] In one embodiment, when the base element is gallium and the first semiconductor layer 31 and the second semiconductor layer 32 contain GaN, the bond energy of the oxide to the first metal element may be greater than about 200 kJ / mol in order to satisfy the bond energy condition. For example, the first metal element may be one or more selected from the group consisting of Ta, Hf, Zr, La, Si, Ti, and Al.

[0073] For example, the bond energy of gallium nitride (GaN) can be approximately 200 kJ / mol. The bond energy of silicon oxide (SixOy) can be approximately 799.6 kJ / mol. The bond energy of aluminum oxide (AlxOy) can be approximately 501.9 kJ / mol. The bond energy of titanium oxide (TixOy) can be approximately 666.5 kJ / mol. The bond energy of tantalum oxide (TaxOy) can be approximately 839 kJ / mol. The bond energy of hafnium oxide (HfxOy) can be approximately 762 kJ / mol. The bond energy of zirconium oxide (ZrxOy) can be approximately 766.1 kJ / mol. The bond energy of lanthanum oxide (LaxOy) can be approximately 798 kJ / mol. As a result, when the first metal element is selected from the examples mentioned above, and the first semiconductor layer 31 and the second semiconductor layer 32 are GaN, the binding energy condition is met, and the stability of the first device insulating layer 39 can be improved.

[0074] In the embodiment, if the binding energy of the material forming the first element insulating layer 39 is greater than the binding energy of the material forming the interface of the light-emitting element core 30, the influence on the light-emitting element core 30 can be minimized, and the first element insulating layer 39 can be formed more stably. An interface of the light-emitting element core 30 is formed between the light-emitting element core 30 and the first element insulating layer 39, and this interface of the light-emitting element core 30 can mean the boundary region between the light-emitting element core 30 and the first element insulating layer 39. Since the first element insulating layer 39 contains an oxide, an oxide of the base element may be formed at the interface of the light-emitting element core 30. For example, if the first semiconductor layer 31 and the second semiconductor layer 32 contain GaN, gallium oxide may be formed at the interface of the light-emitting element core 30.

[0075] In one embodiment, when the base element is gallium and the interface of the light-emitting element core 30 contains gallium oxide, the binding energy of the oxide to the first metal element may be greater than about 545 kJ / mol in order to satisfy the binding energy condition. For example, the first metal element may be one or more selected from the group consisting of Ta, Hf, Zr, La, Si, and Ti. For example, the binding energy of the oxide to each element may be as described above, and the binding energy of gallium oxide may be about 545 kJ / mol. Thus, when the first metal element is selected from the above examples and the interface of the light-emitting element core 30 contains gallium oxide, the binding energy condition is satisfied and the stability of the first element insulating layer 39 can be improved.

[0076] In the embodiment, the ionic radius of the first metal element in the oxide formed by the first metal element may be greater than the ionic radius of the base element in the oxide formed by the base element. In this case, it may be difficult for the first metal element to pass through the interface of the light-emitting element core 30 and penetrate into the light-emitting element core 30.

[0077] Experimentally, if an unintended metallic substance penetrates the interior of the light-emitting element ED, stress may be generated due to lattice mismatch between the penetrating metallic substance and the light-emitting element core 30. However, since the ionic radius of the first metallic element is selected according to specific criteria, making it difficult for it to penetrate into the light-emitting element core 30 of the light-emitting element ED, the aforementioned risk can be substantially eliminated.

[0078] In one embodiment, when the base element is gallium, the ionic radius for the first metal element may be greater than approximately 0.62 A. For example, the first metal element may be Zn, Ta, or Hf. It may contain one or more of the following: , Zr, and La.

[0079] For example, the ionic radius of gallium in gallium oxide can be approximately 0.62 Å. The ionic radius of silicon in tantalum oxide can be approximately 0.64 Å. (Hafnium) The ionic radius of silicon in oxides can be approximately 0.71 Å. (Zirconium oxide) The ionic radius of silicon in lanthanum oxide can be approximately 0.78 A. The ionic radius of ricon can be approximately 1.032 A. The diameter can be approximately 0.74A to approximately 0.88A. This ensures that, when the first metal element is selected from the examples described above, the ionic radius requirement is met when the gallium oxide structure is formed at the interface of the light-emitting element core 30, thereby preventing the risk of the metallic material penetrating the light-emitting element core 30.

[0080] On the other hand, if the base element in the light-emitting element core 30 is gallium, the first metallic element can include one or more of Ta, Hf, Zr, and La. In this case, a first element insulating layer 39 that satisfies both the binding energy condition and the ionic radius condition described above can be provided.

[0081] The second element insulating layer 38 may be placed on the outer surface (or outer peripheral surface) of the first element insulating layer 39. The second element insulating layer 38 may be placed so as to surround the outer surface of the first element insulating layer 39. The second element insulating layer 38 may extend in one direction X.

[0082] Similar to the first element insulating layer 39, the second element insulating layer 38 covers the sides of the light-emitting element core 30, but leaves both end faces of the light-emitting element core 30 exposed. According to the embodiment, the second element insulating layer 38 may cover only at least a portion of the sides of the light-emitting element core 30. For example, the second element insulating layer 38 may cover only the sides of some semiconductor layers, including the light-emitting layer 33. As another example, the second element insulating layer 38 may cover some areas of the sides of the element electrode layer 37, while leaving other areas of the sides of the element electrode layer 37 exposed.

[0083] The second element insulating layer 38 can protect the first semiconductor layer 31, the second semiconductor layer 32, and the light-emitting layer 33 of the light-emitting element core 30. The second element insulating layer 38 can prevent electrical short circuits that occur when the external electrodes that transmit electrical signals to the light-emitting element ED come into direct contact with the light-emitting layer 33.

[0084] The second element insulating layer 38 may contain a material having insulating properties. For example, the second element insulating layer 39 may contain silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlN), aluminum oxide (AlxOy), titanium oxide (TiOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), or equivalent materials within the scope of the present invention.

[0085] In one embodiment, the second element insulating layer 38 may be an oxide insulating film containing the same material as the first element insulating layer 39. For example, the second element insulating layer 38 and the first element insulating layer 39 may contain hafnium oxide (HfOx), zirconium oxide (ZrOx), or equivalent materials within the scope of the present invention.

[0086] In one embodiment, the thickness of the second element insulating layer 38 in the direction perpendicular to the side surface of the light-emitting element core 30 may be greater than the critical thickness (e.g., about 10 nm). In this case, the second element insulating layer 38 can more stably protect the light-emitting element core 30 (and the first element insulating layer 39) from external influences. Since the thickness of the second element insulating layer 38 is greater than the critical thickness, the second element insulating layer 38 can have an amorphous or polycrystalline structure.

[0087] As described above, the light-emitting element ED includes a first element insulating layer 39 that is arranged to surround the side surface of the light-emitting element core 30 which includes a semiconductor layer, and the first element insulating layer may have a single crystal structure.

[0088] The first element insulating layer 39, which has a single-crystal structure, prevents the diffusion of impurities from the second element insulating layer 38 to the semiconductor layer of the light-emitting element core 30, and can physically separate the internal defects of the second element insulating layer 38 from the semiconductor layer of the light-emitting element core 30.

[0089] Furthermore, the first element insulating layer 39, which has a single-crystal structure, can surface-treat the sides of the first semiconductor layer 31, the second semiconductor layer 32, and the light-emitting layer 33 of the light-emitting element core 30, thereby improving surface defects that occur on the sides of the semiconductor layers of the light-emitting element core 30. Therefore, the element efficiency and reliability of the light-emitting element ED can be improved.

[0090] Figure 3 is a schematic cross-sectional view showing one embodiment of the light-emitting element of Figure 1.

[0091] Referring to Figures 1 to 3, the light-emitting element ED in Figure 3 differs from the embodiment in Figure 2 in that it does not include the second element insulating layer 38.

[0092] The thickness of the first element insulating layer 39 is not limited, as it protects multiple semiconductor layers of the light-emitting element core 30. The thickness of the first element insulating layer 39 may be about 10 nm or less, but is not limited thereto. The thickness of the first element insulating layer 39 may vary depending on the formation method.

[0093] Figure 4 is a schematic cross-sectional view showing one embodiment of the light-emitting element of Figure 1.

[0094] Referring to Figures 2 and 4, Figure 4 differs from the embodiment in Figure 2 in that the second element insulating layer 38_1 of the light-emitting element ED includes a sub-insulating layer.

[0095] The second element insulating layer 38_1 may include the first sub-insulating layer 381 and the second sub-insulating layer 382 (or the third element insulating layer).

[0096] The first sub-insulating layer 381 may be placed on the outer surface (or outer peripheral surface) of the first element insulating layer 39. The first sub-insulating layer 381 may be placed so as to surround the outer surface of the first element insulating layer 39. The structure and material of the first sub-insulating layer 381 may be substantially the same as the structure and material of the second element insulating layer 38 in Figure 2.

[0097] The second sub-insulating layer 382 may be positioned on the outer surface (or outer peripheral surface) of the first sub-insulating layer 381. The second sub-insulating layer 382 may be positioned to surround the outer surface of the first sub-insulating layer 381 and extend in one direction X. Similar to the first sub-insulating layer 381, the second sub-insulating layer 382 may cover the sides of the light-emitting element core 30, while leaving both end surfaces of the light-emitting element core 30 exposed.

[0098] The second sub-insulating layer 382 can protect the first sub-insulating layer 381. For example, the second sub-insulating layer 382 can be positioned to surround the outer surface of the first sub-insulating layer 381 to prevent damage to the first sub-insulating layer 381 or the light-emitting element core 30 during the manufacturing process of the display device 10 (see Figure 18) in the process of forming the second insulating layer 520 (see Figure 20) and / or other components of the display device 10. The second sub-insulating layer 382 may include the material that constitutes the second element insulating layer 38 in Figure 2.

[0099] The first sub-insulating layer 381 and the second sub-insulating layer 382 may, but are not limited to, contain different materials. For example, the first sub-insulating layer 381 and the second sub-insulating layer 382 may contain the same material.

[0100] Figure 5 is a schematic cross-sectional view showing one embodiment of the light-emitting element of Figure 1. Figure 6 is an enlarged view of region P in Figure 5.

[0101] Referring to Figures 2, 5, and 6, the embodiment in Figure 2 differs from the embodiment in that the first element insulating layer 39_1 of the light-emitting element ED has a superlattice structure.

[0102] The first element insulating layer 39_1 has a superlattice layer structure in which the first layer 391 and the second layer 392 are repeatedly stacked alternately on each other in a direction perpendicular to the side surface of the light-emitting element core 30, and the first layer 391 and the second layer 392 may each be oxide insulating films having a single crystal structure.

[0103] In Figure 5, the first layer 391 and the second layer 392 are shown to be stacked alternately three times, but the structure is not limited to this. For example, the first element insulating layer 39_1 may have a structure in which the first layer 391 and the second layer 392 are stacked alternately fewer times, or it may have a structure in which they are stacked alternately more times.

[0104] The first layer 391 may be directly placed on the side (or outer periphery) of the light-emitting element core 30 and may be arranged to surround the outer surface of the light-emitting element core 30, and the second layer 392 may be placed on the outer surface of the first layer 391 and may be arranged to surround the outer surface of the first layer 391.

[0105] The structure (e.g., thickness) and material of the first layer 391 and the second layer 392 may be substantially the same as the structure and material of the first element insulating layer 39 in Figure 2. For example, the thickness of the first layer 391 and the second layer 392 may be about 10 nm or less. The thickness of the first layer 391 and the second layer 392 may be the same, but are not limited to this; for example, the thicknesses of the first layer 391 and the second layer 392 may be different from each other. The first layer 391 and the second layer 392 may contain different materials from those that constitute the first element insulating layer 39.

[0106] Because the first element insulating layer 39_1 has a superlattice layer structure, the overall thickness d1 of the first element insulating layer 39_1 can be thicker than when it contains a single single-crystal insulating film. Therefore, multiple layers having a single-crystal structure can be formed, which can more efficiently improve surface defects in the light-emitting element core 30 and also improve the insulating reliability of the first element insulating layer 39_1.

[0107] When the first element insulating layer 39_1 has a superlattice layer structure, the first layer 391 and the second layer 392 included in the first element insulating layer 39_1 can be formed by metal-organic chemical vapor deposition (MOCVD) or atomic layer deposition (ALD), respectively. In an exemplary embodiment, the first layer 391 and the second layer 392 included in the first element insulating layer 39_1 can be formed by atomic layer deposition performed at low temperatures.

[0108] As described above, the first element insulating layer 39_1 has a superlattice layer structure in which layers are stacked alternately with each other, thereby allowing the first element insulating layer 39_1 to maintain a single crystal structure despite having a thick thickness d1. As a result, the first element insulating layer 39_1 can efficiently prevent the diffusion of impurities from the outside or from the second element insulating layer 38 to the semiconductor layer of the light-emitting element core 30. Therefore, the element efficiency and reliability of the light-emitting element ED can be further improved.

[0109] Figure 7 is a schematic cross-sectional view showing one embodiment of the light-emitting element of Figure 1.

[0110] Referring to Figures 5 and 7, Figure 7 differs from the embodiment in Figure 5 in that the second element insulating layer 38_1 of the light-emitting element ED includes multiple sub-insulating layers.

[0111] The second element insulating layer 38_1 may include a first sub-insulating layer 381 and a second sub-insulating layer 382.

[0112] Since the first sub-insulating layer 381 and the second sub-insulating layer 382 have been explained with reference to Figure 4, a further explanation of the first sub-insulating layer 381 and the second sub-insulating layer 382 will be omitted.

[0113] Figure 8 is a schematic cross-sectional view showing one embodiment of the light-emitting element of Figure 1.

[0114] Referring to Figures 7 and 8, the embodiment in Figure 7 differs from the embodiment in that the second element insulating layer 38_2 of the light-emitting element ED includes a first sub-insulating layer 381 and a third sub-insulating layer 383, and the first element insulating layer 39_1 having a superlattice layer structure is interposed between the first sub-insulating layer 381 and the third sub-insulating layer 383.

[0115] The third sub-insulating layer 383 may be arranged to surround the side surface of the light-emitting element core 30. The third sub-insulating layer 383 may be arranged directly on the side surface of the light-emitting element core 30. The third sub-insulating layer 383 may contain a material having insulating properties. The third sub-insulating layer 383 may contain the material that constitutes the second element insulating layer 38 in Figure 2.

[0116] The first sub-insulating layer 381 may be positioned on the outer surface of the third sub-insulating layer 383 and may be positioned to surround the outer surface of the third sub-insulating layer 383. The first sub-insulating layer 381 may be separated from the third sub-insulating layer 383.

[0117] The first element insulating layer 39_1 may be placed between the first sub-insulating layer 381 and the third sub-insulating layer 383. The first element insulating layer 39_1 may be placed on the outer surface of the third sub-insulating layer 383, and the first sub-insulating layer 381 may be placed on the outer surface of the first element insulating layer 39_1.

[0118] Figures 9 and 10 are schematic perspective views of a light-emitting element according to one embodiment. Figures 9 and 10 show embodiments in which the light-emitting element ED has various shapes.

[0119] Referring to Figure 9, the light-emitting element ED in Figure 9 extends in one direction and may have a hexagonal prism shape. The light-emitting element core 30 of the light-emitting element ED in Figure 9 may have a hexagonal prism shape, and the first element insulating layer 39 and the second element insulating layer 38 may be arranged to surround the side surface of the light-emitting element core 30.

[0120] Referring to Figure 10, the light-emitting element ED in Figure 10 extends in one direction X and may have a frustoconical shape. The light-emitting element core 30 of the light-emitting element ED in Figure 10 may also have a frustoconical shape.

[0121] The manufacturing process of the light-emitting diode (ED) will be explained step by step below, with reference to other drawings.

[0122] Figures 11 to 17 are cross-sectional views showing the manufacturing process of the light-emitting element shown in Figure 1.

[0123] In the following drawings illustrating the manufacturing process of the light-emitting element ED, a first direction DR1, a second direction DR2, and a third direction DR3 are defined. The first direction DR1 and the second direction DR2 are perpendicular to each other, and the third direction DR3 may be perpendicular to the plane in which the first direction DR1 and the second direction DR2 are located.

[0124] The third direction DR3 may be parallel to the direction X, which is the extension direction of the light-emitting element ED formed on the lower substrate 1000. Unless otherwise stated in the embodiments describing the manufacturing process of the light-emitting element ED, “upper” refers to the direction in which the semiconductor layers of the light-emitting element ED are stacked on one side of the third direction DR3 from one surface (or top surface) of the lower substrate 1000, and “top surface” refers to the surface facing one side of the third direction DR3. Also, “lower” refers to the other side of the third direction DR3, and “bottom surface” refers to the surface facing the other side of the third direction DR3.

[0125] Referring to Figure 11, the lower substrate 1000 can be prepared.

[0126] The lower substrate 1000 may include a base substrate 1100 and a buffer material layer 1200 disposed on the base substrate 1100.

[0127] The base substrate 1100 may include a transparent substrate such as a sapphire substrate (AlxOy) or glass. However, it is not limited to these, and the base substrate 1100 may also include conductive substrates such as GaN, SiC, ZnO, Si, GaP, and GaAs.

[0128] A semiconductor layer can be formed on the base substrate 1100. The semiconductor layer can be formed by growing a seed crystal on the base substrate 1100 by an epitaxial method. The method for forming the semiconductor layer can be electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporation, sputtering, metal-organic chemical vapor deposition (MOCVD), or similar methods within the scope of the present invention.

[0129] The buffer material layer 1200 may be formed on one surface (or top surface) of the base substrate 1100. The buffer material layer 1200 can serve to reduce the lattice constant difference between the base substrate 1100 and the first semiconductor material layer 3100 (see Figure 12), which will be described later. The buffer material layer 1200 may contain an undoped semiconductor. The buffer material layer 1200 contains the same material as the first semiconductor material layer 3100, which will be described later, but may contain a first conductivity type dopant or a second conductivity type dopant, for example, an undoped material of n-type or p-type. The buffer material layer 1200 may be a single layer, but is not limited to this; for example, the buffer material layer 1200 may contain multiple layers. The buffer material layer 1200 may be omitted depending on the type of base substrate 1100.

[0130] Referring to Figure 12, the first laminated structure 3000 can be formed on the lower substrate 1000.

[0131] A first laminated structure 3000 can be formed on the lower substrate 1000, in which a first semiconductor material layer 3100, a light-emitting material layer 3300, a second semiconductor material layer 3200, and an electrode material layer 3700 are sequentially stacked on each other.

[0132] The layers included in the first stacked structure 3000 may correspond to each layer included in the light-emitting element core 30 according to one embodiment. The first semiconductor material layer 3100, light-emitting material layer 3300, second semiconductor material layer 3200, and electrode material layer 3700 of the first stacked structure 3000 correspond to the first semiconductor layer 31, light-emitting layer 33, second semiconductor layer 32, and element electrode layer 37 of the light-emitting element core 30, respectively, and may contain the same materials as those contained in each layer.

[0133] Referring to Figure 13, the first stacked structure 3000 can be etched to form light-emitting cores 30 that are separated from each other.

[0134] As shown in Figure 13, a process of etching the first laminated structure 3000 in a direction perpendicular to the upper surface of the lower substrate 1000, for example, in a third direction DR3, can form light-emitting cores 30 that are spaced apart from each other. The first laminated structure 3000 can be etched by a conventional patterning method. For example, the patterning method can be performed by forming an etching mask layer on top of the first laminated structure 3000 and etching the first laminated structure 3000 along the etching mask layer in a third direction DR3.

[0135] For example, the process of etching the first laminated structure 3000 may be a dry etching method, a wet etching method, a reactive ion etching method (RIE), an inductively coupled plasma reactive ion etching method (ICP-RIE), or an equivalent method within the scope of the present invention. In the case of a dry etching method, Anisotropic etching is possible and suitable for vertical etching. According to the example, etching of the first laminated structure 3000 may be performed by combining a dry etching method and a wet etching method.

[0136] For example, after etching in the third direction DR3 by a dry etching method, the etched sidewall can be placed on a plane perpendicular to the upper surface of the lower substrate 1000 by a wet etching method, which is isotropic etching.

[0137] Defects may occur on the surface of the light-emitting element core 30 formed by etching the first stacked structure 3000 due to the etchant used in the etching process. For example, defects in the semiconductor material may occur on the surface of the semiconductor layer contained in each of the multiple light-emitting element cores 30. Defects formed on the outer surface of the light-emitting element core 30 can cause electron leakage or hole trapping in the semiconductor layer, hindering the coupling of electrons and holes and potentially reducing the optical efficiency of the light-emitting element ED. Furthermore, if a second element insulating layer 38 (see Figure 16) is directly formed on the outer surface of a light-emitting element core 30 with surface defects, diffusion of impurities from the second element insulating layer 38 to the semiconductor layer may occur along the boundary between the second element insulating layer and the light-emitting element core 30, potentially reducing the element reliability and efficiency of the light-emitting element ED.

[0138] Next, referring to Figure 14, a first insulating material layer 390 can be formed on the light-emitting element core 30.

[0139] To reduce surface defects on the outer surface of the semiconductor layer of the light-emitting element core 30, a first insulating material layer 390 having a single-crystal structure may be formed directly on the side surface of the light-emitting element core 30.

[0140] The first insulating material layer 390 is formed over the entire surface of the lower substrate 1000 and may be formed not only on the outer surface of the light-emitting element core 30 but also on the upper surface of the lower substrate 1000 exposed by the light-emitting element core 30. The first insulating material layer 390 may correspond to the first element insulating layer 39 of the light-emitting element ED.

[0141] In one embodiment, the first insulating material layer 390 may include the same material as the first element insulating layer 39, for example, an oxide having a single-crystal structure. For example, the first insulating material layer 390 may include zirconium oxide (ZrOx) having a single-crystal structure.

[0142] To improve efficiency while maintaining the reliability of the light-emitting element ED, the first insulating material layer 390 must maintain a single-crystal structure. For this reason, the first insulating material layer 390 can be formed on the outer surface of the light-emitting element core 30 with a predetermined thickness d1. The thickness d1 of the first insulating material layer 390 can be within a range below the critical thickness of the material contained in the first insulating material layer 390. For example, if the first insulating material layer 390 contains zirconium oxide (ZrOx), the thickness d1 of the first insulating material layer 390 can be about 10 nm or less.

[0143] The first insulating material layer 390 can be formed by atomic layer deposition, chemical vapor deposition, metal-organic chemical vapor deposition, or an equivalent method within the scope of the present invention.

[0144] According to the embodiment, the first insulating material layer 390 may be formed to have a superlattice layer structure as described with reference to Figure 5. When the first insulating material layer 390 has a superlattice layer structure, the first insulating material layer 390 may be formed so that layers containing a compound semiconductor having a single crystal structure are stacked alternately. In this case, each of the layers may be formed to have a thickness less than or equal to the critical thickness of the material contained in the layer.

[0145] Referring to Figure 15, a second insulating material layer 380 can be formed on the first insulating material layer 390. The second insulating material layer 380 can correspond to the second element insulating layer 38 through subsequent processes. Therefore, the second insulating material layer 380 can contain the materials included in the second element insulating layer 38. For example, the second insulating material layer 380 can be formed by atomic layer deposition or chemical vapor deposition.

[0146] Referring to Figure 16, the first insulating material layer 390 and the second insulating material layer 380 can be partially removed to form the first element insulating layer 39 and the second element insulating layer 38 surrounding the side surface of the light-emitting element core 30.

[0147] The process of forming the first element insulating layer 39 and the second element insulating layer 38 may include an etching step to partially remove the first insulating material layer 390 and the second insulating material layer 380 so that one end face of the light-emitting element core 30, for example, the upper surface of the element electrode layer 37, is exposed. The step of partially removing the first insulating material layer 390 and the second insulating material layer 380 may be carried out through an anisotropic etching process such as dry etching or etch-back.

[0148] Referring to Figure 17, the light-emitting element ED can be separated from the lower substrate 1000. The process for separating the light-emitting element ED from the lower substrate 1000 is not particularly limited. For example, the separation process of the light-emitting element ED can be carried out by a physical separation method, a chemical separation method, or an equivalent method within the scope of the present invention.

[0149] Figure 18 is a schematic plan view of a display device according to one embodiment.

[0150] Referring to Figure 18, the display device 10 can display videos and still images. The display device 10 refers to or can be applied to any electronic device that provides a display screen. For example, the display device 10 may include televisions, laptops, monitors, billboards, the Internet of Things, mobile phones, smartphones, tablet PCs (Personal Computers), electronic clocks, smartwatches, watch phones, head-mounted displays, mobile communication terminals, electronic organizers, e-books, PMPs (Portable Multimedia Players), navigation systems, game consoles, digital cameras, camcorders, and more.

[0151] The display device 10 may include a display panel that provides a display screen. Examples of display panels include inorganic light-emitting diode display panels, organic light-emitting display panels, quantum dot light-emitting display panels, plasma display panels, field emission display panels, or equivalents within the scope of the present invention.

[0152] In the following, we will describe an example of a display panel in which the above-mentioned light-emitting diode (ED), specifically an inorganic light-emitting diode display panel, is applied. However, the invention is not limited to this, and can be applied to other display panels as long as the same technical concept is applicable within the scope of the present invention.

[0153] In the following drawings of the embodiment describing the display device 10, a fourth direction DR4, a fifth direction DR5, and a sixth direction DR6 are defined. The fourth direction DR4 and the fifth direction DR5 can be directions perpendicular to each other within a single plane. The sixth direction DR6 can be a direction perpendicular to the plane in which the fourth direction DR4 and the fifth direction DR5 are located. The sixth direction DR6 is perpendicular to each of the fourth direction DR4 and the fifth direction DR5. In the embodiment describing the display device 10, the sixth direction DR6 indicates the thickness direction of the display device 10.

[0154] The display device 10 may have a rectangular shape on a plane, with a longer side and a shorter side where the fourth direction DR4 is longer than the fifth direction DR5. On a plane, the corners where the longer and shorter sides of the display device 10 intersect may be right angles, but are not limited to this, and may have rounded curved shapes. The planar shape of the display device 10 is not limited to those exemplified, and may have other shapes such as a square, a quadrilateral with rounded corners (vertices or corners), other polygons, or a circle.

[0155] The display surface of the display device 10 may be positioned on one side of the sixth direction DR6, which is the thickness direction. Unless otherwise specified in the embodiments describing the display device 10, “upper” refers to the display direction toward one side of the sixth direction DR6, and “top surface” refers to the surface facing toward one side of the sixth direction DR6. Also, “lower” refers to the other side of the sixth direction DR6, which is the opposite direction of the display, and “bottom surface” refers to the surface facing toward the other side of the sixth direction DR6. Furthermore, “left,” “right,” “up,” and “down” refer to the directions when the display device 10 is viewed from a plane. For example, “right side” refers to one side of the fourth direction DR4, “left side” refers to the other side of the fourth direction DR4, “upper side” refers to one side of the fifth direction DR5, and “lower side” refers to the other side of the fifth direction DR5.

[0156] The display device 10 may include a display area DPA and a non-display area NDA. The display area DPA is the area where the screen can be displayed, and the non-display area NDA is the area where the screen cannot be displayed.

[0157] The shape of the display area DPA can correspond to the shape of the display device 10. For example, the shape of the display area DPA can be a rectangle on a plane, similar to the overall shape of the display device 10. The display area DPA may occupy roughly the center of the display device 10.

[0158] The display area DPA may include pixels PX. Pixels PX may be arranged (or positioned) in the matrix direction. The shape of each pixel PX may be a rectangle or square on a plane, but is not limited to this; the shape of each pixel PX may also be a rhombus with each side tilted in one direction. Each pixel PX may be of the stripe type or Pentile type. TM They can be arranged alternately in this type.

[0159] A non-display area (NDA) may be arranged around the display area (DPA). The non-display area (NDA) may enclose the display area (DPA) entirely or partially. In an exemplary embodiment, the display area (DPA) may be rectangular in shape, and the non-display area (NDA) may be arranged adjacent to all four sides of the display area (DPA). The non-display area (NDA) may constitute the bezel of the display device 10. Pads on which wiring, circuit drive units, or external devices included in the display device 10 are mounted may be arranged in the non-display area (NDA).

[0160] Figure 19 is a schematic plan view showing one embodiment of the pixels included in the display device of Figure 18. Figure 20 is a schematic cross-sectional view showing one embodiment of the pixels cut along the line I-I' in Figure 19.

[0161] Referring to Figure 19, each pixel PX of the display device 10 can include an emitting region EMA and a non-emitting region. The emitting region EMA can be defined as the region from which light emitted from the light-emitting element ED is emitted, and the non-emitting region can be defined as the region from which light is not emitted because the light emitted from the light-emitting element ED does not reach it.

[0162] The light-emitting region (EMA) may include the region where the light-emitting element (ED) is located and its adjacent regions. The light-emitting region may further include regions where light emitted from the light-emitting element (ED) is reflected or refracted by other components and emitted.

[0163] Each pixel PX may further include a sub-region SA located in a non-emitting region. A light-emitting element ED may not be located in the sub-region SA. The sub-region SA may be located above the planar light-emitting region EMA within a single pixel PX.

[0164] The sub-region SA may be located between the light-emitting regions EMA of pixels PX that are adjacent to each other in the fifth direction DR5. The sub-region SA may include a region in which the electrode layer 200 and the contact electrode 700 are electrically connected via contact portions CT1 and CT2.

[0165] The sub-region SA may include a separation region ROP. The separation region ROP of the sub-region SA may be a region in which the first electrode 210 and the second electrode 220 included in the electrode layer 200 contained in each adjacent pixel PX along the fifth direction DR5 are separated from each other.

[0166] Referring to Figures 19 and 20, the display device 10 can include a substrate SUB, a circuit element layer disposed on the substrate SUB, and a light-emitting layer disposed on the circuit element layer.

[0167] The substrate SUB may be an insulating substrate. The substrate SUB may be made of an insulating material such as glass, quartz, or polymer resin. The substrate SUB may be a rigid substrate, but may also be a flexible substrate that is capable of bending, folding, rolling, or equivalent within the scope of the present invention.

[0168] The circuit element layer may be arranged on a substrate SUB. The circuit element layer may include a lower metal layer 110, a semiconductor layer 120, a first conductive layer 130, a second conductive layer 140, a third conductive layer 150, and an insulating film.

[0169] The lower metal layer 110 is placed on the substrate SUB. The lower metal layer 110 may include a light-shielding pattern BML. The light-shielding pattern BML may be positioned to cover at least the channel region of the active layer ACT of the transistor TR at the bottom. However, it is not limited to this, and the light-shielding pattern BML may be omitted.

[0170] The lower metal layer 110 may include a light-blocking material. For example, the lower metal layer 110 can be formed from an opaque metallic substance that blocks the transmission of light.

[0171] The buffer layer 161 may be placed on the lower metal layer 110. The buffer layer 161 may be placed so as to cover the entire surface of the substrate SUB on which the lower metal layer 110 is located. The buffer layer 161 can serve to protect the transistor from moisture penetrating through the moisture-vulnerable substrate SUB.

[0172] The semiconductor layer 120 may be placed on the buffer layer 161. The semiconductor layer 120 may include the active layer ACT of the transistor TR. The active layer ACT of the transistor TR may be placed superimposed on the light-shielding pattern BML of the lower metal layer 110.

[0173] The semiconductor layer 120 may include polycrystalline silicon, single-crystal silicon, oxide semiconductor, or equivalent materials within the scope of the present invention.

[0174] The active layer (ACT) of a transistor (TR) may include multiple doped regions doped with impurities, and channel regions between these regions.

[0175] The gate insulating film 162 may be placed on the semiconductor layer 120.

[0176] The first conductive layer 130 may be placed on the gate insulating film 162. The first conductive layer 130 may include the gate electrode GE of the transistor TR. The gate electrode GE may be placed so as to overlap the channel region of the active layer ACT with the sixth direction DR6.

[0177] The first interlayer insulating film 163 may be placed on the first conductive layer 130. The first interlayer insulating film 163 may be placed so as to cover the gate electrode GE. The first interlayer insulating film 163 can function as an insulating film between the first conductive layer 130 and other layers placed on it, thereby protecting the first conductive layer 130.

[0178] The second conductive layer 140 may be placed on the first interlayer insulating film 163. The second conductive layer 140 may include the drain electrode SD1 of the transistor TR and the source electrode SD2 of the transistor TR.

[0179] The drain electrode SD1 and source electrode SD2 of transistor TR can be electrically connected to the regions at both ends of the active layer ACT of transistor TR via contact holes that penetrate the first interlayer insulating film 163 and the gate insulating film 162, respectively. The source electrode SD2 of transistor TR can be electrically connected to the light-shielding pattern BML of the lower metal layer 110 via other contact holes that penetrate the first interlayer insulating film 163, the gate insulating film 162, and the buffer layer 161.

[0180] The second interlayer insulating film 164 may be placed on the second conductive layer 140. The second interlayer insulating film 164 may be placed so as to cover the drain electrode SD1 and the source electrode SD2 of the transistor TR. The second interlayer insulating film 164 can function as an insulating film between the second conductive layer 140 and other layers placed on it, thereby protecting the second conductive layer 140.

[0181] The third conductive layer 150 may be placed on the second interlayer insulating film 164. The third conductive layer 150 may include a first voltage line VL1, a second voltage line VL2, and a conductive pattern CDP.

[0182] The first voltage line VL1 can be superimposed on at least a portion of the drain electrode SD1 of the transistor TR and the sixth direction DR6. A high potential voltage (or first power supply voltage) supplied to the transistor TR may be applied to the first voltage line VL1.

[0183] The second voltage line VL2 may be electrically connected to the second electrode 220 via a second electrode contact hole CTS that penetrates the via layer 166 and passivation layer 165, as described later. A low potential voltage (or second power supply voltage) lower than the high potential voltage supplied to the first voltage line VL1 may be applied to the second voltage line VL2. For example, the first voltage line VL1 may be supplied with the high potential voltage (or first power supply voltage) supplied to the transistor TR, and the second voltage line VL2 may be supplied with a low potential voltage (or second power supply voltage) lower than the high potential voltage supplied to the first voltage line VL1.

[0184] The conductive pattern CDP can be electrically connected to the source electrode SD2 of the transistor TR. The conductive pattern CDP can be electrically connected to the source electrode SD2 of the transistor TR via a contact hole penetrating the second interlayer insulating film 164. Furthermore, the conductive pattern CDP can be electrically connected to the first electrode 210 via a first electrode contact hole CTD penetrating the via layer 166 and passivation layer 165, which will be described later. The transistor TR can transmit the first power supply voltage applied from the first voltage line VL1 to the first electrode 210 via the conductive pattern CDP.

[0185] The passivation layer 165 may be placed on the third conductive layer 150. The passivation layer 165 may be placed so as to cover the third conductive layer 150. The passivation layer 165 can serve to protect the third conductive layer 150.

[0186] The buffer layer 161, gate insulating film 162, first interlayer insulating film 163, second interlayer insulating film 164, and passivation layer 165 described above contain an inorganic insulating material and may consist of one or more inorganic layers. For example, the inorganic layer may include at least one of silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiOxNy).

[0187] The via layer 166 may be placed on the passivation layer 165. The via layer 166 may contain an organic insulating material, such as polyimide (PI). The via layer 166 can perform a surface planarization function. Therefore, the upper (or surface) of the via layer 166 can have a substantially flat surface, regardless of the shape of the pattern placed below it or whether such a pattern exists.

[0188] The light-emitting element layer may be arranged on a circuit element layer. The light-emitting element layer may be arranged on a via layer 166. The light-emitting element layer may include a first bank 400, an electrode layer 200, a first insulating layer 510, a second bank 600, a light-emitting element ED, and a contact electrode 700.

[0189] The first bank 400 may be positioned on the via layer 166 in the light-emitting region EMA. The first bank 400 may be positioned directly on one surface of the via layer 166. The first bank 400 may have a structure in which at least a portion protrudes in the sixth direction relative to one surface of the via layer 166. The protruding portion of the first bank 400 may have inclined sides. The first bank 400, including its inclined sides, may serve to change the direction of propagation of light emitted from the light-emitting element ED and traveling toward the sides of the first bank 400 to an upward direction (e.g., the display direction).

[0190] The first bank 400 may include a first subbank 410 and a second subbank 420 that are spaced apart from each other. The first subbank 410 and the second subbank 420, which are spaced apart from each other, provide space for the light-emitting element ED to be arranged and can also assist in acting as reflective barriers that change the direction of propagation of light emitted from the light-emitting element ED to the display direction.

[0191] In Figure 20, the side surface of the first bank 400 is shown as being inclined in a linear shape, but is not limited thereto. For example, the side surface (or outer surface) of the first bank 400 may have a curved semicircular or semielliptical shape.

[0192] The first bank 400 may, but is not limited to, organic insulating materials such as polyimide (PI).

[0193] The electrode layer 200 has a shape that extends in one direction and can be arranged to cross the light-emitting region EMA and the sub-region SA. The electrode layer 200 can transmit electrical signals applied from the circuit element layer to the light-emitting element ED to cause the light-emitting element ED to emit light. The electrode layer 200 can also be used to generate an electric field used in the alignment process of the light-emitting element ED.

[0194] The electrode layer 200 may be placed on the first bank 400 and the via layer 166 on which the first bank 400 is exposed. In the light-emitting region EMA, the electrode layer 200 may be placed on the first bank 400, and in the non-light-emitting region, the electrode layer 200 may be placed on the via layer 166 on which the first bank 400 is exposed.

[0195] The electrode layer 200 may include a first electrode 210 and a second electrode 220. The first electrode 210 and the second electrode 220 can be separated from each other.

[0196] The first electrode 210 may be positioned to the left of each pixel PX on the plane. The first electrode 210 may have a shape that extends in the fifth direction DR5 on the plane. The first electrode 210 may be positioned to cross the light-emitting region EMA and the sub-region SA.

[0197] The first electrode 210 extends in the fifth direction DR5 on a plane, but can be separated from the first electrode 210 of adjacent pixels PX in the fifth direction DR5 at the separation portion ROP of the sub-region SA.

[0198] The second electrode 220 can be separated from the first electrode 210 in the fourth direction DR4. The second electrode 220 may be positioned to the right of each pixel PX on the plane. The second electrode 220 may have a shape that extends in the fifth direction DR5 on the plane. The second electrode 220 may be positioned to cross the light-emitting region EMA and the sub-region SA. The second electrode 220 extends in the fifth direction DR5 on the plane and may be separated from the second electrode 220 of a pixel PX adjacent to it in the fifth direction DR5 at the separation portion ROP of the sub-region SA.

[0199] In the light-emitting region (EMA), the first electrode 210 may be positioned on the first subbank 410, and the second electrode 220 may be positioned on the second subbank 420. The first electrode 210 may also be positioned on a via layer 166 extending outward from the first subbank 410, exposing the first subbank 410. Similarly, the second electrode 220 may also be positioned on a via layer 166 extending outward from the second subbank 420, exposing the second subbank 420. The first electrode 210 and the second electrode 220 can be separated from each other and facing each other in the separation region between the first subbank 410 and the second subbank 420. The via layer 166 may be exposed in the region where the first electrode 210 and the second electrode 220 are separated from each other and facing each other.

[0200] The first electrode 210 can be separated from the first electrode 210 of other adjacent pixels PX in the fifth direction DR5 across the separation portion ROP in the sub-region SA. Similarly, the second electrode 220 can be separated from the second electrode 220 of other adjacent pixels PX in the fifth direction DR5 across the separation portion ROP in the sub-region SA. Therefore, in the separation portion ROP of the sub-region SA, the first electrode 210 and the second electrode 220 can expose the via layer 166.

[0201] The first electrode 210 can be electrically connected to the conductive pattern CDP of the circuit element layer via a first electrode contact hole CTD that penetrates the via layer 166 and the passivation layer 165. The first electrode 210 can contact the upper surface of the conductive pattern CDP exposed by the first electrode contact hole CTD. The first power supply voltage applied from the first voltage line VL1 can be transmitted to the first electrode 210 via the conductive pattern CDP.

[0202] The second electrode 220 can be electrically connected to the second voltage line VL2 of the circuit element layer via a second electrode contact hole CTS that penetrates the via layer 166 and the passivation layer 165. Specifically, the second electrode 220 can contact the upper surface of the second voltage line VL2 exposed by the second electrode contact hole CTS. The second power supply voltage applied from the second voltage line VL2 can be transmitted to the second electrode 220.

[0203] The electrode layer 200 may contain a highly reflective conductive material. For example, the electrode layer 200 may contain metals such as silver (Ag), copper (Cu), and aluminum (Al) as highly reflective materials, or alloys such as aluminum (Al), nickel (Ni), and lanthanum (La). The electrode layer 200 can reflect light emitted from the light-emitting element ED and traveling toward the side of the first bank 400 toward the upper direction of each pixel PX.

[0204] However, the electrode layer 200 may further contain a transparent conductive material. For example, the electrode layer 200 may contain materials such as ITO, IZO, and ITZO. In some embodiments, the electrode layer 200 may have a structure in which a transparent conductive material and a highly reflective metal layer are laminated one or more layers on each other, or it may be formed as a single layer including these. For example, the electrode layer 200 may have a laminated structure such as ITO / Ag / ITO, ITO / Ag / IZO, or ITO / Ag / ITZO / IZO.

[0205] The first insulating layer 510 may be placed on the via layer 166 on which the electrode layer 200 is formed. The first insulating layer 510 protects the electrode layer 200 and can insulate the first electrode 210 and the second electrode 220 from each other.

[0206] The first insulating layer 510 may include an inorganic insulating material. The first insulating layer 510 made of an inorganic material may have a surface shape that reflects the pattern shape of the electrode layer 200 located below it. For example, the first insulating layer 510 may have a stepped structure depending on the shape of the electrode layer 200 located below it. Specifically, the first insulating layer 510 may include a stepped structure in which a portion of the upper surface is recessed in the region where the first electrode 210 and the second electrode 220 are spaced apart from each other and facing each other. Thus, the height of the upper surface of the first insulating layer 510 located above the first electrode 210 and above the second electrode 220 may be higher than the height of the upper surface of the first insulating layer 510 located above the via layer 166 where the first electrode 210 and the second electrode 220 are not located. In this specification, the height of the upper surface of any layer may be compared by the height measured from a flat reference plane without a lower stepped structure (e.g., the upper surface of the via layer 166).

[0207] The first insulating layer 510 may include a first contact portion CT1 that exposes a portion of the upper surface of the first electrode 210 and a second contact portion CT2 that exposes a portion of the upper surface of the second electrode 220 in the sub-region SA. The first electrode 210 may be electrically connected to the first contact electrode 710 in the sub-region SA via the first contact portion CT1 that penetrates the first insulating layer 510, and the second electrode 220 may be electrically connected to the second contact electrode 720 in the sub-region SA via the second contact portion CT2 that penetrates the first insulating layer 510.

[0208] The second bank 600 may be arranged on the first insulating layer 510. The second bank 600 may be arranged in a grid pattern, including portions extending in the fourth direction DR4 and the fifth direction DR5 on a plane.

[0209] The second bank 600 is positioned across the boundaries of each pixel PX, separating adjacent pixels PX and dividing the light-emitting region EMA from the sub-region SA. Furthermore, the second bank 600 is formed to have a greater height than the first bank 400, so that during the inkjet printing process for aligning the light-emitting elements ED in the manufacturing process of the display device 10, the dispersed ink of the light-emitting elements ED is not mixed with adjacent pixels PX and is instead sprayed into the light-emitting region EMA.

[0210] The light-emitting element ED may be located in the light-emitting region EMA. The light-emitting element ED may not be located in the sub-region SA.

[0211] The light-emitting element ED may be placed on the first insulating layer 510 between the first subbank 410 and the second subbank 420. The light-emitting element ED may be placed on the first insulating layer 510 between the first electrode 210 and the second electrode 220.

[0212] The light-emitting element ED can have a shape that extends in one direction, and the light-emitting element ED can be arranged so that both ends are placed on the first electrode 210 and the second electrode 220, respectively. For example, the light-emitting element ED can be arranged so that one end of the light-emitting element ED is placed on the first electrode 210 and the other end of the light-emitting element ED is placed on the second electrode 220.

[0213] The length of each light-emitting element ED (i.e., the length of the light-emitting element ED in the fourth direction DR4 in the drawing) can be smaller than the shortest distance between the first subbank 410 and the second subbank 420 separated in the fourth direction DR4. Alternatively, the length of each light-emitting element ED can be larger than the shortest distance between the first electrode 210 and the second electrode 220 separated in the fourth direction DR4. By forming the distance between the first subbank 410 and the second subbank 420 to the fourth direction DR4 to be greater than the length of each light-emitting element ED, and the distance between the first electrode 210 and the second electrode 220 to the fourth direction DR4 to be smaller than the length of each light-emitting element ED, the light-emitting elements ED can be arranged such that both ends rest on the first electrode 210 and the second electrode 220, respectively, in the region between the first subbank 410 and the second subbank 420.

[0214] The light-emitting elements ED can be spaced apart from each other along the fifth direction DR5, from which the first electrode 210 and the second electrode 220 extend, and can be aligned substantially parallel to each other.

[0215] The second insulating layer 520 may be placed on the light-emitting element ED. The second insulating layer 520 may be placed partially on the light-emitting element ED so as to expose both ends of the light-emitting element ED. The second insulating layer 520 may be placed so as to partially cover the outer surface of the light-emitting element ED, but not to cover one end and the other end of the light-emitting element ED.

[0216] The portion of the second insulating layer 520 placed on the light-emitting element ED is positioned on a plane, extending in the fifth direction DR5 from above the first insulating layer 510, thereby forming linear or island-shaped patterns within each pixel PX. The second insulating layer 520 protects the light-emitting element ED and can fix the light-emitting element ED in place during the manufacturing process of the display device 10. The second insulating layer 520 can also be positioned to fill the separation space between the light-emitting element ED and the first insulating layer 510 below it.

[0217] The contact electrode 700 may be placed on the second insulating layer 520. It may also be placed on the first insulating layer 510 on which the light-emitting element ED is placed. The contact electrode 700 may include a first contact electrode 710 and a second contact electrode 720 that are spaced apart from each other.

[0218] The first contact electrode 710 may be positioned on the first electrode 210 in the light-emitting region EMA. The first contact electrode 710 may have a shape that extends in the fifth direction DR5 on the first electrode 210. The first contact electrode 710 may be in contact with one end of the first electrode 210 and the light-emitting element ED, respectively.

[0219] The first contact electrode 710 can contact the first electrode 210 exposed by the first contact portion CT1 penetrating the first insulating layer 510 in the sub-region SA, and can contact one end of the light-emitting element ED in the light-emitting region EMA. For example, the first contact electrode 710 can play a role in electrically connecting the first electrode 210 and one end of the light-emitting element ED.

[0220] The second contact electrode 720 may be positioned on the second electrode 220 in the light-emitting region EMA. The second contact electrode 720 may have a shape that extends in the fifth direction DR5 on the second electrode 220. The second contact electrode 720 may be in contact with the second electrode 220 and the other end of the light-emitting element ED, respectively.

[0221] The second contact electrode 720 can contact the second electrode 220 exposed by the second contact portion CT2 that penetrates the first insulating layer 510 in the sub-region SA, and can contact the other end of the light-emitting element ED in the light-emitting region EMA. For example, the second contact electrode 720 can play a role in electrically connecting the second electrode 220 and the other end of the light-emitting element ED.

[0222] The first contact electrode 710 and the second contact electrode 720 can be separated from each other on the light-emitting element ED. Specifically, the first contact electrode 710 and the second contact electrode 720 can be separated from each other by the second insulating layer 520. The first contact electrode 710 and the second contact electrode 720 can be electrically insulated from each other.

[0223] The first contact electrode 710 and the second contact electrode 720 may contain the same material. For example, the first contact electrode 710 and the second contact electrode 720 may each contain a conductive material. For example, the first contact electrode 710 and the second contact electrode 720 may contain ITO, IZO, ITZO, aluminum (Al), or equivalents within the scope of the present invention. As an example, the first contact electrode 710 and the second contact electrode 720 may each contain a transparent conductive material. By containing a transparent conductive material in the first contact electrode 710 and the second contact electrode 720, light emitted from the light-emitting element ED can pass through the first contact electrode 710 and the second contact electrode 720 and proceed toward the first electrode 210 and the second electrode 220, and be reflected by the surfaces of the first electrode 210 and the second electrode 220.

[0224] The first contact electrode 710 and the second contact electrode 720 may contain the same material and be formed in the same layer. The first contact electrode 710 and the second contact electrode 720 may be formed simultaneously through the same process.

[0225] The third insulating layer 530 may be placed on the contact electrode 700. The third insulating layer 530 can cover the light-emitting element layer located below it. The third insulating layer 530 can cover the first bank 400, the electrode layer 200, the first insulating layer 510, the light-emitting element ED, and the contact electrode 700. The third insulating layer 530 may be placed on the second bank 600 and can also cover the second bank 600.

[0226] The third insulating layer 530 can protect the light-emitting element layer located below it from foreign matter such as moisture / oxygen or dust particles. The third insulating layer 530 can protect the first bank 400, the electrode layer 200, the first insulating layer 510, the light-emitting element ED, and the contact electrode 700.

[0227] Figure 21 is a schematic cross-sectional view showing an enlarged version of region Q in Figure 20, illustrating one embodiment.

[0228] Referring to Figure 21, the light-emitting element ED may be arranged such that the extension direction of the light-emitting element ED is parallel to one surface of the substrate SUB. The semiconductor layers included in the light-emitting element ED may be arranged sequentially along a direction parallel to the upper surface of the substrate SUB (or the upper surface of the via layer 166). For example, the first semiconductor layer 31, the light-emitting layer 33, and the second semiconductor layer 32 of the light-emitting element ED may be arranged sequentially relative to each other parallel to the upper surface of the substrate SUB.

[0229] The light-emitting element ED may be arranged such that one end is placed on the first electrode 210 and the other end is placed on the second electrode 220. However, it is not limited to this arrangement, and the light-emitting element ED may also be arranged such that one end is placed on the second electrode 220 and the other end is placed on the first electrode 210.

[0230] The second insulating layer 520 may be placed on the light-emitting element ED. The second insulating layer 520 may be placed so as to surround the outer surface of the light-emitting element ED. The second insulating layer 520 may be placed on the second element insulating layer 38 of the light-emitting element ED and may surround the outer surface of the second element insulating layer 38 of the light-emitting element ED facing the display direction DR6.

[0231] In the region where the light-emitting element ED is placed, the second insulating layer 520 is arranged to surround the outer surface of the light-emitting element ED (specifically, the second element insulating layer 38 of the light-emitting element ED), and in the region where the light-emitting element ED is not placed, the second insulating layer 520 may be placed on the first insulating layer 510 where the light-emitting element ED is exposed.

[0232] The first contact electrode 710 can contact one end of the light-emitting element ED where the second insulating layer 520 is exposed. The first contact electrode 710 may be positioned to enclose one end surface of the light-emitting element ED where the second insulating layer 520 is exposed. The first contact electrode 710 can contact the second element insulating layer 38 and the element electrode layer 37 of the light-emitting element ED.

[0233] The second contact electrode 720 can contact the other end of the light-emitting element ED where the second insulating layer 520 is exposed. The second contact electrode 720 may be positioned to enclose the other end surface of the light-emitting element ED where the second insulating layer 520 is exposed. The second contact electrode 720 can contact the second element insulating layer 38 and the first semiconductor layer 31 of the light-emitting element ED.

[0234] The first contact electrode 710 and the second contact electrode 720 can be separated from each other by the second insulating layer 520. At least a portion of the upper surface of the second insulating layer 520 can be exposed between the first contact electrode 710 and the second contact electrode 720.

[0235] The first contact electrode 710 and the second contact electrode 720 may be formed in the same layer and contain the same material. For example, the first contact electrode 710 and the second contact electrode 720 may be formed in one masking process. They can be formed simultaneously. Therefore, since no additional masking step is required to form the first contact electrode 710 and the second contact electrode 720, the efficiency of the manufacturing process of the display device 10 can be improved.

[0236] Figure 22 is a schematic cross-sectional view showing an enlarged version of region Q in Figure 20, illustrating one embodiment.

[0237] Referring to Figures 21 and 22, the contact electrode 700_1 in Figure 22 differs from the embodiment in Figure 21 in that it includes a first contact electrode 710 and a second contact electrode 720_1 formed on different layers with a fourth insulating layer 540 in between.

[0238] The first contact electrode 710 may be positioned on the first electrode 210 and one end of the light-emitting element ED. The first contact electrode 710 may extend from one end of the light-emitting element ED toward the second insulating layer 520 and may also be positioned on one side wall of the second insulating layer 520 and on the upper surface of the second insulating layer 520. The first contact electrode 710 is positioned on the upper surface of the second insulating layer 520, but at least a portion of the upper surface of the second insulating layer 520 may be exposed.

[0239] The fourth insulating layer 540 may be positioned on the first contact electrode 710. The fourth insulating layer 540 may be positioned to completely cover the first contact electrode 710. The fourth insulating layer 540 may be positioned to completely cover one sidewall and the top surface of the second insulating layer 520, but not on the other sidewall of the second insulating layer 520. One end of the fourth insulating layer 540 may be aligned with the other sidewall of the second insulating layer 520.

[0240] The second contact electrode 720_1 may be positioned on the second electrode 220 and the other end of the light-emitting element ED. The second contact electrode 720_1 may also extend from the other end of the light-emitting element ED toward the second insulating layer 520 and be positioned on the other side wall of the second insulating layer 520 and on the upper surface of the fourth insulating layer 540.

[0241] The third insulating layer 530 may be placed on the fourth insulating layer 540 and the second contact electrode 720_1, and can cover them.

[0242] By forming the first contact electrode 710 and the second contact electrode 720_1 on different layers and interposing a fourth insulating layer 540 between them, an additional step is added to the manufacturing process of the display device 10, which may reduce the efficiency of the manufacturing process of the display device 10, but the reliability of the display device 10 can be improved. By forming the first contact electrode 710 and the second contact electrode 720_1 on different layers and further placing a fourth insulating layer 540 between them, the problem of the first contact electrode 710 and the second contact electrode 720_1 being short-circuited during the manufacturing process of the display device 10 can be minimized.

[0243] Figure 23 is a schematic cross-sectional view showing an enlarged version of region Q in Figure 20, illustrating one embodiment.

[0244] Referring to Figures 21 and 23, the embodiment in Figure 23 differs from the embodiment in Figure 21 in that the light-emitting element ED of Figure 5 is applied.

[0245] The light-emitting element ED may include a first element insulating layer 39 having a superlattice layer structure. In a light-emitting element ED placed on a first electrode 210 and a second electrode 220, a first element insulating layer 39, in which a first layer 391 and a second layer 392 are stacked alternately on each other, may be interposed between the light-emitting element core 30 and the second element insulating layer 38.

[0246] Figure 24 is a schematic cross-sectional view showing an enlarged version of region Q in Figure 20, illustrating one embodiment.

[0247] Referring to Figures 21 and 24, Figure 24 differs from the embodiment in Figure 21 in that the thickness of the second element insulating layer 38_2 of the light-emitting element ED differs from region to region.

[0248] The second element insulating layer 38_2 of the light-emitting element ED, which is aligned between the first electrode 210 and the second electrode 220, can have different thicknesses in each region.

[0249] On a cross-section of the light-emitting element ED, the second element insulating layer 38_2 located above (or positioned above) the light-emitting element core 30 has a first thickness d21 in the region where it overlaps with the second insulating layer 520, while the second element insulating layer 38_2 located above the light-emitting element core 30 on a cross-section of the light-emitting element ED may have a second thickness d22 that is thinner than the first thickness d21 in the region where it does not overlap with the second insulating layer 520. The second element insulating layer 38_2 located below the light-emitting element core 30 on a cross-section of the light-emitting element ED may have a third thickness d23 that is the same as the first thickness d21. A portion of the second element insulating layer 38_2 located above the light-emitting element core 30 may face the display direction, while another portion of the second element insulating layer 38_2 located below the light-emitting element core 30 may face the first insulating layer 510.

[0250] For example, a second element insulating layer 38_2 that is superimposed on the second insulating layer 520 and located above the light-emitting core 30 can have the same thickness as a second element insulating layer 38_2 located below the light-emitting core 30, while a second element insulating layer 38_2 that is not superimposed on the second insulating layer 520 and located above the light-emitting core 30 can be thinner than a second element insulating layer 38_2 that is superimposed on the second insulating layer 520 and located above the light-emitting core 30. These can be formed by etching a portion of the second element insulating layer 38_2 during the manufacturing process of the display device 10.

[0251] While preferred embodiments of the present invention have been described above with reference to the present invention, a person skilled in the art or with ordinary knowledge in the art will understand that the present invention can be modified and altered in various ways without departing from the spirit and technical scope of the invention as described in the claims below. Therefore, the technical scope of the present invention is not limited to what is described in the detailed description of the specification, but should be defined by the claims.

Claims

1. A light-emitting core comprising a first semiconductor layer, a second semiconductor layer separated from the first semiconductor layer, and a light-emitting layer disposed between the first and second semiconductor layers; The first element insulating layer surrounds the side surface of the light-emitting element core, The first element insulating layer is an oxide insulating film having a single crystal structure, wherein the light-emitting element is a light-emitting element.

2. The light-emitting element according to claim 1, wherein the thickness of the first element insulating layer in a direction perpendicular to the side surface of the light-emitting element core is greater than about 0 nm and less than or equal to about 10 nm.

3. The light-emitting element according to claim 1, wherein the first element insulating layer comprises a metal oxide containing two or more metal elements.

4. The light-emitting element according to claim 3, wherein the two or more metallic elements are one or more selected from the group consisting of Ta, Hf, Zr, La, Si, Ti, and Al.

5. The first element insulating layer contains a first metal element, At least a portion of the light-emitting core contains a base element, The light-emitting element according to claim 1, wherein the bonding energy of the oxide to the first metal element is greater than the bonding energy of the base element to the oxide.

6. The light-emitting element according to claim 5, wherein the ionic radius of the first metal element is greater than the ionic radius of the base element in the oxide.

7. The light-emitting element according to claim 1, wherein the first element insulating layer is disposed directly on the side surface of the light-emitting element core.

8. The light-emitting element according to claim 1, further comprising a second element insulating layer surrounding the outer surface of the first element insulating layer.

9. The light-emitting element according to claim 8, wherein the second element insulating layer is an oxide insulating film having an amorphous or polycrystalline structure.

10. The light-emitting element according to claim 9, wherein the first element insulating layer and the second element insulating layer contain only the same material to each other.

11. The light-emitting element according to claim 9, further comprising a third element insulating layer surrounding the outer surface of the second element insulating layer.

12. The first element insulating layer has a superlattice layer structure in which a first layer and a second layer containing different materials are alternately stacked in multiple layers. The light-emitting element according to claim 1, wherein the first layer and the second layer are stacked in a direction perpendicular to the side surface of the light-emitting element core.

13. The light-emitting element according to claim 12, wherein the first layer and the second layer are each an oxide insulating film having a single crystal structure.

14. The light-emitting element according to claim 13, wherein the thickness of the first layer and the second layer, in a direction perpendicular to the side surface of the light-emitting element core, is greater than about 0 nm and less than or equal to about 10 nm.

15. A first electrode and a second electrode are arranged on a substrate and spaced apart from each other; Includes a light-emitting element disposed between the first electrode and the second electrode, The light-emitting element is A light-emitting core comprising a first semiconductor layer, a second semiconductor layer separated from the first semiconductor layer, and a light-emitting layer disposed between the first and second semiconductor layers; The first element insulating layer surrounds the side surface of the light-emitting element core, The first element insulating layer is an oxide insulating film having a single crystal structure, in a display device.

16. The display device according to claim 15, wherein the first element insulating layer has a thickness greater than about 0 nm and less than or equal to about 10 nm in a direction perpendicular to the side surface of the light-emitting core.

17. The display device according to claim 15, wherein the first element insulating layer comprises a metal oxide containing two or more metal elements.

18. The display device according to claim 17, wherein the two or more metallic elements are one or more selected from the group consisting of Ta, Hf, Zr, La, Si, Ti, and Al.

19. The light-emitting element further includes a second element insulating layer surrounding the outer surface of the first element insulating layer, The display device according to claim 15, wherein the second element insulating layer is an oxide insulating film having an amorphous or polycrystalline structure.

20. The first element insulating layer has a superlattice layer structure in which a first layer and a second layer containing different materials are alternately stacked in multiple layers. The first and second layers are stacked in a direction perpendicular to the side surface of the light-emitting core. The display device according to claim 15, wherein the first layer and the second layer are each an oxide insulating film having a single crystal structure.

Images