Full wafer thickness map reflectivity measurement

Abstract

A method for measuring the thickness of a semiconductor structure includes illuminating the semiconductor structure with non-coherent and non-parallel light from at least one light source, and acquiring at least one image of the semiconductor structure illuminated by the light source using a camera. The at least one image includes separate images of a first color, a second color, and a third color, where the first, second, and third colors are distinct from each other. A thickness map is generated for at least two layers of the semiconductor structure based on the images of the first, second, and third colors and reference images of a reference silicon wafer in the first, second, and third colors.

Description

Cross-reference with related applications

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 505,750, filed on 2 June 2023, the entire disclosure of which is incorporated herein by reference. [Technical Field]

[0002] This field relates to semiconductor wafer thickness mapping, and more specifically, to methods, systems, and apparatus for measuring the reflectivity of full wafer thickness maps of silicon-on-insulator ("SOI") wafers and thick oxide wafers. [Background technology]

[0003] A silicon structure on an insulator ("SOI structure") generally includes a handle wafer, a silicon layer (also characterized as a "device layer"), and a dielectric layer (such as an oxide layer) between the handle wafer and the silicon layer. Many silicon semiconductor device designs benefit from using SOI substrates rather than polished bulk silicon wafers or substrates coated with epitaxial layers. In mass production applications, the advantages typically include improved insulation of the device layer, enabling high-bandwidth transistors while reducing electromagnetic crosstalk between adjacent cells within the device.

[0004] SOI structures D can be fabricated from silicon wafers sliced ​​from single-crystal silicon ingots grown according to the Czochralski (Cz) method. In one method of preparing an SOI substrate, a dielectric layer is deposited on the polished front surface of a donor wafer. Ions are implanted to a predetermined depth beneath the front surface of the donor wafer, forming a damaged layer in the donor wafer at the predetermined implantation depth. The donor wafer is then bonded to a handle wafer, and the two wafers are pressed together to form a bonded wafer pair. The bonded wafer pair is then cleaved along the cleavage plane in the damaged layer, removing the donor wafer portion beneath the damaged layer and leaving a thin silicon layer (in other words, a device layer) on top of the handle wafer to form an SOI laminated substrate.

[0005] Mechanical cleavage of a bonded wafer pair can result in uneven device layer thickness as the cleavage progresses from the leading edge where cleavage begins to the trailing edge where the bonded wafer is completely separated. Furthermore, in some cases, cleavage may fail, resulting in the bonded wafer structure not being cleaved along the desired cleavage plane, or not being cleaved at all. While cleavage variability has traditionally been monitored by operator observation in downstream processes, this may not provide timely feedback for monitoring and adjusting upstream processes or cleavage appropriately.

[0006] This section is intended to introduce to the reader various aspects of the technology that may be relevant to various aspects of the present disclosure, which are described and / or claimed below. This discussion is intended to be useful in providing the reader with background information to better understand various aspects of the present disclosure. Accordingly, these descriptions should be read in this context and should be understood not as an admission of prior art. [Overview of the Initiative]

[0007] One embodiment is a thickness measurement system comprising a camera positioned above the center of a semiconductor structure to acquire light reflected by the semiconductor structure, at least one light source providing non-coherent and uncollimated light, and a control device including a processor and memory. The control device is operably coupled to the RGB camera and the at least one light source. The memory includes instructions, when executed by the processor, to illuminate the semiconductor structure with non-coherent, uncollimated light from the at least one light source and to cause the camera to acquire at least one image of the semiconductor structure illuminated by the light from the light source. The at least one image includes separate images of a first color, a second color, and a third color, where the first, second, and third colors are distinct from each other. Furthermore, these instructions cause the processor to generate a thickness map of at least two layers of the semiconductor structure based on the images of the first, second, and third colors and the images of the first, second, and third colors of a reference silicon wafer.

[0008] Another embodiment is a method for measuring the thickness of a semiconductor structure. This method includes illuminating the semiconductor structure with non-coherent and non-parallel light from at least one light source and acquiring at least one image of the semiconductor structure illuminated by the light source using a camera. The at least one image includes separate images of a first color, a second color, and a third color, where the first, second, and third colors are distinct from each other. Thickness maps of at least two layers of the semiconductor structure are generated based on the first, second, and third color images and the first, second, and third color images of a reference silicon wafer.

[0009] Various improvements exist to the features described in relation to the embodiments described above. Further features can also be incorporated into the embodiments described above. These improvements and additional functions may exist individually or in any combination. For example, various features described later in relation to any of the illustrated embodiments can be incorporated into the embodiments described above, individually or in any combination. [Brief explanation of the drawing]

[0010] [Figure 1] FIG. 1 is a schematic view of a cleavage system for separating a bonded wafer structure along a cleavage plane. [Figure 2] FIG. 2 is a cross-sectional view of a donor structure having a donor wafer with a dielectric layer thereon. [Figure 3] FIG. 3 is a cross-sectional view during ion implantation. [Figure 4] FIG. 4 is a cross-sectional view of a donor structure bonded to a handle structure. [Figure 5] FIG. 5 is a cross-sectional view of a bonded wafer structure when the donor structure is cleaved along the cleavage plane. [Figure 6] FIG. 6 is a cross-sectional view of a bonded wafer structure having a chuck and a blade for propagating cleavage. [Figure 7] FIG. 7 is an example of an imaging station for performing reflectometry. [Figure 8] FIG. 8 is a graph of an example of the filter spectrum of an RGB camera. [Figure 9] FIG. 9 is a graph of an example of the white spectrum of an LED. [Figure 10] [[ID=​​​​​​​​​​​​​​FIG. 15 is an example of a method for reducing lighting incompleteness and creating a layer thickness map without calibration. [Figure 16] FIG. 16 is a graph of the ratios rGR and rBR modeled as functions of dSOI and dBOX. [Figure 17] FIG. 17 is a graph of a weight function between a given set of measured ratios rGR and rBR and the modeled ratios rGR and rBR. [Figure 18] FIG. 18 is a graph showing the modeled ratios rGR and rBR as functions of dSOI and dBOX for a narrower range of dSOI and dBOX than in FIG. 16. [Figure 19] FIG. 19 is a block diagram of an example embodiment of a computing device.

[0011] Corresponding reference characters indicate corresponding parts throughout the drawings.

BEST MODE FOR CARRYING OUT THE INVENTION

[0012] [DETAILED DESCRIPTION]

[0013] Referring to FIG. 1, a cleaving system 100 for separating a bonded wafer structure is schematically shown. The cleaving system 100 includes a cleaving device 110 for cleaving the bonded wafer structure and an acoustic sensor 120 for sensing sounds emitted from the bonded wafer structure during cleaving.

[0014] The bonded wafer structures that may be processed by the cleaving device 110 include semiconductor structures that desirably are separated into two different structures. In some embodiments, the structure being processed may be a bonded wafer structure used to fabricate a silicon-on-insulator structure. Such a bonded structure can include a handle wafer, a donor wafer, and a dielectric layer disposed between the handle wafer and the donor wafer. The following is merely an example of a method and system for processing a bonded wafer structure.

[0015] Figure 2 shows an example of a donor structure 30 that may be bonded to a handle structure to form a bonded wafer structure. The donor structure 30 may be formed by a dielectric layer 15 deposited on the front surface of a donor wafer 12. Alternatively, the dielectric layer may be grown or deposited on the handle wafer, or the dielectric layer may be grown on both the donor wafer and the handle wafer, and it should be understood that these structures may be bonded in any of a variety of arrangements, without limitation. A suitable donor wafer 12 can be made of silicon, germanium, silicon germanium, gallium nitride, aluminum nitride, gallium arsenide, indium gallium arsenide, and any combination thereof. In some embodiments, the donor wafer is made of single-crystal silicon.

[0016] The dielectric layer 15 may be any electrical insulating material suitable for use in an SOI structure, such as a material consisting of SiO2, Si3N4, aluminum oxide, or magnesium oxide. In some embodiments, the dielectric layer 15 is SiO2 (in other words, the dielectric layer is essentially made of SiO2). In various embodiments, the dielectric layer forms a buried oxide (BOX) layer of the final SOI structure. The dielectric layer 15 can be applied according to techniques known in the art, such as thermal oxidation, wet oxidation, thermal nitriding, or a combination thereof. In this regard, while layered semiconductor structures may be described herein as having a dielectric layer, it should be understood that in some embodiments, the dielectric layer is eliminated (in other words, the dielectric layer is not deposited on the donor wafer or handle wafer before bonding), and the handle wafer and donor wafer are "directly bonded". In this specification, references to such dielectric layers should not be considered in a limited sense. Any of the many techniques known to those skilled in the art can be used to manufacture such directly bonded structures. In such embodiments, the bonding surface of the donor structure is the surface of the donor wafer itself.

[0017] For example, as shown in Figure 3, ions (e.g., hydrogen atoms, helium atoms, or a combination of hydrogen and helium atoms) can be implanted to a substantially uniform depth beneath the front surface 22 of the donor structure to define the cleavage plane 17. It should be noted that when helium and hydrogen ions are co-substituted into the structure to form the cleavage plane, they may be implanted simultaneously or sequentially. In some embodiments, the ions are implanted before the dielectric layer 15 is deposited. If the implantation is performed before the deposition of the dielectric layer 15, the subsequent growth or deposition of the dielectric layer on the donor wafer is preferably carried out at a temperature low enough to prevent premature separation or cleavage along the surface 17 in the donor layer (in other words, before the wafer bonding process step). The handle structure may include a handle wafer obtained from any suitable material for preparing a multilayer structure, such as silicon, silicon carbide, sapphire, germanium, silicon germanium, gallium nitride, aluminum nitride, gallium arsenide, indium gallium arsenide, quartz, and combinations thereof. The handle structure 10 (Figure 4) may include a dielectric layer deposited on the handle wafer, or, as in other embodiments, may consist only of the handle wafer (in other words, without a dielectric layer). The handle wafer and donor wafer may be single-crystal silicon wafers, or single-crystal silicon wafers sliced ​​from a single-crystal ingot grown according to the conventional Czochralski crystal growth method.

[0018] As shown in Figure 4, the front surface of the dielectric layer 15 of the donor structure and the front surface of the handle structure 10 are suitably joined, and a bonded wafer structure 20 is formed through a bonding process. The dielectric layer 15 and the handle structure 10 can be bonded while surface activation is performed, for example, by exposing the surface of the structures to a plasma containing oxygen or nitrogen. Subsequently, the wafers are pressed together, and a bond is formed at the bonding interface 18. Generally speaking, wafer bonding can be achieved using essentially any technique known in the art, as long as the energy used to achieve the formation of the bonding interface is sufficient to ensure that the integrity of the bonding interface is maintained during subsequent processing (in other words, layer transfer by separation along the cleavage plane or separation plane 17 in the donor wafer). Once prepared, the bonded wafer structure 20 is placed in a cleavage apparatus 110 (Figure 1), and a portion of the donor wafer is separated (in other words, cleaved) from the bonded structure along the cleavage plane to form a layered semiconductor structure. Generally speaking, the cleaving device 110 can induce this fracture using techniques known in the art, such as thermally and / or mechanically induced cleaving techniques.

[0019] Referring to Figure 5, two structures 30 and 31 are formed during separation. Since the separation of the bonded wafer structure 20 is performed along the cleavage plane 17 of the donor structure 12 (Figure 4), a portion of the donor structure remains as part of both structures (in other words, a portion of the donor wafer is transferred along with the dielectric layer). Structure 30 constitutes a portion of the donor wafer. Structure 31 is an SOI structure and includes a handle layer 10, a dielectric layer 15 (also called a BOX layer), and a device layer 25 (the portion of the donor wafer remaining after cleavage) placed on top of the dielectric layer 15. In this specification, the device layer may also be referred to as the SOI layer. In embodiments in which both the donor structure and the handle structure include a dielectric layer, the dielectric layers are bonded to form the dielectric layer 15 of the SOI structure. The cleavage plane of the layered semiconductor structure (in other words, the thin device layer of the donor wafer) has a rough surface that may be smoothed by additional processing. Structure 31 may undergo additional processing to produce a device layer surface with desirable characteristics for manufacturing a device on it. The cleaving apparatus 110 used to separate the bonded wafer structure along the cleavage plane may be a mechanical cleaving apparatus that uses mechanical force to induce or achieve separation, either alone or in addition to annealing. For example, the bonded structure can be placed in a fixture that applies mechanical force perpendicular to the opposing sides of the bonded structure in order to pull a portion of the donor structure away from the bonded structure.

[0020] As shown in Figure 6, an exemplary cleavage apparatus includes a suction cup 60 that applies mechanical force near the leading cleave edge of the bonded wafer structure 20. Separation of the donor wafer can be initiated at the edge of the bonded wafer by applying a mechanical wedge or blade 65 to the cleavage surface 17 to initiate crack propagation along the cleavage surface 17. The mechanical force applied by the suction cup 60 then pulls the portion of the donor structure away from the bonded structure, forming an SOI structure. Cleavage apparatuses are commercially available, such as Debond & Cleave Tools from Silicon Genesis (San Jose, California).

[0021] In an alternative embodiment, the cleaving apparatus 110 is a thermal cleaving apparatus in which fracture is achieved by annealing the bonded structure. For example, thermal cleaving can be performed in an inert (e.g., argon or nitrogen) atmosphere or under ambient conditions at a temperature of about 200°C to about 800°C, or about 250°C to about 650°C, for at least about 10 seconds, at least about 1 minute, at least about 15 minutes, at least about 1 hour, or at least about 3 hours (higher temperatures require shorter annealing times, and vice versa). The thermal cleaving apparatus 110 may be a belt furnace in which the propagation of cleavage is achieved at the leading edge of the bonded structure (in other words, the leading edge in the direction of travel of the structure through the furnace) and proceeds toward the trailing edge of the bonded wafer structure. Other types of cleaving apparatuses may also be used.

[0022] The cleaving apparatus 110 can generally be configured to process bonded wafer structures of any size, including, for example, bonded wafer structures with a diameter of 200 mm, 300 mm, greater than 300 mm, or 450 mm. In some embodiments, the cleaving apparatus is configured to process bonded wafer structures with a diameter of 200 mm or 300 mm.

[0023] Referring again to Figure 1, the cleavage system 100 includes an acoustic sensor 120 for sensing sound emitted from the bonded wafer structure during cleavage and generating an output in response to the sensed sound. The acoustic sensor 120 can be a microphone, a piezo sensor, a MEMS device, a sound pressure / sound field converter, etc.

[0024] The control device 130 is configured to control the cleavage apparatus and generate one or more metrics related to the attributes of the cleavage (e.g., duration of the cleavage, quality of the cleavage, whether a state of no interlayer transfer occurred as the cleavage progressed across the wafer, or whether a pause occurred in the cleavage) based on the output recorded from the acoustic sensor 120. In some embodiments, the metrics generated by the control device 130 are derived from an audio power profile generated during cleavage. The audio power profile can be derived from audio amplitude. Examples of metrics that can be calculated include the delay between the triggering of cleavage and the sensing of the start of cleavage, the duration of the cleavage, the average power during cleavage, the maximum power, the frequency of maximum power occurrences, the standard deviation of power, the magnitude of power fluctuations, the amount of cleavage time below the threshold power, the maximum single dip (dip) time below the threshold power, and the number of power dips below the threshold power. In some embodiments, two or more measurement criteria are generated, or three or more, five or more, seven or more, or ten or more measurement criteria are generated by the control device 130.

[0025] The control device 130 may be a computer system. In this specification, a computer system refers to known computing devices and computer systems. All such computer systems, as described herein, include processors and memory. However, any processor in a computer system referred to herein may refer to one or more processors located in a single computing device or in multiple computing devices operating in parallel. Furthermore, any memory in a computer device referred to herein may refer to one or more memory locations, and these memory locations may be in a single computing device or in multiple computing devices operating in parallel.

[0026] As used herein, the term "processor" refers to a central processing unit, microprocessor, microcontroller, reduced instruction set circuit (RISC), application-specific integrated circuit (ASIC), logic circuit, and other circuits or processors capable of performing the functions described herein. The foregoing are illustrative examples and do not limit the definition or meaning of the term "processor."

[0027] The term "database" may refer to the data itself, a relational database management system (RDBMS), or both, and includes any collection of data, including hierarchical databases, relational databases, flat-file databases, object-relational databases, object-oriented databases, and other structured collections of records or data stored in a computer system. The above are examples and do not limit the definition or meaning of the term database. Examples of RDBMS include, but are not limited to, Oracle Database, MySQL, IBM DB2, Microsoft SQL Server, Sybase, and PostgreSQL. However, any database that enables the systems and methods described herein may be used. (Oracle is a registered trademark of Oracle Corporation (Redwood Shores, California), IBM is a registered trademark of International Business Machines Corporation (Armonk, New York), Microsoft is a registered trademark of Microsoft Corporation (Redmond, Washington), and Sybase is a registered trademark of Sybase (Dublin, California)).

[0028] In one embodiment, a computer program for implementing the control device 130 is provided, and this program is implemented on a computer-readable medium. In this embodiment, it does not require connection to a server computer and runs on the computer system alone. In a further embodiment, the computer system runs in a Windows environment (Windows is a registered trademark of Microsoft Corporation, Redmond, Washington). In yet another embodiment, the computer system runs in a mainframe environment and a UNIX server environment (UNIX is a registered trademark of X / Open Company Limited, Reading, Berkshire, UK). Alternatively, the computer system runs in any suitable operating system environment. This computer program is flexible and designed to operate in a variety of different environments without compromising its core functionality. In some embodiments, the computer system includes multiple components distributed across multiple computing devices. One or more components may take the form of computer-executable instructions implemented on a computer-readable medium.

[0029] Computer systems and processes are not limited to the specific embodiments described herein. Furthermore, each component of a computer system and each process can be carried out independently and separately from other components and processes described herein. Each component and process can also be used in combination with other assembly packages and processes.

[0030] In another embodiment, the memory included in the computer system of the control device 130 may include a plurality of modules. Each module may include instructions configured to be executed using at least one processor. When the instructions included in the plurality of modules are executed by one or more processors of the computing device, at least a portion of the methods described herein can be implemented.

[0031] One embodiment of a computer system includes a media output component for presenting information to a user. The media output component is any component that can convey information (e.g., metrics related to cleavage) to the user. In some embodiments, the media output component includes output adapters such as a video adapter and / or an audio adapter. The output adapter is operably coupled to a processor and is further configured to be operably coupled to an output device such as a display device (e.g., a liquid crystal display (LCD), an organic light-emitting diode (OLED) display, a cathode ray tube (CRT), or an "electronic ink" display) or an audio output device (e.g., a speaker or headphones).

[0032] Figure 7 shows an example of an imaging station 700 for performing reflectivity measurement (also referred to herein as a thickness measurement station or system). The imaging station 700 may be part of the cleavage system 100 or it may be separate from the cleavage system 100. Furthermore, the imaging station 700 can be additionally used for imaging other than reflectivity imaging. In an example embodiment, the imaging station 700 is used to image the SOI structure 31 after cleavage has been performed. In some embodiments, the imaging station 700 can be used on the bonded wafer 20 before cleavage. In addition, or alternatively, the imaging station 700 can be used for imaging and / or reflectivity measurement of the wafer or structure at any point in the manufacturing process.

[0033] The imaging station 700 includes a camera 702, a light source 704, and a control device 706 that controls the camera 702 and the light source 704 to image the SOI structure 31 and create one or more thickness maps of the SOI structure 31.

[0034] In one embodiment, the imaging station 700 is used for RGB reflectance measurement, and the camera 702 is an RGB camera capable of separately capturing red, green, and blue light in separate channels. In another embodiment, the camera is an n-color camera. For example, a monochrome camera can be used in combination with n filters. Each filter is used with the camera to acquire one of n different color images.

[0035] Camera 702 is positioned above the center of the structure 31 (or the structure is moved so that its center is directly below camera 702). Camera 702 has a field of view wide enough to capture the entire SOI structure 31 without moving.

[0036] Although two lights are shown, any suitable number of light sources 704 can be included. In this embodiment, the light sources 704 include independently controllable red, green, and blue light-emitting diodes (LEDs), each emitting light at a known wavelength. In other embodiments, the light sources are full-spectrum LEDs, LEDs of any other color or combination of colors, or other light sources suitable for use in reflectivity measurements. In this embodiment, the light sources 704 are non-coherent light sources; that is, the light sources are not coherent and produce light containing multiple wavelengths, frequencies, and / or phases.

[0037] The control device 706 may be the control device 130, or another control device containing similar components. The control device 706 controls the light source 704 to illuminate the SOI structure 31 and controls the camera 702 to image the reflected light from the SOI structure 31. At least a portion of the light that strikes the SOI structure 31 passes through one or more layers of the structure 31 before being reflected back to the camera 702. Based on the wavelength of the light, how the material of each layer affects the speed of light, reflection, and absorption, and the intensity of the light acquired by the camera 702, the thickness of the layers of the SOI structure 31 throughout the structure may be determined by the control device 706.

[0038] Next, one or more parameters of the cleavage process performed by the cleavage apparatus are modified by the control device 706 based on the generated thickness map to correct errors or generally improve the cleavage process for the next wafer.

[0039] In this embodiment, the control device 706 controls the light source 704 to illuminate the SOI structure 31, and the camera 702 acquires an image of the SOI structure. The image includes red, green, and blue images, each captured by a different channel of the RGB camera 702.

[0040] The accuracy of the described method can be improved by capturing and stacking multiple images, but this comes at the cost of additional time required to capture multiple images. Furthermore, the degree of improvement may vary depending on the amount of noise contained in each image. For example, if the gain and exposure are set to generate images with a noise factor of a single order of magnitude, 100 images can improve accuracy tenfold (or reduce the error tenfold). In addition, the resolution of camera 702 is a factor that determines the accuracy of the thickness map generated by this method. When camera 702 has an 8-bit resolution, the relative error of some of the ratios described later is less than 0.02, while when camera 702 has a 10-bit resolution, the error is less than 0.005.

[0041] The illumination provided by light source 704 can also affect the accuracy of the resulting thickness map. As the graphs in Figures 8-14 show, diffused, broad-spectrum white light does not yield more accurate results than narrowly separated light in the red, green, and blue wavelength bands. Figure 8 is a graph of an example of the filtered spectrum of an RGB camera. Figure 9 is a graph of the white spectrum of an example LED. Figure 10 is a graph of the resulting channel spectrum when the RGB camera from example Figure 8 is used with the white LED from example Figure 9. Figure 11 is a graph of the spectrum of an example RGB LED. Figure 12 is a graph of the resulting channel spectrum when the RGB camera from example Figure 8 is used with the RGB LED from example Figure 11. Figure 13 is a graph of the resulting channel spectrum from Figure 12, along with wavelength-dependent SOI and BOX deviation sensitivity. Figure 14 is a graph of the resulting channel spectrum from Figure 11, along with wavelength-dependent SOI and BOX deviation sensitivity.

[0042] Figure 15 shows some examples of methods to reduce illumination imperfections and create a layer thickness map without calibration.

[0043] As part of map generation, in step 1, the control device 706 captures or acquires red, green, and blue intensity images (IR, IG, and IB) of the SOI structure 31 (sometimes called the sample), and also acquires red, green, and blue intensity images (IrR, IrG, and IrB) of a reference bare silicon wafer acquired with the same or similar camera 702 under the same or similar conditions (e.g., illumination, temperature). Two types of illumination defects are visible in the images of the sample SOI structure and the bare silicon reference wafer. The first type of defect is caused by the illumination to the structure (both bare silicon and SOI structures) not being calibrated when imaging the structure. These defects appear as intensity hotspots located in the northeast and southwest of the wafer. The second type of defect is wavelength-dependent illumination defects. These defects appear as checkerboard-like intensity patterns on the image.

[0044] In step 2, the control device 706 corrects the uncalibrated illumination of the structure by using the ratio of the image intensities of two different color images to a third color image. For example, the control device 706 calculates the ratio of the intensity of the green image to the intensity of the red image of the SOI structure and the reference bare silicon wafer. Thus, the ratio of the SOI structure is TIFF2026525162000002.tif10150, the ratio of the reference wafer is The result is TIFF2026525162000003.tif10150. Furthermore, the control device 706 calculates the ratio of the intensity of the blue image to the intensity of the red image in an SOI structure. TIFF2026525162000004.tif10150, on the reference wafer The calculation is performed using TIFF2026525162000005.tif10150. Any of the three colors may be used as the denominator of the ratio, however, the same color must be used for all ratios in a given map calculation. As can be seen in the image of Step 2, taking these ratios reduces or eliminates the intensity hotspots seen in Step 1. Furthermore, in other embodiments, more than three colors can be used, and the technique described herein can be extended to include additional ratios using additional colors. Furthermore, it should be understood that, for example, when taking the ratio of a green image to a red image, the intensity value of each pixel in the green image is divided by the intensity value of the corresponding pixel in the red image. Thus, the result is a new image in which the intensity value of each pixel in the new image is equal to the ratio obtained by dividing the intensity value of the corresponding pixel from the green image by the intensity value of the corresponding pixel from the red image. This result may be referred to herein as an image or ratio.

[0045] In step 3, to reduce wavelength-dependent illumination imperfections, the ratio determined above for the SOI structure is divided by the corresponding intensity ratio of the reference bare silicon wafer. In other words, the control device is TIFF2026525162000006.tif10150 and Calculate TIFF2026525162000007.tif10150. As can be seen in the image of step 3, this reduces or removes the checkerboard pattern seen in the image of step 2.

[0046] When step 3 is completed, the correction of the image to compensate for uncalibrated illumination is completed, and the resulting intensity image (e.g., r GR and r BR ) is further processed to calculate the layer thickness map. The resulting intensity images r GR and r BR can be processed using any known technique for creating a thickness map from such images. A process example is described below.

[0047] First, calculate the average thickness of each layer of the entire structure from the obtained images r GR and r BR . This can be determined by inputting both r GR and r BR into the layer model. For example, FIG. 17 is a graph of the weight function for a given set of measured ratios r GR and r BR , and is for the modeled ratios r GR and r BR . The weight at each pixel / location is determined by Equation 1 below. JPEG2026525162000008.jpg17142 The peaks in FIG. 17 are where the measured ratios r GR and r BR are very close to the modeled ratios r GR and r BR . This is used when non-linearly searching for the wafer average dSOI / dBOX value using the wafer average values of measured r GR and r BR .

[0048] SOI layer JPEG2026525162000009.jpg676 and BOX layer Once the overall average thickness of JPEG2026525162000010.jpg676 is determined, a thickness map is calculated using a linear approximation formula. GR and r BR The ratio r is modeled as a function of dSOI and dBOX. GR and r BR As shown in Figure 16, which is the graph, it is a nonlinear function over a wide dSOI / dBOX range. However, when viewed in a small dSOI / dBOX range as shown in Figure 18, r GR and r BR It is quite close to a linear function and can be linearly approximated within a narrow dSOI / dBOX range typical of the deviations from the target of dSOI and dBOX in an SOI structure.

[0049] The thickness map is created by calculating the thickness of all points in the SOI structure as a linear deviation map from the average thickness. That is, the control device 706 determines how much each point in the layer of the SOI structure 31 differs (positive or negative) from the calculated average thickness. This linear approximation can be performed, for example, as follows: This can be done using JPEG2026525162000011.jpg9130. Equivalent to JPEG2026525162000012.jpg9119, Use JPEG2026525162000013.jpg18127.

[0050] Finally, the determined thickness is corrected for errors caused by angular distortion resulting from the camera being relatively close to the surface of the SOI structure 31 and not using collimation optics. That is, for example, not all light perpendicular and parallel to each other to the surface of the SOI structure enters the camera. Instead, some of the light near the center enters the camera 702 roughly perpendicular to the surface of the SOI structure 31, while some (particularly light reflected from the edges of the wafer) enters at a significantly different angle and is not parallel to the light reflected from the center. This correction can be determined as follows: JPEG2026525162000014.jpg12134

[0051] Figure 19 is a block diagram of an example embodiment of a computing device 400 suitable for use as a control device 130 (Figure 1) and / or a control device 706 (Figure 7). For example, computing device 400 is representative of computing device 106 described above with reference to Figure 2. A wafer measuring device 102, a wafer processing device 104, and a removal map profile library 110 may include all or a subset of the components of computing device 400. Computing device 400 includes a processor 405 for executing instructions. In some embodiments, executable instructions are stored in a memory area 410. The processor 405 may include one or more processing units (e.g., a multi-core configuration). The memory area 410 is any device that allows information such as executable instructions and / or data to be stored and retrieved. The memory area 410 may include one or more computer-readable storage devices or other computer-readable media, including transient and non-transient computer-readable media.

[0052] In at least some embodiments, the computing device 400 also includes at least one media output component 415 for presenting information to the user 401. The media output component 415 is any component that can convey information to the user 401. In some embodiments, the media output component 415 includes an output adapter, such as a video adapter and / or an audio adapter. The output adapter is operably connected to the processor 405 and operably connected to an output device, such as a display device (e.g., a liquid crystal display (LCD), an organic light-emitting diode (OLED) display, a cathode ray tube (CRT), or an "electronic ink" display) or an audio output device (e.g., a speaker or headphones). In some embodiments, at least one such display device and / or audio device is included in the media output component 415.

[0053] In some embodiments, the computing device 400 includes an input device 420 for receiving input from a user 401. The input device 420 may include, for example, a keyboard, a pointing device, a mouse, a stylus, a touch-sensitive panel (e.g., a touchpad or touchscreen), a gyroscope, an accelerometer, a position detector, or an audio input device. A single component, such as a touchscreen, may also function as both an output device and an input device 420 for the media output component 415.

[0054] The computing device 400 may also include a communication interface 425, which can be communicatively connected to one or more remote devices such as a wafer measuring device 102, a wafer processing device 104, and / or a removal map profile library 110. The communication interface 425 may include, for example, a wired or wireless network adapter or a wireless data transceiver for use with a cellular network (e.g., GSM (Global System for Mobile communications), 3G, 4G, or Bluetooth) or other mobile data network (e.g., WiMAX (Worldwide Interoperability for Microwave Access)).

[0055] Storing in the memory area 410 are, for example, processor-executable instructions for providing a user interface to user 401 via media output component 415 and, optionally, for receiving and processing input from input device 420. The memory area 410 may include, but is not limited to, any computer operating hardware suitable for storing and / or retrieving processor-executable instructions and / or data. The memory area 410 may include random access memory (RAM) such as dynamic RAM (DRAM) and static RAM (SRAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and non-volatile RAM (NVRAM). Furthermore, the memory area 410 may include multiple storage units such as hard disks or solid-state disks in an inexpensive redundant array (RAID) configuration. The memory area 410 may include a storage area network (SAN) and / or network-attached storage (NAS) system. In some embodiments, the memory area 410 includes memory integrated into the computing device 400. For example, computing device 400 may include one or more hard disk drives as memory area 410. Memory area 410 may also include memory located outside computing device 400 and accessible by multiple computing devices. The types of memory described above are illustrative and do not limit the types of memory that a processor can use to store instructions and / or data.

[0056] Where used herein in conjunction with ranges of dimensions, concentrations, temperatures, or other physical or chemical properties or characteristics, the terms “about,” “substantially,” “essentially,” and “approximately” mean to encompass any variations that may exist in the upper and / or lower limits of the range of properties or characteristics, including variations resulting from, for example, rounding, measurement methods, or other statistical variations.

[0057] When describing elements or embodiments of the present disclosure, the articles “a,” “an,” “the,” and “said” are intended to indicate that there is one or more elements. The terms “comprising,” “including,” “containing,” and “having” are intended to indicate comprehensiveness and mean that there may be additional elements other than those listed. The use of terms indicating a particular orientation (e.g., “up,” “down,” “side,” etc.) is for explanatory convenience and does not require a particular orientation of the item being described.

[0058] Because various modifications are possible in the above configuration and method without departing from the scope of this disclosure, all matters included in the above description and shown in the accompanying drawings are intended to be illustrative and not limiting.

Claims

1. A camera positioned above the center of the semiconductor structure to acquire light reflected by the semiconductor structure. At least one light source that provides non-coherent and non-parallel light, and A control device comprising a processor and memory, operably coupled to the RGB camera and the at least one light source, When executed by the processor, the memory performs the following processing on the control unit: Illuminating the semiconductor structure with non-coherent and non-parallel light from at least one of the aforementioned light sources, The method involves causing the camera to acquire at least one image of the semiconductor structure illuminated by light from the light source, wherein the at least one image includes separate images of a first color, a second color, and a third color, and the first, second, and third colors are different from each other. Based on the images of the first, second, and third colors and the reference images of the first, second, and third colors of a reference silicon wafer, a thickness map is generated for at least two layers of the semiconductor structure. Includes instructions to execute, Thickness measurement system.

2. The instruction causes the control device to generate the thickness map based at least in part on the ratio of the light intensity of the images of the first, second, and third colors of the semiconductor structure and the reference images of the first, second, and third colors of the reference silicon wafer. The thickness measuring system according to claim 1.

3. The aforementioned instruction instructs the control device to perform the following process: To determine a first semiconductor structure ratio, which is the ratio of the light intensity of the first color image of the semiconductor structure to the light intensity of the third color image of the semiconductor structure. To determine the second semiconductor structure ratio, which is the ratio of the light intensity of the second color image of the semiconductor structure to the light intensity of the third color image of the semiconductor structure. To determine a first reference ratio, which is the ratio of the light intensity of the first color image of the reference silicon wafer to the light intensity of the third color image of the reference silicon wafer, and Determine a second reference ratio, which is the ratio of the light intensity of the second color image of the reference silicon wafer to the light intensity of the third color image of the reference silicon wafer. By executing this, the thickness map is generated, at least partially. The thickness measuring system according to claim 2.

4. The aforementioned instruction instructs the control device to perform the following process: The first resulting ratio is determined by dividing the first semiconductor structure ratio by the first reference ratio, and The second resulting ratio is determined by dividing the second semiconductor structure ratio by the second reference ratio. By executing this, the thickness map is generated as at least a part of it. The thickness measuring system according to claim 3.

5. The command causes the control device to calculate the average thickness of each layer and, for each layer, to calculate a final layer thickness map as a linear deviation map from the average thickness of that layer. A thickness measuring system according to any one of claims 1 to 4.

6. The instruction causes the control device to correct the thickness map for angular distortion resulting from the camera being positioned relatively close to the semiconductor structure and the absence of a collimation optical system. A thickness measuring system according to any one of claims 1 to 4.

7. The semiconductor structure includes a silicon-on-insulator (SOI) structure, and the at least two layers include an SOI layer and an embedded oxide (BOX) layer. A thickness measuring system according to any one of claims 1 to 4.

8. The first color is red, the second color is green, and the third color is blue. A thickness measuring system according to any one of claims 1 to 4.

9. The aforementioned camera includes red, green, and blue cameras (RGB cameras), The thickness measuring system according to claim 8.

10. The at least one light source includes red, green, and blue (RGB) light-emitting diode (LED) lights, The thickness measuring system according to claim 8.

11. A method for measuring the thickness of a semiconductor structure, Illuminating the semiconductor structure with non-coherent and non-parallel light from at least one light source, The method involves using a camera to acquire at least one image of the semiconductor structure illuminated by light from the light source, wherein the at least one image includes separate images of a first color, a second color, and a third color, and the first, second, and third colors are distinct from each other. This includes generating a thickness map for at least two layers of the semiconductor structure based on the images of the first, second, and third colors and the reference images of the first, second, and third colors of a reference silicon wafer. method.

12. The generation of the thickness map includes generating the thickness map based at least in part on the ratio of the light intensity of the first, second, and third color images of the semiconductor structure and the first, second, and third color reference images of the reference silicon wafer. The method according to claim 11.

13. Generating the aforementioned thickness map is To determine a first semiconductor structure ratio, which is the ratio of the light intensity of the first color image of the semiconductor structure to the light intensity of the third color image of the semiconductor structure. To determine the second semiconductor structure ratio, which is the ratio of the light intensity of the second color image of the semiconductor structure to the light intensity of the third color image of the semiconductor structure. To determine a first reference ratio, which is the ratio of the light intensity of the first color image of the reference silicon wafer to the light intensity of the third color image of the reference silicon wafer, and This includes determining a second reference ratio, which is the ratio of the light intensity of the second color image of the reference silicon wafer to the light intensity of the third color image of the reference silicon wafer. The method according to claim 12.

14. Generating the aforementioned thickness map is The first resulting ratio is determined by dividing the first semiconductor structure ratio by the first reference ratio. The second resulting ratio is determined by dividing the second semiconductor structure ratio by the second reference ratio. This includes generating a thickness map based on the first result ratio and the second result ratio, The method according to claim 13.

15. Generating the aforementioned thickness map is This includes calculating the average thickness of each layer and, for each layer, calculating a final thickness map as a linear deviation map from the average thickness of that layer. The method according to any one of claims 11 to 14.

16. For each layer, calculating the final thickness map as a linear deviation map from the average thickness of that layer is: This is done using The method according to claim 15.

17. the following: Use The method according to claim 15.

18. The method further includes correcting the thickness map for angular distortion resulting from the camera being positioned relatively close to the semiconductor structure and the absence of a collimation optical system. The method according to any one of claims 11 to 14.

19. The correction of the aforementioned thickness map is as follows: Use The method according to claim 18.

20. The semiconductor structure includes a silicon-on-insulator (SOI) structure, and the at least two layers include an SOI layer and an embedded oxide (BOX) layer. The method according to any one of claims 11 to 14.

21. The first color is red, the second color is green, and the third color is blue. The method according to any one of claims 11 to 14.

22. Acquiring at least one image of the semiconductor structure using a camera includes acquiring the at least one image using a red, green, and blue camera (RGB camera). The method according to claim 18.

23. Illuminating the semiconductor structure includes illuminating the semiconductor structure using red, green, and blue light-emitting diode (RGB LED) light. The method according to claim 18.

Images