Semiconductor wafers and manufacturing processes

Abstract

Semiconductor wafer (100) which exhibits: first and second main surfaces (102, 104) that are opposite each other in a vertical direction (y); a side surface (106) that surrounds the semiconductor wafer (100); and a lateral distance (108) perpendicular to the vertical direction (y) between the side face (106) and a center (110) of the semiconductor wafer (100), wherein the lateral distance (108) comprises first and second parts (112, 114), the first part (112) extending from the side face (106) to the second part (114) and the second part (114) extending from the first part (112) to the center (110), and wherein a mean concentration of oxygen in the first part (112) is greater than 5 x 10 14 cm -3and the mean concentration of oxygen in the first part (112) exceeds the mean concentration in the second part (114) by more than 20%, and wherein a concentration profile of oxygen corresponds to a diffusion profile of oxygen entering the semiconductor wafer (100) through the side surface (106) via an oven diffusion process.

Description

BACKGROUND

[0001] The fabrication of semiconductor devices requires various processes, such as material deposition, removal, structuring, and modification of the semiconductor's electrical properties. Reference is made, by way of example, to the disclosures in publications JP H05-062 867 A and JP H07-086 291 A. Some of these processes are carried out at high temperatures, for example, epitaxial growth and annealing. Processing the semiconductor at high temperatures creates thermal gradients within the semiconductor, which lead to mechanical stresses. The semiconductor can respond to mechanical stresses exceeding a certain threshold, for example, by changing its crystal structure to relieve the stress, such as by shifting crystal planes relative to each other along preferred crystal lattice planes.This leads to a local disruption of the lattice, accompanied by crystal defects such as slip lines. Slip lines can be detrimental to the performance of electrical devices, for example, by increasing leakage current. As wafer dimensions increase, the problem of crystal defect generation due to wafer processing methods such as front-end-of-line (FEOL) processing becomes even more challenging.

[0002] It is desirable to increase the mechanical stability of a semiconductor wafer and to specify a method for producing a semiconductor wafer with improved mechanical stability. SUMMARY

[0003] The problem is solved by teaching independent patent claims. Further developments are the subject of dependent claims.

[0004] The expert will recognize additional features and advantages upon reading the following detailed description and examining the accompanying illustrations. BRIEF DESCRIPTION OF THE IMAGES

[0005] The accompanying drawings are included to provide a further understanding of embodiments of the invention and are incorporated into and form part of the disclosure of this invention. The drawings illustrate the embodiments of the present invention and, together with the description, serve to explain the principles. Other embodiments of the invention and many of the intended advantages are immediately appreciated, as they are better understood with reference to the following detailed description. Fig. Figure 1A is a schematic top view of an embodiment of a semiconductor wafer. Fig. Figure 1B is a schematic cross-sectional view of the semiconductor wafer of Fig. 1A along the intersection line A-A'. Fig. 1C is a diagram illustrating embodiments of profiles and mean concentrations of at least one element consisting of oxygen and nitrogen from a side surface of the semiconductor wafer of Fig. 1A to the center of the semiconductor wafer. Fig. Figure 2 is a flowchart of an embodiment of a method for manufacturing a semiconductor wafer. Fig. Figure 3 is a schematic representation of an embodiment of processing a semiconductor wafer starting with a semiconductor ingot or semiconductor bar. Fig. Figure 4 is a flowchart of another embodiment of a method for processing a semiconductor wafer. Fig. Figure 5 is a schematic representation of an embodiment of introducing at least one element consisting of nitrogen and oxygen into a semiconductor wafer. DETAILED DESCRIPTION

[0006] The following detailed description refers to the accompanying drawings, which form part of the disclosure and show specific embodiments for illustrative purposes in which the invention can be implemented. It is understood that other embodiments can be used and structural or logical modifications can be made without departing from the scope of the present invention. For example, features illustrated or described for one embodiment can be used in or in conjunction with other embodiments to arrive at yet another embodiment. It is intended that the present invention encompasses such modifications and changes. The examples are described using specific language, which should not be interpreted as limiting the scope of the appended claims.The drawings are not to scale and are for illustrative purposes only. For clarity, the same elements are marked with corresponding reference symbols in the various drawings, unless otherwise stated.

[0007] The terms "have," "contain," "comprise," "exhibit," and similar terms are open-ended, indicating the presence of the identified structures, elements, or features without excluding additional elements or features. Indefinite and definite articles should encompass both the plural and singular unless the context clearly indicates otherwise.

[0008] The term "electrically connected" describes a permanent, low-resistance connection between electrically connected elements, for example, a direct contact between the elements in question or a low-resistance connection via a metal and / or a highly doped semiconductor. The term "electrically coupled" implies that one or more intermediate elements designed for signal transmission may be present between the electrically coupled elements, for example, elements that provide a low-resistance connection in a first state and a high-resistance electrical decoupling in a second state.

[0009] The figures illustrate relative doping concentrations by indicating "-" or "+" next to the doping concentration "n" or "p". For example, "n-" indicates a doping concentration lower than that of an "n" doping area, while an "n+" doping area has a higher doping concentration than an "n" doping area. Doping areas with the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" doping areas can have the same or different absolute doping concentrations.

[0010] The terms "wafer," "substrate," or "semiconductor wafer," as used in the following description, can encompass any semiconductor-based structure that has a semiconductor surface. Wafer and structure are to be understood as including silicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor substrate, and other semiconductor structures. The semiconductor need not be silicon-based; it could just as easily be silicon-germanium, germanium, or gallium arsenide. According to other embodiments, silicon carbide (SiC) or gallium nitride (GaN) can form the semiconductor substrate material.

[0011] The term "horizontal," as used in this description, is intended to describe an orientation essentially parallel to a first surface of a semiconductor substrate or body. This could be, for example, the surface of a wafer, a die, or a chip.

[0012] The term “vertical”, as used in the present description, is intended to describe an orientation that is essentially perpendicular to the first surface of the semiconductor substrate or semiconductor body.

[0013] In this description, a second surface of a semiconductor substrate or semiconductor body is considered to be formed by the lower or backside surface, while the first surface is considered to be formed by the upper, front, or main surface of the semiconductor substrate. The terms "above" and "below," as used in this description, are therefore intended to describe the relative position of one structural feature to another.

[0014] In this description, n-doped refers to a first conductivity type, while p-doped refers to a second conductivity type. Alternatively, the semiconductor devices can be formed with opposite doping relationships, so that the first conductivity type can be p-doped and the second conductivity type n-doped.

[0015] The semiconductor device can have contact points, such as contact pads (or electrodes), that allow electrical contact with the integrated circuits or a separate semiconductor device contained within the semiconductor body. The electrodes can comprise one or more electrode metal layers applied to the semiconductor material of the semiconductor chips. The electrode metal layers can be manufactured with any desired geometric shape and material composition. For example, the electrode metal layers can be in the form of a layer covering an area. Any desired metal, such as Cu, Ni, Sn, Au, Ag, Pt, Pd, and an alloy of one or more of these metals, can be used as the material. The electrode metal layer, orThe electrode metal layers do not need to be homogeneously made from a single material, allowing for different compositions and concentrations of the materials contained within them. For example, the electrode layers can be large enough to be bonded or connected to a wire.

[0016] In the embodiments disclosed herein, one or more conductive layers are applied. It should be emphasized that terms such as "formed" or "applied" are to be understood as encompassing all types and techniques of layer application. In particular, they mean that they include techniques in which layers are applied all at once, for example, as a whole, such as lamination techniques, as well as techniques in which layers are applied sequentially, such as by sputtering, plating, molding, CVD (chemical vapor deposition), PVD (physical vapor deposition), evaporation, hybrid physicochemical vapor deposition (HPCVD), and so on.

[0017] The conductive layer used can comprise, among other things, one or more layers of metal, such as copper or tin, or an alloy thereof, a layer of conductive paste, and a layer of bonding material. The metal layer can be a homogeneous layer. The conductive paste can comprise metal particles dispersed in a vaporizable or curable polymer material, and the paste can be fluid, viscous, or waxy. The bonding material can electrically and mechanically secure or connect the semiconductor chip, for example, to a substrate or a contact clip. A soft solder material, or in particular a solder material capable of forming diffusion solder bonds, can be used, for example, a solder material comprising one or more components of tin, tin ag, tin-auger, tin-cubic copper, inferred oxide, inferred oxide, inferred oxide, inferred oxide, inferred oxide, inferred oxide, and inferred oxide.

[0018] A singulation process can be used to divide the wafer into individual chips. Any division technique can be applied, such as knife cutting (sawing), laser cutting, etching, and so on. Stealth cutting, in particular, is a specific technique that utilizes laser cutting. Stealth cutting allows for the suppression of cutting waste and is therefore a suitable process for cutting workpieces prone to damage. Furthermore, it is a dry process that does not require cleaning and is therefore also suitable for processing sensitive structures, such as MEMS, that are subject to stress.Further advantages that can be achieved through stealth splitting technology include high-speed splitting, superior fracture strength, a narrow kerf, and low operating costs.

[0019] One embodiment of a semiconductor wafer 100 is described in the Fig. Shown 1A to 1C. Fig. 1A relates to a schematic top view of the semiconductor wafer 100, Fig. 1B relates to a schematic cross-sectional view along the section line AA' of Fig. 1A, and Fig. 1C relates to a diagram for representing a concentration c of at least one element consisting of nitrogen (N) and oxygen (O) along the intersection line AA' of Fig. 1A.

[0020] The semiconductor wafer 100 has first and second principal surfaces 102, 104, which are opposite each other in a vertical direction y. A side surface 106 surrounds the semiconductor wafer 100. A lateral distance 108 perpendicular to the vertical direction y between the side surface 106 and a center 110 of the semiconductor wafer 100 defines first and second parts 112, 114. The first part 112 extends from the first side surface 106 to the second part 114. The second part extends from the first part 112 to the center 110. The average concentration ca1 of oxygen in the first part 112 is greater than 5 x 10 14 cm -3 and exceeds the mean concentration ca2 of oxygen in the second part 114 by more than 20% of the mean concentration ca2 of oxygen in the second part 114. In some embodiments, the mean concentration ca1 of oxygen in the first part 112 is greater than 3 x 10 17 cm -3, and larger than 5 x 10 17 cm -3 , or even larger than 8 x 10 17 cm -3 Exemplary profiles of the oxygen concentration c in the first and second parts 112, 114 are schematically represented by curves c1, c2 in Fig. Figure 1C illustrates this. Curve c1 represents an embodiment of a concentration profile in which the oxygen element decreases along more than 80% of a lateral dimension of the first part, starting from side face 106. A profile corresponding to curve c1 and similar profiles can be obtained by diffusion of the oxygen element through the side face 106 of the semiconductor wafer 100. Curve c2 represents an exemplary concentration profile in which the oxygen element, along a lateral direction x, corresponds to a step-like concentration profile, including a decrease in concentration at an interface between the first part 112 and the second part 114.A profile corresponding to curve c2 and similar profiles can be formed by ion implantation and / or diffusion of the element oxygen through one or both of the first and second main surfaces 102, 104 using an ion implantation and / or diffusion mask which covers the semiconductor wafer 100 in the second part 114 and exposes the semiconductor wafer 100 in the first part 112.

[0021] In some embodiments, the semiconductor wafer 100 is a Czochralski (CZ) silicon wafer, produced, for example, by the standard CZ process, the magnetic CZ (MCZ) process, or the continuous CZ (CCZ) process. In some other embodiments, the semiconductor wafer 100 is a float-zone (FZ) silicon wafer. Optionally, an epitaxial layer may be deposited on at least one of the first and second principal surfaces 102, 104. In some embodiments, the thickness of this epitaxial layer is between 1 µm and 200 µm.

[0022] In some embodiments, a lateral dimension l of the first part 112 between the side surface 106 and the second part 114 lies between 10 µm and 1 cm, or between 20 µm and 5 mm.

[0023] In some embodiments, the mean concentration of oxygen in an edge region 118 of the semiconductor wafer 100 exceeds the mean concentration of oxygen in the central part 120 of the semiconductor wafer 100, which is surrounded by the edge region 118, by more than 20%, or even by more than 50%, or even by more than a factor of 2. The relationship between the mean concentration of oxygen in the central part and the edge region 120, 118 may be invalid with respect to a portion of the side surface 106 that covers a notch or flat. In the Fig. In the embodiment shown in Figure 1A, a flat 122 is shown schematically. In some other embodiments, the semiconductor wafer 100 may additionally or alternatively have a notch or another type of marking which indicates the crystallographic planes of the semiconductor wafer 100.

[0024] In some embodiments, the semiconductor wafer 100 is a 12-inch semiconductor wafer or larger.

[0025] In some embodiments, the mean concentration of the element oxygen in the first part 112 is more than ten times, or more than one hundred times, than in the second part 114.

[0026] The presence of oxygen in the quantities required to raise the stress threshold at which slip lines form in silicon leads to the formation of thermal donors in the silicon. These are detrimental to lightly doped silicon wafers, such as those used as base material for insulated-gate bipolar transistors (IGBTs). Even if an epitaxial layer or layers are formed on CZ or MCZ wafers, the required oxygen quantities can be critical due to oxygen diffusion during the formation of the epitaxial layer or layers, for example, through deposition or growth of the epitaxial layer or layers and subsequent high-temperature processing.Since nitrogen reacts with hydrogen in silicon and with defects created by proton implantation, for example in the production of field stop zones by means of proton implantation, unwanted electrically active effects can be generated.

[0027] The embodiments described herein provide a semiconductor wafer with improved mechanical stability. In these embodiments, the mechanical stability of the first part 112, which acts as a nucleation zone for slip lines extending towards the center 110 of the semiconductor wafer, is enhanced by the addition of oxygen. The first part 112 can correspond to, or form part of, an edge inclusion region along a circumference of the semiconductor wafer 100 in which no semiconductor dies are manufactured. Since the concentration of oxygen in the second part 114 of the semiconductor wafer 100 is lower than in the first part 112, undesirable defect generation caused by oxygen in the first part 112 can be counteracted and / or avoided.

[0028] Fig. Figure 2 shows a flowchart of an embodiment of a method 200 for manufacturing a semiconductor wafer.

[0029] While Method 200 is presented and described as a sequence of operations or events, the presented sequence of such operations or events is not to be interpreted restrictively. For example, some operations may occur in a different order and / or concurrently with other operations or events, apart from those presented and / or described herein. Likewise, not all of the presented operations are necessarily required to implement one or more aspects of embodiments of this disclosure. Likewise, one or more of the operations shown herein may be performed in one or more separate operations and / or surfaces.

[0030] In the S200, a block of semiconductor material is provided. The semiconductor block comprises opposing first and second surfaces as well as a side surface surrounding the semiconductor block. In some embodiments, the semiconductor block is a silicon block. In some other embodiments, the semiconductor block can be other than silicon and consist of a material whose mechanical stability can be enhanced by at least one nitrogen and oxygen element. The semiconductor block can be formed from a semiconductor ingot or a semiconductor rod by a cutting process, for example, a sawing process such as wire sawing.

[0031] In S210, at least one nitrogen-oxygen element is introduced into the semiconductor block through the side face. A lateral distance between the side face and the center of the semiconductor block is divided into first and second parts. The first part extends from the side face to the second part, and the second part extends from the first part to the center. The average concentration of the at least one nitrogen-oxygen element in the first part is greater than 5 x 10⁻⁶. 14 cm -3 and exceeds the average concentration of the at least one element of nitrogen and oxygen in the second part by more than 20% of the average concentration of the at least one element of nitrogen and oxygen in the second part.

[0032] In S220, the semiconductor block is sliced ​​into semiconductor wafers. The semiconductor wafers can be formed by slicing the semiconductor block, for example, using a sawing process such as wire sawing.

[0033] In some embodiments, the at least one nitrogen-oxygen element is introduced into the semiconductor body through the side surface by means of an oven diffusion process. In some embodiments, the oven diffusion process is carried out in a nitrogen atmosphere at temperatures greater than 900°C, or even greater than 1000°C, for a duration of more than one hour. Additionally or alternatively, the oven diffusion process can also be carried out in an oxygen atmosphere at temperatures greater than 1100°C, or greater than 1150°C, or even greater than 1200°C, for a duration of more than one hour.

[0034] Fig. Figure 3 is a schematic representation of an exemplary process 300 for manufacturing a silicon wafer.

[0035] Starting with a silicon ingot 350, which is produced, for example, by drawing a silicon crystal, a silicon block 352 is cut from the silicon ingot 350 in phase P1, e.g., by a sawing process.

[0036] In phase P2, the silicon ingot 352 is subjected to an oven process. During this process, nitrogen diffuses through an outer surface of the silicon ingot 352 into a surface region 353 within a volume of the silicon ingot 352. The oven process can be carried out in a nitrogen atmosphere at temperatures greater than 900°C, or even greater than 1000°C, for more than one hour. Higher temperatures, for example, 1100°C or 1200°C or even higher, and longer diffusion times, for example, 2 hours, 4 hours, 10 hours, or even longer, can be used depending on the desired nitrogen concentration in the surface region 353. Alternatively, phase P1 can be omitted, so that the entire silicon ingot 350 is subjected to the oven process for the diffusion of nitrogen and / or oxygen.

[0037] Then, in phase P3, the silicon block 352 is sliced ​​into silicon wafer 355. The nitrogen introduced into the silicon block 352 at P2 is present only in the surface region 353 that surrounds an inner or middle part of the semiconductor wafer 355. In this inner or middle part of the semiconductor wafer 355, the nitrogen concentration corresponds to the concentration previously established in the silicon ingot 350. Enriching the silicon wafer 355 with nitrogen in the surface region 353 enables improved mechanical stability of the silicon wafer 355.

[0038] Fig. Figure 4 is a flowchart of an embodiment of a method 400 for manufacturing a semiconductor wafer. While Method 400 is presented and described as a sequence of operations or events, the presented sequence of such operations or events is not to be interpreted restrictively. For example, some operations may occur in a different sequence and / or concurrently with other operations or events, apart from those presented and / or described herein. Likewise, not all of the presented operations are necessarily required to implement one or more aspects of embodiments of this disclosure. Likewise, one or more of the operations shown herein may be performed in one or more separate operations and / or surfaces.

[0039] In S400, a semiconductor wafer is formed by cutting a block of semiconductor material, e.g. by a sawing process.

[0040] In S410, a diffusion barrier is formed on at least one of the opposing first and second surfaces of the semiconductor wafer, wherein the diffusion barrier covers a central portion of the semiconductor wafer on the first and second surfaces and leaves at least a peripheral portion of the semiconductor wafer uncovered on at least one of the first and second surfaces. In some embodiments, the diffusion barrier is formed by completely covering the semiconductor wafer with a diffusion barrier material, e.g., by a thermal oxidation process, and partially removing the diffusion barrier material. In some embodiments, the diffusion barrier is formed on one of the first and second principal surfaces of the semiconductor wafer, for example, on a front face of the semiconductor wafer where planar or gate-trench electrodes are formed during FEOL processes.Oxygen entering the semiconductor wafer from the back or rear side can increase stability against slip line formation without interfering with field-stop doping. Since the semiconductor material can be removed from the back or rear side before a field-stop ion implantation process, oxygen penetrating the back side of the silicon wafer can only lead to negligible amounts of thermal donors. Optionally, an oxygen diffusion barrier, such as an oxide / nitride layer stack, can be formed on a surface region of the silicon wafer where, for example, dies or raw chips are later implemented via FEOL processing. This restricts oxygen diffusion to a region of the silicon wafer near the wafer edge.If both the first and second main surfaces of the semiconductor wafer are subjected to FEOL processing without removing the semiconductor material from either the first or second main surfaces, the diffusion barrier can be formed on both of the opposing first and second main surfaces of the semiconductor wafer.

[0041] In S420, at least one element consisting of nitrogen and oxygen is introduced into the semiconductor wafer through an uncovered area of ​​the semiconductor wafer, for example by a diffusion and / or ion implantation process.

[0042] In some embodiments, the semiconductor wafer is a silicon wafer. In some other embodiments, the semiconductor wafer differs from silicon and consists of a material whose mechanical stability can be enhanced by at least one element consisting of nitrogen and oxygen.

[0043] In some embodiments, the diffusion barrier is formed as a single layer or as a stack of layers of oxide and nitride.

[0044] In some embodiments, the maximum lateral dimension between a side face of the semiconductor wafer and the diffusion barrier is between 1 mm and 1 cm.

[0045] In some embodiments, the at least one nitrogen-oxygen element is introduced into the semiconductor wafer via an oven diffusion process. The oven diffusion process can be carried out in a nitrogen atmosphere at temperatures greater than 900°C, or greater than 1000°C, or even greater than 1100°C for a duration of more than 1 hour, more than 5 hours, or even more than 20 hours. Additionally or alternatively, the oven diffusion process is carried out in an oxygen atmosphere at temperatures greater than 1100°C, or even greater than 1200°C, for a duration of more than 1 hour, more than 5 hours, or even more than 20 hours.

[0046] Fig. Figure 5 is a schematic representation of an exemplary process for manufacturing a silicon wafer.

[0047] Starting with a silicon wafer 550, which is produced, for example, by cutting a silicon block, a diffusion barrier material 552 is formed on a surface of the silicon wafer 550 in the PP1 phase, for example by growing onto the silicon wafer by thermal oxidation.

[0048] In phase PP2, part of the diffusion barrier material 552 is removed from a side surface 554 and from an edge region 556 of the silicon wafer 550, thereby exposing the silicon wafer at the side surface 554 and at opposite main surfaces in the edge region 556.

[0049] In phase PP3, nitrogen is introduced into an unmasked surface region 558 of the semiconductor wafer 550 through a side surface 554 and through opposing main surfaces in the edge region 556, for example by a diffusion and / or ion implantation process. In some embodiments, diffusion takes place in an oven diffusion process in a nitrogen atmosphere at temperatures greater than 900°C, or even greater than 1000°C, for a duration of more than 1 hour, or more than 2 hours, or even more than 5 or 10 hours. In some embodiments, the silicon wafer 550 has an oxygen concentration of less than 2.5 x 10⁻⁵. 17 cm -3 up, or less than 2.0 x 10 17 cm -3To prevent the formation of thermal donors and any interference with field stop zones produced by a proton irradiation process, an oven diffusion process can optionally, additionally, or alternatively be performed at temperatures above 1100°C, 1150°C, or even 1200°C in an oxygen atmosphere, for example, prior to a front-side polishing process. This can lead to oxygen diffusion across the entire surface of the 550 semiconductor wafer. Most of the oxygen introduced through the front side is removed by the front-side thinning / polishing process. Optionally, a barrier layer, such as an oxide / nitride stack, acting as a diffusion barrier against oxygen diffusion, can be formed on the front side, for example, by layer deposition.The front surface can be one of two opposing main surfaces of the silicon wafer 550 where planar or gate-trench electrodes are formed during FEOL processes. Oxygen penetrating the silicon wafer from the back surface can also increase stability against slip line formation without interfering with field-stop doping. Since semiconductor material on the back surface can be removed before a field-stop ion implantation process, oxygen entering the silicon wafer 550 from the back surface can only lead to thermal donors in negligible amounts. Optionally, an oxygen diffusion barrier, for example, an oxide / nitride layer stack, can be formed on a surface region of the silicon wafer 550 where dies or raw chips are later implemented via FEOL processing, thereby facilitating oxygen diffusion into a region of the silicon wafer 550 near the wafer edge.

[0050] In phase PP4, the diffusion barrier 552 is removed, for example by mechanical and / or chemical processes such as etching and polishing.

[0051] Front-end-of-line (FEOL) processing can follow on the main surfaces of the silicon wafer 550 to produce dies or raw chips, including discrete semiconductor devices and / or integrated circuits.

[0052] Although specific embodiments are illustrated and described here, it is obvious to those skilled in the art that a multitude of alternative and / or equivalent designs can be used for the specific embodiments shown and described without departing from the scope of the present invention. This application is therefore intended to cover any adaptations or modifications of the specific embodiments discussed herein.

Claims

[1] Semiconductor wafer (100) which has: first and second main surfaces (102, 104) that are opposite each other in a vertical direction (y); a side surface (106) that surrounds the semiconductor wafer (100); and a lateral distance (108) perpendicular to the vertical direction (y) between the side face (106) and a center (110) of the semiconductor wafer (100), wherein the lateral distance (108) comprises first and second parts (112, 114), the first part (112) extending from the side face (106) to the second part (114) and the second part (114) extending from the first part (112) to the center (110), and wherein a mean concentration of oxygen in the first part (112) is greater than 5 x 10 14 cm -3and the mean concentration of oxygen in the first part (112) exceeds the mean concentration in the second part (114) by more than 20%, and wherein a concentration profile of oxygen corresponds to a diffusion profile of oxygen entering the semiconductor wafer (100) through the side surface (106) via an oven diffusion process. [2] Semiconductor wafer (100) according to claim 1, wherein the semiconductor wafer (100) is a Czochralski silicon wafer or a float-zone silicon wafer. [3] Semiconductor wafer (100) according to one of the preceding claims, wherein a lateral dimension (l) of the first part (112) between the side surface (106) and the second part (114) is between 10 µm and 1 cm. [4] Semiconductor wafer (100) according to one of the preceding claims, wherein the concentration of oxygen decreases along more than 80% of a lateral dimension (l) of the first part (112) starting from the side surface (106). [5] Semiconductor wafer (100) according to any of the preceding claims, wherein an average concentration of oxygen in an edge region (118) of the semiconductor wafer (100) exceeds an average concentration of oxygen in a central region (120) surrounded by the edge region (118) by more than 20%. [6] Semiconductor wafer (100) according to claim 5, wherein a maximum lateral dimension of the edge region (118) between the side surface (106) and the middle region (120) is between 10 µm and 1 cm. [7] Semiconductor wafer (100) according to claim 1, wherein the semiconductor wafer (100) is a 12 inch semiconductor wafer or larger. [8] Semiconductor wafer (100) according to claim 1, wherein the average concentration of oxygen in the first part (112) is more than ten times greater than in the second part (114). [9] Method (200) for producing a semiconductor wafer which has: Providing a block of semiconductor material, wherein the block of semiconductor material has opposing first and second surfaces and a side surface surrounding the semiconductor block (S200); Introducing at least oxygen into the semiconductor block through the side surface, wherein a lateral distance between the side surface and a center of the semiconductor block comprises first and second parts, the first part extending from the side surface to the second part and the second part extending from the first part to the center, and wherein an average concentration of oxygen in the first part is greater than 5 x 10 14 cm -3 is and the mean concentration of oxygen in the first part exceeds the mean concentration of oxygen in the second part by more than 20% (S210), and wherein the oxygen is introduced into the semiconductor block through the side surface by means of an oven diffusion process; and Cutting the semiconductor block in the semiconductor wafer (S220). [10] Method (200) according to claim 9, wherein the furnace diffusion process is carried out in an oxygen atmosphere at temperatures greater than 1100°C for a duration of more than 1 hour. [11] Method (400) for processing a semiconductor wafer which has: Forming a semiconductor wafer by cutting a semiconductor block (S400); Forming a diffusion barrier on at least one of opposing first and second surfaces of the semiconductor wafer, wherein the diffusion barrier covers a central part of the semiconductor wafer on at least one of the first and second surfaces and leaves a peripheral region of the semiconductor wafer uncovered on the first and second surfaces (S410); and Introducing at least one nitrogen and oxygen compound into the semiconductor wafer through an uncovered area of ​​the semiconductor wafer (S420) at the first and second surfaces, wherein the at least one nitrogen and oxygen compound is introduced into the semiconductor wafer by an oven diffusion process. [12] Method (400) according to claim 11, wherein the diffusion barrier is formed as a single layer or as a stack of layers of oxide and nitride. [13] Method (400) according to claim 11, wherein a maximum lateral dimension between a side face of the semiconductor wafer and the diffusion barrier is between 10 µm and 1 cm. [14] Method (400) according to claim 11, wherein the furnace diffusion process is carried out in a nitrogen atmosphere at temperatures greater than 900°C for a duration of more than 1 hour. [15] Method (400) according to claim 11, wherein the furnace diffusion process is carried out in an oxygen atmosphere at temperatures greater than 1200°C for a duration of more than 1 hour.

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