Embedding of photonic integrated circuits in semiconductor packages for high-bandwidth memory and computing.

Abstract

A photonic integrated circuit (PIC) comprising: a semiconductor die disposed on a substrate and coupled to one another, containing an active portion and a passive portion, wherein the active portion is configured to consume power when activated, and the passive portion comprises an optical transmission medium configured to propagate optical signals to or from the active portion of the PIC; an electronic integrated circuit (EIC) electrically coupled to the active portion of the PIC and comprising components that electrically act on the active portion of the PIC; and a packaging compound that at least partially encapsulates the PIC, wherein the packaging compound defines a cavity on the side of the semiconductor die opposite the substrate, and the cavity is filled with an optically transparent medium so that optical signals can be received from or transmitted to the passive portion of the PIC through the cavity.

Description

Background Art

[0001] (Cross - reference to related applications) This application claims the benefit of U.S. Provisional Patent Application No. 63 / 616,465, filed Dec. 29, 2023, entitled “Photonic Interconnect Platform for Memory and Compute”; claims the benefit of U.S. Patent Application No. 18 / 583,749, filed Feb. 21, 2024, entitled “Embedding a Photonic Integrated Circuit in a Semiconductor Package for High Bandwidth Memory and Compute”; is a continuation application, claiming the benefit of U.S. Patent Application No. 18 / 584,748, filed Feb. 22, 2024, entitled “Embedding a Photonic Integrated Circuit in a Semiconductor Package for High Bandwidth Memory and Compute”, both of which are incorporated herein by reference.

[0002] The demand for artificial intelligence (AI) computing, such as machine learning (ML) and deep learning (DL), is increasing faster than can be satisfied by the available processing capacity. The rising demand and growing complexity of AI models drive the need to connect multiple chips within a system such that the chips can transmit data to each other at high speed with short latency. The performance when processing a certain amount of work is limited by memory and interconnect bandwidth. In many conventional systems, data movement leads to significant power consumption, poor performance, and excessive latency. Therefore, a multi - node computing system that can process and transmit data quickly and efficiently between nodes can be advantageous for the implementation of (ML) models.

Summary of the Invention

Means for Solving the Problems

[0003] This specification describes a photonic integrated circuit (PIC) comprising a semiconductor die containing an active portion and a passive portion, arranged on a substrate and coupled to each other, wherein the active portion is configured to consume power when activated, and the passive portion comprises an optical transmission medium configured to allow optical signals to propagate to or from the active portion of the PIC; an electronic integrated circuit (EIC) comprising a component electrically coupled to and acting electrically on the active portion of the PIC; and a packaging compound that at least partially encapsulates the PIC, wherein the packaging compound defines a cavity on the side of the semiconductor die opposite the substrate, and the cavity is filled with a transparent (i.e., optically transparent) medium so that optical signals can be received from or transmitted to the passive portion of the PIC through the cavity.

[0004] This specification also describes a method for embedding a photonic integrated circuit (PIC) in a package comprising the PIC and at least one electronic integrated circuit (EIC), wherein the PIC comprises an active portion that consumes power when the PIC is activated and a passive portion comprising an optical transmission medium configured to allow optical signals to propagate to or from the active portion, and the method comprising the steps of masking a portion of the surface of the PIC with a mask material, wherein the portion corresponds to one or more photonic ports in the passive portion of the PIC; depositing a layer of molding material to at least partially encapsulate the PIC, including the mask material; and removing a portion of the molding material sufficient to expose the mask material.

[0005] This specification also describes a method for embedding a photonic integrated circuit (PIC) in a package comprising the PIC and at least one electronic integrated circuit (EIC), wherein the PIC comprises an active portion that consumes power when the PIC is activated and a passive portion comprising an optical transmission medium configured to allow optical signals to propagate to or from the active portion, and the method comprising: depositing a first layer of curable material on a portion of the surface of the PIC, wherein the portion of the surface corresponds to one or more photonic ports in the passive portion of the PIC; curing the curable material to provide a layer of solid and transparent material adjacent to the portion of the surface of the PIC; depositing a layer of molding material to at least partially encapsulate the PIC including the layer of solid and transparent material; and removing a portion of the molding material sufficient to expose the solid and transparent material.

[0006] Additional features and advantages will be described in the following description. The features and advantages of the technology described herein can be realized and obtained, in particular, using the systems and methods pointed out in the appended claims. Such features will be more fully apparent from the following description and the appended claims, or can be acquired by the practice of the disclosed subject matter as described later in this specification. [Brief explanation of the drawing]

[0007] To illustrate the manner in which the above and other features of this specification can be obtained, more specific descriptions will be given with reference to the specific examples illustrated in the accompanying drawings. For a deeper understanding, similar elements are designated by the same reference numbers throughout the various accompanying drawings. With understanding that the drawings depict several exemplary embodiments, the embodiments will be described and explained with additional specificity and detail through the use of the accompanying drawings. [Figure 1-1] Figure 1-1 is a schematic diagram illustrating the components of an exemplary package-in-a-system (SIP). [Figure 1-2]Figure 1-2 is a block diagram illustrating the various components of the computing node embodiment shown in Figure 1-1. [Figure 1-3] Figure 1-3 is a block diagram illustrating the various components of the exemplary computing node shown in Figure 1-1. [Figure 1-4] Figure 1-4 is a schematic diagram illustrating a side view of an exemplary structural implementation of the circuit package shown in Figure 1-1. [Figure 2-1] Figure 2-1 illustrates an example of a circuit package that implements an in-chip bidirectional photonic channel between a first computing node and a second computing node. [Figure 2-2] Figure 2-2 illustrates an exemplary circuit package that implements an inter-chip bidirectional photonic channel between a computing node and an additional computing node located on an additional circuit package. [Figure 3-1] Figure 3-1 is a schematic diagram illustrating an example of a circuit package that implements multiple computing nodes. [Figure 3-2] Figure 3-2 is a schematic diagram illustrating an embodiment of the circuit package shown in Figure 3-1. [Figure 3-3] Figure 3-3 is a schematic diagram illustrating an embodiment of the circuit package shown in Figure 3-1. [Figure 3-4] Figure 3-4 is a schematic diagram illustrating an embodiment of the circuit package shown in Figure 3-1. [Figure 3-5] Figure 3-5 is a schematic diagram illustrating an embodiment of the circuit package shown in Figure 3-1. [Figure 4] Figure 4 is a schematic diagram illustrating an exemplary implementation of four interconnected circuit packages from Figure 2-1. [Figure 5-1] Figure 5-1 illustrates the steps in an exemplary process for packaging a combined EIC-PIC stack. [Figure 5-2] Figure 5-2 illustrates another step in the exemplary process shown in Figure 5-1. [Figure 5-3]Figure 5-3 illustrates yet another step in the exemplary process shown in Figure 5-1. [Figure 5-4] Figure 5-4 illustrates yet another step in the exemplary process shown in Figure 5-1. [Figure 5-5] Figure 5-5 illustrates additional steps between the exemplary processes shown in Figure 5-1. [Figure 5-6] Figure 5-6 illustrates one or more steps in the exemplary process shown in Figure 5-1. [Figure 6] Figure 6 illustrates an example of a combined EIC-PIC stack. [Figure 7-1] Figure 7-1 illustrates the steps in another exemplary process for packaging the combined EIC-PIC stack. [Figure 7-2] Figure 7-2 illustrates another step in the exemplary process shown in Figure 7-1. [Figure 7-3] Figure 7-3 illustrates yet another step in the exemplary process shown in Figure 7-1. [Figure 7-4] Figure 7-4 illustrates yet another step in the exemplary process shown in Figure 7-1. [Figure 7-5] Figure 7-5 illustrates yet another step in the exemplary process shown in Figure 7-1. [Figure 7-6] Figure 7-6 illustrates additional steps between the exemplary processes shown in Figure 7-1. [Figure 7-7] Figure 7-7 illustrates additional steps between the exemplary processes shown in Figure 7-1. [Figure 7-8] Figure 7-8 illustrates further additional steps between the exemplary process shown in Figure 7-1. [Figure 7-9] Figure 7-9 illustrates further additional steps between the exemplary process shown in Figure 7-1. [Figure 7-10] Figure 7-10 illustrates one or more steps in the exemplary process shown in Figure 7-1. [Figure 7-11]Figure 7-11 illustrates one or more additional steps during the exemplary process of Figure 7-1. [Figure 7-12] Figure 7-12 illustrates another embodiment of a cap that can be used within the exemplary process shown in Figures 7-1 through 7-11, in a cross-sectional profile. [Figure 7-13] Figure 7-13 illustrates a top view of an embodiment of a cap that can be used within the exemplary process shown in Figures 7-1 through 7-11. [Figure 7-14] Figure 7-14 illustrates a top view of another embodiment of a cap that can be used within the exemplary process shown in Figures 7-1 through 7-11. [Figure 7-15] Figure 7-15 illustrates a top view of another embodiment of a cap that can be used within the exemplary process shown in Figures 7-1 through 7-11. [Figure 7-16] Figure 7-16 illustrates a top view of another embodiment of a cap that can be used within the exemplary process shown in Figures 7-1 through 7-11. [Figure 8] Figure 8 illustrates another embodiment of a circuit package that implements an inter-chip bidirectional photonic channel between a computing node and an additional computing node located on an additional circuit package. [Figure 9] Figure 9 illustrates a component that can be included within a computer system.

Mode for Carrying Out the Invention

[0008] Detailed Description This specification describes a computing system implemented by one or more circuit packages, e.g., SIPs, that achieve reduced power consumption and / or increased processing speed. According to various embodiments, in particular, power consumed for data movement is reduced compared to conventional computer systems by increasing data localization within each circuit package and reducing energy loss when data movement is required. Power-efficient data movement can be achieved by leveraging photonic channels for data movement in scenarios where the resistance within the electronic domain and / or the speed at which data can move within the electronic domain leads to bandwidth limitations that cannot be overcome using existing electronic technologies, while moving data over short distances within the electronic domain. Accordingly, in some embodiments, each circuit package includes an electronic integrated circuit (EIC) comprising multiple circuit blocks, hereafter referred to as "processing elements" or "computing nodes," which are connected in a hybrid optoelectronic (also called optoelectronic) on-chip network (NoC) by bidirectional photonic channels, for example, implemented in a separate layer of the package or within a PIC on a chip. Multiple such NoCs can be connected within a larger optical-electric network by inter-chip bidirectional photonic channels, for example, implemented by optical fibers between individual circuit packages, allowing the computing system to be scaled to any size without significant power or speed losses.

[0009] The computing systems and their various novel aspects described are generally applicable to a wide range of processing tasks, but they are particularly suited for implementing ML models, especially artificial neural networks (ANNs). When applied to ANNs, the interconnected circuit packages and systems described herein are also referred to as "ML processors" and "ML accelerators," respectively. A neural network generally includes one or more layers of artificial neurons that compute neuron output activations from a weighted sum corresponding to a sum-of-products (MAC) operation of a set of input activations. With respect to a given neural network, the flow of activations between nodes and layers is fixed. Furthermore, once the training of the neural network is complete, any other parameters associated with the steps of computing neuron weights and activations in the weighted sum are also fixed. Therefore, NoCs as described herein are suitable for implementing neural networks by assigning neural nodes to computing nodes, preloading fixed weights associated with the nodes into the memory of individual computing nodes, and configuring data routing between computing nodes based on a predetermined flow of activations. The weighted sums can be efficiently performed using a dot product engine, also referred to herein as a “digital neural network (DNN)” due to its availability for ANNs.

[0010] The above-mentioned general description of the various beneficial aspects, features, and underlying concepts of the computing system being described will become clearer from the following description of exemplary embodiments.

[0011] Figure 1 is a schematic diagram illustrating the components of an exemplary circuit package 100, for example, a SIP. The circuit package 100 may function, for example, as an ML processor. The circuit package 100 includes an electronic integrated circuit 101 (EIC), for example, a digital and mixed-signal application-specific integrated circuit (ASIC), and a photonic integrated circuit 102 (PIC). The EIC 101 and PIC 102 are formed in different layers of the circuit package 100, which may be referred to as the “electronic circuit layer” and the “photonic circuit layer,” respectively, as further illustrated below with reference to Figure 1-4, and one is stacked on top of the other, for example, using copper pillars, bump mounting, or other means, to create an electrical interconnection for transmitting and receiving messages, packets, and / or data between the EIC and the PIC. The PIC or multiple PIC102s receive light from one or more laser sources, which are either integrated into the PIC102 itself or implemented separately from the PIC102, either inside or outside the circuit package 100, and can be coupled into the PIC102 via a suitable optical coupler. The optical coupler and laser sources are omitted from Figure 1-1 but are shown, for example, in Figure 1-4. Generally, the laser sources and optical couplers are selected to provide optical signals within a wavelength band intended for the PIC102 and other optical components in the system to operate. In some embodiments, the operating wavelength is within a spectral band in the range of 1,500 nm to 1,600 nm, for example, referred to as the C-band and / or L-band.

[0012] The EIC101 includes a plurality of computing nodes 1104. As will be discussed in detail herein, the computing nodes 1104 may communicate with each other via one or more in-chip bidirectional channels. The in-chip bidirectional channels may include one or more bidirectional photonic channels implemented, for example, using optical waveguides in the PIC102, and / or one or more electronic channels implemented, for example, within the network of the EIC101. The computing nodes 1104 may be electronic circuits of the same or at least substantially similar design, and may form identical “tiles” arranged in an array, matrix, grid, or any other arrangement, which is suitable for carrying out the techniques described herein, as shown.

[0013] In this embodiment, the EIC101 has 16 computing nodes 1104 arranged in a 4x4 array, but the number and arrangement of computing nodes can generally vary. More generally, neither the shape of the computing nodes nor the grid in which the computing nodes are arranged necessarily has to be rectangular; for example, diagonal quadrilateral, triangular, or hexagonal shapes and grids, as well as topologies with three or more dimensions, can also be used. Furthermore, tiling can provide efficient use of available on-chip occupancy, but the computing nodes 104 do not need to be equally sized and regularly arranged in all embodiments. As shown in Figure 1-1, in some embodiments, the computing nodes 104 are arranged in a linear array, for example, a conceptual square array.

[0014] Each computing node 1104 within the EIC101 may include one or more circuit blocks that act as processing engines. For example, in the implementation shown in Figure 1-1, each computing node 1104 includes a dot product engine or DNN 1106 and a tensor engine 1108. The DNN 1106 performs high-speed MAC operations with reduced energy per MAC, and can, for example, execute either a convolution function or a dot product function, which are commonly used in neural networks. The tensor engine 108 may perform other non-MAC operations, for example, to implement a nonlinear activation function, such as one applied to weighted sums in a neural network. In other embodiments, the computing node 1104 may have any combination of processing elements such as a CPU, GPU, TPU, and equivalents, and the DNN 1106 and tensor engine 1108 may also be included or omitted, depending on the application.

[0015] Each computing node 1104 includes a message router 1110. The message router 1110 interfaces with channels, such as electronic and / or photonic channels, as described below with reference to Figure 1-2, and facilitates data flow to and from the computing nodes 1104. Furthermore, each computing node 1104 has a memory system, for example, including a level 1 static random access memory (L1SRAM) 1112 and a level 2 static random access memory (L2SRAM) 1114. The L1SRAM 1112 is optional and, if included, can serve as scratchpad memory for each computing node 1104. The L2SRAM 1114 may function as primary memory for each computing node 1104 and may store fixed operands, such as weights for machine learning models, used by the DNN 1106 and tensor engine 1108, in physical proximity to the DNN 1106 and tensor engine 1108. L2SRAM1114 may also store any intermediate results used when running machine learning models or other computing tasks.

[0016] Figure 1-2 is a block diagram illustrating various components of an embodiment of the computing node 1104 of Figure 1-1. Here, the computing node 104 includes various computing components 130, which may include, among other things, the DNN 1106, tensor engine 1108, interface controller, routing controller, L1SRAM 1112, and / or L2SRAM 1114 of Figure 1-1. In some embodiments, the computing component 130 includes memory components, such as a memory controller, vertically stacked high-bandwidth memory, so that the computing node 104 may be a memory node as will be described herein. The computing component 130 is implemented on the EIC 101-1 of the computing node 104 and communicates with the message router 110. For example, the message router 110 may receive messages from other computing components via either an optical port or an electronic connection 128, and may also send messages generated by individual computing nodes 104 of the message router 110 via either an optical port or an electronic connection 128. The message router is implemented on the EIC 101-1 and may be implemented through hardware, software, or a combination of hardware and software. The message router is shown as a single block, but may also include message routers associated with each photonic interface. As shown in Figure 1-2, the PIC 102 and EIC 101 may be part of the PIC 102 and / or EIC 101 in Figure 1-1, and may include various other computing components.

[0017] In some embodiments, the computing node 104 connects to one or more computing components through electronic channels, such as on-chip electronic channels. For example, as will be discussed in detail below, each of the various computing nodes 104 in Figure 1-1 may be connected to an adjacent node via an electronic channel. The computing node 104 may also be connected to any other computing components via one or more electronic channels. In some embodiments, the computing node 104 is configured to connect to up to four adjacent computing nodes 104 via electronic channels. In some embodiments, the computing node 104 may process data in the electrical domain within the computing node 104 using electrical ports (not shown) included in block 128, which are configured to connect to additional components and / or nodes via electronic connections, such as other on-chip components. Each electronic channel connected to the computing node 104 may be connected to a message router 110, which is represented by an electronic connection 128. The electronic connection 128 may be implemented within the EIC 101 of the computing node 104. Messages or packets transmitted through the electronic connection 128 are therefore passed to the message router 110, which is then acted upon to automatically forward those messages to additional computing components, or to pass messages from within to the computing component 130 of the computing node 104. Thus, the computing node 104, more specifically the message router 110, may be configured to connect to and communicate with one or more computing components through the electronic connection 128.

[0018] In some embodiments, the computing node 104 is configured to connect to one or more optical connections or photonic channels. For example, as shown in Figure 1-2, the computing node 104 includes four photonic ports 120-1, 120-2, 120-3, and 120-4, collectively known as photonic port 120. The four photonic ports 120-1 through 120-4 connect to four photonic channels. Photonic port 120 facilitates the connection of photonic connections to the computing node 104. For example, photonic port 120 may include and / or connect to one or more waveguides to directly transmit optical signals to and / or from the computing node 104. Photonic port 120 is implemented within PIC102-1. In some embodiments, the photonic channel is a bidirectional photonic channel to facilitate both transmission and reception of communications through photonic port 120. For example, each bidirectional photonic channel may include two or more unidirectional links, such as one or more transmit links and one or more receive links. The unidirectional links may be associated with and connected to the individual transmit and receive components of the photonic interface 122, as discussed below. In this way, the photonic port 120 facilitates the connection of the computing node 104 to one or more bidirectional photonic channels for photonic communication with other computing devices.

[0019] Each photonic port 120 is associated with and connected to a corresponding photonic interface 122 (PI), i.e., photonic port 120-1 is connected to photonic interface 122-1, and so on. The photonic interfaces 122 facilitate the conversion of messages or signals between the electronic domain and the photonic domain. In particular, each photonic interface, as illustrated with respect to, for example, photonic interface 122-2, includes an electrical / optical (EO) interface 124 for converting electronic signals to optical, e.g., photonic signals, and an optical / electrical (OE) interface 126 for converting signals to electronic signals. Figure 1-2 shows PI 122-2 having only the EO interface 124 and the OE interface 126, but each PI 122 may include one or both of these interfaces, and typically includes multiple unidirectional photonic links connecting to the port in both directions, supporting, for example, wavelength division multiplexing (WDM) or other schemes.

[0020] As discussed above, each bidirectional photonic channel may include two or more unidirectional photonic links. Each unidirectional photonic link may include both the EO interface 124 and the OE interface 126, or may be associated with both the EO interface 124 and the OE interface 126. For example, as shown in Figure 1-3, the EO interface 124 of computing node 104a connects to the OE interface 126 of another computing device 104b, for example, another instance of the computing node, via a photonic port 120 and waveguides, etc., forming a unidirectional photonic link to send packets from computing node 104a to the other computing device 104b. Similarly, the EO interface 124 of the other computing device 104b connects to the OE interface 126 of computing node 104a, forming a unidirectional link to receive packets from the other computing device 104b to computing node 104a. In this way, PI 122 can facilitate bidirectional communication via bidirectional photonic channels connected to the photonic port 120.

[0021] In some embodiments, PI122 each includes various optical and electronic components. For example, EO interface 124 may include an optical modulator and an optical modulator driver. The optical modulator generally acts on an optical, e.g., laser light carrier signal, encoding information into an optical carrier signal, thereby transmitting the information optically / photonically. The optical modulator may be controlled or driven by an optical modulator driver. The optical modulator driver may receive an electronic signal, e.g., a packet encoded into an electronic signal, from the message router 110, and control the modulation of the modulator, converting or encoding the electronic signal into an optical signal. Thus, the optical modulator and driver may constitute EO interface 124 to facilitate the optical transmission of messages from the computing node 104.

[0022] The modulator can be an electroabsorption modulator (EAM), a semiconductor device that modulates the intensity of an optical signal by varying the absorption of the optical signal as it traverses the modulator based on the voltage applied to the EAM. Generally, the principle of operation of an EAM is based on the Franz-Keldysh effect, i.e., a change in the absorption spectrum caused by the applied electric field, which changes the bandgap energy, and therefore the photon energy of the absorption edge, but usually without the excitation of carriers by the electric field.

[0023] In some embodiments, the EAM is fabricated in the form of a waveguide with electrodes to apply an electric field perpendicular to the modulated optical signal. In some embodiments, the EAM is implemented within a layer of germanium silicon, for example, an epitaxially grown layer of GeSi. The germanium can be stoichiometrically more than 90% or 90% of the GeSi material, for example, more than 95% or 95%, more than 96% or 96%, more than 97% or 97%, more than 98% or 98%, or more than 99% or 99%.

[0024] In some embodiments, the OE interface 126 includes a photodiode and a transimpedance amplifier (TIA). The photodiode receives an optical signal, for example, from another computing device, through a unidirectional link of a bidirectional photonic channel, and converts the optical signal into an electronic signal. The photodiode may be connected to a TIA, which may include components and / or a network for gain control and signal level normalization, extract a bitstream, and communicate with the message router 110. Thus, the OE interface 126 may include a photodiode and a TIA to facilitate the optical reception of messages to the computing node 104.

[0025] In some embodiments, the PI122 is partially implemented within the PIC102-1 and partially implemented within the EIC101-1. For example, the optical modulator may be implemented within the PIC102-1 and electrically coupled to an optical modulator driver implemented within the EIC101-1. For example, the EIC101-1 and PIC102-1 may be stacked horizontally, and the optical modulator and optical modulator driver may be coupled through an electronic interconnect of the two components, such as copper pillars and / or bump mounts of various sizes. Similarly, the photodiode may be implemented within the PIC102-1 and the TIA may be implemented within the EIC101-1. The photodiode and TIA may be coupled through an electronic interconnect of the two components.

[0026] As shown in Figure 1-2, each PI 122 communicates with the message router 110. The PI 122 is connected to the message router 110 through an electronic interconnect in the EIC 101-1. The PI 122 communicates with the message router 110, transmits signals to the message router 110, and / or receives signals from there. In some embodiments, the message router 110 includes an electronic network and / or logic to facilitate the conversion of data packets into electronic signals, and then into optical signals in conjunction with the EO interface 124. Similarly, the message router 110 may include an electronic network and / or logic to facilitate the conversion of optical signals into electronic signals, and then into data packets in conjunction with the OE interface 124. Thus, the message router 110 can facilitate the conversion of data between the electronic domain and the optical domain and / or the operation of data.

[0027] The message router 110 may facilitate the routing of information and / or data packets to and from the computing node 104. For example, the message router 110 may examine an address contained in a message and determine that the message is destined for the computing node 104. The message router 110 may therefore automatically forward or transmit some or all of the message from its internal location to various computing components 130 of the computing node 104, for example, via an electronic connection. In another embodiment, the message router 110 may determine that the message is destined for another computing device, for example, that the message is either generated by the computing node 104 or received for transmission from one computing device to another. The message router 110 may therefore automatically forward or transmit some or all of the message to the other computing device through one or more of the channels (e.g., electronic or photonic) of the computing node 104. Thus, the message router 110 can connect to the electronic connection 128 and the bidirectional photonic channel connected to the photonic port 120, facilitating the implementation of computing nodes 104 within a network of computing devices for generating, transmitting, receiving, and automatically forwarding messages between various computing devices. In some embodiments, the computing node 104 is implemented within a network of multiple computing nodes 104, such as those shown in Figure 1-1.

[0028] The PIC102-1 includes one or more waveguides. A waveguide is a structure that guides and / or confines light waves to facilitate the propagation of light along a desired path and to a desired location. For example, a waveguide may be an optical fiber, a planar waveguide, a glass-etched waveguide, a photonic crystal waveguide, a free-space waveguide, any other suitable structure for directing optical signals, and a combination thereof. In some embodiments, one or more internal waveguides are formed within the PIC102-1. In some embodiments, one or more external waveguides, such as an optical fiber or a ribbon comprising multiple optical fibers, are mounted outside the PIC102-1.

[0029] The PIC102-1 may include one or more waveguides connecting to the photonic ports 120. For example, as will be discussed in more detail below, one or more of the photonic ports 120 may be connected to another port of another computing node, which is included as a computing node 104 within the circuit package 100, for example on the same chip. Such connections may be intra-chip connections. In some embodiments, internal waveguides may be implemented, for example, formed within the PIC102-1 to connect these photonic ports from within the chip. In other embodiments, one or more photonic ports 120 may be connected to photonic ports of another computing device located in a separate circuit package or on a separate chip, forming an inter-chip connection. In some embodiments, external waveguides are used to connect these photonic ports across multiple chips. For example, the photonic ports 120 may be connected across multiple chips via optical fibers. In some embodiments, the external waveguides, for example optical fibers, directly connect across multiple chips to the photonic ports 120 of individual computing devices. In some embodiments, the external waveguide is implemented in connection with one or more internal waveguides formed within the PIC102 of one or more chips. For example, one or more internal waveguides may internally connect one or more photonic ports 120 located in another part of the circuit package, e.g., another part of the PIC102, to one or more additional optical components to facilitate the coupling of optical signals to and from the external waveguide. For example, the internal waveguide may connect to one or more optical coupling structures, including fiber mounting units (FAUs) located above a grating coupler or edge coupler. In some embodiments, one or more FAUs are implemented to facilitate the coupling of the external waveguide to the internal waveguide, facilitate chip / chip interconnection to another circuit package, and perform both transmission and reception.For example, one or more FAUs can be used to supply optical power from an external laser light source to the PIC102-1 and to provide, for example, one or more carrier signals to drive photonics within the PIC102-1.

[0030] Figure 1-4 is a schematic diagram illustrating a side view of an exemplary structural implementation 1400 of the circuit package 100 of Figure 1-1. In this embodiment, the EIC 1401 and PIC 1402 are formed within separate semiconductor chips, typically silicon chips, although the use of other semiconductor materials is also possible. The PIC 1402 is placed directly on substrate 1440, shown with solder bumps for subsequent mounting to a printed circuit board (PCB). The EIC 1401 and FAU 1432, which connect the PIC 1402 to an external waveguide 1433, for example, an optical fiber, are positioned above the PIC 1402 and optically connected to it. Optionally, as discussed below, the circuit package 1400 may further include on-chip memory 1442, positioned above the PIC 1402 adjacent to the EIC 1401, as shown.

[0031] The depicted structure of circuit package 1400 is merely one of several possible ways of assembling and packaging various components. In some embodiments, some or all of the EIC1401 are placed on a substrate. In some embodiments, some or all of the PIC1402 are placed on top of the EIC1401. In some embodiments, it is also possible to fabricate the EIC1401 and PIC1402 within different layers of a single semiconductor chip. In some embodiments, the photonic circuit layer includes multiple PIC1402s in multiple sublayers, or is fabricated from multiple PIC1402s. Multiple layers or multilayer PIC1402s may help reduce waveguide intersections. Furthermore, the structure depicted in Figure 1-4 may be modified to include multiple EIC1401s connected to a single PIC1402. For example, multiple EIC1401s may be interconnected via photonic channels within the PIC1402s.

[0032] In general, the EICs and PICs described herein can be manufactured using standard wafer processing processes, such as photolithography patterning, etching, and ion implantation. Furthermore, in some embodiments, heterogeneous material platforms and integrated processes are used. For example, various active photonic components, such as optical modulators and photodetectors used in laser light sources and / or photonic channels, may be implemented using III-V semiconductor components.

[0033] A laser light source or multiple light sources can be mounted either inside or outside the circuit package 1400. When mounted externally, connection to the circuit package 1400 may be optically performed using a lattice coupler in the PIC1402 directly beneath the FAU1432 and / or using an edge coupler, as shown. In some embodiments, the lasers are mounted inside the circuit package 1400 by using an interposer containing several lasers that can be co-packaged and edge-coupled with the PIC1402. In some embodiments, the lasers are integrated directly into the PIC1402 using heterogeneous or homogeneous integration. Homogeneous integration allows the lasers to be mounted directly into a silicon substrate, in which the waveguide of the PIC1402 is formed, enabling architectures such as lasers of different materials, such as indium phosphide (InP), and quantum dot lasers. Heterogeneous assembly of lasers on the PIC1402 allows III-V semiconductors or other materials to be precisely mounted on the PIC1402 and optically coupled to waveguides mounted on the PIC1402.

[0034] As will be discussed in more detail below, several circuit packages 1400 may be interconnected to bring about a single system that provides a larger optoelectronic network by connecting several chip-level optoelectronic networks, for example, as described below. Multiple circuit packages configured as ML processors may be interconnected to form a larger ML accelerator. For example, photonic channels, optical connections, laser sources, passive optical components, and external optical fibers on the PCB within several circuit packages or ML processors may be utilized in various combinations and configurations with other photonic elements to form a photonic fabric of a multi-package system or multi-ML processor accelerator.

[0035] Figure 2-1 illustrates an embodiment of a circuit package 300 that implements an in-chip bidirectional photonic channel 342 between a first computing node 304-1 and a second computing node 304-2. The circuit package 300 includes various electronic and optical components that are implemented across the EIC 301 and PIC 302. The package 300 includes two computing nodes 304-1 and 304-2, collectively, a computing node 204, which each includes separate computing blocks 358-1 and 358-2, which may include various processing, storage, and / or communication functions. Each computing node 304 includes AMS blocks 360-1 and 360-2, collectively, an AMS block 360, which each includes analog / mixed-signal circuits for interface with the PIC 302. Each computing block 358 includes interfaces 292-1 and 292-2, collectively, interface 292, for communicating with AMS block 360, more specifically, with the components of AMS block 360. Each AMS block 360 includes modulator drivers 362-1 and 362-2, collectively, driver 362, and transimpedance amplifiers 364-1 and 364-2, collectively, TIA264.

[0036] The PIC302 includes a pair of modulators 356-1 and 356-2 and a pair of photodetectors 366-1 and 366-2. The PIC302 also includes a lattice coupler 354 or any other optical interface (OI) configured to receive light and pass it onto one or more components and a splitter 368.

[0037] The optical engine 350 provides an optical carrier signal for communication between the first computing node 304-1 and the second computing node 304-2. The optical engine 350 provides the carrier signal to the FAU 332 of the circuit package 300 via an optical fiber or the like. The FAU 332 is optically coupled to a lattice coupler 354, which directs the optical carrier signal onto other components of the electronics package 300. The splitter 368 receives the optical carrier signal from the lattice coupler 354 and splits the optical signal along two optical paths 370 and 372. More generally, the splitter 368 may distribute the optical carrier signal over any number of photonic paths consistent with those described herein. The optical paths 270 and 272 may be implemented as any suitable optical transmission medium, and may include a mixture of waveguides and optical fibers or any other transmission medium consistent with those described herein. In this embodiment, the optical paths 270 and 272 are implemented as waveguides within the PIC 302.

[0038] Optical paths 370 and 372 pass from splitter 368 to optical modulators 356-1 and 356-2, respectively. Each optical modulator modulates the optical carrier signal it receives from splitter 368 based on information from its individual optical drivers 362-1 and 362-2, and transmits the modulated signal along its individual optical path. The first photodetector 266-1 receives the modulated signal from the optical path, for example, from its associated modulator 256. As described, the optical path from modulator 356-1 connects to photodetector 266-2, and the optical path from modulator 356-2 connects to photodetector 266-1. The photodetector converts the received modulated signal into individual electrical signals and passes the electrical signals to transimpedance amplifier 264, which facilitates computing nodes 304-1 and 304-2 receiving the information encoded in the signals. Thus, communication occurs between computing nodes through the various components described above. The PIC302 described herein includes an embodiment of an in-chip bidirectional photonic channel, each comprising two unidirectional photonic links to facilitate communication both to and from computing nodes. Here, the first unidirectional photonic link is defined by a modulator driver 362-1, an optical modulator 356-1, an optical path 370, a photodiode 366-2, and a transimpedance amplifier 364-2. Similarly, the second unidirectional link is defined by a modulator driver 362-2, an optical modulator 356-2, an optical path 370, a photodiode 366-1, and a transimpedance amplifier 364-1. The first and second unidirectional links operate in opposite directions. In addition, one or more of the computing nodes 304 may include one or more serializers and / or deserializers to further facilitate signal communication between computing nodes 304. Thus, the two unidirectional photonic links form an in-chip bidirectional photonic channel 342.

[0039] Figure 2-2 illustrates an exemplary circuit package 200 that implements an inter-chip bidirectional photonic channel between a computing node 304 and an additional computing node 254 located on an additional circuit package 290, such as a memory node on a memory circuit package. The computing node 304 and / or electronic equipment package 200 may include an EIC 301 and a PIC 302, which include components discussed above with reference to Figure 2-1. Furthermore, the PIC 302 includes a demultiplexer 380 and a multiplexer 390. Generally, demultiplexers and multiplexers can be used within the PIC for wavelength division multiplexing of optical signals.

[0040] In the inter-chip configuration shown in Figure 2-2, the optical modulator 356 transmits the modulated signal along the optical path 374 to the grid coupler 354. The modulated signal is passed through the multiplexer 390 prior to being passed to the grid coupler 354. From the grid coupler 354, the modulated signal travels through the FAU 332 along the optical fiber to another grid coupler in the additional circuit package 290, where the receiving components of the additional circuit package 290 receive and process the incoming signal. The receiving components may be identical or similar to the receiving components of the circuit package 300 discussed above, or may include any other means for receiving and processing the incoming signal.

[0041] Similarly, the additional circuit package 290 generates and transmits signals to the computing node 304. The additional circuit package 290 generates and transmits signals using transmission components, which may include transmission components similar to or identical to those of the circuit package 300 discussed above, or any other means. The additional circuit package 290 transmits signals, for example, along optical fiber, to the FAU 332 and lattice coupler 354 of the computing node 304. The signals travel along optical path 276 to photodetector 366, which converts the optical signals into electrical signals as discussed herein. The received signals are passed through demultiplexer 280 prior to being passed to photodetector 266. Thus, an inter-chip bidirectional photonic channel is defined by two unidirectional photonic links. Here, the first unidirectional photonic link is defined by a modulator driver 362, an optical modulator 356, an optical path 374, a multiplexer 378, a grid coupler 354, a FAU 332, an optical fiber, and the receiving components of an additional circuit package. Similarly, the second unidirectional photonic link is defined by the transmission components of an additional circuit package 290, an optical fiber, a FAU 332, a grid coupler 354, a demultiplexer 380, an optical path 376, a photodetector 366, and a transimpedance amplifier 364. The first and second unidirectional photonic links operate in opposite directions. In this way, the two unidirectional photonic links form an inter-chip bidirectional photonic channel.

[0042] Figure 3-1 is a schematic diagram illustrating an embodiment of a circuit package 3000 that implements multiple computing nodes 3004. Each computing node 3004, more specifically, the message router within each computing node 3004, is connected to one or more electronic channels 3040. The computing nodes 3004 direct messages transmitted via the electronic channels 3040, such as those described herein with reference to Figure 1-2, through the message router. In addition, the circuit package includes an EIC 3001 and a PIC 3002, and the computing nodes 3004, routers, and electronic channels 3040 are implemented on the EIC 3001 as described herein. The circuit package may include additional networks and / or components in addition to those shown in Figure 3-1.

[0043] Sixteen computing nodes 304 are arranged in a 4x4 array and, for ease of reference, are indexed according to Cartesian coordinates [0,0]-[3,3] as shown. The array of computing nodes 3004 includes four corner nodes, eight non-corner edge nodes, hereafter referred to as "edge nodes", and four internal nodes. More generally, a circuit package may include any number of computing nodes, and the computing nodes may be arranged in any array, configuration, or arrangement that is consistent with the techniques described herein.

[0044] The computing nodes 3004 are internally connected through multiple electrical channels 3040. Specifically, each computing node 3004 is connected to each adjacent computing node 3004 via one of the electrical channels 3040. Thus, each corner node is connected to two adjacent nodes via two electrical channels, each edge node is connected to three adjacent nodes via three electrical channels, and internal nodes are connected to four adjacent nodes via four electrical channels. In this way, the computing nodes 3004 form an electronic network 3041 for communicating and / or transmitting messages between computing nodes 3004 via the electronic channels 3040. Each computing node 3004 is connected either directly, for example, to an adjacent node, or indirectly, through one or more other nodes, to any other computing node 3004. Thus, the connection of all adjacent computing nodes 3004 via the electrical channels 3040 represents the maximum adjacency configuration for the electronic network 3041, in that all adjacent nodes are connected. This can facilitate a more complete, faster, and / or more robust electronic network that provides the maximum amount of transmission paths between nodes and / or through the network, as will be described in more detail herein. Thus, the electronic network 3041 may be configured within a rectangular mesh topology.

[0045] More generally, the electronic network connecting the computing nodes can also be configured according to other topologies. For example, one or more nodes do not have to be connected to all adjacent nodes, and for example, one or more of the electronic channels 3040 in a rectangular mesh topology may be omitted. For example, all nodes may be connected to at least one other node and therefore can be internally connected to any other node, but not necessarily to every adjacent node. In a non-limiting embodiment, each internal node may be connected to only one edge node and not to any other nodes. Any number of topologies for electronically internally connecting all computing nodes 3004 without connecting all adjacent nodes will be understood by those skilled in the art, and such configurations are assumed by this disclosure. Connecting all nodes with such a less-than-maximum adjacent configuration may represent, for example, an intermediate adjacent configuration in which less than all adjacent nodes are connected, or an even less adjacent configuration, for example, a minimum number of adjacent connections to maintain connectivity for all nodes. Internally connecting the computing nodes 3004 in such a less-than-maximum adjacent configuration may simplify the design, production, and / or implementation of the electronic network and / or circuit package. For example, such a configuration can simplify the process of determining the transmission path through the network, thereby facilitating simpler routing of messages.

[0046] In some embodiments, one or more electrical channels 3040 connect to non-adjacent nodes. These may be connected in either the maximum adjacency or less-than-maximum adjacency configurations discussed above. Such configurations may increase or further maximize the use of configurable electronic connections for each computing node 3004, thereby increasing the robustness and speed of the electronic network 3041.

[0047] Such internal connectivity of computing nodes 3004 can facilitate the forwarding of messages through the electronic network 3041. For example, a message may be forwarded directly between routers of any two directly connected, e.g., adjacent computing nodes 3004. Message forwarding between any two computing nodes 3004 that are not directly connected may also be accomplished by passing the message through one or more intervening computing nodes 3004. For example, with respect to a message originating from node [0,3] and directed for transmission to node [1,2], the router for node [0,3] may forward the message to the router for node [0,2], which may then automatically forward or transmit the message to the router for node [1,2]. Similarly, message forwarding can be implemented through the route [0,3]-[1,3]-[1,2]. Thus, the message may be transmitted between any two indirectly connected, for example, non-adjacent nodes, along a path through one or more intervention computing nodes 3004 in the electronic network 3041, via one or more "hops".

[0048] As described herein, each computing node 3004 may be configured to connect to one or more, for example, up to four, bidirectional photonic channels for bidirectional data transmission between nodes. As will be understood by those skilled in the art, photonic channels are typically faster and more energy-efficient than electronic channels as distance or resistance increases. In some embodiments, as will be discussed in relation to the various configurations described below, various computing nodes 3004 are connected through bidirectional photonic channels to leverage the speed and energy efficiency of photonic channels for an improved network. However, in some embodiments, adjacent computing nodes 3004 are not internally connected to bidirectional photonic channels, but rather are still connected through an electronic network 3041, as shown and described with reference to Figure 3-1. Implementing the electronic network 3041 in this manner for adjacent connections may allow the photonic ports of each computing node 3004 to be utilized for up to four bidirectional photonic connections, for example, with non-adjacent nodes and nodes contained within other circuit packages, as described herein. This can help increase the speed, robustness, and integrity of the computing node 3004 network, even though it employs slower, less efficient electronic connections for adjacent nodes. For example, while the transmission speed and energy efficiency for electronic channels typically decrease with distance, photonic channels can maintain high speed and energy efficiency over longer distances. Therefore, for example, utilizing electronic channels 3040 for short interconnections between nearby nodes, while implementing faster, more energy-efficient photonic connections for connections between more distant nodes, can increase the overall and / or average speed of the network and reduce energy consumption.Thus, implementing the electronic network 341 can facilitate improved network performance by enabling various configurations of photonic channels and network topologies as described below. The aforementioned hardware configurations allow for flexibility when the code is executed, as software schemes, compilers, schedulers, and equivalents can utilize and / or route packets through electronic or photonic channels in a manner most favorable to the needs of the algorithm being executed.

[0049] As is evident in the exemplary network of Figure 3-1, the greater the separation between two nodes, the greater the number of hops and the greater the number of possible transmission paths between the two nodes. For example, at least four hops are required to transmit a message from node [0,1] to node [3,2]. In more extreme cases, a message transmitted between node [0,0] and node [3,3] may be carried out over six or more hops. In some embodiments, one or more non-adjacent computing nodes 304 are connected to facilitate a reduction in the number of hops for one or more transmission paths between computing nodes 3004.

[0050] Figures 3-2 and 3-3 are schematic diagrams illustrating embodiments of the circuit package 300 of Figure 3-1, respectively, with multiple connections between non-adjacent computing nodes 304. The multiple non-adjacent connections may be implemented either separately or in connection with adjacent connections, as discussed above with reference to Figure 3-1.

[0051] In some embodiments, the circuit package 3000 includes one or more in-chip bidirectional photonic channels 3042. The in-chip bidirectional photonic channels 3042 are implemented within the PIC 3002. In some embodiments, the in-chip bidirectional photonic channels connect to one or more pairs of non-adjacent computing nodes 3004. For example, one or more of the computing nodes 3004 located along the periphery of the array, e.g., corner and edge nodes or “peripheral nodes”, may be connected to other peripheral nodes through the in-chip bidirectional photonic channels 3042. In some embodiments, all peripheral nodes are connected to other peripheral nodes through the in-chip bidirectional photonic channels 3042. In some embodiments, each peripheral node is connected to a peripheral node at the opposite end of the array. For example, each corner node is connected to two corner nodes on the adjacent side of the array, e.g., node[0,3] is connected to node[3,3] and node[0,0]. In addition, each edge node is connected to another edge node located on the opposite side of the array, for example, at the same location on the opposite side of the array. For example, edge node [2,0] is connected to edge node [2,3], and edge node [0,1] is connected to edge node [3,1]. None of the internal nodes are connected to the in-chip bidirectional photonic channel 3042. Thus, each side of the array can be connected to the opposite side of the array by winding or through connections of peripheral nodes via the in-chip bidirectional photonic channel 3042.

[0052] The in-chip bidirectional photonic channel 3042 is implemented within the PIC3002. For example, as described above, each computing node 3004 may include one or more photonic ports within the PIC layer of the computing node 3004, and the waveguide may be connected to the photonic ports of a pair of computing nodes 3004. In some embodiments, the waveguide is an internal waveguide implemented or formed within the PIC3002. Thus, the PIC3002 may be manufactured together with the waveguide, which is included for implementing the in-chip bidirectional photonic channel 3042. In some embodiments, the waveguide includes an external waveguide, such as an optical fiber, for implementing the in-chip bidirectional photonic channel 3042.

[0053] The in-chip bidirectional photonic channel 3042 may be implemented in addition to the electrical channel 3040, which connects the computing node 3004 into the electronic network 3041. For clarity and to facilitate discussion, the electronic channel 3040 may appear to be implemented in conjunction with the in-chip bidirectional photonic channel 3042 in Figure 3-3, although it is not shown in Figure 3-2. The combination of the computing node 3004 connected through such an electronic channel 3040 and the in-chip bidirectional photonic channel 3042 may form an optical-electric network 3043, for example, an in-chip optical-electric network. The optical-electric network 3043 may be an in-chip network of computing nodes 3004, and may constitute the computing nodes as a two-dimensional torus interconnect. Thus, the optical-electric network 3043 may have a toroidal mesh topology. For example, a computing node 3004 may be physically implemented within a two-dimensional planar array, but each side of the plane may "wrap around" the opposite side, for example, left and right and up and down, so that the array can conceptually take on a torus shape. In this way, adjacent nodes are directly connected, and peripheral nodes are conceptually "adjacent" and directly connected to peripheral nodes on the opposite side of the array through the in-chip bidirectional photonic channel 3042.

[0054] Such a toroidal mesh topology for the optical-electric network 3043 helps reduce the average number of hops between pairs of computing nodes 3004 in the network. In the embodiment given above, the transmission path between node [0,1] and node [3,2] requires a minimum of four hops through the electronic network 3041. By implementing the optical-electric network 3043, which includes an in-chip bidirectional photonic channel 3042, the transmission of a message from node [0,1] to node [3,2] can be accomplished in only two hops, e.g., [0,1]-[3,1]-[3,2]. Similarly, the transmission path from node [0,0] to [3,3] is reduced from six hops in the electronic network 3041 to two hops in the optical-electric network 3043. Thus, implementing the optical-electric network 3043 can increase the speed, reliability, and robustness of the computing node 3004 network by enabling message delivery through fewer hops. In addition, the optical network 3043 can therefore reduce the overall amount of traffic that individual routers have to process as messages traverse the network.

[0055] Figure 3-4 is a schematic diagram illustrating an embodiment of the circuit package 300 of Figure 3-1 that implements multiple connections to one or more additional circuit packages. The circuit package 300 includes one or more inter-chip bidirectional photonic channels 344, and one or more of the computing nodes 304 may be connected to one or more additional computing devices of one or more other circuit packages. The inter-chip bidirectional photonic channels 344 may be implemented either separately or in connection with the electronic channels 340 discussed above with reference to Figure 3-1 and / or the intra-chip bidirectional photonic channels 342 discussed above with reference to Figures 3-2 and 3-3.

[0056] In some embodiments, the inter-chip bidirectional photonic channel 3044 is implemented using an external waveguide such as an optical fiber. For example, the optical fiber may be contained within the circuit package 3000 and coupled through an internal waveguide to any suitable optical interface, such as a FAU as described with reference to Figures 2-1 and 2-2, which connects to one or more photonic ports of one or more computing nodes 3004. In some embodiments, the optical fiber connects directly to the photonic ports of one or more computing nodes 3004 without an internal waveguide. The optical fiber may have similar connections to one or more computing devices in separate circuit packages to which it connects. For example, the optical fiber may be connected to two circuit packages by connecting to the FAU of each circuit package. One or more such connected optical fibers may form one or more unidirectional photonic links, each associated with a circuit package, including a driver, a modulator, a waveguide, a lattice coupler, a FAU, a photodiode, and a transimpedance amplifier. Thus, the inter-chip bidirectional photonic channel may be formed using any of the components described herein with reference to Figures 2-1 and 2-2.

[0057] In some embodiments, the inter-chip bidirectional photonic channel 3044 connects to one or more of the peripheral nodes. In some embodiments, each peripheral node connects to the inter-chip bidirectional photonic channel 3044. For example, each corner node may connect to two inter-chip bidirectional photonic channels 3044, and each edge node may connect to one inter-chip bidirectional photonic channel 3044. Such connections to peripheral nodes can facilitate the connection and / or arrangement of multiple circuit packages in a grid or array. For example, in some embodiments, as will be discussed in more detail below, multiple circuit packages 3000 are connected together in an array to form a larger interconnection and / or network via the inter-chip bidirectional photonic channel 3044. In some embodiments, a circuit package 3000 connects to similar or complementary circuit packages instead of, or in addition to, the same or other instances of the circuit package 3000. Thus, the inter-chip bidirectional photonic channel 3044 can facilitate the integration of the circuit packages 3000 and computing nodes 3004 into a larger inter-chip network.

[0058] In some embodiments, the circuit package 3000 includes an inter-chip bidirectional photonic channel 3044 in addition to the electronic channel 3040 and the intra-chip bidirectional photonic channel 3042 described above. For clarity and to facilitate discussion, only the inter-chip bidirectional photonic channel 3044 is shown in Figure 3-4, but an implementation with all channels may be seen in Figure 3-5. A combination of computing nodes 3004 connected through such an electronic channel 3040, intra-chip bidirectional photonic channel 3042, and inter-chip bidirectional photonic channel 3044 may form a larger inter-chip optical-electrical network 3045. For example, the inter-chip bidirectional photonic channel 3044 may facilitate the splicing or connection of an intra-chip optical-electrical network 3043 together with an intra-chip network of one or more other circuit packages into a larger and more robust network.

[0059] In the various embodiments described and shown with reference to Figures 3-2 to 3-5, and similarly in other embodiments described herein, various photonic channels, both inter-chip and intra-chip, are depicted as connecting or terminating at the edges of the computing node 3004. However, it should be understood that these depictions are intended to illustrate the connectivity of the various components described herein and are not intended to limit to the actual physical layout or implementation of the various components. For example, the various photonic channels may extend within or directly beneath the computing node 3004. The various channels may be terminated or terminated at the transceiver or AMS block of the computing node 3004. The various channels may be terminated or terminated in a central area or location within the computing node 3004. In addition, although the computing node 3004 is shown connecting to the various channels at its north, east, south, and / or west locations, it should be understood that this is merely illustrative, and the photonic ports of the computing node 3004 may be located at any location relative to the computing node 3004, including one or more photonic ports in the same or adjacent locations. For example, all four photonic ports of computing node 3004 may be located in the same location on computing node 3004.

[0060] In some embodiments, circuit package 3000 is connected to one or more additional circuit packages 3000 via inter-chip bidirectional photonic channels 3044. Figure 4 illustrates an exemplary implementation of four of the interconnected circuit packages 300 of Figure 2-1. In particular, system 400 includes circuit packages 300' arranged in a two-dimensional array. Circuit package 300' includes circuit packages 300-1 (top left), 300-2 (top right), 300-3 (bottom left), and 300-4 (bottom right). As shown, peripheral (corner, or non-corner, edge) nodes on each side of a circuit package, adjacent to the side of another circuit package, may be directly connected to the corresponding adjacent node on the adjacent circuit package via inter-chip bidirectional photonic channels 344. Thus, circuit packages 300-1 to 300-4 form a grid of 64 computing nodes 304, arranged in an 8x8 grid of adjacent, directly connected computing nodes 304.

[0061] In some embodiments, each circuit package 300' includes electronic connections between adjacent nodes and / or intra-chip bidirectional photonic channels between peripheral nodes. For clarity, such connections are not shown in Figure 4. Thus, the benefits of internal connectivity of computing node 304 within a single circuit package discussed above can similarly be applied to the interconnectivity of multiple circuit packages 300' into a larger inter-chip network. For example, transmitting a message from the upper-left node of circuit package 300-1 to the lower-right node of circuit package 300-2, which would otherwise take 10 hops through adjacent nodes, can be achieved in 4 hops by utilizing intra-chip bidirectional photonic channels connecting to peripheral nodes within each circuit package, as described above.

[0062] As shown, all peripheral nodes of each circuit package 300' are connected to one or more inter-chip bidirectional photonic channels 344. For example, in addition to the adjacent sides of the circuit package 300' being directly connected, one or more peripheral nodes on the non-adjacent sides of the inter-chip grid, for example on the periphery, may also be directly connected to other nodes. Any number of configurations or topologies of the inter-chip optoelectronic network 345 can be envisioned by interconnecting the nodes and the inter-chip bidirectional photonic channels 344. Such configurations can leverage the configurability of each computing node 304 to reduce and / or minimize the number of hops between pairs of computing nodes 304 by connecting to two or more photonic channels (four are shown in this embodiment). Thus, high network efficiency and flexibility for various routing schemes can be maintained even with respect to networks implementing multiple circuit packages and / or a large number of computing nodes, depending on the algorithm being executed.

[0063] Figures 5-1 to 5-6 illustrate the steps in an exemplary process 5000 for packaging an EIC-PIC stack on a semiconductor substrate, as depicted in various embodiments shown in Figures 1-1 to 1-4 above, where the EIC and PIC are coupled to each other (for example, in Figure 2-2, a driver 363 on the EIC 301 is coupled to a modulator 356 on the PIC 302 to modulate an optical carrier signal, while a photodetector (PD) 366 on the PIC 302 is coupled to a transimpedance amplifier 364 on the EIC to provide a detected electrical signal). In a combined EIC-PIC stack, one technical challenge is to provide a path for coupling an optical carrier signal, such as C-band or L-band laser light, from outside the package to the PIC in the package. Process 5000 is an embodiment of a solution to address the technical challenge of providing the optical carrier signal to the PIC stacked under the EIC, such as in their stacked arrays, as depicted in various embodiments shown in Figures 1-1 to 1-4 above.

[0064] Figure 5-1 shows that in step 5001, a redistribution layer (RDL) 5001R and copper (Cu) pillars 5001C, shown as pillars, are grown on the carrier 5002. The RDL 5001R is for redistributing input / output (I / O) connections from the original (often fine-pitch) bonding pads on the die to different pitches or arrangements that meet the requirements of the package or interposer. This enables better connectivity between the integrated circuit and external components such as other chips or package substrates. The step of forming the RDL layer may include the step of forming a copper wiring layer and an insulating layer. In some cases, the step of growing the RDL formation may include the step of applying plasma during the formation process for descamming, cleaning, hydrophilization of the surface-modified substrate, and control of the surface shape, all of which can prevent oxidation and corrosion of the copper wiring. As shown, the RDL 5001R may include a dielectric layer 5001D and a passivation layer 5001P. The dielectric layer 5001D may contain polyimide or other low-k dielectric material to facilitate the formation of signal traces. The passivation layer 5001P may include a protective coating that effectively prevents environmental factors such as humidity and contaminants from affecting the integrity of the RDL and the underlying semiconductor structure. Copper pads 5001C are embedded to electrically connect the RDL to the underlying substrate. Copper studs 5000L are arranged to connect to one or more EICs in the EIC-PIC stack. Carrier 5002 may be a glass carrier.

[0065] Figure 5-2 shows that in step 5010, semiconductor dies 5011, 5012, and 5013 are positioned on the RDL5001R and carrier 5002. For example, dies 5011, 5012, and 5013 can be positioned on the RDL5001R, which is temporarily bonded to the glass carrier using adhesive. The glass carrier can later be peeled off and the temporary bond removed using laser irradiation. Here, dies 5011, 5012, and 5013 can be formed using die dicing, also known as wafer dicing, which is a manufacturing process for separating individual dies onto a finished wafer via wafer dicing for further packaging and assembly. Dies 5011, 5012, and 5013 are embodiments of bridge dies, which are not limited to any specific number. Importantly, dies 5011, 5012, and 5013 are embedded in the package so that the die can bridge intra-chip data communication between various components, for example, positioned above the die within the package. As discussed above with reference to Figures 2-1 and 2-2, the PIC302 may be formed within die 5013. For example, modulators 356-1 and 356-2 and photodetectors 366-1 and 366-2, together with the grid coupler 354 and an optical transmission medium, such as a waveguide or fiber, can be formed within die 5013.

[0066] A photoresist coating 5014 is formed on a portion of the surface of the die 5013 opposite the carrier 5002. The photoresist coating 5014 may be formed by spraying droplets of photoresist material. In addition, or alternatively, the formation may be done using 3D printing. The main portion of the die 5013 generally corresponds to the photonic ports of the active photonic components on the PIC302. Here, active photonic components refer to bulk optical modulators without electrodes or electrical contacts, e.g., modulators 356-1 and 356-2, or bulk photodetectors without electrodes or electrical contacts, e.g., photodetectors 366-1 and 366-2. The active photonic components consume power provided by the EIC upon activation, e.g., when powered on. On the PIC, the portion containing the active components is also referred to as the active portion of the PIC. The active portion consumes power once the active photonic components are activated. For example, both optical modulators and photodetectors operate using power. For illustrative purposes, the remaining parts of the PIC may be referred to as the passive parts of the PIC. The passive parts of the PIC may provide, for example, optical transmission media, such as waveguides and fibers, a grid coupler 354, and optical ports, such as optical input or output ports. A photoresist coating 5014 may mask the passive parts of the PIC.

[0067] Figure 5-3 shows that in step 5020, the packaging material is applied to the upper side of the assembly from step 5010, and the dies 5011, 5012, and 5013 are encapsulated within layer 5021. Examples of packaging materials include epoxy molding compound (EMC), also known as epoxy resin or duroplast. In some cases, the layer of packaging material (5021) can be about 100 μm thick. The packaging material is then polished, for example, using a polishing pad 5022, and partially removed to expose the photoresist coating 5014.

[0068] Figure 5-4 shows that in step 5030, the photoresist coating 5014 is dissolved using a solvent so that the cavity 5031 is exposed. As shown, the cavity 5031 is defined by the volume occupied by the photoresist coating 5014. Since an active photonic component, e.g., an optical modulator or photodetector excluding electrodes, is located on the PIC, a clear optical path is provided by the cavity 5031, which is fabricated, for example, using a curable material. For example, the curable material can fill the cavity 5031 so that photonic ports, e.g., input and output photonic ports for the active photonic component, can be optically coupled to a fiber array unit (FAU) once the curable material has cured and become a solid and optically transparent material. Here, "optically transparent" generally refers to desirable transmittance within the operating optical wavelength. For L-band light, the operating wavelength is approximately 1565 nm to 1625 nm, which falls within the near-infrared band. With respect to other bands within the telecommunications optical wavelength band, such as the C-band, the operating wavelength may vary as appropriate. A preferred embodiment of transmittance is low attenuation through the medium, also known as transmission loss. For example, the transmission loss may be less than 1 dB per kilometer. An embodiment of curable material is ultraviolet (UV) curable epoxy. Once solidified, the curable material provides an optical refractive index that substantially matches that of the optical transmission medium of the FAU or passive photonic component. In various cases, the curable material can be 15, 20, or 30 μm thick. The cavity can be between approximately 3 mm wide and 40 mm long. The FAU can be, for example, a fiber bundle containing 42 channels. Each channel can include an optical fiber, such as a single-mode fiber (SMF). As discussed above with reference to Figures 2-1 and 2-2, the FAU 332 can be coupled to the photonic port of the PIC 302 through a lattice coupler (GC) 354. The lattice coupler can be mounted on the PIC's photonic port. The lattice coupler can also be mounted on the FAU's port.In addition, or alternatively, the FAU can also be coupled to the photonic port via an edge coupler, as described above with reference to Figure 1-4.

[0069] Figure 5-5 shows that in step 5040, the high-bandwidth memory (HBM) 5041, processor 5042, and EIC 5043 are mounted to the upper side of the assembly resulting from step 5030, using mechanical pressure, for example, by a copper column. For example, the copper column can be appropriately positioned on the landing pad on the EIC 5043 to mate with a plated hole on the landing pad on the die 5013 constructed as the PIC. In this embodiment, the plated hole may have a diameter of about 10 μm laterally, while the copper column can be sized to 30 μm or less than 30 μm laterally, for example, about 20 μm. Since the copper column is sized larger than the hole 5601, precise matching is not required when mating. In some cases, another RDL layer 5044 may be placed between the layer 5012 of the packaging material and the stacked high-bandwidth memory (HBM) 5041, processor 5042, and EIC 5043 above it. The implementation is not limited to the exact order or specific number of memory / processor / EIC arrays as shown in Figure 5-5. Here, the EIC 5043 is stacked on top of the PIC, coupled to the FAU. Bridge dies 5011 and 5012 operate an electrical bridge for the HBM 5041 and processor 5042. Furthermore, the EIC 5043 acts as a bridge between the PIC and the HBM 5041 and processor 5042. As stated above, the HBM 5041, processor 5042, and EIC 5043 may each have a local clock, while the assembly operates by mesochronous clocking.

[0070] Figure 5-6 shows that in step 5050, the carrier 5002 is peeled off, for example, using laser irradiation, and thus the temporary bond formed by the adhesive is debonded, as described above with reference to step 5001. Once the carrier 5002 is peeled off, the assembly is bonded to a printed circuit board (PCB), which may be a high-density interconnect (HDI) PCB, substrate 5051. The bond can be formed using a molded interposer package (MIP) process. Electrical connections are formed, for example, using wire traces between the assembly and the substrate. For example, the anodes of the modulator and photodiode can be electrically connected to a bias voltage on the substrate.

[0071] In addition, or alternatively, in step 5010, instead of a photoresist coating, a first layer of curable material may be provided on a portion of the surface of the die 5013 opposite the carrier 5002. The curable material may be cured and become a solid and transparent material before the packaging material is applied in step 5020. Here, the packaging material may be polished and exposed to the first layer of curable material so that an optically transparent window may be provided to access the photonic port of the active photonic component. The packaging then may deposit a second layer of curable material on this optically transparent window, and for example, once the second layer of curable material is cured, the photonic port of the active photonic component may be optically coupled to the FAU.

[0072] Figure 6 shows an exemplary EIC-PIC package 600, which includes, for example, a fiber array unit FAU601 that receives C-band or L-band light from a laser source and transmits the laser light through a cavity 5031 filled with light-transmitting, cured epoxy.

[0073] Specifically, the FAU601 may include a number of optical channels configured to transport, for example, C-band or L-band light at a particular wavelength to or from the PIC, as illustrated above with reference to Figures 1-4, 2-1, and 2-2, respectively. In some cases, the FAU may have 42 optical channels, including 16 channels for transmitting light to the PIC, 16 channels for receiving light from the PIC, 8 channels for providing light illumination power, and 2 dummy channels for indicating optical matching between the FAU and the optical interface of one or more photonic ports of the PIC5013.

[0074] The passive portion 603P of the PIC5013, which is not actively electrically powered, may include an optical waveguide or fiber supporting one or more photonic ports. The passive portion 603P thus optically provides L-band light capable of carrying an information load between the EIC5041, 5042, 5043 and the neighboring EIC-PIC package when the L-band light is modulated in the active portion 603A, which for example contains one or more optical modulators or one or more photodetectors (e.g., photodiodes).

[0075] Figures 7-1 to 7-6 illustrate another exemplary process 7000 for packaging the EIC-PIC stack onto a semiconductor substrate, as depicted in the various embodiments shown in Figures 1-1 to 1-4 above. Similar to the embodiments illustrated in Figures 5-1 to 5-6, the exemplary process 700 can also provide a pathway to address the technical challenges of feeding the optical carrier signal, for example, a C-band or L-band laser beam, to the PIC in the package from outside the package, thereby feeding the optical carrier signal to the PIC in the EIC-PIC stack.

[0076] Figure 7-1 shows that in step 7001, similar to step 5001 in Figure 5-1, a redistribution layer (RDL) 5001R and copper (Cu) pillars 5001C, shown as pillars, are grown on the carrier 5002. As shown, the RDL 5001R may include a dielectric layer 5001D and a passivation layer 5001P. Copper pads 5001C are embedded in the RDL 500R to connect the RDL to the underlying substrate. Copper studs 5000L are positioned to connect to one or more EICs in the EIC-PIC stack. The carrier 5002 may be a glass carrier.

[0077] Figure 7-2 shows that in step 7010, semiconductor dies 5011, 5012, and 5013 are positioned on the RDL5001R and carrier 5002. Similar to step 5010 in Figure 5-2, the RDL5001R is temporarily bonded to the glass carrier, which can later be peeled off and the temporary bond removed using laser irradiation. Dies 5011, 5012, and 5013 can each be formed using die assembly. Dies 5011, 5012, and 5013 are embodiments of bridge dies, which are embedded in a package so that the dies can bridge intra-chip data communication between various components, for example, positioned above the dies in the package.

[0078] Figure 7-2 also provides an enlarged view of the cap 7011. Here, the term “cap” is used synonymously with “hat” or “lid.” As shown, the cap 7011 includes a crown 7011C and a brim 7011B. The crown 7011C defines a cavity 7011A, which provides an open space above the port 7003. The brim 7011B surrounds the base of the crown 7011 so that the cap 7011, with the cavity 7011A, sits on the PIC 5013, including the passive portion of the PIC 5013, which contains the port.

[0079] The cap 7011 is fabricated, for example, from a molding material, which may be the same as or different from the packaging material used in layer 5021, as depicted in Figure 5-3. The cap 7011 can be attached to the surface of the underlying PIC 5013 using a suitable adhesive, such as an epoxy adhesive, polyimide, or bonding adhesive. When positioning the cap 7011 on the PIC 5013, the alignment between the hat 7011 and the underlying PIC 5013 can be based on alignment markers, which may be located on the PIC 5013 or the glass carrier 5002. In some embodiments, alignment markers or a group of markers can be formed within the surface of the PIC 5013 to ensure alignment between the cap 7011 and the photonic port 7003. For example, a groove can be molded to match the brim 7011B and etched within the surface of the PIC 5013 during the process to facilitate easy and accurate alignment of the cap 7011.

[0080] Figure 7-3 shows that in step 7020, the packaging material is applied to the upper side of the assembly from step 7010 so that the PIC 5013, together with the bridge dies 5011 and 5012, is encapsulated within layer 7021. The packaging material may include epoxy molding compound (EMC), also known as epoxy resin or duroplast. In some cases, the layer of packaging material (7021) may be about 100 μm thick. In some cases, the cavity may have a thickness of about 50 μm or less, a lateral dimension of about 3 mm in width, and a length of about 40 mm.

[0081] Subsequently, in step 7030 shown in Figure 7-4, the packaging material may be polished, for example, using a chemical mechanical polishing (CMP) process, which may scrape (or cut) off the cap 7011, remove a portion of the molding material, and remove the upper portion of the crown, so as to provide an opening over one or more photonic ports 7003 that are exposed and embedded in the passive portion of the PIC5013. Through this cavity 7031, a clear and unobstructed optical path can be provided using a curable material. For example, once the curable material is cured and becomes a solid and optically transparent material with an optical refractive index substantially matching that of the optical transmission medium of the FAU or passive photonic component, the cavity 7031 can be filled so that the photonic ports 7003, for example, input and output photonic ports for the active photonic component on the PIC5013, can be optically coupled to the fiber array unit (FAU). As shown in Figure 5-4, cavity 7031 may be filled with UV-curable epoxy, which can be between 15, 20, or 30 μm thick, and about 3 mm wide and 40 mm long.

[0082] In step 7040 shown in Figure 7-5, FAU601 is provided on top of cavity 7031, which is filled with an optically transparent material having a matching optical refractive index. FAU601 can be, for example, a fiber bundle containing 42 channels and can be coupled to the photonic port of PIC302 through a lattice coupler (GC) as shown in Figures 2-1 and 2-2. The lattice coupler can be mounted on the photonic port 7003 of PIC5013. The lattice coupler can also be mounted on the port of FAU601. In addition, or alternatively, FAU601 can also be coupled to the photonic port 7003 through an edge coupler as described above with reference to Figure 1-4.

[0083] In step 7045 illustrated in Figure 7-6, the high-bandwidth memory (HBM) 7041, processor 7042, and EIC 7043 are mounted to the upper side of the assembly resulting from step 7040 using mechanical pressure, for example, by copper pillars. The implementation is not limited to the exact order or specific number of memory / processor / EIC arrays as shown in Figure 7-6. Here, the EIC 7043 is stacked on top of the PIC, coupled to the FAU 601. Bridge dies 5011 and 5012 operate an electrical bridge for the HBM 7041 and processor 7042. Furthermore, the EIC 7043 acts as a bridge between the PIC and the HBM 7041 and processor 7042. Referring to Figure 5-5 as described above, the assembly operates by mesochronous clocking, while the HBM 7041, processor 7042, and EIC 7043 may each have their own local clocks. Subsequently, the carrier 5002 may be peeled off, for example, using laser irradiation. The assembly is then bonded to a printed circuit board (PCB), such as a high-density interconnect (HDI) PCB. Bonding to the substrate can be formed using a molded interposer package (MIP) process, as illustrated above with reference to Figure 5-6.

[0084] Importantly, the process described with respect to Figures 7-1 to 7-6 can be repeated to allow vertical stacking of additional layers (e.g., EIC layers) while preserving the vertical optical paths to the ports in the PIC5013. In step 7050 illustrated in Figure 7-7, the cap 7051 can be mounted on top of the already formed cavity 7031. As shown, the brim 7051B is placed on top of layer 7021 so that the crown 7051C covers the opening to the cavity 7031. Similar to steps 7-1 to 7-4, the cap 7051 is fabricated from a molding material.

[0085] In step 7060, illustrated in Figure 7-8, a layer of packaging material (7061) is deposited on top of layer 7021, enclosing the cap 7051 and embedding the underlying structure, including the PIC 5013, along with the photonic port 7003 embedded in the passive portion of the PIC 5013. The packaging material may be the same as the molding material for the cap 7051, as discussed above with reference to Figure 7-3.

[0086] In step 7070 illustrated in Figure 7-9, after polishing layer 7061 using a CMP process, a portion of the packaging material is removed along with the upper portion of crown 7051C so that the opening is exposed to an existing cavity 7031 and thus provides an unobstructed optical path to a photonic port 7003 which will be embedded in the passive portion of PIC5013.

[0087] In step 7080 illustrated in Figure 7-10, the opening can be filled with an optically transparent epoxy (e.g., UV-curable epoxy) with an optical refractive index that substantially matches the optical transmission medium on, for example, PIC5031 or FAU601. As shown, FAU601 can be provided above the opening to the cavity 7031.

[0088] In step 7085, illustrated in Figure 7-11, a second layer of EIC components, such as EIC7081, can be unfolded on layer 7061. Additional layers of EIC components can be further stacked upwards by iteratively following steps 7030, 7040, and 7050, while maintaining optical access to the photonic port 7003, which is embedded in the passive portion of the PIC5013.

[0089] Cap 7011 provides space with a rectangular cross-section as described above, but more generally, implementations are not limited to these exemplary shapes and forms. Generally, caps of any shape are used that are suitable for providing the desired space footprint and depth while withstanding the packaging process. For example, caps with a non-rectangular polyhedral shape and a vertical cross-section can also be used.

[0090] An embodiment of such a cap is shown in Figure 7-12. Here, the cap 7012 (shown in vertical section) provides a trapezoidal cavity 7012A. Furthermore, the cavity 7012A is provided by a side wall 7012C, with increasing thickness closer to the bottom (i.e., the side in contact with the PIC), and the brim does not extend beyond the side wall.

[0091] The cross-section (i.e., footprint) of the cap in the plane of the PIC can also vary. Generally, the brim footprint is shaped so that the cavity provides sufficient access to the photonic port and the brim securely supports the cap once it is attached to the surface of the PIC. Figures 7-13-7-16 show examples of brim footprints. In some embodiments, the brim and the outer perimeter of the cavity have the same shape. For example, Figure 7-13 shows a cap 7013 having a brim with a rectangular cavity perimeter 7013A and a rectangular outer perimeter 7013C. Another embodiment is shown in Figure 7-14, in which the cap 7104 includes a brim with a circular cavity perimeter 7013A and a circular outer perimeter 7013C.

[0092] In some embodiments, the brim and cavity have differently molded footprints. For example, Figure 7-15 shows an embodiment of cap 7015 having a cavity with a circular circumference 7015A and a brim with a square circumference 7015C. Figure 7-16 shows cap 7016 having a cavity with a rectangular circumference 7016A and a brim with a circular circumference 7016C. The cavity may have a cylindrical cross-sectional shape, as is evident in the top plan view in Figure 7-12 relating to cap 7014 (providing cavity 7014A) and cap 7015 (providing cavity 7015A). Other molded circumferences are also possible.

[0093] In some cases, the cap may have a footprint that matches the overall size and shape of the PIC5013, with the crown positioned over the photonic ports. For example, the cap may be formed from a block of material having a certain thickness, including blind holes on the surface at the locations of the photonic ports that precisely define the cavities. In other words, the cap may be pre-machined to cover the entire PIC with cavities that define the desired cavities. Similarly, the cap may cover all features on the glass carrier 5002, including the PIC5013 and bridge dies 5011 and 5012, with cavities at corresponding locations for the passive parts of the PIC5013.

[0094] In general, any of the circuit packages described above can be packaged using the techniques described herein. For example, referring to Figure 8, circuit package 800 can be formed by encapsulating the circuit package 200 shown in Figure 2-2 using the techniques described above with reference to Figures 7-1 to 7-15. As described above, circuit package 800 implements a bidirectional photonic channel between computing node 804 and an additional computing node 254 located on an additional circuit package 290, such as a memory node on a memory circuit package. Computing node 804 has the same architecture as computing node 304 described above, except that the PIC and EIC are mounted on PCB 801 and encapsulated by a layer 810 of the packaging compound.

[0095] The EIC overlaps the upper surface of the PIC, and the components of the EIC are in close proximity to the components of the PIC. For example, the modulator 356 can be located less than 2 mm or 2 mm (e.g., less than 1 mm or 1 mm, less than 0.5 mm or 0.5 mm, less than 0.25 mm or 0.25 mm, e.g., greater than 0.1 mm or 0.1 mm) from the driver 362. Positioning the modulator in close proximity to its corresponding driver, and / or positioning the photodetector near its corresponding TIA, can allow for relatively short electrical signal lines between the passive elements in the PIC and the active elements in the EIC. In some cases, the lines can be short enough that the network can be omitted without unacceptable loss in electrical signal fidelity, which is commonly used to reduce noise associated with longer signal lines.

[0096] Optical access to the lattice coupler 354 at the photonic port on the upper surface of the PIC302 through layer 810 is provided by a cavity 820. The cavity 820 is bounded by a cap sidewall 822 resulting from the packaging process described above. The cavity 820 can be filled with an optically transparent medium. The cap sidewall 822 can be formed from the same packaging compound as layer 810 or from a different material. The FAU 332 is mounted on the circuit package 804 on the upper surface of layer 810 above the cavity 820.

[0097] The modulator 356 can be a relatively thermally stable EAM. In other words, the modulator 356 can operate reliably over a wide temperature range (e.g., room temperature to 80°C). Therefore, the modulators and / or photodetectors can be positioned in close proximity to the active electronic elements within the EIC; for example, each modulator can be positioned in close proximity to its corresponding modulator driver, and / or each photodetector can be positioned in close proximity to its corresponding TIA. Here, close proximity means that the components within the PIC are subjected to substantial thermal load when the EIC is active, and may be subjected to significant temperature changes (e.g., changes of 10°C or above, 20°C or above, 30°C or above) when switching between active and inactive states.

[0098] In some cases, the EIC may include other integrated circuits that generate a significant thermal load on the same chip as the driver and TIA. For example, the EIC may include one or more application-specific integrated circuits (ASICs) on the same chip, such as circuits for processing machine learning models.

[0099] As a result of the thermally stable components, the circuit packages described herein, such as circuit package 804, can be relatively compact. Computer system

[0100] Figure 9 illustrates a component that may be included in computer system 800. One or more computer systems 900 may be used to implement the various devices, components, and systems described herein.

[0101] The computer system 900 includes a processor 901. The processor 901 may be a general-purpose single or multi-chip microprocessor, such as an advanced RISC (Reduced Instruction Set Computer) machine (ARM), a special-purpose microprocessor, such as a digital signal processor (DSP), a microcontroller, a programmable gate array, etc. The processor 901 may be referred to as a central processing unit (CPU). Only a single processor 901 is shown in the computer system 900 of Figure 9; however, in alternative configurations, a combination of processors, such as ARM and DSP, may be used.

[0102] The computer system 900 also includes a memory 903 that communicates electronically with the processor 901. The memory 903 may be any electronic component capable of storing electronic information. For example, the memory 903 may be embodied as random access memory (RAM), read-only memory (ROM), magnetic disk storage medium, optical storage medium, flash memory device in RAM, onboard memory included with the processor, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, etc. (including combinations thereof).

[0103] Instruction 905 and data 907 are stored in memory 903. Instruction 905 is executable by processor 901 and implements some or all of the functionality disclosed herein. The step of executing instruction 905 may involve the use of data 907, which is stored in memory 903. Any of the various embodiments of the modules and components described herein may be implemented, in part or in whole, as instruction 905, which is stored in memory 903 and executed by processor 901. Any of the various embodiments of the data described herein may be in data 907, which is stored in memory 903 and may be used during the execution of instruction 905 by processor 901.

[0104] The computer system 900 may also include one or more communication interfaces 909 for communicating with other electronic devices. One or more communication interfaces 909 may be based on wired communication technology, wireless communication technology, or both. Some embodiments of the communication interface 909 include Universal Serial Bus (USB), Ethernet® adapters, wireless adapters operating according to the IEEE 802.11 wireless communication protocol, Bluetooth® wireless communication adapters, and infrared (IR) communication ports.

[0105] The computer system 900 may also include one or more input devices 911 and one or more output devices 913. Some embodiments of the input device 911 include a keyboard, mouse, microphone, remote control device, button, joystick, trackball, touchpad, and light pen. Some embodiments of the output device 913 include a speaker and printer. One specific type of output device typically included in the computer system 900 is a display device 915. Used in conjunction with the embodiments disclosed herein, the display device 915 may utilize any preferred image projection technology such as a liquid crystal display (LCD), light-emitting diode (LED), gas plasma, electroluminescence, or equivalent. A display controller 917 may also be provided to convert data 907 stored in memory 903 into text, graphics, and / or moving images (as needed) to be displayed on the display device 915.

[0106] Various components of the computer system 900 may be coupled together by one or more buses, which may include a power bus, a control signal bus, a status signal bus, a data bus, and so on. For clarity, the various buses are illustrated in Figure 9 as a bus system 919.

[0107] The techniques described herein may be implemented in hardware, software, firmware, or any combination thereof, unless otherwise specifically described as being implemented in a specific manner. Any feature described as a module, component, or equivalent may also be implemented together in an integrated logical device, or separately as discrete but interoperable logical devices. When implemented in software, the techniques may be realized by a non-transient processor-readable storage medium comprising instructions that, when executed at least partially by at least one processor, perform one or more of the methods described herein. The instructions may be organized into routines, programs, objects, components, data structures, etc., which may perform specific tasks and / or implement specific data types, which may be combined or distributed as desired in various embodiments.

[0108] A computer-readable medium can be any available medium that can be accessed by a general-purpose or special-purpose computer system. A computer-readable medium that stores computer-executable instructions is a non-transient computer-readable storage medium, i.e., a device. A computer-readable medium that carries computer-executable instructions is a transmission medium. Thus, as an example, and not limited to, embodiments of the present disclosure may comprise at least two separately distinct types of computer-readable media, i.e., a non-transient computer-readable storage medium and a transmission medium.

[0109] Embodiments of the present disclosure may therefore utilize a special-purpose or general-purpose computing system, including, for example, one or more processors and system memory, which are computer hardware. Embodiments within the scope of the present disclosure also include physical and other computer-readable media for transporting or storing computer-executable instructions and / or data structures, including applications, tables, data, libraries, or other modules, which are used to perform specific functions or to direct the selection or execution of other modules. Such computer-readable media can be any available media that can be accessed by a general-purpose or special-purpose computer system. A computer-readable medium that stores computer-executable instructions (or software instructions) is a physical storage medium. A computer-readable medium that transports computer-executable instructions is a transmission medium. Thus, as an example, and not limited to, embodiments of the present disclosure may include at least two separately different types of computer-readable media, namely physical storage media and / or transmission media. Combinations of physical storage media and transmission media should also be included within the scope of computer-readable media.

[0110] Both physical storage media and transmission media may be used to temporarily store or transport software instructions in the form of computer-readable program code, enabling the implementation of embodiments of the present disclosure. Physical storage media may further be used to permanently or permanently store such software instructions. Embodiments of physical storage media include physical memory, e.g., RAM, ROM, EPROM, EEPROM, etc.; optical disc storage devices, e.g., CD, DVD, HDDVD, Blu-ray®, etc.; storage devices, e.g., magnetic disk storage devices, tape storage devices, diskettes, etc.; flash or other solid-state storage devices or memory; or any other non-transmission media that can be used to store program code in the form of computer-executable instructions or data structures, and in which such program code can be accessed by a general-purpose or special-purpose computer, whether stored as or contained within software, hardware, firmware, or a combination thereof.

[0111] A “network” or “communication network” can generally be defined as one or more data links that enable the transport of electronic data between computer systems and / or modules, engines, and / or other electronic devices. When information is transferred to or provided to a computing device via a communication network or another communication connection (either wired, wireless, or a combination of wired and wireless), the computing device appropriately considers the connection as a medium of transmission. The medium of transmission may include communication networks and / or data links, carriers, radio signals, and equivalents, which may be used to carry desired program or template code means or instructions in the form of computer executable instructions or data structures, which may be accessed by general-purpose or special-purpose computers.

[0112] Furthermore, program code, in the form of computer executable instructions or data structures, can be automatically or manually transferred from a transmission medium to a physical storage medium or vice versa, depending on its destination to various computer system components. For example, computer executable instructions or data structures received via a network or data link can be buffered in memory within a network interface module (NIC), such as RAM, and then finally transferred to the computer system RAM and / or low-volatility physical storage medium within the computer system. Therefore, it should be understood that physical storage mediums can also, or even more, be contained within computer system components that primarily utilize the transmission medium. Industrial availability

[0113] As discussed in detail herein, this disclosure includes several practical applications having the features described herein that provide benefits and / or solve problems associated with providing multi-node computing systems with sufficient memory, processing, bandwidth, and energy efficiency constraints for the effective operation of AI and / or ML models. Several exemplary benefits are discussed herein in relation to various features and functionalities provided by computing systems as described. It should be understood that the benefits expressly discussed in relation to one or more embodiments described herein are provided as examples and are not intended to be an exhaustive list of benefits that can be considered as all possible computing systems.

[0114] For example, the various circuit packages and their connections described herein enable the construction of complex topologies of computing and memory nodes that can play the best role for specific applications. In a simple embodiment, a set of photonic channels connects memory nodes, e.g., memory circuit packages with memory resources, to one or more computing circuit packages with computing nodes. Computing and memory circuit packages can be connected and configured within any number of network topologies, which can be facilitated through the use of one or more photonic channels, including optical fibers. This can provide the benefit of relaxing distance constraints between computing and / or memory nodes, for example, memory circuit packages can be physically located arbitrarily away from computing circuit packages within the optical buffet of the photonic channels.

[0115] Various network topologies can offer significant speed and energy savings. For example, photonic data transport is typically more efficient than high-bandwidth electrical interconnects of homogeneous elements within the EIC of the circuit package itself. By implementing one or more photonic channels, the electrical cost of transmitting data can be significantly reduced. In addition, photonic channels are typically much faster than electrical interconnects, and therefore, the use of photonic channels enables the grouping and topological configuration of memory and computing circuit packages that best serve the bandwidth and connectivity requirements of a given application. In fact, the architectural separation of memory and computing networks allows them to be optimized for data size, traffic patterns, and bandwidth for each network application, respectively. A further additional benefit is that, since distance and arrangement are not determined by electrical interfaces, it is possible to control the power density of the system by spacing out memory and computing circuit packages and optimizing cooling efficiency.

[0116] One or more specific embodiments of the innovative technology are described herein. In addition, in an attempt to provide a concise description of these embodiments, not all features of the actual embodiments may be described herein. It should be understood that in the development of any such actual implementation, as in any engineering or design project, numerous embodiment-specific decisions will be made to achieve the developer's specific objectives, such as compliance with system-related and business-related constraints, which may vary from embodiment to embodiment. Furthermore, it should be understood that such development efforts may be complex and time-consuming, however, to a person skilled in the art who is interested in this disclosure, this would be the normal work of design, fabrication, and manufacturing.

[0117] The numbers, percentages, ratios, or other values ​​described herein are intended to include, and also other values ​​that are described "about" or "approximately," as will be understood by those skilled in the art, and are encompassed by the embodiments of this disclosure. The described values ​​should therefore be interpreted broadly enough to include values ​​that are at least close to the described value in order to perform the desired function or achieve the desired result. The described values ​​may include values ​​that are at least within 5%, 1%, 0.1%, or 0.01% of the described value, including the variation that would be expected in a preferred manufacturing or production process.

[0118] The terms “approximately,” “about,” and “substantially,” as used herein, still refer to quantities that are close to the stated quantity and perform the desired function or achieve the desired result. For example, the terms “approximately,” “about,” and “substantially” may refer to quantities that are less than 5%, less than 1%, less than 0.1%, and less than 0.01% of the stated quantity. Furthermore, it should be understood that any direction or reference frame in the preceding description is simply a relative direction or movement. For example, any reference to “up” and “down” or “above” or “below” simply describes the relative position or movement of the relevant element.

[0119] The following are non-limiting embodiments of the innovative embodiments of this disclosure.

[0120] A1. A method for embedding a photonic integrated circuit (PIC) in a package comprising the PIC and at least one electronic integrated circuit (EIC), wherein the PIC comprises an active portion that consumes power when the PIC is activated and a passive portion comprising an optical transmission medium configured to propagate optical signals to or from the active portion, the method comprising: masking a portion of the surface of the PIC with a mask material, wherein the portion corresponds to one or more photonic ports in the passive portion of the PIC; depositing a layer of molding material to at least partially encapsulate the PIC, including the mask material; and removing a portion of the molding material sufficient to expose the mask material.

[0121] A2. The method according to A1, further comprising the steps of removing a mask material from the surface of a PIC and providing a cavity within a molding material, wherein the cavity exposes one or more photonic ports, and filling the cavity with an optically transparent medium so that optical signals can be received or transmitted through the cavity.

[0122] A3. The method of A2, further comprising the step of placing the PIC on a glass carrier.

[0123] A4. The method according to A3, further comprising the steps of peeling off a glass carrier and mounting the package onto a printed circuit board (PCB) after peeling off the glass carrier.

[0124] A5. The method according to A2, wherein the step of filling a cavity is to introduce a certain volume of a curable material into the cavity so that the cavity is at least partially filled, and to cure the curable material in the cavity to provide an optically transparent window in the cavity, wherein the curable material is an ultraviolet-curable epoxy.

[0125] A6. The method of A5, further comprising the step of matching an optical interface with a passive portion of a PIC such that an optical signal can be received from or transmitted to the optical interface through an optically transparent window in a cavity, wherein the optical interface is a fiber optic mounting unit (FAU).

[0126] A7. The method according to A6, further comprising the step of placing a coupler between an optical interface and a cavity, and coupling an optical signal from the optical interface to one of the photonic ports, wherein the coupler includes at least one of a lattice coupler or an edge coupler.

[0127] A8. The method of A6, further comprising the step of coupling an optical interface to at least one of an optical engine or an optical interface on another package.

[0128] A9. The method according to A1, wherein the layer of molding material is 100 μm or less in thickness.

[0129] A10. The method according to A1, further comprising the step of providing high-bandwidth memory (HBM) and a processor in a package, wherein at least one EIC bridges the PIC to the HBM and the processor.

[0130] A11. A method for embedding a photonic integrated circuit (PIC) in a package comprising the PIC and at least one electronic integrated circuit (EIC), wherein the PIC comprises an active portion that consumes power when the PIC is activated and a passive portion that includes an optical transmission medium configured to allow optical signals to propagate to or from the active portion, the method comprising: depositing a first layer of curable material on a portion of the surface of the PIC, the portion of the surface corresponding to one or more photonic ports in the passive portion of the PIC; curing the curable material to provide a layer of solid and transparent material adjacent to the portion of the surface of the PIC; depositing a layer of molding material to at least partially encapsulate the PIC including the layer of solid and transparent material; and removing a portion of the molding material sufficient to expose the solid and transparent material.

[0131] A12. The method according to A11, wherein the curable material is an ultraviolet (UV) curable epoxy.

[0132] A13. The method according to A11, wherein the step of removing a portion of the layer comprises grinding or polishing the layer of molding material to provide a substantially planar surface of the molding material and a solid and transparent material, the layer of molding material having a thickness of less than 100 μm, yet providing sufficient rigidity to package the PIC together with at least one EIC.

[0133] A14. The method according to A11, further comprising the step of introducing a second layer of curable material between a solid and transparent material and an optical interface such that an optical signal can be received from or transmitted from a photonic port to an optical interface, wherein the optical interface is a fiber optic attachment unit (FAU).

[0134] A15. The method of A14, further comprising the step of placing the PIC on a glass carrier.

[0135] A16. The method according to A15, further comprising the steps of removing the glass carrier from the package and mounting the package onto a printed circuit board (PCB) after the glass carrier has been removed.

[0136] A17. The method according to A14, further comprising the step of curing a second layer of a curable material.

[0137] A18. The method of A17, further comprising the step of matching the optical interface with the passive portion of the PIC such that once the second layer of the curable material has cured, optical signals can be received through the optical interface or transmitted thereto through the layer of solid, transparent material.

[0138] A19. The method according to A17, further comprising the steps of: positioning a coupler between an optical interface and a cavity so as to couple an optical signal from an optical interface to one of a photonic port, wherein the coupler includes at least one of a lattice coupler or an edge coupler; and coupling the optical interface to at least one of an optical interface on an optical engine or another package.

[0139] A20. The method according to A11, further comprising the step of providing high-bandwidth memory (HBM) and a processor in a package, wherein at least one EIC bridges the PIC to the HBM and the processor.

[0140] A21. A package comprising: a photonic integrated circuit (PIC) comprising a semiconductor die containing an active portion and a passive portion, which is arranged on a substrate and coupled to one another, wherein the active portion is configured to consume power when activated, and the passive portion includes an optical transmission medium configured to propagate optical signals to or from the active portion of the PIC; an electronic integrated circuit (EIC) comprising a component electrically coupled to and acting electrically on the active portion of the PIC; and a packaging compound that at least partially encapsulates the PIC, wherein the packaging compound defines a cavity on the side of the semiconductor die opposite the substrate, and the cavity is filled with an optically transparent medium so that optical signals can be received from or transmitted to the passive portion of the PIC through the cavity.

[0141] A22. The package as described in A21, wherein the active component includes at least one of an optical modulator or a photodetector.

[0142] A23.EIC is a package as described in A22, comprising at least one of a driver coupled to an optical modulator on a PIC and configured to drive the optical modulator so that information content is modulated on an optical signal, and a transimpedance amplifier coupled to a photodetector and configured to act on the photodetector so that the modulated optical signal is converted into an electrical signal.

[0143] A24. The optical transmission medium is the package described in A21, comprising at least one of a waveguide or a fiber.

[0144] A25. The optically transparent medium comprises an ultraviolet (UV) curable epoxy, and the optically transparent medium is characterized by an optical refractive index that substantially matches that of an optical transmission medium, as described in A21.

[0145] A26. The package as described in A25, wherein the cavity is coupled to an optical interface including a fiber optic attachment unit (FAU), the cavity has a thickness of approximately 50 μm or less than approximately 50 μm, and the cavity has lateral dimensions of approximately 3 mm in width and approximately 40 mm in length.

[0146] A27. The package as described in A26, further comprising a coupler positioned between the optical interface and the optical transmission medium on the PIC, wherein the coupler comprises at least one of a grid coupler or an edge coupler.

[0147] A28. The optical interface is coupled to at least one of the optical engines or FAUs on another package, and the optical interface accommodates one or more optical channels, as described in A26.

[0148] A29. The circuit board is a printed circuit board (PCB), packaged as described in A21.

[0149] A30. The package described in A21 further includes high-bandwidth memory (HBM) and a processor, with the EIC bridging the PIC to the HBM and processor.

[0150] B1. A method for embedding a photonic integrated circuit (PIC) in a package comprising the PIC and at least one electronic integrated circuit (EIC), wherein the PIC comprises an active portion that consumes power when the PIC is activated and a passive portion that includes an optical transmission medium configured to propagate optical signals to or from the active portion, and the method comprises: placing a cap on the surface of the PIC and covering one or more photonic ports on the surface of the passive portion of the PIC, wherein the cap comprises a crown that forms an opening over one or more photonic ports and a brim on the surface of the PIC; depositing a layer of molding material to at least partially enclose the PIC and the cap; polishing the layer of molding material, removing a portion of the molding material, removing the upper portion of the crown, and exposing one or more photonic ports through openings over the photonic ports.

[0151] B2. The method according to B1, further comprising the step of machining a cap using a mold that defines an opening within the cap such that when the cap is placed on the PIC, the opening is directly above one or more photonic ports.

[0152] B3. The method of B2, wherein the opening is molded such that, when the cap is placed on the PIC, the upper portion of the opening has a larger lateral dimension than the lower portion of the opening.

[0153] B4. The method according to B2, wherein the step of placing the cap on the PIC includes aligning the cap with the PIC based at least partially on one or more alignment markers.

[0154] B5. The method according to B1, wherein the layer of molding material is 100 μm or less in thickness.

[0155] B6. The method according to B1, further comprising the step of filling the opening with an optically transparent medium having an optical refractive index substantially matching that of one or more photonic ports.

[0156] B7. The method according to B6, the step of filling an opening comprising introducing a certain volume of curable material into an opening so that the opening is at least partially filled, and curing the curable material in the opening to provide an optically transparent window in the opening so that an optical signal can be received or transmitted through an optically transparent window, wherein the curable material is an ultraviolet (UV) curable epoxy having an optical refractive index substantially matching that of one or more photonic ports.

[0157] B8. The method according to B5, further comprising the steps of mounting a fiber optic attachment unit (FAU) on an optically transparent window and optically coupling the FAU to at least one or more photonic ports through at least one of a grid coupler or an edge coupler.

[0158] B9. The method according to B1, further comprising the steps of: placing an additional cap, including a crown that forms an opening, on top of an opening above one or more photonic ports; and polishing the additional cap and removing the upper portion of the crown on top of the opening so that the opening is exposed.

[0159] B10. The method according to B9, further comprising the step of filling the openings of the crown of an additional cap with an optically transparent medium having an optical refractive index substantially matching that of one or more photonic ports.

[0160] B11. The method according to B1, further comprising the steps of placing a PIC on a glass carrier, peeling off the glass carrier, and mounting the package on a printed circuit board (PCB) after peeling off the glass carrier.

[0161] B12. The method according to B1, further comprising the step of providing high-bandwidth memory (HBM) and a processor in a package, wherein at least one EIC bridges the PIC to the HBM and the processor.

[0162] B13. A package comprising a photonic integrated circuit (PIC) having an active portion and a passive portion, which are arranged on a substrate and coupled to each other, the active portion being configured to consume power when activated, and the passive portion being configured to propagate optical signals to or from the active portion of the PIC, which includes an optical transmission medium; a cavity formed on the side of the semiconductor die opposite the substrate, which is filled with an optically transparent medium having an optical refractive index substantially matching that of the optical transmission medium, so that optical signals can be received to or transmitted to the passive portion of the PIC through the cavity; and a fiber optic mounting unit (FAU) mounted on the cavity for coupling optical signals to or from the outside of the package.

[0163] B14. The package described in B13 further includes an electronic integrated circuit (EIC) which includes a component that is electrically coupled to and acts electrically on the active part of the PIC.

[0164] B15. The package according to B14, comprising a packaging compound that at least partially encapsulates a PIC, further comprising a packaging compound that defines a cavity.

[0165] B16. The package as described in B14, wherein the cavity has a thickness of approximately 50 μm or less than approximately 50 μm, and the cavity has lateral dimensions of approximately 3 mm in width and approximately 40 mm in length.

[0166] The package described in B14, wherein the active portion of the PIC includes at least one of an optical modulator or a photodetector, and the EIC includes at least one of a driver coupled to the optical modulator on the PIC and configured to drive the optical modulator so that information content is modulated on an optical signal, and a transimpedance amplifier coupled to the photodetector and configured to act on the photodetector so that the modulated optical signal is converted into an electrical signal.

[0167] B18. The circuit board is a printed circuit board (PCB), packaged as described in B14.

[0168] B19. The package described in B14 further includes high-bandwidth memory (HBM) and a processor, with the EIC bridging the PIC to the HBM and processor.

[0169] The package described in B13 further includes a coupler, which is positioned between the FAU and the optical transmission medium on the PIC, the coupler comprising at least one of a grid coupler or an edge coupler.

[0170] B21. The package according to B13, wherein the optical transmission medium comprises at least one of a waveguide or a fiber, and the optically transparent medium comprises an ultraviolet (UV) curable epoxy having an optical refractive index substantially matched to that of the optical transmission medium.

[0171] B22. The package according to B13, further comprising an additional cavity formed on top of the cavity, the additional cavity being filled with an optically transparent medium so that optical signals can be received or transmitted through the additional cavity and cavity.

[0172] B23. A package comprising an electronic integrated circuit (EIC) and a photonic integrated circuit (PIC) electrically coupled to the EIC through one or more electrical connections, the photonic integrated circuit (PIC) comprising a semiconductor die having an active portion electrically connected to the EIC and configured to consume power when activated, and a passive portion including an optical transmission medium configured to propagate optical signals to or from the active portion of the PIC, the passive portion including one or more photonic ports on the surface of the PIC; a layer of packaging compound at least partially encapsulating the EIC and the PIC; an optical path through the layer of packaging compound to one or more photonic ports on the surface of the PIC; and a fiber optic attachment unit (FAU) mounted in the package and arranged to couple optical signals to or from the PIC via one or more photonic ports.

[0173] The package described in B23, wherein the active portion of the PIC includes at least one of an optical modulator and a photodetector, and the EIC includes at least one of a driver electrically coupled to the optical modulator through one or more electrical connections and configured to drive the optical modulator and modulate an optical signal propagating through an optical transmission medium on the PIC, and a transimpedance amplifier electrically coupled to the photodetector through one or more electrical connections and configured to convert the modulated optical signal received at the photodetector into an electrical signal.

[0174] B25. The driver is located 2 mm or less from the optical modulator in the package described in B24.

[0175] B26.EIC is the package described in B23, which at least partially overlaps with the surface of the PIC.

[0176] B27. The optical path is located in a part of the PIC, not overlapping with the EIC, and is in the package described in B26.

[0177] B28. The package described in B23, further including a circuit board, which supports the PIC on the opposite side of the PIC's EIC.

[0178] B29. The package described in B23 further includes high-bandwidth memory (HBM) and a processor, with the EIC bridging the PIC to the HBM and processor.

[0179] B30. The optical path is the package described in B23, which includes a layer of ultraviolet (UV) curable epoxy.

[0180] This specification includes many specific implementation details, which should be interpreted not as limitations on the scope of the claimed content as defined by the claims themselves, but rather as descriptions of features that may be specific to a particular implementation of a particular invention. Certain features described herein in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually or in any preferred secondary combination in multiple implementations. Furthermore, features may be described above to act in a certain combination, and may also be initially claimed as such, but one or more features from the claimed combination may, in some cases, be excluded from the combination, and the claims may also cover secondary combinations or variations of secondary combinations.

Claims

1. A method for embedding a photonic integrated circuit (PIC) in a package comprising the PIC and at least one electronic integrated circuit (EIC), wherein the PIC comprises an active portion that consumes power when the PIC is activated and a passive portion comprising an optical transmission medium configured to propagate optical signals to or from the active portion, and the method is The cap is placed on the surface of the PIC and covers one or more photonic ports on the surface of the passive portion of the PIC, wherein the cap comprises a crown forming an opening over the one or more photonic ports and a brim on the surface of the PIC. A layer of molding material is deposited, and the PIC and the cap are at least partially sealed inside. The process involves polishing the layer of the molding material, removing a portion of the molding material, removing the upper portion of the crown, and exposing one or more photonic ports through the opening above the photonic ports. Methods that include...

2. The method according to claim 1, further comprising machining the cap using a mold that defines the opening within the cap such that when the cap is placed on the PIC, the opening is directly above the one or more photonic ports, the opening is molded such that when the cap is placed on the PIC, the opening has a larger lateral dimension toward the upper portion of the opening than the lower portion of the opening, and placing the cap on the PIC involves aligning the cap and the PIC at least partially based on one or more alignment markers.

3. The method according to claim 1, wherein the layer of the molding material has a thickness of 100 μm or less.

4. The method further includes filling the opening with an optically transparent medium having an optical refractive index substantially matching that of the one or more photonic ports, Filling the aforementioned opening is Introducing a certain volume of curable material into the opening so that the opening is at least partially filled, The curable material in the opening is cured so that the optical signal can be received or transmitted through the optically transparent window, thereby providing an optically transparent window within the opening. Includes, The method according to claim 1, wherein the curable material is an ultraviolet (UV) curable epoxy having an optical refractive index substantially matching that of the one or more photonic ports.

5. The fiber optic mounting unit (FAU) is mounted on the optically transparent window, Optically coupling the FAU to one or more photonic ports through at least one of a lattice coupler or an edge coupler. The method according to claim 4, further comprising:

6. An additional cap, including a crown that forms the opening, is placed above the opening on one or more of the photonic ports. The additional cap is polished and the upper portion of the crown above the opening is removed so that the opening is exposed. The opening of the crown of the additional cap is filled with an optically transparent medium having an optical refractive index substantially matching that of the one or more photonic ports. The method according to claim 1, further comprising:

7. The PIC is placed on a glass carrier, The glass carrier is to be removed, After peeling off the glass carrier, the package is mounted on a printed circuit board (PCB). The method according to claim 1, further comprising:

8. The method according to claim 1, further comprising providing a high-bandwidth memory (HBM) and a processor within the package, wherein the at least one EIC bridges the PIC to the HBM and the processor.

9. It is a package, A photonic integrated circuit (PIC) comprising a semiconductor die having active and passive parts arranged on a substrate and coupled to each other, wherein the active part is configured to consume power when activated, and the passive part comprises an optical transmission medium configured to propagate optical signals to or from the active part of the PIC, A cavity formed on the side of the semiconductor die opposite the substrate, the cavity being filled with an optically transparent medium having an optical refractive index substantially matching that of the optical transmission medium, such that the optical signal can be received from or transmitted to the passive portion of the PIC through the cavity. A fiber optic mounting unit (FAU) mounted on the cavity and coupling the optical signal to or from the outside of the package. A package that includes the following features.

10. An electronic integrated circuit (EIC) comprising a component electrically coupled to the active portion of the PIC and electrically acting on the active portion of the PIC, High-bandwidth memory (HBM) and, Processor and Furthermore, The package according to claim 9, wherein the EIC bridges the PIC to the HBM and the processor.

11. A packaging compound that at least partially encapsulates the PIC, wherein the packaging compound defines the cavity. Furthermore, The cavity has a thickness of approximately 50 μm or less. The package according to claim 10, wherein the cavity has lateral dimensions of approximately 3 mm in width and approximately 40 mm in length.

12. The active portion of the PIC comprises at least one of an optical modulator or a photodetector. The aforementioned EIC is A driver coupled to the optical modulator on the PIC and configured to drive the optical modulator so that information content is modulated on the optical signal, A transimpedance amplifier coupled to the photodetector and configured to act on the photodetector so that the modulated optical signal is converted into an electrical signal, Includes at least one of the following: The package according to claim 11, wherein the substrate is a printed circuit board (PCB).

13. The package according to claim 9, further comprising a coupler disposed between the FAU and the optical transmission medium on the PIC, the coupler comprising at least one of a grid coupler or an edge coupler, the optical transmission medium comprising at least one of a waveguide or a fiber, and the optically transparent medium comprising an ultraviolet (UV) curable epoxy having an optical refractive index substantially matching that of the optical transmission medium.

14. The package according to claim 9, further comprising an additional cavity formed in the upper part of the cavity, wherein the additional cavity is filled with the optically transparent medium so that the optical signal can be received or transmitted through the additional cavity and the cavity.

15. It is a package, Electronic integrated circuits (EICs) and A photonic integrated circuit (PIC) electrically coupled to the EIC through one or more electrical connections, wherein the PIC comprises a semiconductor die, the semiconductor die comprising an active portion electrically connected to the EIC and configured to consume power when activated, and a passive portion comprising an optical transmission medium configured to propagate optical signals to or from the active portion of the PIC, the passive portion comprising one or more photonic ports on the surface of the PIC, A layer of packaging compound that at least partially encapsulates the EIC and the PIC, An optical path through the layer of the packaging compound to one or more photonic ports on the surface of the PIC, A fiber optic mounting unit (FAU) is mounted on the package and arranged to couple optical signals to or from the PIC via one or more photonic ports. A package that includes the following features.

16. The active portion of the PIC comprises at least one of (i) an optical modulator and (ii) a photodetector, The package according to claim 15, wherein the EIC comprises at least one of: (i) a driver, the driver being electrically coupled to the optical modulator through one or more electrical connections and configured to drive the optical modulator and modulate an optical signal propagating through the optical transmission medium on the PIC; and (ii) a transimpedance amplifier, the transimpedance amplifier being electrically coupled to the photodetector through one or more electrical connections and configured to convert a modulated optical signal received by the photodetector into an electrical signal.

17. The package according to claim 16, wherein the driver is positioned within 2 mm of the optical modulator, and the EIC at least partially overlaps the surface of the PIC.

18. The optical path is located in a part of the PIC that does not overlap with the EIC. The package according to claim 17, wherein the optical path comprises a layer of ultraviolet (UV) curable epoxy.

19. The package according to claim 15, further comprising a substrate that supports the PIC on the side of the PIC opposite to the EIC.

20. High-bandwidth memory (HBM) and, Processor and Furthermore, The package according to claim 15, wherein the EIC bridges the PIC to the HBM and the processor.

21. A method for embedding a photonic integrated circuit (PIC) in a package comprising the PIC and at least one electronic integrated circuit (EIC), wherein the PIC comprises an active portion that consumes power when the PIC is activated and a passive portion comprising an optical transmission medium configured to propagate optical signals to or from the active portion, and the method is The method involves masking a portion of the surface of the PIC with a mask material, wherein the portion corresponds to one or more photonic ports within the passive portion of the PIC. A layer of molding material is deposited, and the PIC is at least partially encapsulated, including the mask material. Removing a portion of the molding material layer sufficient to expose the mask material and Methods that include...

22. The mask material is removed from the surface of the PIC, and a cavity is provided within the molding material, the cavity exposing one or more photonic ports. The cavity is filled with an optically transparent medium so that the optical signal can be received or transmitted through the cavity. The method according to claim 21, further comprising:

23. The PIC is placed on a glass carrier, The glass carrier is to be removed, After peeling off the glass carrier, the package is mounted on a printed circuit board (PCB). The method according to claim 22, further comprising:

24. Filling the aforementioned cavity is Introducing a certain volume of a curable material into the cavity so that the cavity is at least partially filled, The curable material in the cavity is cured to provide an optically transparent window in the cavity, wherein the curable material is an ultraviolet-curable epoxy. The method according to claim 22, including the method described in claim 22.

25. The optical interface and the passive portion of the PIC are matched such that the optical signal can be received from or transmitted to the optical interface through the optically transparent window in the cavity, wherein the optical interface is a fiber optic mounting unit (FAU). The coupler is positioned between the optical interface and the cavity, and the optical signal from the optical interface is coupled to one of the photonic ports, wherein the coupler comprises at least one of a lattice coupler or an edge coupler. The optical interface is coupled to at least one of the optical engine or an optical interface on another package. The method according to claim 24, further comprising:

26. The method according to claim 21, wherein the layer of the molding material has a thickness of 100 μm or less.

27. The method according to claim 21, further comprising providing a high-bandwidth memory (HBM) and a processor within the package, wherein the at least one EIC bridges the PIC to the HBM and the processor.

28. A method for embedding a photonic integrated circuit (PIC) in a package comprising the PIC and at least one electronic integrated circuit (EIC), wherein the PIC comprises an active portion that consumes power when the PIC is activated and a passive portion comprising an optical transmission medium configured to allow optical signals to propagate to or from the active portion, and the method is The method involves depositing a first layer of a curable material onto a portion of the surface of the PIC, wherein the portion of the surface corresponds to one or more photonic ports within the passive portion of the PIC. The curable material is cured to provide a layer of solid and transparent material adjacent to the part of the surface of the PIC, A layer of molding material is deposited, and the PIC, including the layer of solid and transparent material, is at least partially encapsulated. Removing a portion of the layer of the molding material sufficient to expose the solid and transparent material, wherein the curable material is an ultraviolet (UV) curable epoxy. Methods that include...

29. Removing the portion of the aforementioned layer includes grinding or polishing the layer of the molding material to provide a substantially planar surface of the molding material and the solid and transparent material. The method according to claim 28, wherein the layer of the molding material has a thickness of less than 100 μm, yet provides sufficient rigidity to package the PIC together with the at least one EIC.

30. The method involves introducing a second layer of the curable material between the solid and transparent material and the optical interface so that the optical signal can be received from the photonic port through the optical interface or transmitted to the optical interface, wherein the optical interface is a fiber optic attachment unit (FAU). The curing of the second layer of the curable material The method according to claim 28, further comprising:

31. The PIC is placed on a glass carrier, Removing the glass carrier from the package, After removing the glass carrier, the package is mounted on a printed circuit board (PCB). The method according to claim 30, further comprising:

32. Once the second layer of the curable material is cured, the optical interface and the passive portion of the PIC are matched so that the optical signal can be received from or transmitted to the optical interface through the layer of solid and transparent material. The coupler is positioned between the optical interface and the cavity such that the optical signal from the optical interface is limited to one of the photonic ports, and the coupler comprises at least one of a lattice coupler or an edge coupler. The optical interface is coupled to at least one of the optical engine or an optical interface on another package. The method according to claim 30, further comprising:

33. The method according to claim 28, further comprising providing a high-bandwidth memory (HBM) and a processor within the package, wherein the at least one EIC bridges the PIC to the HBM and the processor.

34. It is a package, A photonic integrated circuit (PIC) comprising a semiconductor die containing an active portion and a passive portion arranged on a substrate and coupled to each other, wherein the active portion is configured to consume power when activated, and the passive portion comprises an optical transmission medium configured to propagate optical signals to or from the active portion of the PIC, An electronic integrated circuit (EIC) comprising a component electrically coupled to the active portion of the PIC and electrically acting on the active portion of the PIC, A packaging compound that at least partially encapsulates the PIC, wherein the packaging compound defines a cavity on the side of the semiconductor die opposite the substrate, and the cavity is filled with an optically transparent medium so that the optical signal can be received from or transmitted to the passive portion of the PIC through the cavity. A package that includes the following features.

35. The aforementioned active portion is, Optical modulator and Photodetector and Includes at least one of the following: The aforementioned EIC is A driver coupled to the optical modulator on the PIC and configured to drive the optical modulator so that information content is modulated on the optical signal, A transimpedance amplifier coupled to the photodetector and configured to act on the photodetector so that the modulated optical signal is converted into an electrical signal, Includes at least one of the following: The package according to claim 34, wherein the substrate is a printed circuit board (PCB).

36. The optical transmission medium comprises at least one of a waveguide or a fiber, The optically transparent medium comprises an ultraviolet (UV) curable epoxy. The package according to claim 34, wherein the optically transparent medium is characterized by an optical refractive index that substantially matches that of the optical transmission medium.

37. The cavity is connected to an optical interface equipped with a fiber optic attachment unit (FAU). The cavity has a thickness of approximately 50 μm or less. The package according to claim 36, wherein the cavity has lateral dimensions of approximately 3 mm in width and approximately 40 mm in length.

38. The package according to claim 37, further comprising a coupler disposed between the optical interface and the optical transmission medium on the PIC, wherein the coupler comprises at least one of a grid coupler or an edge coupler.

39. The optical interface is coupled to at least one of the optical engine or an FAU on another package. The package according to claim 37, wherein the optical interface accommodates one or more optical channels.

40. High-bandwidth memory (HBM) and, Processor Furthermore, The package according to claim 34, wherein the EIC bridges the PIC to the HBM and the processor.

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