POWER DEVICE AND METHOD FOR ASSEMBLING POWER DEVICE

Abstract

According to one embodiment, a power device (100) comprises at least two power semiconductor modules (1) and a carrier (2) having a top surface (20) and an opposite bottom surface (21). The power semiconductor modules are mounted on the carrier and thermally connected to the carrier. The at least two power semiconductor modules are arranged in an overlapping configuration such that at least one power semiconductor module mounted on the top surface and at least one power semiconductor module mounted on the bottom surface at least partially overlap when viewed in plan of the top surface.

Description

[Technical field]

[0001] The present disclosure relates to power devices and methods of assembling power devices. [Background technology]

[0002] Power devices such as inverters are widely known. They usually comprise several power semiconductor modules mounted on one side of a carrier, for example for liquid or air cooling. The power semiconductor modules may be arranged in a row on the top side of the carrier so that serial cooling can be provided. Summary of the Invention [Problem to be solved by the invention]

[0003] There is a need for improved power devices, for example power devices having good thermal properties and compact designs with reduced area and / or space consumption, and further, there is a need for methods of assembling such power devices. [Means for solving the problem]

[0004] SUMMARY OF THE DISCLOSURE An embodiment of the present disclosure relates to an improved power device. Another embodiment of the present disclosure relates to a method of assembling a power device.

[0005] First, the power device is identified. According to one embodiment, a power device comprises at least two power semiconductor modules and a carrier having a top side and an opposite bottom side. The power semiconductor modules are mounted on the carrier and thermally connected to the carrier. The at least two power semiconductor modules are arranged in an overlapping configuration such that at least one power semiconductor module mounted on the top side and at least one power semiconductor module mounted on the bottom side at least partially overlap when viewed in plan of the top side.

[0006] The invention is based, inter alia, on the realization that semiconductor power modules arranged in a row on one side of a carrier make the installation and electrical connection of the power semiconductor modules relatively easy. On the other hand, the complete set-up is becoming relatively long, since the row is created by the power modules and the corresponding clamping mechanisms. For example, the length of the carrier may exceed the size limits of the desired application, for example in the automotive field, where the available space is limited.

[0007] The inventors have come up with the idea, inter alia, of arranging the power semiconductor modules on the top and bottom sides of the carrier in an overlapping configuration in order to save space, for example the length of the carrier can be reduced by up to 50%.

[0008] The power semiconductor modules of a power device may all be of the same type and similarly configured, and therefore any feature disclosed herein for one power semiconductor module is also disclosed for further or all other power semiconductor modules of the power device.

[0009] Each of the power semiconductor modules may include one or more power semiconductor chips. The power semiconductor chips may be electrically, thermally, and / or mechanically interconnected within the module, for example. Each of the power semiconductor modules may include a substrate, which may have an upper metallization, a lower metallization, and an insulating layer therebetween. The one or more power semiconductor chips may be electrically, mechanically, and / or thermally connected to the upper metallization. The substrate may be, for example, a direct bonded copper (DBC) substrate, or a direct bonded aluminum (DBA) substrate, or an active metal bracing (AMB) substrate with an insulating ceramic layer, or an isolated metal substrate (IMS) with an insulating resin layer. Furthermore, each of the power semiconductor modules may include a terminal that may be bonded to the upper metallization.

[0010] The power semiconductor modules may each be adapted to handle a current in excess of 10 A. The power semiconductor modules may be low voltage modules adapted to handle voltages below 1 kV, or medium voltage modules adapted to handle voltages between 1 kV and 30 kV.

[0011] The power semiconductor chips and / or substrates and / or terminals of the power semiconductor modules may be arranged in a housing of the respective power semiconductor module. The housing may be filled with or may be an encapsulant, and the power semiconductor chips and / or substrates and / or terminals are embedded in the encapsulant. The encapsulant may be a resin or a dielectric gel. For example, the encapsulant is formed by casting or molding, for example transfer molding.

[0012] The power semiconductor module may further comprise a base plate on which the power semiconductor chips and / or the substrate are attached. For example, the substrate is attached to the base plate with the lower metallization facing the base plate. The base plate is configured to dissipate heat from the power semiconductor chips, for example. For example, the base plate is formed of a metal, such as Cu or Al, or a composite material, such as aluminum silicon carbide or magnesium silicon carbide.

[0013] The carrier may be a cooling carrier. For example, the carrier comprises or consists of a metal, such as Cu or Al. The carrier may be formed in one piece or in several pieces, for example in two half shells.

[0014] The power semiconductor modules arranged in an overlapping configuration may overlap in part or in whole when viewed in a plan view of the top surface. In other words, when the semiconductor chips in the overlapping configuration are projected onto the top surface of the carrier, the projected power semiconductor modules overlap in part or in whole. For example, at least 25% or at least 30% of the area of ​​the semiconductor module on the top surface overlaps with the power semiconductor module on the bottom surface, and / or vice versa. Additionally or alternatively, up to 75% or up to 70% of the area of ​​the power semiconductor module on the top surface may overlap with the power semiconductor module on the bottom surface, and / or vice versa. For example, some or each power semiconductor module of the power device mounted on one side of the carrier is arranged in an overlapping configuration with at least one other power semiconductor module on the other side of the carrier.

[0015] The power semiconductor modules of the power device are, for example, electrically connected to each other. A power device may comprise several power semiconductor modules mounted on a top side and / or several power semiconductor modules mounted on a bottom side, where all features disclosed herein for one power semiconductor module on the top side are also disclosed for all other power semiconductor modules on the top side, and all features disclosed herein for one power semiconductor module on the bottom side are also disclosed for all other power semiconductor modules on the bottom side.

[0016] As used herein, the terms "top" and "bottom" or similar terms should in no way be understood to be limited to directions anti-parallel and parallel to the direction of gravity, but rather are used generally to indicate, for example, regions or directions that are opposite one another.

[0017] According to a further embodiment, the power device comprises at least three power semiconductor modules arranged in an overlapping configuration, such that at least two power semiconductor modules attached to the top surface overlap at least one identical power semiconductor module attached to the bottom surface when viewed in a plan view of the top surface, or at least two power semiconductor modules attached to the bottom surface overlap at least one identical power semiconductor module attached to the top surface when viewed in a plan view of the top surface. Each power semiconductor module may overlap at most two power semiconductor modules when viewed in a plan view of the top surface.

[0018] For example, in a plan view of the top surface, one power semiconductor module of one side overlapping two power semiconductor modules of the other side is arranged symmetrically between the two power semiconductor modules of the other side in the lateral direction, for example between the two power semiconductor modules, the lateral direction being in this specification a direction parallel to the top surface of the carrier and / or a direction parallel to the main extension plane of the carrier.

[0019] Concerning the degree of overlap, the same is disclosed for at least three power semiconductor modules arranged in an overlapping configuration as described above in relation to at least two power semiconductor modules arranged in an overlapping configuration.

[0020] Here and below, all features disclosed for at least two power semiconductor modules arranged in an overlapping configuration are also disclosed for all power semiconductor modules arranged in an overlapping configuration.

[0021] The power semiconductor modules of the power device may be arranged in one or more rows when viewed in a plan view of the top surface. Each power semiconductor module in one row may be arranged in an overlapping configuration with at least one other power semiconductor module in the same row. For example, at least one row extends in a longitudinal direction, the longitudinal direction being a lateral direction. At least one semiconductor module in a row may also overlap with a semiconductor module on the other surface and with a semiconductor module in a different row when viewed in a plan view of the top surface.

[0022] According to a further embodiment, the power semiconductor modules arranged in an overlapping configuration each comprise a plurality of cooling elements on a respective back surface. The back surface is the side of the power semiconductor module facing the carrier. The cooling elements may protrude from the back surface towards the carrier. The back surface may be formed by a base plate or substrate and / or a housing. The cooling elements may be formed by a base plate or substrate.

[0023] According to a further embodiment, the carrier comprises at least one upper opening on the top surface. The upper opening may be an opening to a cavity in the carrier. Furthermore, the carrier comprises at least one lower opening on the bottom surface. The lower opening may be an opening to a cavity in the carrier. Each of the upper and lower openings may be assigned to an individual cavity. The individual cavities may be fluidically coupled to each other, for example, via a channel portion. Alternatively, the upper and lower openings may be openings to the same cavity. For example, the carrier is a hollow body having one or more cavities therein. For example, each of the one or more cavities has one of a rectangular parallelepiped shape, a cubic shape, or a cylindrical shape. For example, the one or more cavities do not completely penetrate the carrier.

[0024] According to a further embodiment, at least one upper opening and at least one lower opening are at most partially overlapped when viewed in plan view of the upper surface of the carrier. For example, the upper opening is arranged without overlapping with at least one lower opening when viewed in plan view of the upper surface. In other words, in plan view of the upper surface, the upper opening does not overlap with the lower opening. Alternatively, there may be a slight overlap of the upper opening and the lower opening, for example an overlap of up to 25% or up to 20% or up to 10% of the area of ​​the upper opening or the lower opening.

[0025] The carrier may include several upper and / or lower openings. All features disclosed in relation to one upper opening or one lower opening are also disclosed for all other upper and lower openings, respectively. For example, all openings are arranged without overlapping or at most partially overlapping when viewed in a plan view of the carrier.

[0026] According to a further embodiment, the cooling elements of the power semiconductor modules arranged in an overlapping configuration protrude through the upper and lower openings into the carrier, i.e. into the interior of the carrier, for example into the cavity of the carrier. This means that the cooling elements of the power semiconductor module on the top side protrude through the upper openings and the cooling elements of the power semiconductor module on the bottom side protrude through the lower openings. Each semiconductor module may be assigned either an upper opening or a lower opening on a one-to-one basis and the cooling elements may protrude through the assigned openings.

[0027] The non-overlapping or slightly overlapping arrangement of the upper and lower openings allows the carrier to be designed to be relatively thin.

[0028] According to a further embodiment, the cooling elements are cooling ribs or cooling fins, for example pin fins. For example, the cooling fins have a cylindrical, conical or rhomboidal shape. The cooling elements may protrude columnarly from the rear surface, i.e. the main extension direction of the cooling elements may extend perpendicularly to the main extension plane of the power semiconductor module.

[0029] According to a further embodiment, the power semiconductor modules arranged in an overlapping configuration each comprise a functional area and an auxiliary area. The functional area may be a central area and the auxiliary area may be a peripheral area laterally surrounding the central area, for example laterally completely surrounding the central area. The functional area and the auxiliary area may each be a continuous, uninterrupted area. In a plan view of the top surface, the area of ​​the auxiliary area may be at least 10% or at least 50% and / or at most 100% or at most 70% of the area of ​​the functional area.

[0030] According to a further embodiment, one or more power semiconductor chips are arranged in the functional area of ​​the power semiconductor module. Additionally or alternatively, one or more cooling elements may be arranged in the functional area.

[0031] According to a further embodiment, the auxiliary area of ​​the semiconductor module does not contain a semiconductor chip and / or a cooling element.

[0032] Each power semiconductor module may comprise several functional regions separated laterally by one or more auxiliary regions. All features disclosed in relation to one functional region are also disclosed for all other functional regions of the power semiconductor module. All features disclosed in relation to one auxiliary region are also disclosed for all further auxiliary regions.

[0033] According to a further embodiment, the auxiliary regions of the power semiconductor modules in the overlapping configuration at least partially overlap in a plan view of the top surface, the functional regions of the power semiconductor modules in the overlapping configuration for example do not overlap one another in this plan view, i.e. do not overlap in this plan view.

[0034] The functional areas to which the power semiconductor chips are assigned are, for example, the areas in which most of the heat is generated during operation. In order to distribute the heat evenly on the carrier and thus improve the cooling properties, it is advantageous to arrange the functional areas without overlapping each other. In this way, for example, continuous cooling is improved.

[0035] According to further embodiments, the cooling elements of the power semiconductor modules are in each case arranged in the functional area and outside the auxiliary area, i.e. in a plan view of the top surface of the carrier, the cooling elements of the power semiconductor modules overlap only the functional area and not the auxiliary area. For example, in a plan view of the top surface, the auxiliary area completely surrounds laterally the openings assigned to the cooling elements and / or the semiconductor modules. The area occupied by the cooling elements has, for example, at least the size of the perimeter of the arrangement of the power semiconductor chips of the power semiconductor module.

[0036] According to a further embodiment, the auxiliary region is configured for connecting the power semiconductor module to the carrier. In the auxiliary region, a back surface of the power semiconductor module can be flat for mounting the power semiconductor module to the carrier. At least in the auxiliary region, the back surface can be formed by a substrate or a base plate and / or a housing. In the auxiliary region, the back surface can be at least partially in contact with the encapsulation.

[0037] For example, in the auxiliary region, the semiconductor module is fixed to the carrier by a fastening means. In a plan view of the top surface, the fastening means may simply overlap the auxiliary region. The fastening means may be one or more clamps, with which the power semiconductor module is clamped onto the carrier, and / or one or more screws, with which the power semiconductor module is screwed to the carrier. For example, in the auxiliary region, one or more screw holes are formed through the power semiconductor module, for example through the encapsulant and / or the base plate and / or the substrate.

[0038] A fastening means assigned to a power semiconductor module in an arrangement overlapping another power semiconductor module may overlap this other power semiconductor module, for example its functional area, when viewed in plan view of the top side. A fastening means may also be dedicated to two adjacent power semiconductor modules on one of the top or bottom sides.

[0039] According to a further embodiment, the carrier is configured to guide a cooling fluid for cooling the power semiconductor modules. The cooling fluid may be guided through the interior of the carrier, for example between the top and bottom sides. For example, the carrier is configured to guide the cooling fluid therein in a main extension direction, i.e. in a longitudinal direction, of the row in which the power semiconductor modules are arranged.

[0040] The carrier may include an inlet for guiding the cooling fluid into the carrier and an outlet for guiding the cooling fluid out of the carrier. The cooling fluid may be a gas or a liquid. For example, the cooling fluid is a water-based coolant or an oil. By shortening the length of the carrier, the length of the coolant flow path can be shortened. This can increase the cooling efficiency.

[0041] According to a further embodiment, the carrier is configured to guide the cooling fluid past the cooling element protruding through the opening. Thus, the cooling fluid may flow along and through the cooling element, thereby absorbing heat from the cooling element due to the power semiconductor chip. This may also cause the cooling element to generate turbulence in the cooling fluid, which is advantageous in terms of cooling efficiency.

[0042] According to a further embodiment, at least one channel is formed in the carrier for guiding the cooling fluid. The channel may extend from one end of the carrier to the other end of the carrier. The channel may be connected to an inlet and an outlet. For example, the channel extends from one end of the row in which the power semiconductor modules are arranged to the other end of the row. All openings on the top and bottom may be openings or inlets to the channel.

[0043] One or more cavities in the carrier may be part of or form a channel. For example, the channel may comprise one or more bends. The channel may be serpentine. In a direction perpendicular to the extension of the channel, the channel may be completely surrounded by the material of the carrier.

[0044] The carrier may be a pure cooling carrier with no electrical function, e.g., no current flows through it during normal operation of the power device.

[0045] According to a further embodiment, at least one power semiconductor module, for example some or all of the power semiconductor modules, are joined to the carrier. For example, the power semiconductor module is soldered or sintered or welded or glued to the carrier. In this case, the back side of the power semiconductor module may be flat.

[0046] According to a further embodiment, at least one power semiconductor module, e.g. some or all of the power semiconductor modules, comprises at least one power semiconductor chip which is one of an IGBT, a diode, a MOSFET, a thyristor, a JFET, a HEMT, or the power semiconductor module may comprise a plurality of such power semiconductor chips.

[0047] For example, at least one power semiconductor module comprises a number of power semiconductor chips connected in a half-bridge or full-bridge configuration.

[0048] A half-bridge is an electrical circuit including two switch elements or two pairs each of one switch element and one diode, connected in series between two DC nodes and providing an AC node or output point therebetween. The DC nodes and the AC node / output point may be electrically connected to the power terminals of a power module. Each switch element may consist of one or more semiconductor switches electrically connected in parallel. The switch elements are realized, for example, by the power semiconductor chips mentioned above.

[0049] The power module may be used, for example, in an electrical converter or inverter capable of rectifying an AC voltage supplied to a DC link or to a battery. The inverter may also be capable of generating an AC voltage from a DC voltage supplied to an electric motor, such as the motor of an electric vehicle. The electrical converter may also be a DC-DC converter. The power module may be used in automotive applications, such as electric cars, motorcycles, buses, off-road vehicles, etc.

[0050] The power device may be an inverter or converter for renewable energies, such as wind turbines, photovoltaic panels, tidal power plants and electric vehicles (EVs), or traction applications. The power module may be realized in a so-called six-pack configuration, where three half-bridge power semiconductor modules represent three phases.

[0051] We now identify a method for assembling a power device. The method may be used to assemble a power device according to any embodiment described herein. Thus, all features disclosed in relation to the power device are also disclosed in relation to the method and vice versa.

[0052] According to one embodiment, a method for assembling a power device includes mounting at least one power semiconductor module on a top surface of a carrier, and mounting at least one power semiconductor module on a bottom surface of the carrier opposite the top surface, such that the at least two power semiconductor modules are arranged in an overlapping configuration, where the at least one power semiconductor module on the top surface and the at least one power semiconductor module on the bottom surface at least partially overlap when viewed in a plan view of the top surface.

[0053] The mounting of the power semiconductor module on the carrier can be performed such that the power semiconductor module is fixedly connected to the carrier, for example the power semiconductor module is screwed, clamped, soldered, glued, welded or sintered to the carrier, any combination of these connection methods may also be used.

[0054] According to a further embodiment, after mounting the power semiconductor modules on the carrier, the power semiconductor modules are electrically connected with each other and / or with other parts of the power device, such as capacitors or control electronics.

[0055] Hereinafter, a power device and an assembly method of the power device will be described in more detail based on an exemplary embodiment with reference to the drawings. The attached drawings are included to provide further understanding. In the drawings, elements of the same structure and / or function may be referred to by the same reference numerals. It should be understood that the embodiments shown in the drawings are exemplary representations and are not necessarily drawn to scale. Insofar as elements or components correspond to each other in terms of their functions in different drawings, the description will not be repeated for each of the following drawings. For clarity, elements may not be labeled with corresponding reference numerals in all drawings. [Brief description of the drawings]

[0056] [Figure 1] 1 illustrates an exemplary embodiment of a power device in different views; [Diagram 2] 1 illustrates an exemplary embodiment of a power device in different views; [Diagram 3] 1 illustrates an exemplary embodiment of a power device in different views; [Figure 4] 1 illustrates a further exemplary embodiment of a power device in cross-sectional view. [Diagram 5] 1 shows a flow chart of an exemplary embodiment of a method for assembling a power device. [Figure 6] 1 illustrates a further exemplary embodiment of a power device in cross-sectional view. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0057] The exemplary embodiment of the power device 100 of Figures 1-3 comprises a carrier 2 having a top surface 20 and a bottom surface 21. Figure 1 shows the power device 100 in a plan view of the top surface 20 of the carrier 2. Figure 2 shows a cross-sectional view having a cross section through line AA' of Figure 1.

[0058] Two power semiconductor modules 1 are mounted on a top surface 20 of the carrier 2 and are thermally connected to the carrier 2. A third power semiconductor module 1 is mounted on a bottom surface 21 of the carrier 2 and is thermally connected to the carrier 2.

[0059] FIG. 3 again shows the power device 100 in a plan view on the top surface of the carrier 2, but now the power semiconductor modules 1 on the bottom surface of the carrier 2 are shown in dashed lines to show the relative arrangement between all three power semiconductor modules 1.

[0060] 3, the power semiconductor modules 1 are arranged in an overlapping configuration, such that two power semiconductor modules 1 on a top surface 20 of the carrier 2 both overlap one power semiconductor module 1 on a bottom surface 21 of the carrier 2. Also, the power semiconductor modules 1 are arranged in a row.

[0061] By arranging the power semiconductor modules 1 in an overlapping configuration, the overall length of the carrier 2 can be shortened, while still allowing the power semiconductor modules 1 to be cooled efficiently.

[0062] The power semiconductor modules 1 are fixed to the carrier 2 by fastening means 3. The fastening means 3 are, for example, clamping means. The fastening means 3 are mechanically connected to the power semiconductor modules 1 in auxiliary regions 13, i.e. in the peripheral region 13, of the power semiconductor modules 1. In each power semiconductor module 1, the peripheral region 13 in the lateral direction, i.e. in the direction parallel to the top surface 20, completely surrounds the functional region 12, i.e. in the central region 12, of the power semiconductor module 1. In Fig. 1 and Fig. 2, an imaginary boundary between the peripheral region 13 and the central region 12 is shown by a dashed line. In Fig. 3, the imaginary boundary is shown by a solid line for the power semiconductor modules on the top side and by a dashed line for the power semiconductor modules on the bottom side.

[0063] The design of each power semiconductor module 1 is as follows: the central region 12 of the power semiconductor module 1 is the region in which the power semiconductor chips 11 are arranged. There are no power semiconductor chips in the peripheral region 13. The power semiconductor chips 11 are, for example, IGBTs or diodes or JFETs or MOSFETs or thyristors. The power semiconductor chips 11 are mounted on a substrate 15 and electrically and thermally connected. The power semiconductor chips 11 are, for example, interconnected in a half-bridge configuration on the substrate 15. The substrate 15 is, for example, a DBC or DBA substrate. The substrate 15 is further mounted on a base plate 16 of the power semiconductor module 1. The base plate 16 forms the back side of the power semiconductor module 1 and comprises a plurality of cooling elements 10 in the form of cooling ribs of cooling fins protruding from the back side towards the carrier 2.

[0064] The power semiconductor chip 11 is encapsulated in an encapsulant 13, which may be a resin. For example, the semiconductor chip 11 is molded together with the encapsulant 13, for example by a transfer molding process.

[0065] The cooling elements 10 of the power semiconductor modules 1 are configured for cooling, i.e. for heat dissipation to the carrier 2. For this purpose, the carrier 2 comprises two upper openings 22 on the top side 20 and one lower opening 23 on the bottom side 21. The cooling elements 10 of the power semiconductor modules 1 on the top side 20 protrude through the upper openings 22 into the respective cavities 24 of the carrier 2, and the cooling elements 10 of the power semiconductor modules 1 on the bottom side 21 protrude through the lower openings 23 into the cavities 24 of the carrier 2. As is evident from FIG. 2, the upper openings 22 and the lower openings 23 are arranged without overlap, i.e. do not overlap when viewed in a plan view of the top side 20 of the carrier 2.

[0066] As best seen in FIG. 2, the individual cavities 24 are fluidly coupled by channel portions in the carrier 2 such that channels 25 are formed that extend through the carrier 2. The channels 25 are configured to guide a cooling fluid, such as water, through the carrier 2. The channels 25 begin at an inlet and end at an outlet. The flow direction of the cooling fluid is indicated by arrows in FIG. 2. The cooling fluid can be inserted through the inlet, can flow through the channels 25, can pass through the cooling elements 10 in the cavities 24, and then can exit the carrier 2 through the outlet. During this process, heat is transferred from the cooling elements 10 to the cooling fluid. The structure of the cooling elements 10 as pin fins or ribs further creates turbulence in the cooling fluid, which is beneficial for cooling efficiency.

[0067] Fig. 4 shows a further exemplary embodiment of a power device 100. In contrast to the exemplary embodiment shown in Figs. 1 to 3, the power semiconductor modules 1 do not comprise a cooling element on the rear side, but instead the rear side is each flat. The rear side is likewise formed by a base plate 15. For example, the power semiconductor module 1 is soldered or sintered or glued or screwed or clamped to the carrier 2, for example using thermal grease as thermal interface material.

[0068] The carrier 2 does not include any openings on its top or bottom surfaces, and the top surface 20 and bottom surface 21 are flat. However, cooling channels 25 extend through the carrier 2 as well. Heat from the power semiconductor modules 1 is transferred to the carrier 2 at the top surface 20 and bottom surface 21, respectively, and then passes through the material of the carrier 2 to the channels 25. There, it is absorbed and carried away by the cooling fluid flowing through the channels 25.

[0069] FIG. 5 shows a flow chart of an exemplary embodiment of a method for assembling a power device. For example, the power device of FIG. 1 to FIG. 3 or FIG. 4 can be manufactured by this method. In step S1, at least one power semiconductor module is attached to an upper surface of a carrier. In step S2, at least one power semiconductor module is attached to a bottom surface of the carrier. As a result, at least two power semiconductor modules are arranged in an overlapping configuration, and at least one power semiconductor module on the upper surface and at least one power semiconductor module on the bottom surface at least partially overlap each other when viewed in a plan view of the upper surface of the carrier.

[0070] In Fig. 6, a cross-sectional view of a further exemplary embodiment of a power device 100 is shown. This power device is similar to that of Figs. 1-3. However, instead of several individual cavities 24, each uniquely assigned to an upper opening 22 and a lower opening 23, the carrier 2 of Fig. 6 is a hollow body with one continuous cavity 24. All the upper openings 22 and the lower openings 23 are openings or inlets to this cavity 24, respectively. The cavity 24 is fluidly connected to the inlet and the outlet, whereby the cavity 24 is used to form a channel 25 through the carrier 2 for conducting a cooling fluid.

[0071] The embodiments shown in Figures 1-6 above represent exemplary embodiments of the power devices and methods for assembling the power devices. Therefore, they do not constitute an exhaustive list of all embodiments of the power devices and methods. The actual power devices and methods may differ from the illustrated embodiments, for example, in terms of arrangement, devices, and elements. [Explanation of symbols]

[0072] Reference sign 1 Power Semiconductor Module 2. Career 3 Fixing means 10 Cooling element 11 Power semiconductor chips 12 Functions / Central Area 13 Auxiliary / Peripheral Areas 14 Encapsulating materials 15 Substrate 16 Base plate 20 Top side 21 Bottom 22 Top opening 23 Lower opening 24 Cavity 25 Channels 100 Power Devices S1~S3 Method steps A-A' cross section.

Claims

1. A power device (100), At least two power semiconductor modules (1), A carrier (2) having a top surface (20) and an opposite bottom surface (21); Equipped with The power semiconductor module (1) is mounted on the carrier (2) and thermally connected to the carrier (2); A power device (100) in which at least two power semiconductor modules (1) are arranged in an overlapping configuration, such that at least one power semiconductor module (1) attached to the top surface (20) and at least one power semiconductor module (1) attached to the bottom surface (21) at least partially overlap each other when viewed in plan of the top surface (20).

2. The power device (100) comprises at least three power semiconductor modules (1) arranged in an overlapping configuration, 2. The power device (100) of claim 1, wherein at least two power semiconductor modules (1) attached to one of the top surface (20) and the bottom surface (21) are both configured to overlap at least one identical power semiconductor module (1) attached to the other of the top surface (20) and the bottom surface (21) when viewed in a plan view of the top surface (20).

3. Each of the power semiconductor modules (1) arranged in the overlapping configuration is provided with a plurality of cooling elements (10) on its respective rear surface, The carrier (2) comprises at least one upper opening (22) on the top surface (20) and at least one lower opening (23) on the bottom surface (21); the at least one upper opening (22) and the at least one lower opening (23) at most partially overlap when viewed in plan on the top surface (20); the cooling elements (10) of the power semiconductor modules (1) arranged in the overlapping configuration protrude into the carrier (2) through the upper opening (22) and the lower opening (23); A power device (100) according to claim 1 or 2.

4. The cooling element (10) is a cooling rib or a cooling fin. The power device (100) of claim 3.

5. The power semiconductor modules (1) arranged in the overlapping configuration each comprise a functional area (12) and an auxiliary area (13), one or more power semiconductor chips (11) and / or one or more cooling elements (10) are arranged on the functional area (12), No power semiconductor chip (11) is present in the auxiliary region (13); the auxiliary regions (13) of the power semiconductor modules (1) in the overlapping configuration at least partially overlap in a plan view of the top surface (20), and the functional regions (12) do not overlap one another in this plan view; A power device (100) according to claim 3 or 4.

6. The cooling element (11) is arranged within the functional area (12) and outside the auxiliary area (13), A power device (100) according to claim 3 or 4 in combination with claim 5.

7. the auxiliary area (13) is configured to connect the power semiconductor module (1) to the carrier (2), A power device (100) according to claim 5 or 6.

8. the carrier (2) is configured to guide a cooling fluid for cooling the power semiconductor module (1); A power device (100) according to any one of the preceding claims.

9. the carrier (2) is configured to guide the cooling fluid through the cooling elements (10) protruding through the openings (22, 23); A power device (100) according to claim 8 when dependent on claim 3.

10. At least one channel (25) is formed in the carrier (2) for guiding the cooling fluid. A power device (100) according to claim 8 or 9.

11. The power semiconductor module (1) is joined to the carrier (2). A power device (100) according to any one of the preceding claims.

12. Each of the power semiconductor modules (1) comprises at least one power semiconductor chip (11) which is one of an IGBT, a MOSFET, a diode, a thyristor, a JFET, and a HEMT. A power device (100) according to any one of the preceding claims.

13. A method of assembling a power device (100), comprising the steps of: Mounting at least one power semiconductor module (1) on a top surface (20) of a carrier (2); At least one power semiconductor module (1) is attached to a bottom surface (21) of the carrier (2) opposite the top surface (20), At least two power semiconductor modules (1) are arranged in an overlapping configuration in which at least one power semiconductor module (1) on the top surface (20) and at least one power semiconductor module (1) on the bottom surface (21) at least partially overlap each other when viewed in a plan view of the top surface (20). An assembly method comprising:

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