Semiconductor device and power amplifier

Abstract

To reduce loss of an output signal and increase output power by reducing a size of a wire synthesis unit connected to a drain of a transistor.SOLUTION: A semiconductor device includes first and second transistors disposed on both sides of a gate wire connected to an input wire connected to an input terminal, and a wire synthesis unit connected to the output of the first and second transistors. Each of the first and second transistors includes a source region and a drain region provided along a first direction having each gate electrode therebetween. The wire synthesis unit includes first and second output wires extending in the first direction over the gate electrode and a source wire on the source regions of the first and second transistors and connected to a drain wire on the drain region, a third output wire connecting the first and second output wires to each other, and a fourth output wire connecting the third output wire to an output terminal.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a power amplifier. [Background technology]

[0002] In a field effect transistor formed on a GaAs substrate or a SiC substrate, the gate width can be increased without increasing the layout size by forming a so-called multi-finger type or fishbone type gate electrode. In this case, the gain in the high frequency range is improved by disposing a shield electrode between each drain electrode and a gate transmission line that is wired from the gate pad to the gate electrode (for example, see Patent Document 1).

[0003] Also, by providing a gate pad in the center of the transistor region and directly connecting the gate electrode to the gate pad, delays in electrical signals between the gate electrodes are prevented (see, for example, Patent Document 2). Furthermore, by arranging the multi-finger type gate electrodes with a shift in the extension direction of the gate electrodes, heat dissipation is improved without widening the gap between the gate electrodes (see, for example, Patent Document 3).

[0004] Here, a fishbone-type gate electrode or a fishbone-type transistor will be explained. Fishbone means a fish bone. A fish has a backbone that connects the head and tail fin, and thin bones such as ribs that extend in opposite directions on the dorsal and ventral fin sides almost perpendicular to the backbone. A gate electrode structure in which the gate wiring corresponding to the backbone is at the center and gate electrodes corresponding to the thin bones are arranged on both sides of the gate wiring, sandwiching the gate wiring, is called a fishbone-type gate electrode. Furthermore, a structure in which source regions and drain regions are arranged on both sides of each gate electrode, each forming a transistor cell, is called a fishbone-type transistor. The gate width of a fishbone-type transistor is the sum of the widths of the gate electrodes connected to the gate wiring. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 4-125941 [Patent Document 2] Japanese Patent Application Publication No. 6-5849 [Patent Document 3] International Publication No. 2018 / 020549 Summary of the Invention [Problem to be solved by the invention]

[0006] For example, in power amplifiers that operate at high frequencies such as the millimeter wave band, it is important to improve the output power rather than the gain. In order to improve the output power, it is necessary to reduce the loss of the output signal. For example, in the transistors mounted on the power amplifier, it is necessary to minimize the wiring from the drain, where the signal is output, to the output terminal.

[0007] Therefore, an object of the present disclosure is to reduce the loss of the output signal and increase the output power by reducing the size of the wiring merge section connected to the drain, which is the output of the transistor. [Means for solving the problem]

[0008] According to one aspect of the present embodiment, a semiconductor device includes a gate wiring connected to an input wiring connected to an input terminal and extending in a first direction, a first transistor and a second transistor arranged on both sides of the gate wiring along a second direction perpendicular to the first direction, and a wiring synthesis unit connecting an output of the first transistor and an output of the second transistor to an output terminal, the first transistor and the second transistor including a plurality of gate electrodes connected to the gate wiring and extending in the second direction, a source region and a drain region provided along the first direction with each of the plurality of gate electrodes therebetween, a source wiring arranged on the source region and connected to the source region, and a drain wiring arranged on the drain region and connected to the drain region. a first dummy wiring and a second dummy wiring; the wiring synthesis unit comprises: a first output wiring extending in the first direction over at least one of the source wirings and at least one of the gate electrodes on the first transistor and connected to the drain wiring of the first transistor; a second output wiring extending in the first direction over at least one of the source wirings and at least one of the gate electrodes on the second transistor and connected to the drain wiring of the second transistor; a third output wiring connecting one end of the first output wiring in the first direction and one end of the second output wiring in the first direction to each other; and a fourth output wiring connecting the third output wiring to the output terminal. The first dummy wiring is disposed outside the first transistor and on the other end side of the first output wiring in the first direction, the second dummy wiring is disposed outside the second transistor and on the other end side of the second output wiring in the first direction, the other end of the first output wiring is extended to the outside of the first transistor and connected to the first dummy wiring, and the other end of the second output wiring is extended to the outside of the second transistor and connected to the second dummy wiring. . Effect of the Invention

[0009] According to the present disclosure, by reducing the size of the wiring merge portion connected to the drain, which is the output of the transistor, it is possible to reduce loss of the output signal and increase the output power. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a layout diagram showing an example of a circuit configuration of a semiconductor device according to a first embodiment. [Diagram 2]FIG. 2 is a perspective view showing only a main portion of the transistor of the semiconductor device of FIG. [Diagram 3] FIG. 3 is a system configuration diagram showing an example of a power amplifier in which the semiconductor device of FIG. 1 is mounted, and a communication system including the power amplifier. [Figure 4] FIG. 4 is a perspective view of another semiconductor device (comparative example) having a finger-gate type transistor structure similar to that of the semiconductor device of FIG. [Diagram 5] FIG. 5 is a layout diagram showing an example of a circuit configuration of the semiconductor device according to the second embodiment. [Figure 6] 6 is a perspective view showing only a main part of a transistor of the semiconductor device of FIG. 5. [Figure 7] FIG. 7 is a layout diagram showing an example of a circuit configuration of the semiconductor device according to the third embodiment. [Figure 8] FIG. 8 is a perspective view showing only the main part of the transistor of the semiconductor device of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] [Description of the embodiments of the present disclosure] First, the embodiments of the present disclosure will be listed and described.

[0012] [1] A semiconductor device according to an embodiment of the present disclosure includes a gate wiring connected to an input wiring that is connected to an input terminal and extends in a first direction, a first transistor and a second transistor arranged on both sides of the gate wiring along a second direction perpendicular to the first direction, and a wiring synthesis unit that connects an output of the first transistor and an output of the second transistor to an output terminal, the first transistor and the second transistor including a plurality of gate electrodes connected to the gate wiring and extending in the second direction, source regions and drain regions provided along the first direction with each of the plurality of gate electrodes therebetween, a source wiring arranged on the source region and connected to the source region, and a wiring synthesis unit arranged on the drain region. and a drain wiring connected to the drain region, and the wiring synthesis unit comprises: a first output wiring extending in the first direction over at least one of the source wirings and at least one of the gate electrodes over the first transistor and connected to the drain wiring of the first transistor; a second output wiring extending in the first direction over at least one of the source wirings and at least one of the gate electrodes over the second transistor and connected to the drain wiring of the second transistor; a third output wiring connecting one end of the first direction of the first output wiring and one end of the second output wiring in the first direction to each other; and a fourth output wiring connecting the third output wiring to the output terminal.

[0013] In this semiconductor device, the first and second output wirings of the wiring synthesis section are extended over the first and second transistors, respectively, across the source wiring and gate electrode, and are connected to the drain regions of the first and second transistors, respectively, via the drain wiring. This makes it possible to shorten the electrical length of the third output wiring that connects one end of the first output wiring to one end of the second output wiring. As a result, it is possible to reduce the loss of the output signal from the semiconductor device, and to increase the output power of the semiconductor device. In other words, by making the wiring synthesis section connected to the drain, which is the output of the transistor, smaller, it is possible to reduce the loss of the output signal and increase the output power. In addition, it is possible to reduce the circuit size of the matching circuit connected to the output terminal, and to reduce the size of the semiconductor device.

[0014] [2] In the above [1], a first dummy wiring is disposed outside the first transistor and on the other end side of the first output wiring in the first direction, and a second dummy wiring is disposed outside the second transistor and on the other end side of the second output wiring in the first direction, and the other end of the first output wiring may be extended to the outside of the first transistor and connected to the first dummy wiring, and the other end of the second output wiring may be extended to the outside of the second transistor and connected to the second dummy wiring. By connecting the ends of the first and second output wirings opposite to the connection parts with the third output wiring to the dummy wiring, respectively, it is possible to compensate for the symmetry of the parasitic capacitance due to the first and second output wirings connected to each drain region via each drain wiring. This compensation circuit equalizes the impedance of each drain electrode, which exists in a plurality of types such as a multi-finger type or a fishbone type, and reduces impedance mismatch. As a result, the proposed transistor shape can improve the output power and gain.

[0015] [3] In the above [1], the drain regions may be formed at the ends of the first and second transistors opposite to the third output wiring. In this case, it is possible to compensate for the symmetry of the parasitic capacitances of the first and second output wirings connected to the drain regions via the drain wirings without connecting dummy wirings to the first and second output wirings, thereby improving high frequency characteristics.

[0016] [4] In any of the above [1] to [3], the source wiring and the drain wiring may be formed using a first metal wiring layer, and the first output wiring and the second output wiring may have an air bridge wiring structure formed using a second metal wiring layer that is an upper layer of the first metal wiring layer. In this case, since no insulating film is provided under the first output wiring and the second output wiring, the wiring load can be reduced and high frequency characteristics can be improved.

[0017] [5] In any of the above [1] to [4], the first output wiring may be connected to a center portion of the drain wiring of the first transistor in the second direction, and the second output wiring may be connected to a center portion of the drain wiring of the second transistor in the second direction. This allows the third output wiring to be shorter and the electrical length to be shorter than when the first and second output wirings are arranged on the opposite side of the gate wirings of the first and second transistors. As a result, loss of the output signal from the semiconductor device can be reduced, and the output power of the semiconductor device can be increased.

[0018] [6] A power amplifier according to one embodiment of the present disclosure is equipped with any one of the semiconductor devices described above in [1] to [5]. By mounting any one of the semiconductor devices in a power amplifier, for example, it is possible to increase the communication distance of a radio signal transmitted from a transmitter in which the power amplifier is mounted. As a result, it is possible to increase the distance between the transmitter and the receiver.

[0019] [Details of the embodiment of the present disclosure] A specific example of the semiconductor device of the present disclosure will be described below with reference to the drawings. Note that the present embodiment is not limited to the following description. For example, the number of gate electrodes provided in one transistor region TRA is at least two, and is not limited to the number shown in each drawing.

[0020] [First embodiment] [Semiconductor Device Layout] Fig. 1 is a layout diagram showing an example of a circuit configuration of a semiconductor device according to the first embodiment. For example, the semiconductor device 100 shown in Fig. 1 is mounted on a power amplifier of a millimeter wave band (tens of GHz to hundreds of GHz) and used to amplify the power of a high-frequency signal.

[0021] The semiconductor device 100 includes transistors TR1 and TR2 that amplify a high-frequency input signal supplied to a common input terminal IN and output the amplified high-frequency output signal from a common output terminal OUT. The transistors TR1 and TR2 are arranged side by side along a direction DIR2. For example, each of the transistors TR1 and TR2 is a gallium nitride high electron mobility transistor (GaN HEMT). Each of the transistors TR1 and TR2 is formed in a transistor region TRA indicated by a dotted rectangle. Although not particularly limited, for example, the gate length of each of the transistors TR1 and TR2 is 100 nm (nanometers), and the gate width of each of the transistors TR1 and TR2 is 60 μm (microns).

[0022] The transistor TR1 includes four gate electrodes G1 extending in a direction DIR2, and source regions S1 and drain regions D1 alternately provided in each gate electrode G1 along a direction DIR1 perpendicular to the direction DIR2. The direction DIR1 is an example of a first direction, and the direction DIR2 is an example of a second direction. The gate electrodes G1 are formed using a first metal wiring layer M1. In the example shown in FIG. 1, in a transistor region TRA in which the transistor TR1 is formed, source regions S1 are formed on both ends of the direction DIR1. The transistor TR1 has three source regions S1 and two drain regions D1 alternately provided.

[0023] A ground wiring GND formed using a first metal wiring layer M1 is directly connected to the source region S1 on the source region S1. The ground wiring GND formed on the source region S1 is an example of a source wiring and a source electrode. A drain wiring (drain electrode) WD1 formed using the first metal wiring layer M1 is directly connected to the drain region D1. The first metal wiring layer M1 is the metal wiring layer closest to the semiconductor substrate on which the semiconductor device 100 is formed.

[0024] The ground wiring GND formed on the source region S1 is connected at both ends in the direction DIR2 to the ground wiring GND extending in the direction DIR1. The ground wiring GND extending in the direction DIR1 is formed using a second metal wiring layer M2. The second metal wiring layer M2 is a metal wiring layer provided on the first metal wiring layer M1 in the semiconductor device 100.

[0025] The drain wiring WD1 formed on the drain region D1, directly connected to the drain region D1, and extended in the direction DIR2 is connected to the output wiring WO1 extended in the direction DIR1. The output wiring WO1 is formed using the second metal wiring layer M2 and is connected to the center of each drain wiring WD1 in the direction DIR2. The output wiring WO1 has a so-called air bridge wiring structure, and is provided above the gate electrode G1 and above the ground wiring GND provided on the source region S1 without an interlayer insulating film. One end of the output wiring WO1 on the output terminal OUT side is connected to one end of the output wiring WO3 formed using the first metal wiring layer M1.

[0026] The transistor TR2 includes four gate electrodes G2 extending in the direction DIR2, and source regions S2 and drain regions D2 alternately provided along the direction DIR1 in each gate electrode G2. The gate electrodes G2 are formed using a first metal wiring layer M1. As with the transistor TR1, in another transistor region TRA in which the transistor TR2 is formed, the source regions S2 are formed on both ends in the direction DIR1. The transistor TR2 has three source regions S2 and two drain regions D2 alternately provided.

[0027] A ground wiring GND formed using the first metal wiring layer M1 is directly connected to the source region S2 on the source region S2. The ground wiring GND formed on the source region S2 is an example of a source wiring and a source electrode. A drain wiring (drain electrode) WD2 formed using the first metal wiring layer M1 is directly connected to the drain region D2. The ground wiring GND formed on the source region S2 is connected to ground wiring GND extending in the direction DIR1 on both ends of the direction DIR2. The ground wiring GND extending in the direction DIR1 is formed using the second metal wiring layer M2.

[0028] The drain wiring WD2 formed on the drain region D2, directly connected to the drain region D2, and extending in the direction DIR2 is connected to the output wiring WO2 extending in the direction DIR1. The output wiring WO2 is formed using the second metal wiring layer M2 and is connected to the center of each drain wiring WD2 in the direction DIR2. The output wiring WO2 has an air bridge wiring structure, similar to the output wiring WO1, and is provided above the gate electrode G2 and above the ground wiring GND provided on the source region S2 without an interlayer insulating film. One end of the output wiring WO2 on the output terminal OUT side is connected to the other end of the output wiring WO3. As a result, the output wirings WO1 and WO2 are connected to each other via the output wiring WO3.

[0029] The output wiring WO3 is electrically connected to the output terminal OUT via an output wiring WO4 formed using the first metal wiring layer M1. The output wirings WO3 and WO4, indicated by dashed lines, function as a wiring synthesis section WOUT that synthesizes the output signals output from the drain regions D1 and D2 of the transistors TR1 and TR2, respectively.

[0030] The gate electrodes G1 and G2 are connected to each other via a gate wiring WG. The gate wiring WG is electrically connected to an input terminal IN via an input wiring WI1. That is, the semiconductor device 100 constitutes a fishbone transistor. For example, the gate wiring WG and the input wiring WI1 are formed using a first metal wiring layer M1. The gate wiring WG and the input wiring WI1 may be integrally formed.

[0031] By connecting the output wiring WO1 to the center of each drain wiring WD1 in the direction DIR2 and connecting the output wiring WO2 to the center of each drain wiring WD2 in the direction DIR2, the length of the output wiring WO3 in the direction DIR2 can be minimized. This makes it possible to minimize the electrical length of the output wiring WO3 in the direction DIR2. In addition, it is possible to reduce the phase shift of the output signals transmitted to the output wirings WO1 and WO2.

[0032] As a result, it is possible to reduce loss of the output signal from the semiconductor device 100 and increase the output power of the semiconductor device 100. In other words, by reducing the size of the wiring composite portion WOUT connected to the drains, which are the outputs of the transistors TR1 and TR2, it is possible to reduce output signal loss and increase output power.

[0033] Furthermore, the wiring length of the wiring combination section WOUT can be shortened, and the output wirings WO1 to WO4 are laid out symmetrically with respect to the direction DIR1, thereby minimizing the phase shift of the high-frequency output signals output from the drain regions D1 and D2, respectively.

[0034] [Extracting the signal from the drain to the output terminal] FIG. 2 is a perspective view showing only a main part of the transistor TR1 of the semiconductor device 100 of FIG. 1. In particular, the perspective view shows an outline of the output wiring WO1, which is the second metal wiring layer M2 connected from the drain wiring WD1 on the drain region D1 to one end of the output wiring WO3, and an outline of the GND wiring, which is the second metal wiring layer M2 connecting the ground wirings GND on the multiple source regions S1. As described in FIG. 1, each drain region D1 is connected to the output wiring WO3 via the output wiring WO1 having an air bridge wiring structure. Therefore, an air gap is formed between the output wiring WO1 and the gate electrode G1 and ground wiring GND facing the output wiring WO1. Similarly, an air gap is formed below the GND wiring, which is the second metal wiring layer M2.

[0035] This allows the center of each drain wiring WD1 to be linearly connected to the output wiring WO3. Therefore, the wiring resistance and load capacitance of the output wirings WO1 and WO3 through which the output signal of the transistor TR1 is transmitted can be minimized, and degradation of the high-frequency characteristics of the output signal can be prevented. The structure of the output wiring WO2 connected to the drain wiring WD2 of the transistor TR2 in Fig. 1 is similar to the structure of the output wiring WO1 shown in Fig. 2, and the same effect can be obtained.

[0036] For example, the semiconductor device 100 has a gallium nitride (GaN) layer, an aluminum gallium nitride (AlGaN) layer, and a gallium nitride layer stacked on a silicon carbide (SiC) substrate. A gold (Au) layer is formed on the back surface of the silicon carbide substrate as a ground layer GND.

[0037] On the topmost gallium nitride layer, gate electrodes G1 and G2, a ground wiring GND, and drain wiring WD1 and WD2 are formed using a first metal wiring layer M1. For example, the gate electrodes G1 and G2, the ground wiring GND, and the drain wiring WD1 and WD2 are formed of gold (Au).

[0038] The gate electrodes G1 and G2 are connected to the gallium nitride layer by Schottky contact. The gate electrodes G1 and G2 may have a recessed structure. In the transistor region TRA, the ground wiring GND on the source regions S1 and S2 and the drain electrodes WD1 and WD2 on the drain regions D1 and D2 are in ohmic contact with the gallium nitride layer.

[0039] [Communication system equipped with semiconductor device] Fig. 3 is a system configuration diagram showing an example of a power amplifier equipped with the semiconductor device 100 of Fig. 1 and a communication system SYS including the power amplifier. The communication system SYS has a transmitter 10 that wirelessly transmits a high-frequency signal, and a receiver 20 that receives the high-frequency signal transmitted from the transmitter 10. For example, the transmitter 10 and the receiver 20 are installed in a mobile phone base station.

[0040] The transmitter 10 has a variable gain amplifier 12, a power amplifier 14, and a transmitting antenna 16. The receiver 20 has a receiving antenna 22 and a receiving circuit (not shown). The variable gain amplifier generates an output signal by changing the gain of an input signal in response to a control voltage, for example, and outputs the generated output signal to the power amplifier 14.

[0041] The power amplifier 14 amplifies the power of the signal received from the variable gain amplifier 12 and outputs it to a transmitting antenna 16. The transmitting antenna 16 converts the electrical signal received from the power amplifier 14 into radio waves and transmits them to a receiver 20. The receiver 20 receives the radio waves from the transmitter 10 at a receiving antenna 22 and performs signal processing.

[0042] In mobile phone base stations, the greater the output power of the signal transmitted by the transmitter 10, the longer the communication distance between the base stations can be. By increasing the communication distance, the intervals between the base stations can be increased. For this reason, it is important to improve the output power of the semiconductor device 100.

[0043] [Extracting a signal from the drain of another semiconductor device to an output terminal] Fig. 4 is a perspective view of another semiconductor device (comparative example) having a finger-gate type transistor structure similar to that of the semiconductor device 100 of Fig. 1. As in Fig. 2, this is a perspective view of only the main portion corresponding to the transistor TR1. In Fig. 4, the output wiring WO1 is not an air-bridge wiring structure, but is formed using the first metal wiring layer M1 like the gate wiring WG. Therefore, the output wiring WO1 is formed at a position that allows it to bypass the ground wiring GND formed on the source region S1.

[0044] Since the output wiring WO1 is formed by detouring the ground wiring GND, the electrical length of the output wiring WO3 becomes longer than that in Fig. 2, narrowing the bandwidth of the output signal due to unnecessary reactance component L. In addition, since the output wiring WO3 becomes longer, the circuit size of the matching circuit connected to the output terminal OUT becomes larger.

[0045] As described above, in this embodiment, the output wirings WO1 and WO2 have an air bridge wiring structure, are formed across the ground wiring GND and the gate electrodes G1 and G2 on the source region S1, and are connected to the output wiring WO3. For example, the output wiring WO1 is connected to the center of each drain wiring WD1 in the direction DIR2, and the output wiring WO2 is connected to the center of each drain wiring WD2 in the direction DIR2.

[0046] This makes it possible to minimize the electrical length of the output wiring WO3 in the direction DIR2. Also, it is possible to reduce the phase shift of the output signals transmitted to the output wirings WO1 and WO2. As a result, it is possible to reduce the impedance and loss of the output signal from the semiconductor device 100, and it is possible to increase the output power of the semiconductor device 100. Also, by reducing the impedance, it is possible to reduce the circuit size of a matching circuit (not shown) connected to the output terminal OUT of the semiconductor device 100, and it is possible to reduce the size of the semiconductor device 100. Furthermore, since the output wirings WO1 and WO2 have an air bridge wiring structure, it is possible to reduce the wiring load and improve the high frequency characteristics.

[0047] By mounting the semiconductor device 100 in the power amplifier 14 of the transmitter 10 of the communication system SYS, the communication distance to the receiver 20 can be increased. For example, when the transmitter 10 and the receiver 20 are mounted in mobile phone base stations, respectively, the communication distance between the base stations can be increased. As a result, the intervals between the base stations can be increased, and the equipment costs of the communication system SYS can be reduced.

[0048] Second Embodiment [Semiconductor Device Layout] Fig. 5 is a layout diagram showing an example of a circuit configuration of a semiconductor device according to a second embodiment. The same elements as those in Fig. 1 are given the same reference numerals, and detailed description thereof will be omitted. The semiconductor device 102 shown in Fig. 5 has a similar structure to the semiconductor device 100 in Fig. 1, except that the output wirings WO1 and WO2 are different from the output wirings WO1 and WO2 in Fig. 1.

[0049] The end of the output wiring WO1 opposite to the output wiring WO3 in the direction DIR1 is extended to the outside of the transistor region TRA and is connected to a dummy wiring DMY1 arranged outside the transistor region TRA. The end of the output wiring WO2 opposite to the output wiring WO3 in the direction DIR1 is extended to the outside of another transistor region TRA and is connected to a dummy wiring DMY2 arranged outside the other transistor region TRA.

[0050] For example, the dummy wirings DMY1 and DMY2 are formed using the first metal wiring layer M1. The dummy wiring DMY1 is electrically connected to only the output wiring WO1, and the dummy wiring DMY2 is electrically connected to only the output wiring WO2.

[0051] For example, the distance between the drain wiring WD1 and the dummy wiring DMY1 on the left side of Fig. 5 is equal to the distance between the two drain wirings WD1 and the distance between the drain wiring WD1 and the output wiring WO3 on the right side of Fig. 5. The distance between the drain wiring WD2 and the dummy wiring DMY2 on the left side of Fig. 5 is equal to the distance between the two drain wirings WD2 and the distance between the drain wiring WD2 and the output wiring WO3 on the right side of Fig. 5. Therefore, the output wiring WO1 has symmetry with respect to each drain wiring WD1, and the output wiring WO2 has symmetry with respect to each drain wiring WD2.

[0052] [Output wiring symmetry] 6 is a perspective view showing only a main part of the transistor TR1 of the semiconductor device 102 of FIG. 5. In particular, it is a perspective view showing an outline of the output wiring WO1 connected to the drain wiring WD1 of the transistor TR1. Each drain region D1 is connected to the output wiring WO3 via the output wiring WO1 having an air bridge wiring structure. In this case, one end of the output wiring WO1 is connected to the output wiring WO3, and the other end of the output wiring WO1 is connected to the dummy wiring DMY1.

[0053] For this reason, it is possible to provide symmetry to the partial wiring of the output wiring WO1 that extends to both sides of each drain wiring WD1 in the direction DIR1 and is connected to the adjacent drain wiring WD1 and the output wiring WO3 (or the dummy wiring DMY1). It is also possible to provide symmetry to the partial wiring of the output wiring WO2 that extends to both sides of each drain wiring WD2 in the direction DIR2, similar to the output wiring WO1.

[0054] As a result, the symmetry of the parasitic capacitance due to the output wiring WO1 connected to each drain region D1 via the drain wiring WD1 can be compensated for, improving the high frequency characteristics. Also, the symmetry of the parasitic capacitance due to the output wiring WO2 connected to each drain region D2 via the drain wiring WD2 can be compensated for, improving the high frequency characteristics.

[0055] In addition, when the number of gate electrodes G1 is an odd number (e.g., three), and the gate electrode G1 at the leftmost position in FIG. 6 and the source region S1 are not formed, the dummy wiring DMY1 is also disposed at the position shown in FIG. 6. The output wiring WO1 is connected to the dummy wiring DMY1. The same is true when the number of gate electrodes G2 of the transistor TR2 is an odd number. This makes it possible to compensate for the symmetry of the parasitic capacitances due to the output wirings WO1 and WO2, regardless of the number of gate electrodes G1 and G2.

[0056] As described above, this embodiment can also provide the same effects as the above-mentioned embodiment. Furthermore, in this embodiment, the ends of the output wirings WO1 and WO2 opposite to the connection portion with the output wiring WO3 are connected to the dummy wirings DMY1 and DMY2, respectively. This makes it possible to compensate for the symmetry of the parasitic capacitance caused by the output wirings WO1 and WO2 connected to the drain regions D1 and D2 via the drain wirings WD1 and WD2, and improve the high-frequency characteristics.

[0057] Third embodiment [Semiconductor Device Layout] Fig. 7 is a layout diagram showing an example of a circuit configuration of a semiconductor device according to a third embodiment. The same elements as those in Fig. 1 are given the same reference numerals, and detailed description will be omitted. In a semiconductor device 104 shown in Fig. 7, the order of the source region S1 and the drain region D1 in a transistor TR1 differs from that in Fig. 1. Also, the order of the source region S2 and the drain region D2 in a transistor TR2 differs from that in Fig. 1. Note that Fig. 7 shows a case where the number of gate electrodes G1 and the number of gate electrodes G2 are each even numbers.

[0058] In the transistor TR1, three drain regions D1 are formed at both ends and the center in the direction DIR1, and a source region S1 is formed between each two drain regions D1. A drain wiring WD1 arranged on each drain region D1 is connected to each drain region D1. A ground wiring GND arranged on each source region S1 is connected to each source region S1. The ground wiring GND on the source region S1 is connected to a ground wiring GND arranged on the opposite side to the transistor TR2 outside the transistor region TRA.

[0059] In the transistor TR2, three drain regions D2 are formed at both ends and the center in the direction DIR1, and a source region S1 is formed between each two drain regions D2. A drain wiring WD2 arranged on each drain region D2 is connected to each drain region D2. A ground wiring GND arranged on each source region S2 is connected to each source region S2. The ground wiring GND on the source region S2 is connected to a ground wiring GND arranged on the opposite side to the transistor TR1 outside the other transistor region TRA.

[0060] In this embodiment, the output wiring WO1 is connected to drain wiring WD1 on the drain region D1 located at both ends and the center in the direction DIR1. The output wiring WO1 is connected to the output wiring WO3 via the drain wiring WD1 closest to the output wiring WO3. The output wiring WO2 is connected to drain wiring WD2 on the drain region D2 located at both ends and the center in the direction DIR1. The output wiring WO2 is connected to the output wiring WO3 via the drain wiring WD2 closest to the output wiring WO3.

[0061] [Output wiring symmetry] 8 is a perspective view showing only a main part of the transistor TR1 of the semiconductor device 104 of FIG. 7. In particular, it is a perspective view showing an outline of the output wiring WO1 connected to the drain wiring WD1. As shown in FIG. 8, when the number of gate electrodes G1 is an even number and the drain regions D1 are formed on both ends of the direction DIR1, it is possible to compensate for the symmetry of the parasitic capacitance due to the output wiring WO1 connected to the drain region D1 without forming the dummy wiring DMY1 shown in FIG. 6. Similarly, the output wiring WO2 of the transistor TR2 can compensate for the symmetry of the parasitic capacitance.

[0062] When there are three gate electrodes G1 and the leftmost gate electrode G1 and drain region D1 in FIG. 8 are not formed, a dummy wiring may be formed in place of the drain wiring WD1 located at the leftmost position in FIG.

[0063] As described above, this embodiment can also provide the same effects as the above-mentioned embodiment. Furthermore, this embodiment can compensate for the symmetry of the parasitic capacitance due to the output wirings WO1 and WO2 connected to the drain regions D1 and D2 without forming the dummy wirings DMY1 and DMY2 shown in FIG. 6, and can improve the high frequency characteristics of the output signal.

[0064] Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above embodiments. Various changes, modifications, substitutions, additions, deletions, and combinations are possible within the scope of the claims. These naturally fall within the technical scope of the present disclosure. [Explanation of symbols]

[0065] 10 Transmitter 12 Variable Gain Amplifier 14 Power Amplifier 16 Transmitting Antennas 20 Receiver 22 Antenna 100, 102, 104 Semiconductor device D1, D2 drain regions DIR1, DIR2 direction DMY1, DMY2 dummy wiring G1, G2 gate electrodes GND Ground wiring L1 Electrical length M1 1st metal wiring layer M2 2nd metal wiring layer OUT Output terminal S1, S2 source regions SYS Communication System TR1, TR2 transistors TRA Transistor area WD1, WD2 drain wiring WI1 input wiring WO1, WO2, WO3, WO4 output wiring WOUT wiring synthesis section

Claims

1. a gate wiring connected to an input wiring connected to an input terminal and extending in a first direction, a first transistor and a second transistor disposed on both sides of the gate wiring along a second direction perpendicular to the first direction, and a wiring synthesis section connecting an output of the first transistor and an output of the second transistor to an output terminal, The first transistor and the second transistor a plurality of gate electrodes connected to the gate wiring and extending in the second direction; and a source region and a drain region provided along the first direction with each of the plurality of gate electrodes interposed therebetween; a source wiring disposed on the source region and connected to the source region; a drain wiring disposed on the drain region and connected to the drain region; a first dummy wiring and a second dummy wiring; Equipped with The wiring synthesis unit includes: a first output wiring extending in the first direction over at least one of the source wirings and at least one of the gate electrodes on the first transistor and connected to the drain wiring of the first transistor; a second output wiring extending in the first direction over at least one of the source wirings and at least one of the gate electrodes on the second transistor and connected to the drain wiring of the second transistor; a third output wiring that connects one end of the first output wiring in the first direction and one end of the second output wiring in the first direction to each other; a fourth output wiring that connects the third output wiring to the output terminal; Equipped with the first dummy wiring is disposed outside the first transistor and on the other end side of the first output wiring in the first direction; the second dummy wiring is disposed outside the second transistor and on the other end side of the second output wiring in the first direction; the other end of the first output wiring is extended to the outside of the first transistor and connected to the first dummy wiring; The other end of the second output wiring is extended to the outside of the second transistor and is connected to the second dummy wiring. Semiconductor device.

2. The drain region is formed at the end of the first transistor and the second transistor opposite to the third output wiring. The semiconductor device according to claim 1 .

3. the source wiring and the drain wiring are formed using a first metal wiring layer; The first output wiring and the second output wiring have an air bridge wiring structure formed using a second metal wiring layer which is an upper layer of the first metal wiring layer.

3. The semiconductor device according to claim 1 or 2.

4. the first output wiring is connected to a central portion of the drain wiring of the first transistor in the second direction; The second output wiring is connected to a center portion of the drain wiring of the second transistor in the second direction. The semiconductor device according to claim 1 .

5. 5. A power amplifier comprising the semiconductor device according to claim 1.

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