Semiconductor Device

Abstract

To provide a semiconductor device capable of reducing leakage current while reducing switching loss.SOLUTION: The semiconductor device includes: an IGBT region 11 having an IGBT element; and an FWD region 12 having an FWD element, which are formed on a common semiconductor substrate 30. A barrier region 36 and a first base layer 32a has the peak concentration at a predetermined position of the semiconductor substrate 30 in the thickness direction. Defining the peak concentration of the barrier region 36 as y[×1.0×1016 / cm3], and the peak concentration of the first base layer 32a as x[×10×1017 / cm3], the semiconductor device has the configuration that satisfies y≤1.0429x2-2.4371x+1.48.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a semiconductor device in which an insulated gate bipolar transistor (hereinafter referred to as IGBT) element having an insulated gate structure and a free wheel diode (hereinafter referred to as FWD) element are formed on a common semiconductor substrate. [Background technology]

[0002] Conventionally, in a semiconductor device having an IGBT region and an FWD region, a semiconductor device that reduces the switching loss of the FWD element has been proposed (see, for example, Patent Document 1). - The semiconductor device has a semiconductor substrate constituting a type drift layer, and a base layer is formed on the drift layer. In the IGBT region and the FWD region, a plurality of trenches are formed so as to penetrate the base layer, and a gate insulating film is formed in each trench so as to cover the wall surface, and a gate electrode is formed on the gate insulating film. In the IGBT region, N + An emitter region of a type is formed on the semiconductor substrate, and an upper electrode is formed on one surface of the semiconductor substrate facing the base layer, the upper electrode being electrically connected to the base layer and the emitter region.

[0003] A P-type collector layer and an N-type cathode layer are formed on the other surface of the semiconductor substrate opposite to the one surface, and a lower electrode electrically connected to the collector layer and the cathode layer is formed. In the semiconductor device, the region on the other surface of the semiconductor substrate where the collector layer is formed is an IGBT region, and the region where the cathode layer is formed is an FWD region.

[0004] In addition, an N-type barrier region is formed in the base layer so as to divide the base layer along the thickness direction of the semiconductor substrate. In addition, a pillar region is formed in the base layer so as to reach the barrier region from one surface of the semiconductor substrate, and the pillar region is also connected to the upper electrode. The pillar regions are formed between adjacent trenches, respectively, and are formed over the entire IGBT region and the FWD region.

[0005] In such a semiconductor device, the barrier region and pillar region are formed, so that the injection of holes is suppressed when the FWD region operates as a diode. This makes it possible to reduce the recovery current and the recovery time, thereby reducing switching loss. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2016-225560 A Summary of the Invention [Problem to be solved by the invention]

[0007] However, in the semiconductor device as described above, since the pillar region is connected to the upper electrode, there is a concern about leakage current through the pillar region and the barrier region.

[0008] In view of the above, an object of the present invention is to provide a semiconductor device capable of reducing leakage current while reducing switching loss. [Means for solving the problem]

[0009] In claim 1 for achieving the above object, there is provided a semiconductor device in which an IGBT region (11) having an IGBT element and an FWD region (12) having an FWD element are formed on a common semiconductor substrate (30), the semiconductor substrate including: a drift layer (31) of a first conductivity type; a base layer (32) of a second conductivity type formed on the drift layer; a collector layer (43) of the second conductivity type formed on the IGBT region on the side opposite to the base layer side of the drift layer; and a cathode layer (44) of the first conductivity type formed on the FWD region on the side opposite to the base layer side of the drift layer; The semiconductor substrate includes a first conductive type barrier region (36) that divides the first conductive type barrier region (36) into a second base layer (32b) on one side of the plate, a pillar region (39) that is formed in the base layer in the IGBT region, is connected to the barrier region, and is exposed from one side of the semiconductor substrate, a trench gate structure having a gate insulating film (34) formed on a wall surface of a trench (33) that penetrates the base layer and the barrier region to reach the drift layer in the IGBT region, and a gate electrode (35) formed on the gate insulating film, an emitter region (37) of the first conductive type formed in a surface layer portion of the base layer and in contact with the trench, a first electrode (41) that is disposed on one side of the semiconductor substrate and is electrically connected to the base layer, the pillar region, and the emitter region, and a second electrode (45) that is disposed on the other side of the semiconductor substrate and is electrically connected to the collector layer and the cathode layer. The barrier region and the first base layer are configured to have a peak concentration at a predetermined position in the thickness direction of the semiconductor substrate, and the peak concentration of the barrier region is expressed as y[×1.0×10 16 / cm 3 ], and the peak concentration of the first base layer is x[×10×10 17 / cm 3 ], then y≦1.0429x 2 The configuration satisfies -2.4371x+1.48. The peak concentration of the first base layer is x, which is equal to or greater than 1. .

[0010] According to this, since the barrier region and the pillar region are formed in the IGBT region, the injection of holes is suppressed in the IGBT region when the FWD element operates as a diode, and therefore the switching loss can be reduced.

[0011] In addition, in this semiconductor device, the first base layer and the barrier region are configured to satisfy the above formula, which makes it possible to suppress an increase in leakage current caused by the formation of the pillar region and the barrier region.

[0012] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and specific components described in the embodiments described below. [Brief description of the drawings]

[0013] [Figure 1] 1 is a plan view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view taken along line II-II in FIG. [Diagram 3] FIG. 2 is a cross-sectional view taken along line III-III in FIG. [Figure 4A] 4 is a diagram showing the positional relationship of an emitter region, a contact region, and a pillar region between adjacent trenches in a first region. FIG. [Figure 4B] 13 is a diagram showing the positional relationship of emitter regions and contact regions between adjacent trenches in the second region. FIG. [Figure 4C] 11 is a diagram showing the arrangement relationship of the base layer and the contact region between adjacent trenches in the FWD region. FIG. [Diagram 5] FIG. 2 is a perspective view of the vicinity of a trench in a first region. [Figure 6] FIG. 13 is a diagram showing the relationship between the peak concentration of the barrier region, the gate voltage, and the collector current when the peak concentration of the first base layer is 2.0×10 17 / cm 3 . [Figure 7]FIG. 13 is a graph showing the relationship between the peak concentration of the barrier region, the gate voltage, and the collector current when the peak concentration of the first base layer is 5.0×10 17 / cm 3 . [Figure 8] FIG. 13 is a diagram showing the relationship between the peak concentration of the first base layer and the peak concentration of the barrier region, and the leakage current. [Figure 9] FIG. 13 is a diagram showing the relationship between the peak concentration of the first base layer and the peak concentration of the barrier region, and the on-voltage. [Figure 10] FIG. 13 is a diagram showing the relationship between the peak concentration of the first base layer and the peak concentration of the barrier region, and the forward current flowing through the IGBT region. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0015] (First embodiment) DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment will be described with reference to the drawings. The semiconductor device of the present embodiment is suitable for use as a power switching element used in power supply circuits such as inverters and DC / DC converters.

[0016] As shown in FIG. 1, the semiconductor device has a cell region 10 and an outer peripheral region 20 surrounding the cell region 10. The semiconductor device of this embodiment has two cell regions 10. In each cell region 10, an IGBT region 11 that functions as an IGBT element and an FWD region 12 that is adjacent to the IGBT region 11 and functions as an FWD element are formed. That is, the semiconductor device of this embodiment is an RC (abbreviation of Reverse Conducting)-IGBT in which the IGBT region 11 and the FWD region 12 are formed in a common semiconductor substrate 30 to be described later. Note that, as will be described later in detail, in this embodiment, a portion on a collector layer 43 located on the other surface 30b of the semiconductor substrate 30 is the IGBT region 11, and a portion on a cathode layer 44 located on the other surface 30b of the semiconductor substrate 30 is the FWD region 12.

[0017] In this embodiment, the IGBT regions 11 and the FWD regions 12 are alternately formed along one direction in each cell region 10. That is, the IGBT regions 11 and the FWD regions 12 are alternately formed along one direction in the surface direction of the semiconductor substrate 30 described later. Specifically, the IGBT regions 11 and the FWD regions 12 are rectangular regions each having a longitudinal direction, and are alternately formed along a direction intersecting the longitudinal direction. The IGBT regions 11 and the FWD regions 12 are alternately arranged such that the IGBT regions 11 are located at both ends in the arrangement direction.

[0018] 1, the IGBT region 11 and the FWD region 12 are rectangular with their longitudinal directions extending in the left-right direction of the page, and are alternately formed along the up-down direction of the page. A specific configuration of the semiconductor device of this embodiment will be described below.

[0019] The semiconductor device is, as shown in Figs. -The semiconductor substrate 30 includes a P-type drift layer 31. A P-type base layer 32 is formed on the drift layer 31. Hereinafter, the surface of the semiconductor substrate 30 on the base layer 32 side is also referred to as one surface 30a, and the surface of the semiconductor substrate 30 opposite to the one surface 30a is also referred to as the other surface 30b.

[0020] A plurality of trenches 33 are formed in the semiconductor substrate 30 so as to penetrate the base layer 32 from the one surface 30a side to reach the drift layer 31. As a result, the base layer 32 is separated into a plurality of pieces by the trenches 33. In this embodiment, the plurality of trenches 33 are formed in the IGBT region 11 and the FWD region 12, respectively. In this embodiment, the plurality of trenches 33 are formed in a stripe shape with the longitudinal direction being a direction intersecting the arrangement direction of the IGBT region 11 and the FWD region 12 (i.e., the left-right direction on the paper in FIG. 1). The interval between adjacent trenches 33 (i.e., the pitch interval) is, for example, about 2 μm.

[0021] Each trench 33 is filled with a gate insulating film 34 formed so as to cover the wall surface of each trench 33, and a gate electrode 35 made of polysilicon or the like formed on this gate insulating film 34. This forms a trench gate structure.

[0022] The gate electrode 35 disposed in the trench 33 formed in the IGBT region 11 is connected to a gate pad or the like formed in the peripheral region 20 via a gate wiring (not shown). The gate pad is connected to a drive circuit via a resistor (not shown). A predetermined pulse-like gate voltage is applied to the gate electrode 35. The gate electrode 35 disposed in the trench 33 formed in the FWD region 12 is electrically connected to an upper electrode 41 (to be described later) and is maintained at a predetermined potential.

[0023] An N-type barrier region 36 having a higher impurity concentration than the drift layer 31 is formed in the base layer 32 so as to divide the base layer 32 in the thickness direction of the semiconductor substrate 30. Hereinafter, the portion of the base layer 32 on the drift layer 31 side is also referred to as a first base layer 32a, and the portion of the base layer 32 on the one surface 30a side of the semiconductor substrate 30 is also referred to as a second base layer 32b.

[0024] Here, a region of the IGBT region 11 on the FWD region 12 side is defined as the first region 11a, and a region of the IGBT region 11 different from the first region 11a is defined as the second region 11b. In this embodiment, since the IGBT region 11 and the FWD region 12 are arranged as described above, in the IGBT region 11 in the portion sandwiched between the FWD regions 12, the second region 11b is configured to be sandwiched between the first regions 11a. In addition, in the IGBT region 11 located at both ends in the arrangement direction of the IGBT region 11 and the FWD region 12, the entire region on the end side in the arrangement direction is defined as the second region 11b. The range of the first region 11a is, for example, between the boundary between the IGBT region 11 and the FWD region 12 and a portion separated from the FWD region 12 by the thickness of the semiconductor substrate 30.

[0025] As shown in FIGS. 4A and 4B, the surface layer of the base layer 32 is made of N + The emitter region 37 is a P + 5, the emitter region 37 and the contact region 38 are formed to the same depth. However, for example, the contact region 38 may be formed deeper than the emitter region 37.

[0026] 4A and 5, a pillar region 39 having an impurity concentration higher than that of the drift layer 31 and approximately the same as that of the barrier region 36 is formed in the first region 11a of the IGBT region 11 in a surface layer portion of the base layer 32. The pillar region 39 is formed so as to be connected to the barrier region 36, as shown in FIG.

[0027] Furthermore, in the surface layer of the base layer 32, as shown in FIG. 4C, the FWD region 12 is provided with a P + A mold contact area 38 is formed.

[0028] That is, the pillar region 39 of this embodiment is formed in the first region 11a in the IGBT region 11, and is not formed in the second region 11b and the FWD region 12. In other words, in the IGBT region 11 of this embodiment, the region where the pillar region 39 is formed is the first region 11a, and the region where the pillar region 39 is not formed is the second region 11b.

[0029] In the first region 11a, as shown in Fig. 4A, the emitter region 37, the contact region 38, and the pillar region 39 are formed in this order along the longitudinal direction of the trench 33. In the second region 11b, as shown in Fig. 4B, the emitter region 37 and the contact region 38 are formed alternately along the longitudinal direction of the trench 33. In the FWD region 12, the contact regions 38 are formed scattered along the longitudinal direction of the trench 33. In the FWD region 12, the base layer 32 is exposed from a portion located between adjacent contact regions 38 along the longitudinal direction of the trench 33.

[0030] The first region 11a in Figures 2 and 3 corresponds to a cross section taken along line II-II in Figure 4A. The second region 11b in Figures 2 and 3 corresponds to a cross section taken along line II-II in Figure 4B. The FWD region 12 in Figures 2 and 3 corresponds to a cross section taken along line II-II in Figure 4C. Also, in Figures 4A to 4C, the gate insulating film 34 and the gate electrode 35 disposed in the trench 33 are omitted.

[0031] An interlayer insulating film 40 made of BPSG (abbreviation of borophosphosilicate glass) or the like is formed on one surface 30a of the semiconductor substrate 30. In the interlayer insulating film 40, contact holes 40a are formed to expose the emitter region 37, the contact region 38, and the pillar region 39 in the IGBT region 11. In the interlayer insulating film 40, contact holes 40b are formed to expose the base layer 32 and the contact region 38 in the FWD region 12. Then, on the interlayer insulating film 40, an upper electrode 41 is formed in the IGBT region 11 and electrically connected to the emitter region 37, the contact region 38 (i.e., the base layer 32), and the pillar region 39 through the contact hole 40a formed in the interlayer insulating film 40. On the interlayer insulating film 40, an upper electrode 41 is formed in the FWD region 12 and electrically connected to the base layer 32 and the contact region 38 through the contact hole 40b formed in the interlayer insulating film 40. That is, an upper electrode 41 that functions as an emitter electrode in the IGBT region 11 and functions as an anode electrode in the FWD region 12 is formed on the interlayer insulating film 40. Note that the upper electrode 41 in this embodiment is in ohmic junction with the base layer 32, the contact region 38, and the pillar region 39.

[0032] In this embodiment, a contact hole 40c exposing the gate electrode 35 is formed in the interlayer insulating film 40 in the FWD region 12. The upper electrode 41 is also connected to the gate electrode 35 through this contact hole 40b. As a result, the gate electrode 35 formed in the FWD region 12 is maintained at the same potential as the upper electrode 41. In this embodiment, the upper electrode 41 corresponds to a first electrode.

[0033] An N-type field stop (hereinafter, also referred to simply as an FS layer) 42 having a higher impurity concentration than the drift layer 31 is formed on the side of the drift layer 31 opposite to the base layer 32 side (i.e., the other surface 30b side of the semiconductor substrate 30). This FS layer 42 is not necessarily required, but is provided to improve the performance of the withstand voltage and steady loss by preventing the spread of a depletion layer, and to control the amount of holes injected from the other surface 30b side of the semiconductor substrate 30.

[0034] In the IGBT region 11, the FS layer 42 is sandwiched between the drift layer 31 and the P + In the FWD region 12, a collector layer 43 of N type is formed on the side opposite to the drift layer 31 with the FS layer 42 interposed therebetween. + A cathode layer 44 of a type is formed on the other surface 30b of the semiconductor substrate 30. That is, the IGBT region 11 and the FWD region 12 are defined by whether a layer formed on the other surface 30b of the semiconductor substrate 30 is a collector layer 43 or a cathode layer 44. The region on the collector layer 43 is the IGBT region 11, and the region on the cathode layer 44 is the FWD region 12.

[0035] A lower electrode 45 electrically connected to the collector layer 43 and the cathode layer 44 is formed on the opposite side to the drift layer 31 (i.e., the other surface 30b of the semiconductor substrate 30) with the collector layer 43 and the cathode layer 44 interposed therebetween. That is, the lower electrode 45 is formed to function as a collector electrode in the IGBT region 11 and to function as a cathode electrode in the FWD region 12. In this embodiment, the lower electrode 45 is in ohmic junction with the collector layer 43 and the cathode layer 44. In this embodiment, the lower electrode 45 corresponds to a second electrode.

[0036] The semiconductor device of the present embodiment is configured in this manner, whereby an IGBT element is configured in the IGBT region 11, with the base layer 32 as a base, the emitter region 37 as an emitter, and the collector layer 43 as a collector. Also, in the FWD region 12, an FWD element is configured by PN junction, with the base layer as an anode, and the drift layer 31, the FS layer 42, and the cathode layer 44 as a cathode.

[0037] The above is the configuration of the semiconductor device in this embodiment. + Type, N - The type corresponds to the first conductivity type, and P type, P + The first conductivity type corresponds to the second conductivity type. In the present embodiment, the semiconductor substrate 30 is configured as described above, and includes the collector layer 43, the cathode layer 44, the drift layer 31, the base layer 32, the barrier region 36, the emitter region 37, the contact region 38, the pillar region 39, and the like. In the semiconductor device of the present embodiment, the base layer 32, the barrier region 36, and the like are configured by ion implantation into the semiconductor substrate 30. Therefore, the base layer 32 and the barrier region 36 are configured to have a peak concentration at a predetermined position (for example, approximately the center) in the thickness direction of the semiconductor substrate 30.

[0038] Next, the operation of the semiconductor device will be described, and the detailed configuration of the semiconductor device will be further described.

[0039] In the above-described semiconductor device, when a voltage higher than that of the upper electrode 41 is applied to the lower electrode 45, the PN junction formed between the base layer 32 and the drift layer 31 becomes reverse conductive and a depletion layer is formed. When a low-level (e.g., 0 V) ​​gate voltage Vg that is lower than the threshold voltage Vth of the insulated gate structure is applied to the gate electrode 35, the collector current Ic does not flow between the upper electrode 41 and the lower electrode 45.

[0040] To turn the IGBT element on, a high-level gate voltage Vg that is equal to or higher than the threshold voltage Vth of the insulated gate structure is applied to the gate electrode 35 of the IGBT region 11 while a voltage higher than that of the upper electrode 41 is applied to the lower electrode 45. As a result, in the IGBT region 11, an inversion layer is formed in a portion of the base layer 32 that contacts the trench 33 in which the gate electrode 35 is disposed. In the IGBT element, electrons are supplied to the drift layer 31 from the emitter region 37 through the inversion layer, and holes are supplied to the drift layer 31 from the collector layer 43. The resistance value of the drift layer 31 is reduced by conductivity modulation, and a collector current Ic flows between the upper electrode 41 and the lower electrode 45.

[0041] Furthermore, when the IGBT element is turned off and the FWD element is turned on (i.e., the FWD element is operated as a diode), the voltages applied to the upper electrode 41 and the lower electrode 45 are switched, and a forward voltage is applied to the upper electrode 41 such that a voltage higher than that of the lower electrode 45 is applied to the upper electrode 41. As a result, holes are supplied to the base layer 32 and electrons are supplied to the cathode layer 44, causing the FWD element to operate as a diode.

[0042] At this time, in this embodiment, the pillar region 39 is formed in the first region 11a of the IGBT region 11. Therefore, in the first region 11a, electrons injected from the lower electrode 45 pass through the pillar region 39 to the upper electrode 41 in a low resistance state. Therefore, in the first region 11a, a forward bias is less likely to be applied to the PN junction between the barrier region 36 and the pillar region 39, and the base layer 32, and the injection of holes from the upper electrode 41 is reduced.

[0043] As a result, when the voltage between the upper electrode 41 and the lower electrode 45 is switched from forward bias to reverse bias, the injection of holes is suppressed, so that the recovery current can be reduced and the recovery time can be shortened, thereby reducing switching loss.

[0044] In such a semiconductor device, when a gate voltage Vg is applied to the gate electrode 35 of the IGBT region 11 and a collector current Ic begins to flow, a leakage current due to an electron current may flow through the pillar region 39 and the barrier region 36, as shown by arrow A in FIG. 5.

[0045] In this case, the relationship between the gate voltage Vg and the collector current Ic (i.e., leakage current) is as shown in Fig. 6 and Fig. 7. Note that Fig. 6 shows the relationship between the peak concentration of the first base layer 32a and the collector current Ic (i.e., leakage current) when the peak concentration of the first base layer 32a is 2.0 × 10 17 / cm 3 7 shows the simulation results when the peak concentration of the first base layer 32a is 5.0×10 17 / cm 3 6 and 7 show the collector current Ic when the peak concentration of the barrier region 36 is changed in a semiconductor device configured so that the threshold voltage Vth is 3 V, and each value in the figure indicates the peak concentration of the barrier region 36. In Fig. 6 and Fig. 7, the collector current Ic that flows when the gate voltage Vg is less than 3 V is the leakage current.

[0046] 6 and 7, the leakage current decreases as the threshold voltage Vth increases due to an increase in the peak concentration of the first base layer 32a. The leakage current decreases as the internal resistance increases due to a decrease in the peak concentration of the barrier region 36. In addition, the leakage current before the application of the threshold voltage Vth is currently 1.0×10 -5 It is desirable to keep it at or below A.

[0047] And the leakage current is 1.0×10 -5 The relationship between the peak concentration of the barrier region 36 that is equal to or less than A and the peak concentration of the first base layer 32a is as shown in FIG. 6 and FIG. 7 to FIG. 8. In this case, the peak concentration of the barrier region is expressed as y[×1.0×10 16 / cm 3 ], and the peak concentration of the first base layer 32a is x[×1.0×10 17 / cm 3], the leakage current is 1.0×10 -5 A. Therefore, the peak concentration of the barrier region 36 and the first base layer 32a is adjusted so as to satisfy the following formula 1.

[0048] (Number 1) y≦1.0429x 2 -2.4371x+1.48 On the other hand, as shown in Fig. 9, the on-state voltage of the IGBT element increases as the peak concentration of the first base layer 32a increases, since it becomes more difficult to form an inversion layer. Also, the on-state voltage increases as the peak concentration of the barrier region 36 decreases, since it becomes easier for holes supplied to the drift layer 31 to escape from the base layer 32. Note that Fig. 9 shows the simulation results when the collector current Ic is 400 A.

[0049] Furthermore, during diode operation, the higher the peak concentration of the barrier region 36, the easier it becomes for electrons injected from the lower electrode 45 to escape from the pillar region 39, and the less holes are injected from the upper electrode 41. According to the study by the present inventors, as shown in FIG. 10, the forward current flowing from the first region 11a (i.e., the IGBT region 11) to the FWD region 12 increases when the peak concentration of the barrier region 36 is 2.8×10 16 cm -3 It has been confirmed that when the peak concentration in the barrier region 36 is 2.8×10 16 cm -3 It was confirmed that a larger value of the capacitance can sufficiently reduce switching losses.

[0050] Therefore, it is preferable that the peak concentration of the first base layer 32a and the peak concentration of the barrier region 36 in the semiconductor device of this embodiment are adjusted in consideration of the required characteristics while satisfying the above formula 1. That is, if it is desired to lower the on-voltage, it is sufficient to lower the peak concentration of the first base layer 32a and increase the peak concentration of the barrier region 36 while satisfying the above formula 1. Also, if it is desired to reduce switching loss, it is sufficient to lower the peak concentration of the barrier region 36 to 2.8×10 16 cm -3 It would be better to make it higher.

[0051] In this embodiment, the peak concentration of the first base layer 32a and the peak concentration of the barrier region 36 are constant throughout the IGBT region 11 and the FWD region 12 (i.e., the cell region 10). That is, in this embodiment, the peak concentration of the first base layer 32a and the peak concentration of the barrier region 36 are adjusted to values ​​that satisfy the above formula 1 and take into consideration the required characteristics throughout the IGBT region 11 and the FWD region 12.

[0052] According to the present embodiment described above, the barrier region 36 is formed, and the pillar region 39 is formed in the first region 11a. Therefore, when the FWD element operates as a diode, injection of holes is suppressed in the first region 11a, and switching loss can be reduced.

[0053] Moreover, in this embodiment, the first base layer 32a and the barrier region 36 are formed so as to satisfy the above formula 1. Therefore, an increase in leakage current caused by forming the pillar region 39 and the barrier region 36 can be suppressed.

[0054] (1) In this embodiment, the upper electrode 41 is in ohmic contact with the emitter region 37, the contact region 38, and the pillar region 39. Therefore, titanium or the like can be used as the upper electrode 41, improving the selectivity of the material.

[0055] (2) In this embodiment, the peak concentration in the barrier region 36 is 2.8×10 16 / cm 3 This makes it possible to sufficiently reduce switching loss.

[0056] (3) In this embodiment, the pillar region 39 is disposed in the first region 11a located on the FWD region 12 side of the IGBT region 11. Therefore, during FWD operation, holes are less likely to flow from the IGBT region 11 located on the FWD region 12 side into the FWD region 12, which makes it easier to reduce switching loss.

[0057] (Other embodiments) Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also encompasses various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

[0058] For example, in each of the above embodiments, a semiconductor device in which the first conductivity type is N type and the second conductivity type is P type has been described, but the semiconductor device may also be one in which the first conductivity type is P type and the second conductivity type is N type.

[0059] In the first embodiment, the emitter regions 37 and the contact regions 38 may be arranged in the IGBT region 11 in a direction intersecting the longitudinal direction of the trenches 33. In this case, the emitter regions 37 are formed so as to contact each trench 33, and the contact regions 38 are arranged on the opposite side of the trenches 33 with the emitter regions 37 in between. In the first region 11a, the pillar regions 39 are formed so as to penetrate the contact regions 38 and reach the barrier region 36. That is, in the first region 11a, the emitter regions 37, the contact regions 38, the pillar regions 39, the contact regions 38, and the emitter regions 37 are arranged in this order between the adjacent trenches 33 along the arrangement direction of the trenches 33. Even in such a semiconductor device, the first base layer 32a and the barrier region 36 are configured to satisfy the above formula 1, thereby obtaining the same effect as the first embodiment.

[0060] In each of the above embodiments, the upper electrode 41 may be made of a material that forms a Schottky junction with the pillar region 39. This makes it even more difficult for holes to be injected during FWD operation, thereby making it possible to further reduce recovery loss.

[0061] In the above first embodiment, an example has been described in which the peak concentrations of the first base layer 32a and the barrier region 36 in the entire cell region 10 are configured to satisfy the above relationship. However, in order to reduce the leakage current, it is only necessary that the peak concentrations of the first base layer 32a and the barrier region 36 in at least the first region 11a in which the pillar region 39 is formed are formed to satisfy the above mathematical formula 1. That is, the peak concentrations of the first base layer 32a and the barrier region 36 in the second region 11b and the FWD region 12 do not have to be formed to satisfy the above mathematical formula 1. In this case, only one of the second region 11b and the FWD region 12 may be configured to have a different peak concentration from the first base layer 32a and the barrier region 36 in the first region 11a.

[0062] Furthermore, the pillar region 39 may be formed in the second region 11b in addition to the first region 11a, or may be formed in the FWD region 12. For example, when the pillar region 39 is formed in the second region 11b, the planar shape is the same as that of FIG. 4A. When the pillar region 39 is formed in the FWD region 12, the pillar region 39 is formed so as to penetrate the contact region 38 in FIG. 4C and contact the adjacent trench 33. Furthermore, the pillar region 39 may be formed only in the second region 11b. That is, it is sufficient that the pillar region 39 is formed at least in the IGBT region 11.

[0063] Furthermore, the configuration of the one surface 30a side of the semiconductor substrate 30 in the FWD region 12 can be changed as appropriate, and may be, for example, the same configuration as that of the IGBT region 11. That is, in the FWD region 12, an emitter region 37 and the like may be formed on the one surface 30a side of the semiconductor substrate 30. [Explanation of symbols]

[0064] 11 IGBT area 12 FWD area 30 Semiconductor Substrate 30a one side 30b Other side 31 Drift Layer 32 Base Layer 32a 1st base layer 32b Second base layer 33 Trench 34 Gate insulating film 35 Gate electrode 36 Barrier Region 37 Emitter Area 39 Pillar Region 41 Upper electrode (1st electrode) 45 Lower electrode (second electrode)

Claims

1. A semiconductor device in which an IGBT region (11) having an IGBT element and an FWD region (12) having an FWD element are formed on a common semiconductor substrate (30), the semiconductor substrate having the IGBT region and the FWD region, including a drift layer (31) of a first conductivity type, a base layer (32) of a second conductivity type formed on the drift layer, a collector layer (43) of a second conductivity type formed on a side of the drift layer opposite to the base layer side in the IGBT region, and a cathode layer (44) of a first conductivity type formed on a side of the drift layer opposite to the base layer side in the FWD region, the semiconductor substrate having a surface on the base layer side as one surface (30a) and a surface on the collector layer and cathode layer sides as the other surface (30b); a barrier region (36) of a first conductivity type formed in the base layer and dividing the base layer into a first base layer (32 a) on the drift layer side and a second base layer (32 b) on one surface side of the semiconductor substrate; a pillar region (39) formed in the base layer in the IGBT region, connected to the barrier region and exposed from one surface of the semiconductor substrate; a trench gate structure including a gate insulating film (34) formed on a wall surface of a trench (33) that penetrates the base layer and the barrier region to reach the drift layer in the IGBT region, and a gate electrode (35) formed on the gate insulating film; a first conductivity type emitter region (37) formed in a surface layer portion of the base layer and in contact with the trench; a first electrode (41) disposed on one surface side of the semiconductor substrate and electrically connected to the base layer, the pillar region, and the emitter region; a second electrode (45) disposed on the other surface side of the semiconductor substrate and electrically connected to the collector layer and the cathode layer; The barrier region and the first base layer are configured to have a peak concentration at a predetermined position in the thickness direction of the semiconductor substrate, and the peak concentration of the barrier region is defined as y[×1.0×10 １６ / cm ３ ], and the peak concentration of the first base layer is x[×1.0×10 １７ / cm ３ ], then y≦1.0429x ２ The configuration satisfies −2.4371x+1.48, In the semiconductor device, x indicating a peak concentration of the first base layer is set to 1 or more.

2. The semiconductor device according to claim 1 , wherein the first electrode forms an ohmic junction with the base layer, the pillar region, and the emitter region.

3. The barrier region has a peak concentration of 2.8×10 １６ / cm ３ 3. The semiconductor device according to claim 1 or 2.

4. The IGBT region has a first region (11a) located on the FWD region side and a second region (11b) located on the opposite side to the FWD region with the first region in between, 4. The semiconductor device according to claim 1, wherein the pillar region is formed at least in the first region.

Images