Semiconductor Device

Abstract

A semiconductor device (10) is provided with: a semiconductor substrate (12); a plurality of trenches (22) that extend in a first direction (y), while being arranged at a distance from each other in a second direction (x) that intersects with the first direction; a gate insulating film (24); and a gate electrode (26). The semiconductor substrate has a source region (30), a body region (32), a drift region (34), a plurality of bottom regions (36), a plurality of electric field attenuated regions (38), and a plurality of contact regions (31). When the semiconductor substrate is viewed in plan from above, there are a plurality of overlapping regions (40), in each of which a semiconductor region between trenches and an electric field attenuated region overlap with each other; the plurality of overlapping regions include a plurality of contact overlapping regions (40a), each of which is provided with a contact region, and a plurality of non-contact overlapping regions (40b), each of which is not provided with a contact region; and the contact overlapping regions and the non-contact overlapping regions are alternately arranged in the first direction.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application is a related application of Japanese patent application No. 2021-206356 filed on December 20, 2021, and claims priority based on this Japanese patent application, the entire contents of which are incorporated by reference into this specification.

[0002] The technology disclosed in this specification relates to a semiconductor device. [Background technology]

[0003] US Patent No. 10,586,845 discloses a semiconductor device including a semiconductor substrate, a plurality of trenches arranged at intervals on the upper surface of the semiconductor substrate, a gate insulating film covering the inner surface of each trench, and a gate electrode arranged in each trench. The semiconductor substrate has a plurality of n-type source regions, a p-type body region, a plurality of p-type contact regions, a p-type electric field relaxation region, and an n-type drift region. Each source region is exposed on the upper surface of the semiconductor substrate and contacts the gate insulating film. Each body region is contacted with the gate insulating film below the source region. Each contact region is exposed on the upper surface of the semiconductor substrate and contacts the source region and the gate insulating film. Each electric field relaxation region is contacted with the gate insulating film below the contact region. The drift region contacts the body region and the electric field relaxation region from below. In the semiconductor device of US Patent No. 10,586,845, each source region and each contact region are alternately arranged along the direction in which each trench extends.

[0004] When the semiconductor device of U.S. Pat. No. 10,586,845 is turned off, a depletion layer extends from the body region and the electric field relaxation region into the drift region. In this semiconductor device, a contact region is provided on each of the upper portions of the electric field relaxation regions, so that when the semiconductor device is turned off, holes flow quickly from the electric field relaxation region to the contact region, and a high reverse voltage is applied to the pn junction at the interface between the electric field relaxation region and the drift region. As a result, the depletion layer spreads quickly in the drift region, and electric field concentration near the bottom end of the trench is suppressed. Summary of the Invention

[0005] In the semiconductor device of U.S. Pat. No. 10,586,845, many contact regions are arranged, so the area of ​​the source region exposed on the upper surface of the semiconductor substrate is narrow. As a result, the contact resistance of the source region increases. This specification provides a technology that can stabilize the potential of the electric field relaxation region and reduce the contact resistance of the source region.

[0006] The semiconductor device disclosed in this specification includes a semiconductor substrate, a plurality of trenches provided on an upper surface of the semiconductor substrate, each of which extends in a first direction on the upper surface and is arranged at intervals in a second direction intersecting the first direction on the upper surface, a gate insulating film covering an inner surface of each of the trenches, and a gate electrode disposed in each of the trenches and insulated from the semiconductor substrate by the gate insulating film. The semiconductor substrate has a source region, a body region, a drift region, a plurality of bottom regions, a plurality of electric field reduction regions, and a plurality of contact regions. The source region is an n-type region exposed on the upper surface of the semiconductor substrate and in contact with the gate insulating film in each of the trenches. The body region is a p-type region in contact with the gate insulating film in each of the trenches below the source region. The drift region is an n-type region in contact with the gate insulating film in each of the trenches below the body region and separated from the source region by the body region. Each of the bottom regions is a p-type region extending in the first direction so as to contact the gate insulating film at the bottom surface of the corresponding trench and contacting the drift region. Each of the electric field relaxation regions is a p-type region disposed below the body region, connected to the body region, extending in the second direction, contacting each of the bottom regions, and disposed at intervals in the first direction. Each of the contact regions is a p-type region exposed on the upper surface of the semiconductor substrate and contacting the body region. A semiconductor region located between the plurality of trenches is an inter-trench semiconductor region, and when the semiconductor substrate is viewed in plan from above, there are a plurality of overlapping ranges in which the inter-trench semiconductor region and the electric field relaxation region overlap, and the plurality of overlapping ranges include a plurality of contact overlapping ranges in which the contact region is provided and a plurality of non-contact overlapping ranges in which the contact region is not provided, and the contact overlapping ranges and the non-contact overlapping ranges are alternately disposed in the first direction.

[0007] In the above semiconductor device, when the semiconductor substrate is viewed from above, the semiconductor substrate has a plurality of overlapping areas in which the inter-trench semiconductor region and the electric field relaxation region overlap. The plurality of overlapping areas include a plurality of contact overlapping areas and a plurality of non-contact overlapping areas. The contact overlapping area is an area in which the contact region and the electric field relaxation area overlap. That is, in this semiconductor device, each of the plurality of contact regions is disposed directly above the electric field relaxation area. Therefore, when the semiconductor device is turned off, in the contact overlapping area, holes flow from the bottom region through the electric field relaxation area to the contact region, and the bottom region is maintained at a low potential. In addition, the contact overlapping area and the non-contact overlapping area are disposed alternately in the first direction in which the trench extends. Since the contact overlapping area is disposed in a dispersed manner in this manner, the potential of the entire bottom region is stabilized at a low potential, and the depletion layer spreads from each bottom region into the drift region in a balanced manner. Therefore, the electric field concentration near the bottom end of the trench can be suppressed in a balanced manner. In addition, in the non-contact overlapping area, the source region can be exposed on the upper surface of the semiconductor substrate, so that the area of ​​the source region can be secured. Since the contact overlapping ranges and the non-contact overlapping ranges are alternately arranged in the first direction in which the trench extends, it is possible to ensure a wide non-contact overlapping range (i.e., the area of ​​the source region on the upper surface of the semiconductor substrate), thereby reducing the contact resistance of the source region. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view taken along line II-II in FIG. [Diagram 3] FIG. 2 is a cross-sectional view taken along line III-III in FIG. [Figure 4] FIG. 11 is a plan view of a semiconductor device according to a second embodiment. [Diagram 5] 5 is a cross-sectional view taken along line VV in FIG. 4 . [Figure 6] FIG. 11 is a plan view of a semiconductor device according to a third embodiment. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. [Figure 8] FIG. 7 is a cross-sectional view taken along line VIII-VIII in FIG. [Figure 9] FIG. 7 is a cross-sectional view taken along line IX-IX in FIG. [Figure 10] FIG. 11 is a cross-sectional view of a semiconductor device according to a fourth embodiment, corresponding to FIG. [Figure 11] FIG. 11 is a cross-sectional view of a semiconductor device according to a fifth embodiment, corresponding to FIG. [Figure 12] 3 is a cross-sectional view of the semiconductor device of the reference example, corresponding to FIG. 2; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The technical elements disclosed in this specification are listed below. Note that each of the technical elements below is useful independently.

[0010] In one embodiment disclosed herein, the contact overlapping ranges and the non-contact overlapping ranges may be arranged alternately in the second direction. In this configuration, electric field concentration near the bottom end of the trench can be suppressed in a more balanced manner, and the contact resistance of the source region can be reduced more uniformly.

[0011] In one embodiment disclosed in the present specification, an n-type upper drift region may be provided between each of the electric field relaxation regions and the body region, the n-type upper drift region being in contact with the gate insulating film in each of the trenches below the body region. In this configuration, the upper drift region functions as a current path even in the area where the electric field relaxation region is provided. That is, the channel formed in the body region located above the electric field relaxation region can be effectively utilized. Therefore, the channel resistance can be reduced.

[0012] In one embodiment disclosed in the present specification, the electric field relaxation region may be a first electric field relaxation region, the overlapping range may be a first overlapping range, the contact overlapping range may be a first contact overlapping range, and the non-contact overlapping range may be a first non-contact overlapping range. The semiconductor substrate may further include a plurality of p-type second electric field relaxation regions. Each of the plurality of second electric field relaxation regions may be disposed below the body region, connected to the body region, extend in a third direction intersecting the first direction and the second direction, and contact each of the bottom regions. The plurality of second electric field relaxation regions may be disposed at intervals in a direction intersecting the third direction. When the semiconductor substrate is viewed in plan from above, there may be a plurality of second overlapping ranges in which each of the inter-trench semiconductor regions and each of the second electric field relaxation regions overlap. The plurality of second overlapping ranges may include a plurality of second contact overlapping ranges in which the contact region is provided, and a plurality of second non-contact overlapping ranges in which the contact region is not provided. The second contact overlapping ranges and the second non-contact overlapping ranges may be arranged alternately in the first direction.

[0013] In the above configuration, the first electric field buffer regions and the second electric field buffer regions are provided so as to extend in different directions. Therefore, even if the intervals between the first electric field buffer regions and the intervals between the second electric field buffer regions are widened, the breakdown voltage of the semiconductor device can be ensured. In addition, since the intervals between the electric field buffer regions can be widened, the drift region can be arranged over a wide range in the inter-trench semiconductor region, and the on-resistance can be reduced.

[0014] In one embodiment disclosed in the present specification, the semiconductor device may further include an interlayer insulating film covering the upper surface of the gate electrode and having a contact hole on the upper surface of the semiconductor substrate, and an upper electrode covering a range spanning the upper surface of the interlayer insulating film and the inner surface of the contact hole, contacting the upper surface of the semiconductor substrate within the contact hole, and insulated from the gate electrode by the interlayer insulating film. The upper electrode may include a tungsten-containing layer disposed inside the contact hole, and an aluminum-containing layer covering the upper surface of the interlayer insulating film and the upper surface of the tungsten-containing layer. In this configuration, by disposing the tungsten-containing layer inside the contact hole, it is possible to reduce unevenness of the upper electrode (aluminum-containing layer) caused by the contact hole. In addition, the tungsten-containing layer can densely fill a narrow contact hole, so that the semiconductor device can be miniaturized.

[0015] Example 1 1 to 3 show a semiconductor device 10 according to a first embodiment. The semiconductor device 10 is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). As shown in FIG. 1, the semiconductor device 10 has a semiconductor substrate 12, an upper electrode 14, and a lower electrode 16. Note that the electrode layer and the insulating layer on the upper surface 12a of the semiconductor substrate 12 are omitted from FIG. 1. The semiconductor substrate 12 is made of SiC (silicon carbide). However, the material of the semiconductor substrate 12 is not particularly limited, and may be other semiconductor materials such as Si (silicon) and GaN (gallium nitride). Hereinafter, one direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x-direction, a direction parallel to the semiconductor substrate 12 and perpendicular to the x-direction is referred to as the y-direction, and a thickness direction of the semiconductor substrate 12 is referred to as the z-direction.

[0016] As shown in FIG. 1, a plurality of trenches 22 are provided on the upper surface 12a of the semiconductor substrate 12. Each trench 22 extends long along the y direction. Each trench 22 extends parallel to one another. Each trench 22 is arranged at intervals in the x direction. As shown in FIGS. 2 and 3, a gate insulating film 24 and a gate electrode 26 are disposed in each trench 22. The gate insulating film 24 covers the inner surface of each trench 22. The gate electrode 26 is disposed inside each trench 22. The gate electrode 26 is insulated from the semiconductor substrate 12 by the gate insulating film 24.

[0017] 2 and 3, the upper surface of the gate electrode 26 and the upper surface 12a of the semiconductor substrate 12 are covered with an interlayer insulating film 28. A plurality of contact holes 28a are formed in the interlayer insulating film 28. Each of the contact holes 28a is provided in a range between two adjacent trenches 22. That is, the contact holes 28a are arranged in a range in the x direction where the gate electrode 26 is not provided. Each of the contact holes 28a penetrates the interlayer insulating film 28 from the upper surface to the lower surface.

[0018] The upper electrode 14 covers the range spanning the upper surface of the interlayer insulating film 28 and the inner surface of the contact hole 28a. The upper electrode 14 has a tungsten-containing layer 14a and an aluminum-containing layer 14b. The tungsten-containing layer 14a is disposed inside the contact hole 28a. The tungsten-containing layer 14a contacts the upper surface 12a of the semiconductor substrate 12 at the bottom of the contact hole 28a. The tungsten-containing layer 14a is formed so that its upper surface is substantially flat with respect to the upper surface of the interlayer insulating film 28. The tungsten-containing layer 14a is insulated from the gate electrode 26 by the interlayer insulating film 28. The aluminum-containing layer 14b covers substantially the entire upper surface of the interlayer insulating film 28 and the upper surface of the tungsten-containing layer 14a. In this embodiment, the tungsten-containing layer 14a is made of tungsten, and the aluminum-containing layer 14b is made of an alloy of aluminum and silicon. However, tungsten-containing layer 14a may be any metal layer containing tungsten as a main component, and aluminum-containing layer 14b may be any metal layer containing aluminum as a main component (including elemental aluminum).

[0019] The lower electrode 16 is provided on the lower surface 12b of the semiconductor substrate 12. The lower electrode 16 contacts substantially the entire area of ​​the lower surface 12b of the semiconductor substrate 12.

[0020] Within the semiconductor substrate 12, a source region 30, a plurality of contact regions 31, a body region 32, a drift region 34, a drain region 35, a plurality of bottom regions 36, and a plurality of electric field relief regions 38 are provided.

[0021] The source region 30 is an n-type region. As shown in FIGS. 1 to 3, the source region 30 is provided in each of the semiconductor regions (hereinafter referred to as inter-trench semiconductor regions) located between adjacent trenches 22. The source region 30 is provided at a position exposed on the upper surface 12a of the semiconductor substrate 12, and is in ohmic contact with the upper electrode 14 (tungsten-containing layer 14a). Each source region 30 contacts the gate insulating film 24 in the two trenches 22 located on both sides of the inter-trench semiconductor region.

[0022] The body region 32 is a p-type region. As shown in Fig. 2 and Fig. 3, the body region 32 is disposed below the source region 30 and a contact region 31 described later. The body region 32 contacts the source region 30 and the contact region 31 from below. The body region 32 contacts the gate insulating film 24 in each trench 22 below the source region 30.

[0023] The drift region 34 is an n-type region. As shown in FIGS. 2 and 3, the drift region 34 is disposed below the body region 32 and an electric field relaxation region 38 described later. The drift region 34 contacts the body region 32 and the electric field relaxation region 38 from below. As shown in FIG. 3, the drift region 34 contacts the gate insulating film in each trench 22 below the body region 32 in an area where the electric field relaxation region 38 is not provided. The drift region 34 is distributed from each inter-trench semiconductor region to a region below each trench 22. The drift region 34 is separated from the source region 30 by the body region 32.

[0024] A drain region 35 is provided below the drift region 34. The drain region 35 is an n-type region having a higher n-type impurity concentration than the drift region 34. The drain region 35 contacts the drift region 34 from below. The drain region 35 is in ohmic contact with the lower electrode 16 on the lower surface 12b of the semiconductor substrate 12.

[0025] Each bottom region 36 is a p-type region. Each bottom region 36 contacts the gate insulating film 24 in the corresponding trench 22 at the bottom surface of the corresponding trench 22. Each bottom region 36 extends long in the y direction along the bottom surface of the corresponding trench 22. The bottom region 36 contacts the drift region 34.

[0026] Each electric field relaxation region 38 is a p-type region. As shown in FIG. 2, each electric field relaxation region 38 contacts the body region 32 from below. In FIG. 1, each electric field relaxation region 38 is indicated by gray hatching. As shown in FIG. 1, each electric field relaxation region 38 extends long in a direction (x direction) intersecting with each trench 22. Each electric field relaxation region 38 is arranged at intervals in the direction (y direction) in which each trench 22 extends. That is, as shown in FIG. 1, when the semiconductor substrate 12 is viewed from above in a plan view, each trench 22 and each electric field relaxation region 38 are arranged in a lattice shape. As shown in FIG. 2, each electric field relaxation region 38 extends below the lower end of the trench 22 and contacts the side surface of the bottom region 36. Each bottom region 36 extends below each electric field relaxation region 38. The side surface and the bottom surface of each electric field relaxation region 38 are surrounded by the drift region 34.

[0027] Each contact region 31 is a p-type region. Each contact region 31 has a higher p-type impurity concentration than the body region 32. As shown in FIGS. 1 and 2, each contact region 31 is provided in an inter-trench semiconductor region. A plurality of contact regions 31 are provided in each inter-trench semiconductor region. Each contact region 31 is exposed on the upper surface 12a of the semiconductor substrate 12 and is in ohmic contact with the upper electrode 14. As shown in FIG. 1, the side surface of each contact region 31 is surrounded by the source region 30. As shown in FIG. 2, each contact region 31 is in contact with the body region 32 at its lower surface.

[0028] As described above, the upper end of each electric field relief region 38 is connected to the body region 32. Therefore, each bottom region 36 is connected to the body region 32 via the electric field relief region 38. Therefore, each bottom region 36 is connected to the upper electrode 14 via the electric field relief region 38, the body region 32, and the contact region 31. Therefore, the potential of each bottom region 36 is approximately equal to the potential of the upper electrode 14.

[0029] As shown in FIG. 1, in the semiconductor device 10, when the semiconductor substrate 12 is viewed in plan from above, there are a plurality of overlapping areas 40 (i.e., gray hatched areas) in which the inter-trench semiconductor region and each electric field relaxation region 38 overlap. Hereinafter, among the plurality of overlapping areas 40, the overlapping area 40 in which the contact region 31 is provided is referred to as the contact overlapping area 40a, and the overlapping area 40 in which the contact region 31 is not provided is referred to as the non-contact overlapping area 40b. In the contact overlapping area 40a, the contact region 31 is arranged so as to overlap with the electric field relaxation region 38. In the non-contact overlapping area 40b, the contact region 31 is not arranged, and above the electric field relaxation region 38, the source region 30 is exposed to the upper surface 12a of the semiconductor substrate 12. In the semiconductor device 10, the contact overlapping area 40a and the non-contact overlapping area 40b are arranged alternately in the direction in which the trench 22 extends (y direction). That is, the contact region 31 is arranged every other overlapping area 40 in the y direction. The contact overlapping ranges 40a and the non-contact overlapping ranges 40b are also configured to be arranged alternately in the direction (x direction) in which the electric field reduction region 38 extends. That is, the contact regions 31 are arranged in every other overlapping range 40 in the x direction.

[0030] When the semiconductor device 10 is in use, a higher potential is applied to the lower electrode 16 than to the upper electrode 14. When a voltage equal to or greater than the gate threshold is applied to the gate electrode 26, a channel is formed in the body region 32 in the area in contact with the gate insulating film 24, and the semiconductor device 10 is turned on. When the voltage applied to the gate electrode 26 is reduced to below the gate threshold, the channel disappears and the semiconductor device 10 is turned off.

[0031] When the semiconductor device 10 is in an off state, the potential of the lower electrode 16 is much higher than the potential of the upper electrode 14. In this state, the drift region 34 has a potential close to that of the lower electrode 16. As described above, the bottom region 36 has a potential substantially equal to that of the upper electrode 14. Therefore, a high reverse voltage is applied to the pn junction at the interface between the drift region 34 and the bottom region 36. Therefore, a depletion layer spreads over a wide area from each bottom region 36 into the drift region 34. This suppresses electric field concentration near the bottom end of the trench 22, and ensures the breakdown voltage of the semiconductor device 10.

[0032] Next, the operation when the semiconductor device 10 is turned off will be described in detail. When the semiconductor device 10 is turned off and the potential of the lower electrode 16 rises, holes flow from the bottom region 36 through the electric field relaxation region 38, the body region 32, and the contact region 31 to the upper electrode 14. By the flow of holes in this manner, the potential of the bottom region 36 is maintained at a low potential. In the contact overlapping range 40a, the path from the bottom region 36 to the upper electrode 14 through the contact region 31 is short. As described above, the contact overlapping range 40a and the non-contact overlapping range 40b are alternately arranged in the x direction and the y direction. Therefore, the contact overlapping range 40a (i.e., the contact region 31) is arranged in a substantially uniform distribution on the upper surface of the semiconductor substrate 12. Therefore, even in the non-contact overlapping range 40b, the path from the bottom region 36 to the upper electrode 14 through the contact region 31 is not so long. Therefore, holes are quickly discharged from the bottom region 36 to the upper electrode 14 throughout the bottom region 36. This suppresses the rise in potential of the bottom region 36 that accompanies the rise in potential of the lower electrode 16, and the potential of the bottom region 36 is maintained at approximately the same potential as the potential of the upper electrode 14. As a result, a depletion layer spreads quickly around the bottom region 36, and electric field concentration near the bottom end of the trench 22 is effectively suppressed.

[0033] In the semiconductor device 10, in the non-contact overlapping range 40b, the source region 30 is exposed on the upper surface 12a of the semiconductor substrate 12. Since the contact overlapping range 40a and the non-contact overlapping range 40b are alternately arranged in the x direction and the y direction, it is possible to ensure the non-contact overlapping range 40b (i.e., the area of ​​the source region 30), and it is possible to reduce the contact resistance between the source region 30 and the upper electrode 14.

[0034] In the first embodiment, the contact overlapping ranges 40a and the non-contact overlapping ranges 40b are alternately arranged in both the x and y directions. However, the contact overlapping ranges 40a and the non-contact overlapping ranges 40b do not have to be alternately arranged in the x direction. As long as they are alternately arranged at least in the y direction, it is possible to suppress the electric field concentration near the bottom end of the trench 22 and reduce the contact resistance of the source region 30. The same applies to the other embodiments described below.

[0035] Example 2 Next, a semiconductor device 100 of Example 2 will be described with reference to Figures 4 and 5. As shown in Figure 4, in the semiconductor device 100 of Example 2, the direction in which each electric field buffer region 138 extends is different from that of Example 1. Each electric field buffer region 138 extends long in the m direction intersecting with each trench 22. The m direction is a direction inclined at a predetermined angle with respect to the direction (x direction) perpendicular to the direction in which each trench 22 extends (y direction). As shown in Figure 5, other internal configurations of the semiconductor substrate 12 (source region 30, body region 32, drift region 34, etc.) are the same as those of Example 1.

[0036] In the second embodiment, similarly to the first embodiment, the contact overlapping range 140a and the non-contact overlapping range 140b are arranged alternately in the direction in which the trench 22 extends (y direction). That is, the contact region 31 is arranged alternately for each overlapping range 140 in the y direction. The contact overlapping range 140a and the non-contact overlapping range 140b are also arranged alternately in the direction in which the electric field reduction region 138 extends (m direction). That is, the contact region 31 is arranged alternately for each overlapping range 140 in the m direction. Note that in the second embodiment, the contact overlapping range 140a and the non-contact overlapping range 140b are not arranged alternately in the x direction. In the x direction, either the contact overlapping range 140a or the non-contact overlapping range 140b is arranged continuously for each overlapping range 140.

[0037] In this embodiment as well, the contact overlapping range 140a and the non-contact overlapping range 140b are arranged alternately in the y direction and the m direction, so that it is possible to both suppress electric field concentration near the bottom end of the trench 22 and reduce the contact resistance of the source region 30.

[0038] Example 3 Next, a semiconductor device 200 of Example 3 will be described with reference to Fig. 6 to Fig. 9. As shown in Fig. 6, in the semiconductor device 200 of Example 3, the semiconductor substrate 12 has, in addition to the electric field buffer region 138 of Example 2 (hereinafter referred to as the first electric field buffer region 138), a plurality of p-type second electric field buffer regions 238 extending in a direction (n direction) different from the first electric field buffer region 138. The n direction is a direction intersecting the direction (y direction) in which each trench 22 extends and the direction (m direction) in which the first electric field buffer region 138 extends, and is a direction inclined at a predetermined angle with respect to the x direction perpendicular to the y direction.

[0039] As shown in Fig. 6, when the semiconductor substrate 12 is viewed in plan from above, the first electric field relief region 138 and the second electric field relief region 238 intersect in a range where they overlap with the trench 22. As shown in Fig. 7, each of the first electric field relief regions 138 and each of the second electric field relief regions 238 are connected in a range where they contact the side surface of the trench 22. Each of the first electric field relief regions 138 and each of the second electric field relief regions 238 contacts the bottom region 36 in a range where they are connected to each other. As shown in Fig. 8, in a cross section where the first electric field relief region 138 and the second electric field relief region 238 are not connected, the drift region 34 contacts the side surface of each trench 22 below the body region 32.

[0040] In Example 3, similarly to Examples 1 and 2, in a plurality of overlapping ranges 240 where the inter-trench semiconductor region and the second electric field buffer region 238 overlap, the contact overlapping ranges 240a and the non-contact overlapping ranges 240b are arranged alternately in the direction in which the trench 22 extends (y direction). That is, the contact regions 31 are arranged for every other overlapping range 240 in the y direction. Also, as shown in Figs. 6 and 9, in Example 3, the contact overlapping ranges 240a are arranged at intervals (that is, not consecutively arranged) with respect to each overlapping range 240 in the direction in which the second electric field buffer region 238 extends (n direction).

[0041] In the semiconductor device 200 of the third embodiment, the plurality of first electric field relief regions 138 and the plurality of second electric field relief regions 238 are provided so as to extend in mutually different directions (m-direction and n-direction). Therefore, even if the intervals between the first electric field relief regions 138 and the intervals between the second electric field relief regions 238 are widened, holes can efficiently flow from the bottom region 36 to the contact region 31 through the electric field relief regions 138 and 238, and the breakdown voltage of the semiconductor device 200 can be ensured. In addition, since the intervals between the electric field relief regions 138 and 238 can be widened, the drift region 34 can be disposed over a wide range in the inter-trench semiconductor region, and the on-resistance can be reduced.

[0042] In the range where each electric field relaxation region 138, 238 is provided, the n-type drift region 34 is not in contact with the gate insulating film 24, so that a current does not easily flow through the channel formed in the body region 32. However, in this embodiment, the first electric field relaxation region 138 and the second electric field relaxation region 238 intersect in the range where they overlap with the trench 22, so that electrons can flow from the channel formed in the body region 32 to a wide range of the drift region 34. This prevents the on-resistance from increasing.

[0043] Example 4 Next, a semiconductor device 300 of Example 4 will be described with reference to FIG. 10. FIG. 10 is a cross section corresponding to FIG. 2 of Example 1. In Example 4, an n-type upper drift region 42 is provided between the body region 32 and the electric field relaxation region 38. The upper drift region 42 contacts the body region 32 from below, and contacts the gate insulating film 24 below the body region 32. The upper drift region 42 is separated from the source region 30 by the body region 32. The lower end of the upper drift region 42 is located above the lower end of each trench 22. The electric field relaxation region 38 is disposed below the upper drift region 42. The electric field relaxation region 38 contacts the upper drift region 42 from below. Although not shown, the upper drift region 42 is connected to the drift region 34 in a cross section where the electric field relaxation region 38 is not provided (a cross section corresponding to FIG. 3 of Example 1).

[0044] In the semiconductor device 300 of the fourth embodiment, the upper drift region 42 functions as a current path even in the area where the electric field relaxation region 38 is provided. That is, the channel formed in the body region 32 located above the electric field relaxation region 38 (the channel formed in the cross section of FIG. 2) can be effectively utilized. As a result, the channel resistance can be reduced.

[0045] Example 5 Next, a semiconductor device 400 of Example 5 will be described with reference to FIG. 11. FIG. 11 is a cross section corresponding to FIG. 2 of Example 1. In Example 5, the thickness (length in the z direction) of each bottom region 36 is shorter than that of Example 1. In Example 5, the lower end of each bottom region 36 is located above the lower end of each electric field relaxation region 38. That is, in the range where the electric field relaxation region 38 is provided, each bottom region 36 is not in contact with the drift region 34, and is surrounded by the electric field relaxation region 38.

[0046] In the semiconductor device 400 of Example 5, the thickness of the bottom region 36 is thinner than that of Example 1. Since the distance of the bottom region 36 protruding into the drift region 34 is short, the electrons that flow through the inter-trench semiconductor region can flow into a wider range of the drift region 34, and the on-resistance can be reduced.

[0047] (Reference example) Next, a semiconductor device 500 of a reference example will be described with reference to FIG. 12. The semiconductor device 500 of the reference example is different from the semiconductor device 10 of the first embodiment in that it does not have the bottom region 36. The other configurations are the same as those of the first embodiment. The semiconductor device 500 of the reference example does not have the bottom region 36. However, each electric field relaxation region 38 extends below the lower end of the trench 22. Since a plurality of electric field relaxation regions 38 are provided at intervals in the direction in which each trench 22 extends (y direction), when the semiconductor device 500 is in an off state, the depletion layer spreading from each electric field relaxation region 38 into the drift region 34 can suppress electric field concentration near the lower end of the trench 22. In addition, since the bottom region 36 is not formed in the semiconductor device 500, the manufacturing process can be reduced.

[0048] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or drawings achieves multiple objectives simultaneously, and achieving one of the objectives itself has technical utility.

Claims

1. A semiconductor substrate (12); A plurality of trenches (22) are provided on an upper surface (12a) of the semiconductor substrate, each of which extends in a first direction on the upper surface and is arranged at intervals in a second direction on the upper surface that intersects with the first direction; a gate insulating film (24) covering the inner surface of each of the trenches; a gate electrode (26) disposed in each of the trenches and insulated from the semiconductor substrate by the gate insulating film; Equipped with The semiconductor substrate is an n-type source region (30) exposed on the upper surface of the semiconductor substrate and in contact with the gate insulating film in each of the trenches; a p-type body (32) region in contact with the gate insulating film in each of the trenches below the source region; an n-type drift region (34) in contact with the gate insulating film in each of the trenches below the body region and separated from the source region by the body region; a plurality of p-type bottom regions (36) extending in the first direction so as to contact the gate insulating film at the bottom surface of the corresponding trench and contacting the drift region; a plurality of p-type field relief regions (38, 138), each of which is disposed below the body region, each of which is connected to the body region, each of which extends in the second direction, each of which is in contact with each of the bottom regions, and each of which is spaced apart in the first direction; a plurality of p-type contact regions (31), each of which is exposed on the upper surface of the semiconductor substrate and each of which is in contact with the body region; It has a semiconductor region located between the plurality of trenches is an inter-trench semiconductor region; When the semiconductor substrate is viewed in plan from above, there are a plurality of overlapping areas (40, 140) in which each of the inter-trench semiconductor regions and each of the electric field relief regions overlap, The plurality of overlapping ranges include a plurality of contact overlapping ranges (40a, 140a) in which the contact regions are provided, and a plurality of non-contact overlapping ranges (40b, 140b) in which the contact regions are not provided, The contact overlapping ranges and the non-contact overlapping ranges are alternately arranged in the first direction. Semiconductor device (10, 100, 300, 400).

2. The semiconductor device according to claim 1 , wherein the contact overlapping ranges and the non-contact overlapping ranges are alternately arranged in the second direction.

3. 3. The semiconductor device according to claim 1, further comprising an n-type upper drift region (42) between each of the electric field relief regions and the body region, the n-type upper drift region being in contact with the gate insulating film in each of the trenches below the body region.

4. an interlayer insulating film (28) covering the upper surface of the gate electrode and having a contact hole (28a) in an upper portion of the upper surface of the semiconductor substrate; an upper electrode (14) covering an area spanning an upper surface of the interlayer insulating film and an inner surface of the contact hole, contacting the upper surface of the semiconductor substrate within the contact hole, and insulated from the gate electrode by the interlayer insulating film; It also has The upper electrode is a tungsten-containing layer (14a) disposed within the contact hole; 4. The semiconductor device according to claim 1, further comprising an aluminum-containing layer (14b) covering the upper surface of the interlayer insulating film and an upper surface of the tungsten-containing layer.

5. A semiconductor substrate (12); A plurality of trenches (22) are provided on an upper surface (12a) of the semiconductor substrate, each of which extends in a first direction on the upper surface and is arranged at intervals in a second direction on the upper surface that intersects with the first direction; a gate insulating film (24) covering the inner surface of each of the trenches; a gate electrode (26) disposed in each of the trenches and insulated from the semiconductor substrate by the gate insulating film; Equipped with The semiconductor substrate is an n-type source region (30) exposed on the upper surface of the semiconductor substrate and in contact with the gate insulating film in each of the trenches; a p-type body (32) region in contact with the gate insulating film in each of the trenches below the source region; an n-type drift region (34) in contact with the gate insulating film in each of the trenches below the body region and separated from the source region by the body region; a plurality of p-type bottom regions (36) extending in the first direction so as to contact the gate insulating film at the bottom surface of the corresponding trench and contacting the drift region; a plurality of p-type first field relief regions (138), each disposed below the body region, each connected to the body region, each extending in the second direction, each contacting each of the bottom regions, and spaced apart in the first direction; a plurality of p-type second electric field relief regions (238), each of which is disposed below the body region, each of which is connected to the body region, each of which extends in a third direction intersecting the first direction and the second direction, each of which is in contact with each of the bottom regions, and each of which is spaced apart in a direction intersecting the third direction; a plurality of p-type contact regions (31), each of which is exposed on the upper surface of the semiconductor substrate and each of which is in contact with the body region; It has a semiconductor region located between the plurality of trenches is an inter-trench semiconductor region; When the semiconductor substrate is viewed in plan from above, there are a plurality of first overlapping ranges (140) in which each of the inter-trench semiconductor regions and each of the first electric field relief regions overlap, The plurality of first overlapping ranges include a plurality of first contact overlapping ranges (140a) in which the contact region is provided and a plurality of first non-contact overlapping ranges (140b) in which the contact region is not provided, the first contact overlapping ranges and the first non-contact overlapping ranges are alternately arranged in the first direction, When the semiconductor substrate is viewed in plan from above, there are a plurality of second overlapping ranges (240) in which the inter-trench semiconductor regions and the second electric field relief regions overlap each other; The plurality of second overlapping ranges include a plurality of second contact overlapping ranges (240a) in which the contact region is provided and a plurality of second non-contact overlapping ranges (240b) in which the contact region is not provided, The second contact overlapping range and the second non-contact overlapping range are alternately arranged in the first direction. A semiconductor device (200).

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