Semiconductor Device

Abstract

To provide a semiconductor element having excellent characteristics.SOLUTION: In a semiconductor element, a first intermetallic insulating film 108 that has a low-dielectric material with a dielectric constant lower than that of silicon oxide (SiO) is provided on a substrate 100. A first blocking film 110a containing oxide having a dielectric constant higher than that of the first intermetallic insulating film is provided on the first intermetallic insulating film. A metal wire 123 penetrating through the first intermetallic insulating film and the first blocking film is provided. A second blocking film 124 containing nitride is provided on upper surfaces of the metal wire and the first blocking film. Due to the provision of the first and second blocking films, outgassing of a material contained in the first intermetallic insulating film can be suppressed.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a wiring structure. [Background technology]

[0002] An interlayer insulating film between metal wirings of a semiconductor device is made of a low dielectric film to reduce parasitic capacitance. Some materials contained in the low dielectric film may be outgassed during high temperature processes, which may cause defects in the semiconductor device. Summary of the Invention [Problem to be solved by the invention]

[0003] An object of the present invention is to provide a semiconductor element having excellent characteristics. [Means for solving the problem]

[0004] A semiconductor device according to an embodiment of the present invention for achieving the above object is provided on a substrate, and includes a silicon oxide (SiO 2 A first intermetal insulating film is provided that includes a low-k material having a dielectric constant lower than that of the first intermetal insulating film. A first blocking film is provided on the first intermetal insulating film that includes an oxide having a dielectric constant higher than that of the first intermetal insulating film. A metal wiring is provided that penetrates the first intermetal insulating film and the first blocking film. Then, a second blocking film is provided on an upper surface of the metal wiring and the first blocking film that includes a nitride.

[0005] In addition, the semiconductor device according to the embodiment of the present invention for achieving the above object includes a silicon oxide (SiO 2A lower wiring structure is provided, the lower wiring structure including a lower intermetal insulating film including a low-k material having a dielectric constant lower than that of a first intermetal insulating film, and a lower metal wiring penetrating the lower intermetal insulating film and including a metal. A first intermetal insulating film including a low-k material having a dielectric constant lower than that of silicon oxide is provided on the lower wiring structure. A metal wiring penetrating the first intermetal insulating film is provided. A blocking film structure is provided on the first intermetal insulating film and the metal wiring, the first blocking film having a dielectric constant higher than that of the first intermetal insulating film, and a second blocking film having a dielectric constant higher than that of the first blocking film. A second intermetal insulating film is provided on the second blocking film, the second intermetal insulating film having a dielectric constant higher than that of the first intermetal insulating film. A via contact is provided penetrating the second intermetal insulating film and the second blocking film to contact the metal wiring.

[0006] Further, in a semiconductor device according to an embodiment of the present invention for achieving the above object, a lower structure including a transistor is provided on a substrate. 2 A first intermetal insulating film is provided, the first intermetal insulating film including a low dielectric material having a dielectric constant lower than that of the first intermetal insulating film. A metal wiring is provided penetrating the first intermetal insulating film. A blocking film structure is provided on the first intermetal insulating film and the metal wiring, the blocking film structure including a first blocking film having a dielectric constant higher than that of the first intermetal insulating film, and a second blocking film having a dielectric constant higher than that of the first blocking film. A second intermetal insulating film is provided on the blocking film structure. A via contact is provided penetrating the second intermetal insulating film and the second blocking film to contact the metal wiring. An upper metal pattern is provided on the via contact. An upper interlayer insulating film is provided to cover the upper metal pattern. Effect of the Invention

[0007] In the semiconductor device according to the present invention, the first and second blocking films are provided to suppress outgassing of materials contained in the low dielectric film, and therefore the semiconductor device can have excellent characteristics. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to the present invention. [Diagram 2] 2A to 2C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to the present invention. [Diagram 3] 3A to 3C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to the present invention. [Figure 4] 4A to 4C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to the present invention. [Diagram 5] 5A to 5C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to the present invention. [Figure 6] 6A to 6C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to the present invention. [Figure 7] 7A to 7C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to the present invention. [Figure 8] 8A to 8C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to the present invention. [Figure 9] 9A to 9C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to the present invention. [Figure 10] 10A to 10C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to the present invention. [Figure 11] FIG. 11 is a cross-sectional view for explaining a semiconductor device according to the present invention. [Figure 12] FIG. 12 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the present invention. [Figure 13] FIG. 13 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the present invention. [Figure 14] FIG. 14 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the present invention. [Figure 15] FIG. 15 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the present invention. [Figure 16] FIG. 16 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the present invention. [Figure 17] FIG. 17 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the present invention. [Figure 18] FIG. 18 is a cross-sectional view for explaining a semiconductor device according to the present invention. [Figure 19] FIG. 19 is a cross-sectional view for explaining a semiconductor device according to the present invention. [Figure 20] FIG. 20 is a cross-sectional view for explaining a semiconductor device according to the present invention. [Figure 21] FIG. 21 is a cross-sectional view for explaining a semiconductor device according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0010] 1 is a cross-sectional view illustrating a semiconductor device according to the present invention. As shown in FIG. 1, the semiconductor device includes a lower structure 105 formed on a substrate 100, a first intermetal insulating film 108 provided on the lower structure 105, a first wiring 123, a first blocking film 110a, a second blocking film 124, a second intermetal insulating film 126, a via contact 130, and a second wiring 132.

[0011] The substrate 100 includes silicon, germanium, silicon-germanium, or a III-V compound such as GaP, GaAs, GaSb, etc. The substrate 100 may also be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0012] The lower structure 105 is formed on the substrate 100 and includes, for example, a transistor, a capacitor, a resistor, a lower wiring 104, a lower interlayer insulating film 102, and the like.

[0013] On the lower structure 105, a BEOL wiring structure is provided.

[0014] The first intermetal insulating film 108 is formed on the lower structure 105 and is made of silicon oxide (SiO 2 ) includes a low-k material having a dielectric constant lower than that of silicon dioxide. Silicon dioxide has a dielectric constant of 3.9 to 4.5. The first intermetal insulating film 108 has a dielectric constant of 3.5 or less, for example, a dielectric constant of 2.0 to 3.5. The first intermetal insulating film 108 is silicon dioxide containing carbon and hydrogen (SiCOH). The first intermetal insulating film 108 further contains 10 to 50% carbon. As another example, the first intermetal insulating film 108 is fluorine-doped silicon dioxide (F-SiO2) or porous silicon dioxide.

[0015] A lower insulating film (not shown) may further be included between the lower structure 105 and the first intermetal insulating film 108. The lower insulating film may be silicon oxide, silicon nitride, or SiCN.

[0016] A first blocking film 110a is provided on the first intermetal insulating film 108. The first blocking film 110a includes an oxide having a higher dielectric constant than the first intermetal insulating film 108. The first blocking film 110a includes a silicon oxide having a dielectric constant of 3.9 to 4.5. The first blocking film 110a also includes a silicon oxide formed using TEOS (Tetraethyl orthosilicate) as a source.

[0017] The first blocking film 110a has a higher film density and strength than the first intermetal insulating film 108. Therefore, the first blocking film 110a can block some gas from escaping from the first intermetal insulating film 108 or blocking gas from flowing into the first intermetal insulating film 108. That is, the first blocking film 110a can block gas, such as hydrogen (H 2 ), water vapor (H 2 The first blocking film 110a is provided to prevent hydrogen or water vapor from entering the first intermetal insulating film 108.

[0018] In addition, the first blocking film 110a acts as an adhesive film that facilitates adhesion between the first intermetal insulating film 108 and the second blocking film 124.

[0019] The first blocking film 110a does not contain carbon (C). Carbon-containing carbonized films have a lower dielectric constant (k) and a higher carbon content than silicon nitride (SiN). Carbonized films have a lower density than silicon nitride films, and therefore allow substances outgassed from the first intermetal insulating film to pass through. For example, SiCN and SiCO are not suitable for the first blocking film 110a because they have difficulty blocking outgassing of hydrogen from the first intermetal insulating film.

[0020] The first wiring 123 penetrates the first intermetal insulating film 108 and the first blocking film 110 a and comes into contact with a part of the lower structure 105 .

[0021] The first wiring 123 includes a contact plug 120 and a conductive line 122. The contact plug 120 is in contact with a part of the lower structure 105, and the conductive line 122 is in contact with an upper surface of the contact plug 120 and extends in one direction. Although not shown, a plurality of contact plugs 120 are provided, and the conductive line 122 is in contact with the plurality of contact plugs 120 and has a shape extending in one direction parallel to the upper surface of the substrate 100.

[0022] The contact plug 120 and the conductive line 122 include a first metal having a first resistance. The first metal includes copper. The contact plug 120 and the conductive line 122 also include a first barrier pattern 116a and a metal pattern 118a. The first barrier pattern 116a is formed on a surface of the metal pattern 118a and includes titanium, titanium nitride, tantalum, or tantalum nitride.

[0023] In this manner, the first intermetal insulating film 108 containing a low dielectric material is provided between the first wirings 123 containing the first metal. Therefore, the parasitic capacitance generated by the first wirings 123 is reduced.

[0024] The top surfaces of the first wiring 123 and the first blocking film 110a are on the same plane. Therefore, the first blocking film 110a is provided on the upper sidewall of the first wiring 123. The first blocking film 110a contacts the upper sidewall of the conductive line 122.

[0025] Since the first wiring 123 is provided through the first intermetal insulating film 108 and the first blocking film 110a, the height of the first wiring 123 is the same as the sum of the thicknesses of the first intermetal insulating film 108 and the first blocking film 110a. Therefore, if the first blocking film 110a is thick, the thickness of the first intermetal insulating film 108 becomes relatively thin, and the parasitic capacitance between the first wirings 123 increases. The thickness of the first intermetal insulating film 108 is thicker than the thickness of the first blocking film 110a. The thickness of the first blocking film 110a is smaller than 20% of the sum of the thicknesses of the first intermetal insulating film 108 and the first blocking film 110a. In addition, the first blocking film 110a is preferably thicker than 100 Å in order to block outgassing from the first intermetal insulating film 108.

[0026] The second blocking film 124 covers the upper surface of the first wiring 123 and the first blocking film 110a.

[0027] The second blocking film 124 is formed by blocking gas, such as hydrogen (H 2 ), water vapor (H 2 The second blocking film 124 acts as a main blocking film for suppressing outgassing of oxygen, fluorine, chlorine, etc. That is, the second blocking film 124 has a better property of blocking outgassing of hydrogen or water vapor than the first blocking film 110a. The second blocking film 124 also acts as an etching stopper film and a diffusion prevention film for the first wiring 123.

[0028] The second blocking film 124 includes a nitride having a higher dielectric constant than the first blocking film 110a. Specifically, the second blocking film 124 includes a material having a dielectric constant of 6 or more. For example, the second blocking film 124 includes silicon nitride (SiN).

[0029] In addition, the second blocking film 124 does not contain carbon (C). Since the carbon film has a lower density than the silicon nitride film, it easily allows the substances outgassed from the first intermetal insulating film 108 to pass through it. Therefore, it is unsuitable as the second blocking film 124.

[0030] The second intermetal insulating film 126 is an interlayer insulating film provided between via contacts 130 located at the top of the BEOL wiring structure. The second intermetal insulating film 126 has a higher dielectric constant than the intermetal insulating film 108 located thereunder. The second intermetal insulating film 126 has a lower dielectric constant than the second blocking film 124.

[0031] That is, the second intermetal insulating film 126 includes an oxide having a higher dielectric constant than the first intermetal insulating film 108. The second intermetal insulating film 126 includes a silicon oxide having a dielectric constant of 3.9 to 4.5. As an example, the second intermetal insulating film 126 includes a silicon oxide formed using TEOS as a source. Therefore, the second intermetal insulating film 126 can have higher etch resistance, density, and bond strength than the first intermetal insulating film 108.

[0032] The via contact 130 penetrates the second intermetal insulating film 126 and the second blocking film 124 to contact the top surface of the first interconnect 123 .

[0033] The via contact 130 is a contact plug located at the top of a BEOL wiring structure. The via contact 130 includes a second metal different from a first metal. The second metal has a second resistance higher than the first resistance. The second metal includes a material formed at a higher temperature than the first metal. For example, the second metal can include a material formed at a temperature higher than 300° C. The second metal includes tungsten.

[0034] The via contact 130 also includes a second barrier film 130a and a metal plug 130b. The metal plug 130b includes tungsten, and the second barrier film 130a includes tungsten nitride.

[0035] The second wiring 132 is provided on the via contact 130 and the second intermetal insulating film 126. The second wiring 132 is in contact with the upper surface of the via contact 130 and has a shape extending in one direction. The second wiring 132 is located at the top of the wiring structure of the BEOL.

[0036] In addition, the second wiring 132 includes a third metal having a third resistance lower than the second resistance. The second wiring 132 formed at the top preferably includes a metal material that suppresses corrosion due to oxidation.

[0037] The third metal includes aluminum. When the surface of aluminum oxidizes, the aluminum oxide acts as an oxide film agent for the aluminum underneath. However, copper is easily oxidized, making it unsuitable for use as wiring formed on the topmost part.

[0038] Although not shown, an upper interlayer insulating film is provided to cover the second wiring 132. The upper interlayer insulating film includes silicon oxide. The upper interlayer insulating film may include silicon oxide including hydrogen.

[0039] In the semiconductor device, first and second blocking films 110a and 124 are provided on the low dielectric film located at the top of the BEOL wiring structure, i.e., the first intermetal insulating film 108. That is, the first blocking film 110a is provided on the upper sidewall of the copper wiring located at the top of the BEOL wiring structure, i.e., the first wiring 123, and the second blocking film 124 is provided on the upper surface of the copper wiring and on the first blocking film 110a. Therefore, the first and second blocking films 110a and 124 can prevent outgassing from the low dielectric film.

[0040] 2 through 10 are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to the present invention.

[0041] 2, a lower structure 105 is formed on a substrate 100. A first intermetal insulating film 108 is formed on the lower structure 105. A temporary first blocking film 110 is formed on the first intermetal insulating film 108.

[0042] The lower structure 105 includes, for example, a transistor, a capacitor, a resistor, a lower wiring 104, a lower interlayer insulating film 102, and the like.

[0043] Although not shown, a lower insulating film may be formed on the lower structure, The lower insulating film may include silicon oxide, silicon nitride, or SiCN.

[0044] The first intermetal insulating film 108 is made of silicon oxide (SiO 2 ) is deposited to form a low-k material having a dielectric constant lower than that of the first intermetal dielectric film 108. The first intermetal dielectric film 108 may also be silicon oxide containing carbon and hydrogen (SiCOH). For example, the first intermetal dielectric film 108 contains 10-50% carbon. As another example, the first intermetal dielectric film 108 is fluorine-doped silicon oxide (F-SiO2), a porous silicon oxide.

[0045] The temporary first blocking film 110 can be formed using an oxide having a higher dielectric constant than the first intermetal insulating film 108. The temporary first blocking film 110 is formed of silicon oxide having a dielectric constant of 3.9 to 4.5. The temporary first blocking film 110 can be formed to be thicker than the target first blocking film. The temporary first blocking film 110 can also be formed by chemical vapor deposition using TEOS as a deposition source.

[0046] The temporary first blocking film 110 is provided to prevent gases such as hydrogen or water vapor from entering or exiting the first intermetal insulating film 108. The temporary first blocking film 110 does not contain carbon (C).

[0047] 3, a first etching mask (not shown) is formed on the temporary first blocking film 110, and then the temporary first blocking film 110 and the first intermetal insulating film 108 are sequentially etched. As a result, a first contact hole 112 penetrating the temporary first blocking film 110 and the first intermetal insulating film 108 is formed. The first contact hole 112 is formed to expose an upper surface of a conductive film included in the lower structure, for example, the lower wiring 104. Thereafter, a sacrificial film (not shown) filling the first contact hole 112 is formed.

[0048] After forming a second etching mask (not shown) on the temporary first blocking film 110 and the sacrificial film, the temporary first blocking film 110 and the upper part of the first intermetal insulating film 108 are etched to form a first trench 114. The first trench 114 is formed to extend in one direction parallel to the upper surface of the substrate 100. The first trench 114 and the first contact hole 112 communicate with each other. Although not shown, a plurality of first contact holes 112 are formed, and the first trench 114 extends in communication with the plurality of first contact holes 112.

[0049] The steps of forming the first trench 114 and the first contact hole 112 may be reversed.

[0050] In performing the etching process, an etching gas, such as fluorine or chlorine, used in the etching process may be flowed into the first intermetal dielectric layer 108 .

[0051] 4, a first barrier film 116 is formed along the sidewalls and bottom surface of the temporary first blocking film 110, the first trench 114, and the first contact hole 112. A first metal film 118 is formed on the first barrier film 116 to completely fill the first trench 114 and the first contact hole 112.

[0052] The first barrier film 116 includes titanium, titanium nitride, tantalum, or tantalum nitride. The first metal film 118 includes a metal having a first resistance. The first metal film 118 is formed at a temperature lower than 300° C. For example, the first metal film 118 includes copper. The copper is formed by an electroplating process after forming a seed film (not shown). Also, after the electroplating process, another heat treatment process can be further performed.

[0053] Since the first barrier film 116 and the first metal film 118 are formed at a temperature lower than 300° C., outgassing from the first intermetal insulating film 108 hardly occurs in the process of forming the first barrier film 116 and the first metal film 118. Therefore, the first barrier film 116 and the first metal film 118 are formed in the first trench 114 and the first contact hole 112 without the occurrence of voids.

[0054] 5, the first metal film 118 and the first barrier film 116 are planarized to form a first barrier pattern 116a and a metal pattern 118a. As a result, a first wiring 123 including a contact plug 120 and a conductive line 122 is formed in the first contact hole 112 and the first trench 114. The planarization process is performed by a chemical mechanical polishing (CMP) process and / or an etch-back process.

[0055] The planarization process removes the upper portion of the temporary first blocking film 110 by a predetermined thickness, thereby forming the first blocking film 110a. In the planarization process, the upper surface of the first intermetal insulating film 108 is not exposed. Therefore, the first blocking film 110a is formed on the upper sidewall of the first interconnect 123. The upper surfaces of the first blocking film 110a and the first interconnect 123 are flush with each other.

[0056] The thickness of the first blocking film 110a is smaller than 20% of the sum of the thicknesses of the first intermetal insulating film 108 and the first blocking film 110a. The first blocking film 110a is preferably thicker than 100 Å in order to block outgassing of hydrogen from the first intermetal insulating film 108. The first blocking film 110a is interposed between a second blocking film to be formed later and the first intermetal insulating film 108, and serves as an adhesive film for adhering the second blocking film and the first intermetal insulating film 108.

[0057] 6, a second blocking film 124 is formed on the first blocking film 110a and the first wiring 123. A second intermetal insulating film 126 is formed on the second blocking film 124.

[0058] The second blocking film 124 serves as a main blocking film for preventing gases such as hydrogen or water vapor from entering and exiting the first intermetal insulating film 108. The second blocking film 124 is made of silicon nitride having a higher dielectric constant than the first blocking film 110a. On the other hand, the second blocking film 124 does not contain carbon (C).

[0059] The second intermetal insulating film 126 is formed using an oxide having a higher dielectric constant than the first intermetal insulating film 108. The second intermetal insulating film 126 is formed by depositing silicon oxide having a dielectric constant of 3.9 to 4.5. For example, the second intermetal insulating film 126 is formed by chemical vapor deposition using TEOS as a deposition source.

[0060] As shown in FIGS. 7 and 8, a via hole 128 exposing the upper surface of the first wiring 123 is formed by sequentially etching a portion of the second intermetal insulating film 126 and the second blocking film 124.

[0061] As shown in FIG. 7, the second blocking film 124 is exposed on the lower sidewall of the via hole 128, and the upper surface of the first wiring 123 is exposed on the bottom surface of the via hole 128.

[0062] 8, the via hole 128 may be misaligned and formed partially offset from the edge of the first interconnect 123. In this case, the second blocking film 124 is exposed at the lower sidewall of the via hole 128, and the first blocking film 110a and the upper surface of the first interconnect 123 are exposed at the bottom surface of the via hole 128.

[0063] However, the first intermetal insulating film 108 is not exposed at the bottom of the via hole 128. Therefore, in a later process, the substance contained in the first intermetal insulating film 108 is blocked by the first and second blocking films 110a, 124 and is not outgassed.

[0064] 9, a second barrier film 129a is formed on the surface of the via hole 128 and the second intermetal insulating film 126. A second metal film 129b is formed on the second barrier film 129a to fill the inside of the via hole 128. The second metal film 129b includes a metal material different from that of the metal pattern 118a.

[0065] The second barrier film 129a and the second metal film 129b can be formed at a temperature higher than the temperature for forming the first wiring 123. Specifically, the second barrier film 129a and the second metal film 129b are formed at a temperature higher than 300° C. The second metal film 129b has a second resistance higher than the first resistance. For example, the second barrier film 129a includes tungsten nitride, and the second metal film 129b includes tungsten. The tungsten nitride and tungsten are formed by chemical vapor deposition, atomic layer deposition, physical vapor deposition, or the like.

[0066] Since the second barrier film 129a and the second metal film 129b are formed at a temperature higher than 300° C., when the second barrier film 129a and the second metal film 129b are formed, the bonds of the material of the first intermetal insulating film 108 may be broken and outgassing may occur. For example, outgassing of hydrogen may occur from the first intermetal insulating film 108.

[0067] If outgassing occurs through the via hole 128, the deposition source gas for forming the second barrier film 129a and the second metal film 129b is prevented from reaching the via hole 128, making it difficult for the second barrier film 129a and the second metal film 129b to be formed normally.

[0068] However, the first and second blocking films 110a and 124 are provided on the first intermetal insulating film 108, and the first intermetal insulating film 108 is not exposed at the bottom of the via hole 128. Therefore, the substances (e.g., hydrogen, water vapor (H 2 It is possible to suppress outgassing of oxygen (O), fluorine, chlorine, etc.) through the via hole 128. Therefore, the second barrier film 129a and the second metal film 129b can fill the inside of the via hole 128 without generating voids.

[0069] 10, the second metal film 129b and the second barrier film 129a are planarized so as to expose the upper surface of the second intermetal insulating film 126. As a result, a via contact 130 including a second barrier pattern 130a and a metal plug 130b is formed in the via hole 128. The planarization process includes a chemical mechanical polishing process and / or an etch-back process.

[0070] A third metal film is formed on the via contact 130 and the second intermetal insulating film 136, and the third metal film is patterned to form a second wiring 132. The third metal film includes an aluminum film. The second wiring 132 is located at the top in the BEOL wiring structure.

[0071] Although not shown, an upper interlayer insulating film is provided to cover the second wiring 132. The upper interlayer insulating film contains silicon oxide. The upper interlayer insulating film contains hydrogen and serves as a film for supplying hydrogen.

[0072] 11 is a cross-sectional view for explaining a semiconductor device according to the present invention. In the semiconductor device shown in FIG. 11, the wiring structure of the BEOL includes multi-layer copper wiring.

[0073] 11, the semiconductor device includes lower structures 202, 204a, 204b, 205a, and 205b provided on a substrate 200, a first intermetal insulating film 208 provided on the lower structures, a first metal wiring 210, a first etching stop film 212, a second intermetal insulating film 214, a second metal wiring 220, a second etching stop film 222, a third intermetal insulating film 224, a third metal wiring 230, a first blocking film 232a, a second blocking film 234, a fourth intermetal insulating film 236, a via contact 240, and an upper wiring 242. A lower insulating film 206 is provided between the lower structures and the first intermetal insulating film 208. An upper interlayer insulating film 244 and a protective film 246 covering the upper wiring 242 are further provided.

[0074] The lower structures 202, 204a, 204b, 205a, 205b are formed on the substrate 200 by a front-end-of-line (FEOL) process for forming cells of a memory device. The lower structures include memory cells and peripheral circuits constituting a DRAM. For example, the lower structures include a transistor 202, a capacitor, a resistor, lower wirings 205a, 205b, and lower interlayer insulating films 204a, 204b. The lower interlayer insulating film 204b and the lower wirings 205b are exposed on the top surface of the lower structures. The lower interlayer insulating film 204b includes silicon oxide having a dielectric constant of 3.9 to 4.5.

[0075] A BEOL wiring structure is provided on the substructure.

[0076] A lower insulating film 206 is provided on the lower structure. The lower insulating film 206 is located on a lower sidewall of the bottom wiring of the BEOL. The lower insulating film 206 includes silicon oxide, silicon nitride, or SiCN.

[0077] A first intermetal insulating film 208 is provided on the lower insulating film 206. In addition, a first metal wiring 210 penetrating the first intermetal insulating film 208 and the lower insulating film 206 is provided.

[0078] The first intermetal insulating film 208 is made of silicon oxide (SiO 2 ) includes a low-k material having a dielectric constant lower than that of the first intermetal dielectric film 208. Also, the first intermetal dielectric film 208 is silicon oxide containing carbon and hydrogen (SiCOH). As another example, the first intermetal dielectric film 208 is fluorine-doped silicon oxide (F-SiO2) or porous silicon oxide.

[0079] The first intermetal insulating film 208 and the lower insulating film 206 include a trench. The first metal wiring 210 is located in the trench. The trench has a shape that extends in one direction.

[0080] The first metal wiring 210 includes a first barrier pattern 210a and a first metal pattern 210b. The first metal wiring 210 contacts the lower wiring 205b of the lower structure. The first barrier pattern 210a includes titanium, titanium nitride, tantalum, or tantalum nitride. The first metal pattern 210b includes copper.

[0081] A first etch stop layer 212 and a second intermetal dielectric layer 214 are provided on the first metal wiring 210 and the first intermetal dielectric layer 208 .

[0082] The first etch stop film 212 is in direct contact with the first intermetal dielectric film 208 and is therefore made of a material that easily adheres to the first intermetal dielectric film 208. The first etch stop film 212 includes a SiCN film. However, silicon nitride does not adhere well to the first intermetal dielectric film 208, making it difficult to directly adhere them. Therefore, silicon nitride is not suitable as a material for the first etch stop film 212.

[0083] The second intermetal insulating film 214 is made of silicon oxide (SiO 2 ) and the second intermetal dielectric film 214 includes the same material as the first intermetal dielectric film 208.

[0084] A second metal wiring 220 is provided penetrating the second intermetal insulating layer 214 and the first etch stop layer 212. The second metal wiring 220 is electrically connected to the first metal wiring 210.

[0085] The second metal wiring 220 includes a contact plug and a metal pattern. The contact plug contacts the first metal wiring 210, and the metal pattern extends in contact with an upper surface of the contact plug. The second metal wiring 220 includes a second barrier pattern 220a and a second metal pattern 220b. The second barrier pattern 220a includes titanium, titanium nitride, tantalum, or tantalum nitride. The second metal pattern 220b includes copper.

[0086] 1. However, both side walls of the lower part of the second metal wiring 220 are in contact with the first etch stop film 212. Also, the first blocking film is not provided on both sides of the upper part of the second metal wiring 220.

[0087] In this manner, the first etching stop film 212 formed between the first and second metal wirings 210, 220 includes a SiCN film. Since the second metal wiring 220 formed penetrating the first etching stop film 212 includes copper formed at a temperature lower than 300° C., outgassing from the first and second intermetal insulating films 208, 214 hardly occurs in the process of forming the second metal wiring 220. Therefore, the first etching stop film 212 can be used as a SiCN film having a lower dielectric constant than silicon nitride.

[0088] A second etch stop film 222 and a third intermetal dielectric film 224 are provided on the second metal wiring 220 and the second intermetal dielectric film 214. A first blocking film 232a is provided on the third intermetal dielectric film 224.

[0089] The second etch stop film 222 includes SiCN.

[0090] The third intermetal insulating film 224 is made of silicon oxide (SiO 2 ) The first blocking film 232a includes a low-k material having a dielectric constant lower than that of the first blocking film 232b. The first blocking film 232a includes silicon oxide having a dielectric constant of 3.9 to 4.5. The first blocking film 232a does not include carbon. The first blocking film 232a is the same as the first blocking film described in FIG. 1.

[0091] A third metal wiring 230 is provided penetrating the first blocking film 232a, the third intermetal insulating film 224, and the second etch stop film 222. The third metal wiring 230 includes a contact plug and a metal pattern. The third metal wiring 230 includes a third barrier film 230a and a third metal pattern 230b. The third barrier film 230a includes titanium, titanium nitride, tantalum, or tantalum nitride. The third metal pattern 230b includes copper. That is, the third metal wiring 230 has substantially the same structure as the second metal wiring 220. However, the first blocking film 232a is provided on both sides of the upper portion of the third metal wiring 230.

[0092] The third metal wiring 230 is the uppermost wiring among the wirings containing copper, and the third intermetal insulating film 224 is the uppermost low dielectric film in the BEOL wiring structure. That is, the first blocking film 232a is provided on the upper surface of the low dielectric film that is the uppermost in the BEOL wiring structure.

[0093] Although the above description has been given of the BEOL wiring structure including three-layered copper wiring, the number of layers of the copper wiring is not limited thereto. For example, an etch stop layer, an intermetal dielectric layer including a low dielectric material, and a metal wiring including copper may be further stacked on the third metal wiring 230 and the third intermetal dielectric layer 224. In this case, the first blocking layer 232a is not formed on the third intermetal dielectric layer, but is formed on the upper surface of the uppermost low dielectric layer.

[0094] The second blocking film 234 covers the upper surface of the third metal wiring 230 and the first blocking film 232a. The second blocking film 234 contains silicon nitride. The second blocking film 234 does not contain carbon. The second blocking film 234 is the same as the second blocking film described in FIG. 1.

[0095] In the semiconductor device, the upper sidewall of the third metal wiring 230 is covered by a first blocking film 232a, and the upper surface of the third metal wiring 230 is covered by a second blocking film 234. The first and second blocking films 232a and 234 can prevent outgassing from the third intermetal insulating film 224.

[0096] The fourth intermetal insulating film 236 is provided on the second blocking film 234. The fourth intermetal insulating film 236 has a dielectric constant higher than that of the third intermetal insulating film 224 and lower than that of the second blocking film 234. The fourth intermetal insulating film 236 has a higher etch resistance and bond strength than that of the third intermetal insulating film 224. The fourth intermetal insulating film 236 includes an oxide having a higher dielectric constant than that of the third intermetal insulating film 224. Specifically, the fourth intermetal insulating film 236 includes a silicon oxide having a dielectric constant of 3.9 to 4.5. The fourth intermetal insulating film 236 includes a silicon oxide formed using TEOS as a source.

[0097] The via contact 240 is a contact plug located at the top of the BEOL wiring structure. The via contact 240 penetrates the fourth intermetal insulating film 236 and the second blocking film 234 to contact the top surface of the third metal wiring 230. The via contact 240 is the same as that described in FIG.

[0098] In this manner, the fourth intermetal insulating film 236 having a higher dielectric constant than the lower low dielectric film is provided between the via contacts 240 located at the top of the BEOL wiring structure, thereby improving the reliability of the semiconductor device.

[0099] The upper wiring 242 is provided on the via contact 240 and the fourth intermetal insulating film 236. The upper wiring 242 is a metal pattern electrically connected to the via contact 240. The upper wiring 242 is the same as the second wiring in FIG.

[0100] An upper interlayer insulating film 244 is provided to cover the upper wiring 242. The upper interlayer insulating film 244 contains silicon oxide. Hydrogen is contained in the upper interlayer insulating film 244. For example, the upper interlayer insulating film 244 contains silicon oxide formed by the HDP-CVD process. The upper interlayer insulating film 244 serves as a film for supplying hydrogen to the surface of the substrate 100.

[0101] A protective film 246 is provided on the upper interlayer insulating film 244. The protective film 246 includes silicon nitride.

[0102] The first and second blocking films 232a, 234 can prevent water vapor or hydrogen from flowing into the third intermetal insulating film 224 when performing a process of supplying hydrogen to the surface of the substrate 100 through the first to third metal wirings and the upper wiring. Therefore, damage to the third intermetal insulating film 224 caused by the inflow of water vapor or hydrogen is suppressed, and the semiconductor device can have excellent characteristics.

[0103] 12 to 17 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the present invention.

[0104] The semiconductor element is the semiconductor element in Fig. 11, and can be manufactured by steps similar to those explained in Fig. 2 to Fig. 10. Therefore, the manufacturing method will be briefly explained.

[0105] 12, lower structures 202, 204a, 204b, 205a, and 205b are formed on a substrate 100. For example, the lower structures include a transistor 202, a capacitor, a resistor, lower wirings 205a and 205b, and lower interlayer insulating films 204a and 204b, etc. The lower structures are formed by a front-end-of-line (FEOL) process for forming cells of a memory device.

[0106] A lower insulating film 206 is formed on the lower structure. The lower insulating film 206 includes silicon oxide, silicon nitride, or SiCN.

[0107] A first intermetal insulating film 208 is formed on the lower insulating film 206. The first intermetal insulating film 208 is made of silicon oxide (SiO 2 ) is made of a low-dielectric material having a dielectric constant lower than that of the dielectric constant of the dielectric film.

[0108] A first trench is formed by etching a part of first intermetal insulating film 208 and lower insulating film 206. Lower wiring 205b included in the lower structure is exposed at the bottom surface of the first trench.

[0109] A first metal wiring 210 is formed in the first trench. Specifically, a first barrier film is formed on the first trench and the upper surface of the first intermetal insulating film 208, and a first metal film is formed on the first barrier film so as to fill the first trench. Thereafter, the first barrier film and the first metal film are planarized so that the upper surface of the first intermetal insulating film 208 is exposed, thereby forming the first metal wiring 210. Thus, the first metal wiring 210 includes a first barrier pattern 210a and a first metal pattern 210b.

[0110] 13, a first etch stop film 212 and a second intermetal dielectric film 214 are formed on the first metal wiring 210 and the first intermetal dielectric film 208. The first etch stop film 212 includes SiCN. The first etch stop film 212 is formed by chemical vapor deposition or atomic layer deposition. The second intermetal dielectric film 214 includes a low-k material having a dielectric constant lower than that of silicon oxide.

[0111] A second metal wiring 220 is formed to penetrate the second intermetal insulating layer 214 and the first etch stop layer 212 and to be electrically connected to the first metal wiring 210 .

[0112] Specifically, a part of the second intermetal insulating film 214 may be etched to form a second contact hole and a second trench. A second metal wiring 220 is formed to fill the inside of the second contact hole and the second trench. The second metal wiring 220 includes a second barrier pattern 220a and a second metal pattern 220b. The process of forming the second metal wiring 220 is substantially the same as the process of forming the first wiring described with reference to FIGS. 3 to 5. However, the first blocking film is not provided on the second intermetal insulating film 214.

[0113] As shown in FIG. 14, a second etch stop film 222, a third intermetal insulating film 224, and a temporary first blocking film 232 are formed on the second metal wiring 220 and the second intermetal insulating film 214. The second etch stop film 222 includes SiCN. The third intermetal insulating film 224 includes a low-k material having a lower dielectric constant than silicon oxide. The temporary first blocking film 232 is made of silicon oxide having a higher dielectric constant than the third intermetal insulating film 224. The process of forming the third intermetal insulating film 224 is the same as that of forming the first intermetal insulating film described in FIG. 2. The process of forming the temporary first blocking film 232 is the same as that of forming the temporary first blocking film described in FIG. 2.

[0114] As shown in FIG. 15, a third metal wiring 230 is formed penetrating the temporary first blocking film 232, the third intermetal insulating film 224, and the second etch stop film 222. The third metal wiring 230 includes a third barrier pattern 230a and a third metal pattern 230b. The process of forming the third metal wiring 230 is substantially the same as the process of forming the first wiring described in FIG. 3 to FIG. 5. By performing the process, the thickness of the temporary first blocking film 232 is further reduced to form a first blocking film 232a.

[0115] 16, a second blocking film 234 is formed on the first blocking film 232a and the third metal wiring 230. A fourth intermetal insulating film 236 is formed on the second blocking film 234. The second blocking film 234 includes silicon nitride. The fourth intermetal insulating film 236 is made of silicon oxide having a higher dielectric constant than the third intermetal insulating film 224.

[0116] A via contact 240 is formed through the fourth intermetal insulating film 236 and the second blocking film 234 to be electrically connected to the third metal wiring 230. The via contact 240 includes a fourth barrier pattern 240a and a fourth metal pattern 240b. An upper wiring 242 is formed on the via contact 240 and the fourth intermetal insulating film 236.

[0117] The processes for forming the second blocking layer 234, the fourth intermetal insulating layer 236, the via contact 240, and the upper wiring 242 are substantially the same as those described with reference to FIGS.

[0118] 17, an upper interlayer insulating film 244 is formed to cover the upper wiring 242. The upper interlayer insulating film 244 includes silicon oxide containing hydrogen. The upper interlayer insulating film 244 is a silicon oxide film formed by a HDP (high density plasma)-CVD process.

[0119] A protective film 246 is formed on the upper interlayer insulating film 244. The protective film 246 includes silicon nitride.

[0120] The substrate 200 on which the protective film 246 is formed is heat-treated. When the heat treatment process is performed, hydrogen contained in the upper interlayer insulating film 244 flows into the surface portion of the substrate 200 through the first to third metal wirings 210, 220, 230 and the upper wiring 242. The hydrogen flowing into the surface portion of the substrate 200 can remove trap sites or dangling bonds on the surface of the substrate 100 or in the gate insulating film. Therefore, the electrical characteristics of the transistor 202 formed on the substrate 200 are improved.

[0121] However, when the heat treatment process is performed, hydrogen or water vapor may easily flow into the third intermetal insulating film 224 containing a low dielectric material. In particular, the third intermetal insulating film 224 is easily damaged by plasma during the process of forming the upper interlayer insulating film. As a result, the third intermetal insulating film 224 easily absorbs moisture.

[0122] However, the first and second blocking films 232a and 234 can effectively prevent hydrogen or water vapor from flowing into the third intermetal insulating film 224. Therefore, defects caused by the flow of hydrogen or water vapor into the third intermetal insulating film 224 can be suppressed.

[0123] Fig. 18 is a cross-sectional view for explaining a semiconductor device according to the present invention. In the semiconductor device in Fig. 18, a lower blocking film having the same structure as the first and second blocking films is provided not only on the uppermost low dielectric film but also on at least one of the low dielectric films located below the uppermost low dielectric film in a BEOL wiring structure. The lower blocking film also serves as an etching stop film, so no separate etching stop film is formed. The semiconductor device in Fig. 18 is the same as the semiconductor device in Fig. 11 except for the blocking film.

[0124] 18, the semiconductor device includes a lower structure formed on a substrate 100, a first intermetal insulating film 208, a first metal wiring 210, a first lower blocking film 216, a second lower blocking film 218, a second intermetal insulating film 214, a second metal wiring 220, a first etching stop film 222, a third intermetal insulating film 224, a third metal wiring 230, a first blocking film 232a, a second blocking film 234, a fourth intermetal insulating film 236, a via contact 240, and an upper wiring 242. A lower insulating film 206 is provided on the lower structure. An upper interlayer insulating film 244 and a protective film 246 covering the upper wiring 242 are further provided.

[0125] The first lower blocking film 216 and the second lower blocking film 218 are provided on at least one of the copper interconnects located below the topmost copper interconnect.

[0126] The first lower blocking film 216 is provided on the first intermetal insulating film 208. The first lower blocking film 216 is provided on the upper sidewall of the first metal wiring 210. The first lower blocking film 216 includes the same material as the first blocking film described in FIG 1. The first lower blocking film 216 includes silicon oxide having a dielectric constant of 3.9 to 4.5.

[0127] A first metal wiring 210 penetrates the first lower blocking film 216, the first intermetal insulating film 209, and the lower insulating film 206 to contact a part of the lower structure.

[0128] The second lower blocking film 218 is formed on the first metal wiring 210 and the first lower blocking film 216. The second lower blocking film 218 includes the same material as the second blocking film described in FIG 1. The second lower blocking film 218 includes silicon nitride having a higher dielectric constant than the first lower blocking film 216.

[0129] 18, the first lower blocking film 216 and the second lower blocking film 218 are disposed on the first metal wiring 210. However, as an alternative example, the first lower blocking film 216 and the second lower blocking film 218 are disposed on the second metal wiring 220.

[0130] The first and second blocking films 232a and 234 are formed on the uppermost low dielectric film. That is, the first and second blocking films 232a and 234 are formed on the uppermost copper wiring. The first and second blocking films 232a and 234 are the same as the first and second blocking films described in FIGS. 1 and 11, respectively.

[0131] FIG. 19 is a cross-sectional view for explaining a semiconductor device according to the present invention. In the semiconductor device in FIG. 19, a blocking film having the same structure as the first and second blocking films is provided on all low dielectric films in a BEOL wiring structure. That is, a blocking structure in which the first and second blocking films are stacked is provided on the top of all copper wiring. The blocking film also serves as an etching stopper film, so no separate etching stopper film is formed. The semiconductor device in FIG. 19 is the same as the semiconductor device in FIG. 11 except for the blocking film.

[0132] 19, the semiconductor device includes a lower structure formed on a substrate 100, a first intermetal insulating film 208, a first metal wiring 210, a first lower blocking film 216, a second lower blocking film 218, a second intermetal insulating film 214, a second metal wiring 220, a third lower blocking film 226, a fourth lower blocking film 228, a third intermetal insulating film 224, a third metal wiring 230, a first blocking film 232a, a second blocking film 234, a fourth intermetal insulating film 236, a via contact 240, and an upper wiring 242. A lower insulating film 206 is provided on the lower structure. An upper interlayer insulating film 244 and a protective film 246 covering the upper wiring 242 are provided.

[0133] The first and third lower blocking films 216, 226 and the first blocking film include the same material as the first blocking film described in FIG.

[0134] The second and fourth lower blocking films 218, 228 and the second blocking film include the same material as the second blocking film described in FIG.

[0135] 20 is a cross-sectional view illustrating a semiconductor device according to the present invention, which is the same as the semiconductor device in FIG 11 except for the positions of the first and second blocking films in the BEOL wiring structure.

[0136] 20, the semiconductor device includes a lower structure provided on a substrate 200, a first intermetal insulating film 208 provided on the lower structure, a first metal wiring 210, a first etching stop film 212, a second intermetal insulating film 214, a second metal wiring 220, a second etching stop film 222, a third intermetal insulating film 224, a third metal wiring 230, a first blocking film 233, a second blocking film 235, a fourth intermetal insulating film 236, a via contact 240, and an upper wiring 242. A lower insulating film 206 is provided between the lower structure and the first intermetal insulating film 208. An upper interlayer insulating film 244 and a protective film 246 are provided to cover the upper wiring 242.

[0137] The first blocking film 233 is provided to cover the upper surfaces of the third intermetal insulating film 224 and the third metal wiring 230. The second blocking film 235 is provided on the first blocking film 233. That is, the first blocking film 233 is not located on the upper sidewall of the third metal wiring.

[0138] The first blocking film 233 contains the same material as the first blocking film described in Fig. 1. The second blocking film 235 contains the same material as the second blocking film described in Fig. 1. In this manner, at least two layers of blocking films are stacked on the uppermost low dielectric film, i.e., the third intermetal insulating film 224.

[0139] 21 is a cross-sectional view illustrating a semiconductor device according to the present invention, which is the same as the semiconductor device in FIG. 20 except that the semiconductor device in FIG. 21 further includes a first lower blocking layer and a second lower blocking layer in the BEOL wiring structure.

[0140] In the semiconductor device, a lower blocking film having the same structure as the first and second blocking films is provided on at least one of the low dielectric films located below the uppermost low dielectric film in the BEOL wiring structure, as well as on the uppermost low dielectric film. The lower blocking film also serves as an etch stop film, so no separate etch stop film is formed.

[0141] 21, the semiconductor device includes a lower structure formed on a substrate 100, a first intermetal insulating film 208, a first metal wiring 210, a first etching stopper film 212, a second intermetal insulating film 214, a second metal wiring 220, a first lower blocking film 225, a second lower blocking film 227, a third intermetal insulating film 224, a third metal wiring 230, a first blocking film 233, a second blocking film 235, a fourth intermetal insulating film 236, a via contact 240, and an upper wiring 242. A lower insulating film 206 is provided on the lower structure. An upper interlayer insulating film 244 and a protective film 246 are provided to cover the upper wiring 242.

[0142] The first and second lower blocking films 225, 227 are provided on at least one of the copper interconnects located below the uppermost copper interconnect.

[0143] The first lower blocking film 225 is provided to cover the upper surfaces of the second intermetal insulating film 214 and the second metal wiring 220. The second lower blocking film 227 is provided on the first lower blocking film 225.

[0144] The first lower blocking film 225 includes the same material as the first blocking film described in FIG 1. The second lower blocking film 227 includes the same material as the second blocking film described in FIG 1.

[0145] 21, the first lower blocking film 225 and the second lower blocking film 227 are disposed on the second metal wiring 220. However, as an alternative example, the first lower blocking film 225 and the second lower blocking film 227 are disposed on the first metal wiring 210.

[0146] The semiconductor element can also be applied to wiring structures used in the memory peripheral circuit regions or cell regions of volatile memory devices such as DRAM devices and SRAM devices, and non-volatile memory devices such as flash memory devices, PRAM devices, MRAM devices, and RRAM (registered trademark) devices.

[0147] Although the present invention has been described above with reference to exemplary embodiments, it will be understood that those skilled in the art can make various modifications and variations of the present invention without departing from the spirit and scope of the present invention as set forth in the following claims. [Explanation of symbols]

[0148] 100 Substrates 105 Substructure 108 First intermetal insulating film 123 First Wiring 110a, 232a First blocking film 124, 234 Second blocking membrane 126 Second intermetal insulating film 130, 240 via contact 132 Second Wiring 120 Contact plug 122 Conductive Line 208 First intermetal insulating film 210 First metal wiring 212 First etching stopper film 214 Second intermetallic insulating film 220 Second metal wiring 222 Second Etching Stop Film 224 Third intermetallic insulating film 230 Third metal wiring 236 Fourth Intermetallic Insulating Film 242 Upper Wiring

Claims

1. A silicon oxide (SiO 2 a first intermetal insulating film including a low-k material having a dielectric constant lower than that of the first intermetal insulating film; a first blocking film provided on the first intermetal insulating film and including an oxide having a higher dielectric constant than the first intermetal insulating film; a metal wiring passing through the first intermetal insulating film and the first blocking film; a second blocking film provided on an upper surface of the metal wiring and the first blocking film, the second blocking film including a nitride;

2. 2. The semiconductor device according to claim 1, wherein the first intermetal insulating film comprises silicon oxide containing carbon and hydrogen (SiCOH), silicon oxide doped with fluorine (F-SiO2), or porous silicon oxide.

3. 3. The semiconductor device according to claim 2, wherein the first intermetal insulating film contains 10 to 50% carbon.

4. 2. The semiconductor device according to claim 1, wherein the first intermetal insulating film has a thickness greater than a thickness of the first blocking film.

5. The first blocking film is made of silicon oxide (SiO 2 2. The semiconductor device according to claim 1 , comprising:

6. The first blocking film is a silicon oxide (SiO 2 6. The semiconductor device according to claim 5, comprising:

7. The semiconductor device of claim 1 , wherein the first blocking film comprises an insulating material having a dielectric constant of 3.9 to 4.

5.

8. The semiconductor device of claim 1 , wherein the second blocking film comprises an insulating material having a higher dielectric constant than the first blocking film.

9. 10. The semiconductor device of claim 1, wherein the second blocking film comprises carbon-free silicon nitride.

10. The semiconductor device according to claim 1 , wherein the metal wiring comprises copper.

11. 2. The semiconductor device of claim 1, wherein the metal wiring includes a contact plug and a metal pattern disposed on an upper surface of the contact plug, and the first blocking film contacts an upper sidewall of the metal pattern.

12. a second intermetal insulating film provided on the second blocking film and having a higher dielectric constant than the first intermetal insulating film; 2. The semiconductor device according to claim 1, further comprising a via contact penetrating the second intermetal insulating film and the second blocking film and contacting the metal wiring.

13. The semiconductor device of claim 12 , wherein the via contact comprises a metal material different from that of the metal wiring.

14. an upper metal pattern on the via contact, the upper metal pattern including a metal material different from that of the metal wiring; 13. The semiconductor device of claim 12, further comprising an upper interlayer insulating film covering the upper metal pattern.

15. Furthermore, between the substrate and the first intermetal insulating film, Silicon oxide (SiO 2 a lower intermetal insulating film including a low-k material having a dielectric constant lower than that of the first insulating film; a lower wiring structure including a lower metal wiring penetrating the lower intermetal insulating film; 2. The semiconductor device according to claim 1, wherein the lower wiring structure is formed of a single layer on the substrate, or a plurality of lower wiring structures are stacked on the substrate to form a multi-layer structure.

16. 16. The semiconductor device of claim 15, further comprising an etch stop layer including silicon carbonitride disposed on the lower intermetal insulating film and the lower metal interconnect so as to be interposed between the lower interconnect structures.

17. At least one portion among the portions between the lower wiring structures, a lower first blocking film on the lower intermetal insulating film, the lower first blocking film including an oxide having a higher dielectric constant than the first intermetal insulating film; 16. The semiconductor device of claim 15, further comprising a lower second blocking film that is in direct contact with the lower metal wiring and an upper surface of the lower first blocking film and includes a nitride.

18. Silicon oxide (SiO 2 a lower intermetal insulating film including a low dielectric material having a dielectric constant lower than that of the lower metal wiring, the lower intermetal insulating film penetrating the lower intermetal insulating film and including a metal; a first intermetal insulating film disposed on the lower wiring structure and including a low-k material having a dielectric constant lower than that of silicon oxide; a metal wiring that penetrates the first intermetal insulating film; a blocking film structure including a first blocking film provided on the first intermetal insulating film and the metal wiring, the first blocking film having a higher dielectric constant than the first intermetal insulating film, and a second blocking film having a higher dielectric constant than the first blocking film; a second intermetal insulating film provided on the second blocking film and having a higher dielectric constant than the first intermetal insulating film; a via contact penetrating the second intermetal insulating film and the second blocking film and contacting the metal wiring.

19. 20. The semiconductor device of claim 18, wherein the first blocking film comprises silicon oxide.

20. 20. The semiconductor device of claim 18, wherein the second blocking film comprises carbon-free silicon nitride.

21. 20. The semiconductor device according to claim 18, wherein the lower wiring structure is formed of a single layer or a plurality of lower wiring structures are stacked in a multi-layer structure.

22. 22. The semiconductor device of claim 21, further comprising an etch stop layer including silicon carbonitride disposed on the lower intermetal insulating film and the lower metal interconnect so as to be interposed between the lower interconnect structures.

23. a substructure on the substrate, the substructure including a transistor; A silicon oxide (SiO 2 a first intermetal insulating film including a low-k material having a dielectric constant lower than that of the first intermetal insulating film; a metal wiring that penetrates the first intermetal insulating film; a blocking film structure including a first blocking film provided on the first intermetal insulating film and the metal wiring, the first blocking film having a higher dielectric constant than the first intermetal insulating film, and a second blocking film having a higher dielectric constant than the first blocking film; a second intermetal insulating film provided on the blocking film structure; a via contact penetrating the second intermetal insulating film and the second blocking film and contacting the metal wiring; an upper metal pattern disposed on the via contact; an upper interlayer insulating film covering the upper metal pattern.

24. 24. The semiconductor device of claim 23, wherein the upper metal pattern comprises a different metal material than the metal wiring.

25. 24. The semiconductor device according to claim 23, wherein the upper interlayer insulating film contains silicon oxide containing hydrogen and is provided as a film for supplying hydrogen to the surface of the substrate.

Images