UTBB photodetector pixel units, arrays and methods

Abstract

This application discloses a UTBB photodetector pixel unit, array, and method. The UTBB photodetector pixel unit comprises a silicon film layer (15), a buried oxide layer (4), a charge collection layer (16), and a substrate (7), which are arranged in order from top to bottom. The silicon film layer (15) includes an NMOS or PMOS transistor. The charge collection layer (16) includes a charge collection control region (5) and a charge storage region (6), and the substrate (7) includes an N-type or P-type substrate. A centripetal field is formed around the charge storage region (6), and photo-generated charges are accumulated within the corresponding pixel unit under the action of the centripetal field. The existence of the centripetal field improves photoelectric conversion efficiency, suppresses crosstalk between pixels, and saves area and size reduction for shallow trench isolation, making the UTBB photodetector pixel unit more suitable for submicron pixels.

Description

[Technical field]

[0001] The present application relates to the field of silicon-based photodetectors, and in particular to UTBB photodetector pixel units, arrays and methods. [Background technology]

[0002] Photoelectric imaging detectors are widely used in military, medical, automotive, mobile devices, etc. At present, the mainstream photoelectric imaging detectors are charge-coupled devices (CCDs), photoelectric devices, and CMOS-APS photoelectric devices. CCD photoelectric devices perform direct light detection by charge transfer, while CMOS-APS photoelectric devices collect charges through the photodiodes of the pixel units, and then convert them into voltage signals to be amplified and read by CMOS circuits. The two photodetection devices each have their own advantages and disadvantages. However, due to the structural limitations of the devices themselves, the single pixel units of the two photodetectors contain device structures such as multiple transistors, so that the pixel size is limited to the order of micrometers and cannot be further reduced. The use of a single transistor such as an ultra-thin box and body (UTBB) structure can effectively reduce the pixel unit size of the photodetection unit. However, at present, the technical means of using the UTBB structure as an image sensor requires that they be separated by shallow trenches to suppress crosstalk between pixels, which limits the further reduction of the pixel unit. Summary of the Invention [Problem to be solved by the invention]

[0003] As discussed above, there is a need to provide a photodetector pixel unit, array and method that is small in size and capable of suppressing crosstalk. [Means for solving the problem]

[0004] The present application presents a UTBB photodetector pixel unit, array and method to solve the above problems.

[0005] In a first aspect, the present application provides a semiconductor device comprising a silicon film layer, a buried oxide layer, a charge collection layer, and a substrate, the silicon film layer, the buried oxide layer, the charge collection layer, and the substrate being disposed in order from top to bottom; the silicon film layer includes an NMOS transistor or a PMOS transistor; the charge collection layer includes a charge collection control region that forms a centripetal electric field to collect the photo-generated charges, and in which a lateral electric field and a vertical electric field that constitute the centripetal electric field act together to drift and collect the photo-generated charges, and a charge accumulation region in which the photo-generated charges collected by the charge collection control region are accumulated; the charge collection control region and the charge storage region are disposed in a joined state in a direction along a surface of the substrate; the buried oxide layer is disposed to cover the charge collection control region and the charge storage region; The substrate may include an N-type substrate or a P-type substrate of the same type as the charge collection control region. fruit, The channel of the NMOS transistor or the PMOS transistor is disposed on the charge storage region. A UTBB photodetector pixel unit, (However, this does not include a case where an isolation region is disposed around the charge collection control region and the charge storage region.) to provide.

[0006] Preferably, a source terminal and a drain terminal of the NMOS transistor are located on either side of the channel of the NMOS transistor, respectively, a gate terminal of the NMOS transistor is in the channel of the NMOS transistor, a source terminal and a drain terminal of the PMOS transistor are located on either side of the channel of the PMOS transistor, respectively, and a gate terminal of the PMOS transistor is in the channel of the PMOS transistor.

[0007] In a second aspect, the present application provides a photodetector pixel unit including a plurality of the photodetector pixel units, the plurality of the photodetector pixel units forming a photodetector array, wherein the number of rows and the number of columns of the photodetector array are both natural numbers of 2 or more. the law of nature, next The NMOS transistor or PMOS transistor of the adjacent photodetector pixel unit uses the same source terminal or drain terminal. A UTBB photodetector array is provided.

[0009] Preferably, the photodetector array includes a plurality of columns of word lines, a plurality of rows of bit lines, a common region electrode, and a common source, in which the source terminals of all the NMOS transistors or the source terminals of the PMOS transistors are connected to the common source, all the charge collection control regions of the charge collection layer are connected to the common region electrode, the gate terminals of the photodetectors of each column are connected to a corresponding word line, and the drains of the photodetectors of each row are connected to a corresponding bit line.

[0010] In a third aspect, the present application: For the UTBB photodetector pixel unit according to the first aspect, The corresponding voltage The above applied to the charge collection control region, The above It creates a centripetal electric field around the charge accumulation area, and the incident light The above A charge collecting layer and The above Photogenerated carriers are generated in the substrate, and the photogenerated carriers are drifted and collected by the action of the lateral electric field and the longitudinal electric field that constitute the centripetal electric field, and the collected photogenerated carriers are stored in a charge storage region under a buried oxide layer. A positive voltage is applied to the gate terminal and the drain terminal of the silicon film layer, and a corresponding voltage is applied to the gate terminal and the drain terminal of the silicon film layer. The above applying to a charge collection control region; The above The photogenerated carriers stored in the charge storage region change according to the intensity of light irradiation, thereby changing both the threshold voltage and the drain terminal current of the NMOS transistor or the PMOS transistor; The above A detection method for a UTBB photodetector pixel unit is provided, which includes measuring a drain terminal current of a silicon film layer above a buried oxide layer and evaluating light illumination intensity. Effect of the Invention

[0011] The advantage of the present invention is that by forming a centripetal electric field around the charge accumulation region, the photo-generated charges are accumulated in the corresponding pixel units under the action of the centripetal electric field. The existence of the centripetal electric field improves the photoelectric conversion efficiency, suppresses the crosstalk between pixels, saves the area of ​​the shallow trench isolation, and reduces the size, making it more suitable for sub-micron pixels. [Brief description of the drawings]

[0012] Various other advantages and merits will become apparent to those skilled in the art upon reading the following detailed description of the preferred embodiments. The drawings are used only for the purpose of illustrating the preferred embodiments and are not to be considered as limitations of the present application. Also, the same reference numerals are used to denote the same elements throughout the drawings.

[0013] [Figure 1] FIG. 1 is a structural diagram of a UTBB photodetector pixel unit provided by the present application. [Diagram 2] FIG. 2 is a structural diagram of the UTBB photodetector array provided by the present application. [Diagram 3] FIG. 3 is a step schematic diagram of the detection method of the UTBB photodetector pixel unit provided by the present application. [Figure 4] FIG. 4 is a MOS transistor transition characteristic curve diagram before and after light irradiation of the detection method of the UTBB photodetector pixel unit provided by the present application. [Diagram 5] FIG. 5 is a potential distribution diagram at the interface between adjacent P-type wells and N-type wells and a buried oxide layer before and after light irradiation in the detection method of the UTBB photodetector pixel unit provided by the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, exemplary embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. Although the drawings show exemplary embodiments of the present disclosure, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more complete understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0015] As shown in FIG. 1 , the UTBB photodetector pixel unit provided in the embodiment of the present application includes a silicon film layer, a buried oxide layer, a charge collection layer, and a substrate, in which the silicon film layer, the buried oxide layer, the charge collection layer, and the substrate are arranged in order from top to bottom, the silicon film layer includes an NMOS transistor or a PMOS transistor, the charge collection layer includes a charge collection control region and a charge accumulation region alternately arranged, and the substrate includes an N-type substrate or a P-type substrate.

[0016] The source terminal and drain terminal of the NMOS transistor are located on either side of the channel of the NMOS transistor, respectively, and the gate terminal of the NMOS transistor is in the channel of the NMOS transistor. The source terminal and drain terminal of the PMOS transistor are located on either side of the channel of the PMOS transistor, respectively, and the gate terminal of the PMOS transistor is in the channel of the PMOS transistor.

[0017] The channel lengths of the NMOS and PMOS transistors are between 20 and 100 nanometers, the source terminal lengths are between 20 and 90 nanometers, and the drain terminal lengths are between 20 and 90 nanometers.

[0018] The silicon film thickness of the silicon film layer is from 5 to 20 nanometers.

[0019] The buried oxide layer thickness is between 10 and 30 nanometers.

[0020] The depth of the charge collection layer is between 50 and 1000 nanometers.

[0021] The charge collection layer includes at least one charge storage region, i.e., each pixel unit necessarily includes one charge storage region for generating a centripetal electric field and storing the photo-generated charges.

[0022] The silicon film layer can be either all NMOS transistors or all PMOS transistors, and the use of NMOS or PMOS transistors does not affect the layout of other layers (e.g., charge collection control regions and charge storage regions alternating with charge collection layers) and the substrate (N-type substrate or P-type substrate).

[0023] The charge storage region and the charge collection control region can be adjusted in their lateral relative positions with respect to the MOSFET of the silicon film layer.

[0024] The structure of the charge collection layer is not limited to the alternating P-type well and N-type well structure, and the doping concentration and area of ​​the P-type well and N-type well can be adjusted respectively.

[0025] As shown in FIG. 1, for example, the silicon film layer uses an NMOS transistor, the charge collection control region is an N-type well, the charge storage region is a P-type well, and the substrate is an N-type substrate, so that each pixel unit necessarily includes one charge storage region, and the location of the charge storage region may or may not be at the center of the pixel unit.

[0026] In another embodiment of the present application, the charge collection control region in the charge collection layer may be a P-type well, while the charge storage region is an N-type well.

[0027] The charge collection control region and the charge storage region in the charge collection layer may further include materials having other structures, such as forming a heterojunction.

[0028] A PN junction consists of one N-type well and one P-type well in intimate contact.

[0029] As shown in Figure 1, a lateral PN junction is formed between the P-type well and the N-type well, and a vertical PN junction is formed between the P-type well and the N-type substrate, which act together to form a centripetal electric field as indicated by the arrow in Figure 1. Light is incident on the photodetector from above the device, generating photo-generated charges in the well and the substrate, which are then accumulated in the corresponding pixel units by the action of the centripetal electric field.

[0030] The P-type well and the N-type well can be exchanged, that is, a corresponding voltage is applied to the P-type well, and the photo-generated charges are collected by the N-type well. As shown in Figure 1, in order to make the P-type well generate a centripetal electric field, in this case, an N-type substrate is used to apply a voltage to the N-type well. If we want the N-type well to generate a centripetal electric field, we need to apply a voltage to the P-type well, and at the same time, we need to use a P-type substrate as the substrate.

[0031] Here, light is incident (irradiated) on the photodetector pixel unit from above and / or below.

[0032] The method of forming a centripetal electric field around the charge accumulation region includes, but is not limited to, forming alternating N-type wells and P-type wells in the charge collection layer as the charge collection control region and the charge accumulation region, respectively, forming a lateral PN junction between the P-type well and the N-type well, and forming a vertical PN junction between the P-type well and the N-type substrate, whereby the lateral PN junction and the vertical PN junction fields together form a centripetal electric field. The centripetal electric field can also be formed by forming other structures such as a heterojunction.

[0033] In a second aspect, the present application provides a UTBB photodetector array, as shown in FIG. 2, comprising a plurality of photodetector pixel units, the plurality of photodetector pixel units constituting a photodetector array, where the number of rows and the number of columns of the photodetector array are both natural numbers greater than or equal to 2.

[0034] The NMOS or PMOS transistors of adjacent photodetector pixel units use the same source or drain terminal. Figure 1 includes three pixel units, and the adjacent NMOS or PMOS transistors share the source and drain terminals.

[0035] The photodetector array includes multiple columns of word lines, multiple rows of bit lines, a common region electrode, and a common source, where the source terminals of all the NMOS transistors or the source terminals of the PMOS transistors are connected to the common source, all the charge collection control regions of the charge collection layer are connected to the common region electrode, the gate terminals of the photodetectors of each column are connected to their corresponding word lines, and the drains of the photodetectors of each row are connected to their corresponding bit lines.

[0036] The embodiment of the present application will be further described by taking the silicon film layer as an example for use in an NMOS transistor.

[0037] All NMOS transistor source terminals are connected to a common source Vs and set to 0 potential, all charge collection control regions (N-type wells in this example) in the substrate are connected to a common region electrode (common N-region electrode Vn), the gate terminals of the devices (photodetector pixel units) in each column are connected together to a word line, and the drain terminals of the devices in each row are connected together to a bit line. When the device is reset, all word lines are set to 0 potential, all bit lines are set to 0 potential, and the N-type wells are set to a negative potential. When collecting signals, all word lines and bit lines hold 0 potential, and the N-type wells are set to a positive potential. When reading signals, all bit lines are set to +Vdd, and the word lines of each column are selected in turn, the selected word line potential is set to +Vdd, and the signal current of each NMOS transistor is read by the bit line.

[0038] In a third aspect, the present application provides a detection method for a UTBB photodetector pixel unit, as shown in FIG. 3, comprising: applying a corresponding voltage to a charge collection control region, so that incident light generates photo-generated carriers in a charge collection layer and a substrate, and the photo-generated carriers enter a charge accumulation region under the action of a centripetal electric field, and are accumulated under a buried oxide layer S101; applying a positive voltage to a gate terminal and a drain terminal of a silicon film layer, and applying a corresponding voltage to the charge collection control region S102; the photo-generated holes accumulated in the charge accumulation region change according to the light irradiation intensity, so that the threshold voltage and the drain terminal current of the NMOS transistor or the PMOS transistor both change S103; measuring the drain terminal current of the silicon film layer above the buried oxide layer S104; and evaluating (measuring) the light irradiation intensity S105.

[0039] The voltage applied to the charge collection control region will vary depending on the actual structure and materials employed.

[0040] The embodiment of the present application will be further described by taking as an example that the silicon film layer uses an NMOS transistor, the charge collection control region is an N-type well, the charge storage region is a P-type well, and the substrate is an N-type substrate.

[0041] A positive voltage is applied to the charge collection control region of the charge collection layer, and the incident light generates photo-generated carriers in the charge collection layer and the substrate. The photo-generated carriers enter the charge storage region due to the action of the centripetal electric field and are accumulated under the buried oxide layer. A positive voltage is applied to the gate terminal and drain terminal of the silicon film layer, and a positive voltage is applied to the charge collection control region. The photo-generated carriers accumulated in the charge storage region change according to the light irradiation intensity, and the NMOS transistor threshold voltage and drain terminal current both change. The drain terminal current of the silicon film layer above the buried oxide layer is measured to evaluate the light irradiation intensity.

[0042] The embodiment of the present application will be further described by taking as an example that the silicon film layer uses an NMOS transistor, the charge collection control region is a P-type well, the charge storage region is an N-type well, and the substrate is an N-type substrate.

[0043] By applying a negative voltage to the charge collection control region of the charge collection layer, the incident light generates photo-generated carriers in the charge collection layer and the substrate, the photo-generated carriers enter the charge storage region due to the action of the centripetal electric field and are accumulated under the buried oxide layer, a positive voltage is applied to the gate terminal and drain terminal of the silicon film layer and a negative voltage is applied to the charge collection control region, the photo-generated carriers accumulated in the charge storage region change depending on the light irradiation intensity, and both the threshold voltage and the drain terminal current of the NMOS transistor change, and the drain terminal current of the silicon film layer above the buried oxide layer is measured to evaluate the light irradiation intensity.

[0044] Photogenerated holes and photogenerated electrons are generated when a semiconductor material is excited by light and are collectively called photogenerated carriers. The photogenerated carriers are separated by the self-generated electric field of the PN junction.

[0045] When a positive voltage is applied to the N-type well, the photogenerated holes enter the P-type well due to the action of the centripetal electric field.

[0046] The detection method of the embodiment of this application is mainly divided into three processes: reset, collect and read. Taking the silicon film layer as an example using NMOS transistors, the corresponding electrode bias conditions are shown in Table 1.

[0047] [Table 1]

[0048] In the reset stage, the source, drain and gate voltages of the MOS transistor are zero, and the MOS transistor is in the off state. A reset pulse signal Vreset is applied to the N-well terminal to bias the PN junction, and the bias current injects charge into the floating P-well, resetting the P-well voltage to the initial voltage.

[0049] In the collection phase, the device is exposed and the voltage at the N-well terminal is set to +Vdd to reverse bias the PN junction. Incident light creates photo-generated carriers at the PN junction towards the bottom of the device, where the photo-generated carriers are separated by the built-in electric field of the PN junction. Under the action of the centripetal electric field, the photo-generated holes enter the P-well and are accumulated under the buried oxide layer.

[0050] In the read stage, the optical signal is read by the MOSFET drain terminal current above the buried oxide layer. The NMOS transistor gate electrode (gate terminal) and drain electrode (drain terminal) are both set to a positive voltage. The photo-generated holes accumulated below the buried oxide layer increase the potential at the interface between the buried oxide layer and the substrate, which acts on the MOSFET device channel above the buried oxide layer, and the buried oxide layer forms a structure similar to a capacitor, which increases the reverse-type carriers in the NMOS transistor device channel and reduces the threshold voltage. As shown in Figure 4, under different light illumination intensities, the amount of positive charges accumulated in the substrate below the buried oxide layer is different, which results in different MOSFET device threshold voltages and different drain terminal currents. By measuring the MOSFET drain terminal current above the buried oxide layer, the light illumination intensity can be indirectly evaluated.

[0051] The MOSFET device transition characteristic curves before and after light irradiation are shown in FIG.

[0052] The potential distribution at the interface between the adjacent P-type well and N-type well and the buried oxide layer before and after light irradiation is shown in FIG.

[0053] In the embodiment of the present application, a centripetal electric field is formed around the charge accumulation region, and the photo-generated charges are accumulated in the corresponding pixel units by the action of the centripetal electric field. The charge collection control region and the charge accumulation region alternately arranged in the charge collection layer may be an N-type well (N-type doped region) and a P-type well (P-type doped region), and the N-type substrate or the P-type substrate included in the substrate forms a lateral PN junction between the P-type well and the N-type well, and a vertical PN junction between the P-type well and the N-type substrate, which jointly form a centripetal electric field, and the photo-generated charges are accumulated in the corresponding pixel units by the action of the centripetal electric field. The existence of the centripetal electric field improves the photoelectric conversion efficiency, suppresses the crosstalk between pixels, saves the area of ​​the shallow trench isolation, reduces the size, and makes it more suitable for sub-micron pixels. The centripetal electric field causes the charges to be actively accumulated in the corresponding pixel units, and the photo-generated charges accumulated downward in the buried oxide layer affect the electrical characteristics of the MOSFET by the backgate modulation effect. According to the photodetector array structure of UTBB and centripetal field, the array arrangement of the pixels of each row with shared source and drain avoids the shallow trench isolation and improves pixel density. Each pixel unit can complete the photosensitive function with only a single device, which can effectively reduce the pixel unit size. The centripetal field is used to collect the photo-generated charges, and the lateral and vertical fields work together to make the photo-generated electrons drift and accumulate under the buried oxide layer, and the centripetal field collects the photo-generated charges and suppresses crosstalk. The array arrangement of the shared source and drain can save the area of ​​the shallow trench isolation and is more suitable for sub-micron pixels.

[0054] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any modifications or replacements that are not conceivable through creative work shall be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope limited by the claims. [Explanation of symbols]

[0055] 1: Channel 2: Drain terminal 3: Source terminal 4: Buried oxide layer 5: Charge collection control region 6: Charge accumulation region 7: Substrate 8: Gate terminal 9: Channel length 10:Drain terminal length 11: Source terminal length 12: Silicon film thickness 13: Buried oxide thickness 14: Charge collection layer depth 15: Silicon membrane layer 16: Charge collection layer 17: Light

Claims

1. The semiconductor device includes a silicon film layer, a buried oxide layer, a charge collecting layer, and a substrate, the silicon film layer, the buried oxide layer, the charge collecting layer, and the substrate being disposed in order from top to bottom; the silicon film layer includes an NMOS transistor or a PMOS transistor; the charge collection layer includes a charge collection control region that forms a centripetal electric field to collect the photo-generated charges, and in which a lateral electric field and a vertical electric field that constitute the centripetal electric field act together to drift and collect the photo-generated charges, and a charge accumulation region in which the photo-generated charges collected by the charge collection control region are accumulated; the charge collection control region and the charge storage region are disposed in a joined state in a direction along a surface of the substrate; the buried oxide layer is disposed to cover the charge collection control region and the charge storage region; the substrate comprises an N-type substrate or a P-type substrate of the same type as the charge collection control region; A UTBB photodetector pixel unit, characterized in that the channel of the NMOS or PMOS transistor is disposed on the charge accumulation region (except for those in which an isolation region is disposed around the charge collection control region and the charge accumulation region).

2. The source terminal and the drain terminal of the NMOS transistor are located on both sides of the channel of the NMOS transistor, respectively, and the gate terminal of the NMOS transistor is located on the channel of the NMOS transistor; 2. The UTBB photodetector pixel unit of claim 1, wherein a source terminal and a drain terminal of the PMOS transistor are located on either side of a channel of the PMOS transistor, respectively, and a gate terminal of the PMOS transistor is on the channel of the PMOS transistor.

3. A plurality of UTBB photodetector pixel units according to claim 1 or 2, a plurality of said UTBB photodetector pixel units forming a photodetector array; wherein the number of rows and the number of columns of the photodetector array are both natural numbers of 2 or more; UTBB photodetector array, characterized in that the NMOS or PMOS transistors of adjacent UTBB photodetector pixel units use the same source or drain terminal.

4. the photodetector array includes a plurality of columns of word lines, a plurality of rows of bit lines, a common region electrode, and a common source; Here, the source terminals of all the NMOS transistors or the source terminals of all the PMOS transistors are connected to a common source, all charge collection control regions of the charge collection layer are connected to the common region electrode; The gate terminals of the photodetectors in each column are connected to a corresponding word line; 4. The UTBB photodetector array of claim 3, wherein the drain terminals of the photodetectors in each row are connected to a corresponding bit line.

5. 2. The UTBB photodetector pixel unit of claim 1, wherein: applying a corresponding voltage to the charge collection control region to generate a centripetal electric field around the charge storage region; incident light generates photo-generated carriers in the charge collection layer and the substrate; the photo-generated carriers are drifted and collected by the combined action of the lateral and vertical electric fields that constitute the centripetal electric field; and the collected photo-generated carriers are stored in the charge storage region under a buried oxide layer; applying a positive voltage to the gate and drain terminals of the silicon film layer and a corresponding voltage to the charge collection control region; The photogenerated carriers stored in the charge storage region change according to the intensity of light irradiation, thereby changing both the threshold voltage and the drain terminal current of the NMOS transistor or the PMOS transistor; measuring a drain terminal current of a silicon film layer above the buried oxide layer; and evaluating the light illumination intensity.

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