Semiconductor device and its manufacturing method

Abstract

To provide a semiconductor device capable of shortening an erasing time and suppressing deterioration of retention characteristics.SOLUTION: A semiconductor device MCP includes a semiconductor substrate SUB having a main surface MSF, a gate insulating film GIM formed over the main surface, and a gate electrode CGE formed on the gate insulating film, and the gate insulating film includes a first silicon nitride film NM1, and a first silicon oxide film OM1 disposed between the main surface and the first silicon nitride film and in contact with the first silicon nitride film. A Si-Si bond is formed at the boundary portion BR between the first silicon oxide film and the first silicon nitride film.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] 2. Description of the Related Art Conventionally, there is a semiconductor device provided with a nonvolatile semiconductor memory in which a gate insulating film is configured with a laminated film (ONO film) of a bottom oxide film, a nitride film, and a top oxide film (see, for example, Japanese Patent Application Laid-Open No. 2009-289823).

[0003] In a nonvolatile semiconductor memory, electrons are injected from the semiconductor substrate through the bottom oxide film into the nitride film during writing, and holes are injected from the semiconductor substrate through the bottom oxide film into the nitride film during erasing. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2009-289823 A Summary of the Invention [Problem to be solved by the invention]

[0005] In recent years, there has been a demand for non-volatile semiconductor memories to have lower write and erase voltages and shorter memory erase times. One way to achieve both of these simultaneously is to thin the bottom oxide film. This improves the efficiency of electron and hole injection from the semiconductor substrate to the nitride film.

[0006] However, when the thickness of the bottom oxide film is reduced, electrons injected into the nitride film tend to tunnel into the semiconductor substrate via the bottom oxide film, degrading data retention characteristics.

[0007] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0008] The semiconductor device according to the present embodiment includes a semiconductor substrate having a main surface, a gate insulating film formed on the main surface, and a gate electrode formed on the gate insulating film. The gate insulating film includes a first silicon nitride film and a silicon oxide film disposed between the main surface and the first silicon nitride film and in contact with the first silicon nitride film. Si-Si bonds are formed at the boundary between the silicon oxide film and the first silicon nitride film. Effect of the Invention

[0009] According to the semiconductor device of this embodiment, the erasing time can be shortened and the deterioration of the retention characteristics can be suppressed. [Brief description of the drawings]

[0010] [Figure 1] 1 is a plan view of a semiconductor device according to an embodiment of the present invention; [Diagram 2] 1 is a cross-sectional view showing a configuration of a nonvolatile memory of a semiconductor device according to an embodiment of the present invention. [Diagram 3] 3 is a partial enlarged view of the gate insulating film shown in FIG. 2. [Figure 4] FIG. 4 is a schematic diagram for explaining a Si—Si bond formed in the boundary between a bottom oxide film and a first silicon nitride film in the gate insulating film shown in FIG. 3. [Diagram 5] FIG. 4 is a schematic diagram for explaining a Si—Si bond formed in the boundary between a bottom oxide film and a first silicon nitride film in the gate insulating film shown in FIG. 3. [Figure 6] 1 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7] 4 is a flow chart showing a step of forming an insulating film portion to become a gate insulating film in a manufacturing method of a semiconductor device according to the present embodiment. [Figure 8] FIG. 11 is a schematic diagram for illustrating a termination of a first silicon oxide film in a step (S41) of the method for manufacturing a semiconductor device according to the present embodiment. [Figure 9]FIG. 11 is a schematic diagram for illustrating a termination of a first silicon oxide film in a step (S47) in a step (S42) of the method for manufacturing a semiconductor device according to the present embodiment. [Figure 10] FIG. 11 is a schematic diagram for explaining a termination of a first silicon oxide film in a step (S48) in a step (S42) of the method for manufacturing a semiconductor device according to the present embodiment. [Figure 11] FIG. 11 is a schematic diagram for illustrating a termination of the first silicon oxide film after step (S48) in the step (S42) of the method for manufacturing a semiconductor device according to the present embodiment. [Figure 12] 13 is a graph showing the results of thermal desorption analysis of H 2 O gas desorbed from the surface of the first silicon oxide film in a step (S48) of the manufacturing method of the semiconductor device according to the present embodiment. [Figure 13] 10 is a schematic diagram for illustrating a termination of a first silicon oxide film in a first state in a step (S43) of the method for manufacturing a semiconductor device in accordance with the present embodiment. FIG. [Figure 14] 10 is a schematic diagram for illustrating a termination of a first silicon oxide film in a second state achieved after a first state in a step (S43) of the method for manufacturing a semiconductor device according to the present embodiment. FIG. [Figure 15] 11 is a schematic diagram for illustrating a termination of the first silicon oxide film in a third state achieved after the second state in the step (S43) of the method for manufacturing a semiconductor device according to the present embodiment. FIG. [Figure 16] FIG. 1 is a schematic diagram for explaining a potential barrier formed at the boundary between a first silicon oxide film and a first silicon nitride film against holes injected from a semiconductor substrate into the first silicon nitride film during an erase operation of a semiconductor device according to an embodiment of the present invention. [Figure 17] 1 is an energy band diagram during an erase operation of the semiconductor device according to the present embodiment. FIG. [Figure 18] FIG. 1 is a schematic diagram for explaining a potential barrier formed at the boundary between a first silicon oxide film and a first silicon nitride film against electrons accumulated in the first silicon nitride film when no voltage is applied between a gate electrode and a semiconductor substrate of a semiconductor device according to an embodiment of the present invention. [Figure 19]2 is an energy band diagram when no voltage is applied between the gate electrode and the semiconductor substrate of the semiconductor device according to the present embodiment. FIG. [Figure 20] 4 is an energy band diagram during a write operation of the semiconductor device according to the present embodiment. FIG. [Figure 21] 11 is a graph showing the erasure time in the semiconductor device according to the present embodiment and the erasure time in the semiconductor device according to the comparative example. [Figure 22] 1 is a graph showing retention characteristics of a semiconductor device according to an embodiment and a semiconductor device according to a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, an embodiment will be described with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference numerals, and description thereof will not be repeated.

[0012] <Configuration of Semiconductor Device> As shown in FIG. 1, the semiconductor device MCP according to this embodiment includes a nonvolatile memory circuit NVM, a logic circuit LOG, and an input / output circuit IOC formed on a semiconductor substrate SUB.

[0013] The nonvolatile memory circuit NVM includes a plurality of memory cells. Each of the plurality of memory cells includes a MONOS type transistor MT shown in Fig. 2. The logic circuit LOG is, for example, a CPU (Central Processing Unit). The input / output circuit IOC is an interface for inputting write data and outputting read data between the transistor MT and an external device connected to the semiconductor device MCP.

[0014] <Configuration of transistor MT> As shown in FIG. 2, the transistor MT includes a semiconductor substrate SUB, a gate insulating film GIM, a gate electrode CGE, a sidewall spacer SW, an insulating film IF, interlayer insulating films IL1 and IL2, contact plugs CPG, and wiring ML.

[0015] The semiconductor substrate SUB has a main surface MSF. The semiconductor substrate SUB has a source region SR, a drain region DR, a well region WR, and an isolation region ISR. Each of the source region SR, the drain region DR, the well region WR, and the isolation region ISR is disposed on the main surface MSF. The semiconductor substrate SUB is, for example, a single crystal silicon (Si) substrate.

[0016] The source region SR has a first portion SR1 and a second portion SR2. The first portion SR1 is arranged so as to overlap with the sidewall spacer SW. When the main surface MSF is viewed in a plan view, the second portion SR2 is arranged outside the first portion SR1. The impurity concentration of the first portion SR1 is lower than the impurity concentration of the second portion SR2. The first portion SR1 is a lightly doped drain (LLD) for the second portion SR2.

[0017] The drain region DR is disposed at a distance from the source region SR in a direction along the main surface MSF. The drain region DR has a third portion DR1 and a fourth portion DR2. The third portion DR1 is disposed so as to overlap with the sidewall spacer SW. When the main surface MSF is viewed in a plan view, the fourth portion DR2 is disposed outside the third portion DR1. The impurity concentration of the third portion DR1 is lower than the impurity concentration of the fourth portion DR2. The third portion DR1 is a lightly doped drain (LLD) for the fourth portion DR2.

[0018] When the main surface MSF is viewed in plan, the well region WR is disposed so as to surround the source region SR and the drain region DR.

[0019] The source region SR and the drain region DR have a first conductivity type. The well region WR has a second conductivity type opposite to the first conductivity type. For example, the first conductivity type is n-type and the second conductivity type is p-type.

[0020] The gate insulating film GIM and the gate electrode CGE have the structure shown in Fig. 3. The details of the structures of the gate insulating film GIM and the gate electrode CGE will be described later.

[0021] The sidewall spacer SW is disposed on the sidewall of the gate electrode CGE. The sidewall spacer SW is disposed on the first portion SR1 of the source region SR and the third portion DR1 of the drain region DR. The material constituting the sidewall spacer SW is, for example, silicon nitride (Si 3 N 4 ).

[0022] The insulating film IF is disposed so as to cover the gate electrode CGE, the sidewall spacer SW, and the main surface MSF on which the gate electrode CGE and the sidewall spacer SW are not formed. The material constituting the insulating film IF is, for example, silicon nitride (Si 3 N 4 ).

[0023] The interlayer insulating film IL1 is disposed on the insulating film IF. The upper surface of the interlayer insulating film IL1 is flattened. The material constituting the interlayer insulating film IL1 is, for example, silicon oxide (SiO 2 ).

[0024] The contact plug CPG is embedded in a through hole penetrating the interlayer insulating film IL1 and the insulating film IF. The contact plug CPG is electrically connected to the second portion SR2 of the source region SR. The contact plug CPG is electrically connected to the second portion SR2, for example, via a silicide CNT1 disposed on the second portion SR2.

[0025] The wiring ML and the interlayer insulating film IL2 are disposed on the interlayer insulating film IL1. The wiring ML is electrically connected to the contact plug CPG. The interlayer insulating film IL2 is disposed around the wiring ML.

[0026] Next, the structures of the gate insulating film GIM and the gate electrode CGE will be described in detail with reference to Fig. 3. Note that in Fig. 3, structures other than the semiconductor substrate SUB, the gate insulating film GIM, and the gate electrode CGE are omitted from illustration.

[0027] The gate insulating film GIM includes a first silicon oxide film OM1, a first silicon nitride film NM1, a third silicon oxide film OM3, a second silicon nitride film NM2, and a second silicon oxide film OM2. The first silicon oxide film OM1, the first silicon nitride film NM1, the third silicon oxide film OM3, the second silicon nitride film NM2, and the second silicon oxide film OM2 are laminated in this order from the main surface MSF side.

[0028] The first silicon oxide film OM1 is the bottom oxide film. The second silicon oxide film OM2 is the top oxide film. The first silicon nitride film NM1 is sandwiched between the first silicon oxide film OM1 and the third silicon oxide film OM3. The second silicon nitride film NM2 is sandwiched between the third silicon oxide film OM3 and the second silicon oxide film OM2.

[0029] The thickness of the first silicon oxide film OM1 is, for example, thinner than the thickness of the second silicon oxide film OM2. As described above, the thinner the first silicon oxide film OM1, the lower the retention characteristic. Therefore, the thickness of the first silicon oxide film OM1 may be set so as to realize the required retention characteristic. For example, the thickness of the first silicon oxide film OM1 is 1 nm or more and 3 nm or less. The thickness of the first silicon nitride film NM1 is, for example, thicker than the thickness of the first silicon oxide film OM1. The thickness of the third silicon oxide film OM3 is, for example, thinner than the thickness of the first silicon oxide film OM1. The thickness of the second silicon nitride film NM2 is, for example, thicker than the thickness of the first silicon nitride film NM1. The thickness of the second silicon oxide film OM2 is, for example, thicker than the thickness of the first silicon nitride film NM1 and thinner than the thickness of the second silicon nitride film NM2.

[0030] The band gap of each of the first silicon oxide film OM1, the third silicon oxide film OM3, and the second silicon oxide film OM2 is larger than the band gap of each of the first silicon nitride film NM1 and the second silicon nitride film NM2. As a result, each of the first silicon nitride film NM1 and the second silicon nitride film NM2 acts as a storage film in which electrons are stored. Note that each of the third silicon oxide film OM3, the second silicon nitride film NM2, and the second silicon oxide film OM2, which are stacked on the first silicon nitride film NM1, may be made of another material as long as the above-mentioned relationship in size between the respective band gaps is satisfied.

[0031] The gate electrode CGE is disposed on the second silicon nitride film OM2. The gate electrode CGE is formed of, for example, polycrystalline silicon doped with impurities. The gate electrode CGE is electrically connected to a contact plug (not shown). The gate electrode CGE is electrically connected to the contact plug via, for example, a silicide CNT2. Depending on a voltage applied between the gate electrode CGE of the transistor MT and the semiconductor substrate SUB, the memory cell performs a write or erase operation. When the potential of the gate electrode CGE is set to a sufficiently large positive potential relative to the potential of the semiconductor substrate SUB, the memory cell performs a write operation. When the potential of the gate electrode CGE is set to a sufficiently large negative potential relative to the potential of the semiconductor substrate SUB, the memory cell performs an erase operation.

[0032] 4 and 5, Si-Si bonds and O-Si bonds are formed at the boundary between the first silicon oxide film OM1 and the first silicon nitride film NM1. The boundary between the first silicon oxide film OM1 and the first silicon nitride film NM1 is a region including the interface between the first silicon oxide film OM1 and the first silicon nitride film NM1. The Si-Si bond is formed by bonding a Si atom of the first silicon oxide film OM1 with a Si atom of the first silicon nitride film NM1. The O-Si bond is formed by bonding an O atom of the first silicon oxide film OM1 with a Si atom of the first silicon nitride film NM1.

[0033] In the gate insulating film GIM, the Si-Si bonds are formed only at the boundary portion BR. The Si-Si bonds are formed locally only at the boundary portion BR in the stacking direction of the gate insulating film GIM. The Si-Si bonds are formed discretely from each other in a direction perpendicular to the stacking direction of the gate insulating film GIM. The Si-Si bonds are adjacent to the O-Si bonds.

[0034] In the region of the boundary BR where the Si-Si bonds are formed, holes are more likely to be injected from the semiconductor substrate SUB into the first silicon nitride film NM1 during the erase operation than in the region where the O-Si bonds are formed. That is, in the region of the boundary BR where the Si-Si bonds are formed, the region acts as a point (hereinafter referred to as a hole-through point HTP) where holes are more likely to be injected during the erase operation. The potential barrier against holes at the hole-through point HTP is lower than the potential barrier against holes in the region where the O-Si bonds are formed.

[0035] At the boundary BR, the density of Si-Si bonds (unit: pcs / cm 2 ) is the density of O-Si bonds (unit: pcs / cm 2 ) is lower. The density of Si-Si bonds is calculated using a scanning tunneling microscope (STM) or an atom probe field ion microscope. Specifically, a scanning tunneling microscope (STM) or an atom probe field ion microscope is used to analyze the atomic arrangement of a cross section of the boundary portion BR along the stacking direction of the gate insulating film GIM, and the number of Si-Si bonds (linear density) is measured. The measured value is expanded to an area by calculation, and the areal density is calculated. In this way, the band gap near the interface of the first silicon oxide film OM1 becomes larger than the band gap of the first silicon nitride film NM1 (see Figures 17 and 19).

[0036] Preferably, the density of Si-Si bonds is 7×10 12 pieces / cm 2 The density of Si-Si bonds is 7×10 12 pieces / cm 2 When the Si-Si bond density exceeds 7×1012 pieces / cm 2 When the transistor MT (memory cell) is left standing, the electrons injected into the first silicon nitride film NM1 are more likely to escape, and the retention characteristics deteriorate, compared to when the Si-Si bond density is 7×10 12 pieces / cm 2 If this is the case, the ease with which electrons injected into the first silicon nitride film NM1 escape can be reduced to the same level as in a conventional semiconductor device in which no Si-Si bonds are formed and the thickness of the bottom oxide film is equivalent to the thickness of the first silicon oxide film OM1, thereby suppressing deterioration of the retention characteristics.

[0037] <Method of Manufacturing Semiconductor Device> As shown in FIG. 6, the method for manufacturing the semiconductor device MCP includes steps (S1) to (S11).

[0038] First, a semiconductor substrate SUB having a main surface MSF is prepared (step (S1)). The semiconductor substrate SUB is a silicon single crystal substrate.

[0039] Next, an element isolation region ISR is formed in the semiconductor substrate SUB (step (S2)). The element isolation region ISR is formed by, for example, a shallow trench isolation (STI) method or a local oxidation of silicon (LOCOS) method.

[0040] Next, a well region WR is formed in the semiconductor substrate SUB (step (S3)). The method of forming the well region WR includes a photolithography process and an ion implantation process. When forming a p-type well region WR, ions of a p-type impurity such as boron (B) are implanted. When forming an n-type well region WR, ions of an n-type impurity such as arsenic (As) are implanted.

[0041] Next, a laminate of insulating films to become the gate insulating film GIM is formed on the main surface MSF (step (S4)). This step (S4) includes steps (S41) to (S46) shown in FIG.

[0042] First, a first silicon oxide film OM1 is formed on the main surface MSF (step (S41)). The first silicon oxide film OM1 is formed, for example, by heating the main surface MSF in an atmosphere containing oxygen. In other words, the first silicon oxide film OM1 is, for example, a thermal oxide film. The surface of the first silicon oxide film OM1 formed in this step (S41) is terminated with O atoms, as shown in FIG. 8.

[0043] Next, a Si termination is formed on the surface of the first silicon oxide film OM1 (the upper surface opposite to the surface in contact with the main surface MSF) (S42). In other words, a state is realized in which the surface of the first silicon oxide film OM1 is terminated with Si atoms.

[0044] This step (S42) includes a step (S47) of forming OH termination on the surface of the first silicon oxide film OM1, and a step (S47) of heating the surface of the first silicon oxide film OM1 to remove H from the surface. 2 and a step (S48) of eliminating O.

[0045] In step (S47), the surface of the first silicon oxide film OM1 is exposed to at least one selected from the group consisting of hydrochloric acid / hydrogen peroxide (HPM), ammonia / hydrogen peroxide (APM), hydrofluoric acid (HF), a treatment liquid containing water, hydrogen plasma, hydrogen peroxide gas, and water vapor. The solution or atmosphere to which the surface of the first silicon oxide film OM1 is exposed can be selected from the above group depending on the density of Si-Si bonds to be formed at the boundary portion BR. In other words, the density of Si-Si bonds changes depending on the solution or atmosphere to which the surface of the first silicon oxide film OM1 is exposed in this step (S47). For example, the density of Si-Si bonds formed at the boundary portion BR when APM is used is higher than the density of Si-Si bonds formed at the boundary portion BR when HPM is used, and is lower than the density of Si-Si bonds formed at the boundary portion BR when HF is used.

[0046] On the surface of the first silicon oxide film OM1 that has been subjected to this step (S47), OH terminations terminated by OH groups are formed, as shown in Fig. 9. The density of the OH terminations on the surface of the first silicon oxide film OM1 can be calculated as the surface density of silanol groups calculated by a bromine-based coupling agent modification method.

[0047] In step (S48), the surface of the first silicon oxide film OM1 on which the OH terminations have been formed is heated. As a result, as shown in FIG. 10, one of two adjacent OH groups and an O atom in the other OH group are converted into H 2 The silicon atoms are desorbed as O gas. As a result, a Si termination terminated with Si atoms and an O termination terminated with O atoms are formed on the surface of the first silicon oxide film OM1, as shown in Fig. 11. The O termination is formed next to the Si termination.

[0048] The heating temperature in this step (S48) is, for example, 380° C. or higher and 550° C. or lower. Preferably, the heating temperature is 430° C. or higher and 520° C. or lower. FIG. 12 shows the H desorbed from the surface of the first silicon oxide film OM1 terminated with OH groups. 2 12 is a graph showing the results of a thermal desorption analysis of O gas. The horizontal axis of FIG. 12 is the heating temperature (unit: °C), and the vertical axis of FIG. 12 is the H 2 As shown in FIG. 12, when the heating temperature in this step (S48) is in the range of 380° C. or more and 550° C. or less, a relatively large amount of H 2 It was confirmed that O gas was desorbed from the surface of the first silicon oxide film OM1. The heating in this step (S48) can be performed, for example, as preheating for heating for forming the first silicon nitride film NM1 in the subsequent step (S43).

[0049] Next, a first silicon nitride film NM1 is formed on the surface of the first silicon oxide film OM1 so that Si is bonded to the Si terminations (step (S43)). The method for forming the first silicon nitride film NM1 is, for example, an atomic layer deposition (ALD) method. In this step (S43), dichlorosilane (SiH), which is included in the source gas for forming the first silicon nitride film NM1, is added to each of the Si terminations and O terminations formed on the surface of the first silicon oxide film OM1 in step (S42). 2 Cl 2 ) is supplied. As a result, as shown in FIG. 2 Cl 2 The Si in the SiO2 is bonded to the Si terminus, and hydrogen chloride (HCl) is released, forming Si-Si bonds on the surface as shown in FIG. 14. 2 Cl 2 ) bonds to the O terminus, and hydrogen chloride (HCl) is eliminated, forming Si—O bonds on the surface, as shown in FIG. 14.

[0050] In this step (S43), ammonia (NH 3 ) is supplied to the Si bonded to the Si terminal and the Si bonded to the O terminal, thereby forming a Si-N bond as shown in Fig. 15. In this manner, the first silicon nitride film NM1 is formed.

[0051] This step (S43) is performed, for example, continuously after step (S42) without exposing the surface of the first silicon oxide film OM1 to an atmosphere containing oxygen. This step (S43) is performed, for example, without lowering the temperature of the surface of the first silicon oxide film OM1 after step (S42). When the first silicon nitride film NM1 is formed by the ALD method, the heating temperature in this step (S43) can be set to 380° C. or more and 550° C. or less, similar to the previous step (S48).

[0052] Next, a third silicon oxide film OM3 is formed on the first silicon nitride film NM1 (step (S44)). The third silicon oxide film OM3 can be formed, for example, by exposing the upper surface of the first silicon nitride film NM1 to a treatment liquid containing water.

[0053] Next, the second silicon nitride film NM2 is formed on the third silicon oxide film OM3 (step (S45)). The method for forming the second silicon nitride film NM2 is, for example, the LPCVD method.

[0054] Next, a second silicon oxide film OM2 is formed on the second silicon nitride film NM2 (step (S46)). The method for forming the second silicon oxide film OM2 is, for example, the LPCVD-HTO (High Temperature Oxidation) method.

[0055] In this manner, in the step (S4), a laminate of insulating films is formed which will be processed into a gate insulating film GIM in the subsequent step (S6).

[0056] 6, next, a conductive film to be processed into a gate electrode CGE in a subsequent process (S6) is formed (step (S5)) on the laminate of insulating films formed in the process (S4). The method for forming the conductive film is, for example, a CVD method.

[0057] Next, the stack of insulating films and the conductive film formed in step (S5) are processed to form a gate insulating film GIM and a gate electrode CGE (step (S6)). The method of forming the gate insulating film GIM and the gate electrode CGE includes, for example, a photolithography process and an etching process.

[0058] Next, a first portion SR1 of the source region SR and a third portion DR1 of the drain region DR are formed on the main surface MSF of the semiconductor substrate SUB (step (S7)). The first portion SR1 and the third portion DR1 are formed, for example, by an ion implantation method using the gate electrode CGE as a mask. As a result, when the main surface MSF is viewed in plan, the first portion SR1 and the third portion DR1 are formed on the well region WR so as to sandwich the gate electrode CGE therebetween.

[0059] Next, sidewall spacers SW are formed on the main surface MSF of the semiconductor substrate SUB (step (S8)). The method of forming the sidewall spacers SW includes, for example, a film formation process, a photolithography process, and an etch-back process. As a result, the sidewall spacers SW are formed on parts of each of the first portion SR1 and the third portion DR1.

[0060] Next, the second portion SR2 of the source region SR and the fourth portion DR2 of the drain region DR are formed on the main surface MSF of the semiconductor substrate SUB (step (S9)). The method for forming the second portion SR2 and the fourth portion DR2 is, for example, an ion implantation method using the gate electrode CGE and the sidewall spacer SW as a mask. As a result, when the main surface MSF is viewed in a plan view, the first portion SR1 and the third portion DR1 are formed on the well region WR so as to sandwich the gate electrode CGE and the sidewall spacer SW therebetween.

[0061] Next, the silicides CNT1 and CNT2, the insulating film IF, the interlayer insulating film IL1, and the contact plug CPG are formed in this order (step (S10)). In this step (S10), first, the silicide CNT1 is formed on the second portion SR2 of the source region SR and the fourth portion DR2 of the drain region DR, and the CNT2 is formed on the gate electrode CGE. The method of forming the silicides CNT1 and CNT2 includes, for example, a metal film deposition process, an annealing process, and an etching process. Second, the insulating film IF and the interlayer insulating film IL1 are formed on the main surface MSF. The method of forming the insulating film IF and the interlayer insulating film IL1 includes, for example, a film deposition process, and a photolithography process and an etching process for forming a contact hole in the deposited stack. Third, the contact plug CPG is formed inside the contact hole. The method of forming the contact plug CPG includes, for example, a film deposition process, and an etch-back process or a chemical mechanical polishing (CMP) process.

[0062] Next, an interlayer insulating film IL2 and wiring ML are formed (step (S11)). In this step (S11), first, an interlayer insulating film IL2 is formed on the interlayer insulating film IL1. The method of forming the interlayer insulating film IL2 includes, for example, a film formation process, and a photolithography process and an etching process for forming wiring trenches in the formed insulating film. Second, wiring ML is formed in the wiring trenches of the interlayer insulating film IL2. The method of forming the wiring ML includes, for example, a film formation process, and an etch-back process or a CMP process.

[0063] In this manner, the transistor MT of the semiconductor device MCP shown in FIG. 2 is formed. <Effects> Next, with reference to FIGS. 16 to 22, the effects of the present embodiment will be described in comparison with a comparative example.

[0064] Fig. 16 is a schematic diagram for explaining a potential barrier formed between the first silicon oxide film OM1 and the first silicon nitride film NM1 against holes injected from the semiconductor substrate SUB into the first silicon nitride film NM1 during an erase operation. Fig. 18 is a schematic diagram for explaining a potential barrier formed between the first silicon oxide film OM1 and the first silicon nitride film NM1 against electrons stored in the first silicon nitride film NM1 during data retention.

[0065] 17, 19, and 20 show the semiconductor substrate SUB, the first silicon oxide film OM1, the first silicon nitride film NM1, the third silicon oxide film OM3, the second silicon nitride film NM2, and the second silicon oxide film OM2 of this embodiment, respectively, as a Si single crystal substrate, a SiO 2 , Si by ALD method 3 N 4 , SiO 2 , Si by LPCVD 3 N 4 , and SiO 2Fig. 17 is an energy band diagram when an erase voltage is applied between the gate electrode and the semiconductor substrate (hereinafter referred to as during an erase operation). Fig. 19 is an energy band diagram when the thickness of the first silicon oxide film is reduced and no voltage is applied between the gate electrode CGE and the semiconductor substrate SUB (hereinafter referred to as during data retention). Fig. 20 is an energy band diagram when a write voltage is applied between the gate electrode CGE of the transistor MT and the semiconductor substrate SUB (hereinafter referred to as during a write operation).

[0066] The comparative example differs from the present embodiment only in that no Si-Si bond, i.e., hole-through point HTP, is formed at the boundary between the first silicon oxide film and the first silicon nitride film of the gate insulating film. The thickness of the first silicon oxide film and the operating conditions such as the erase voltage and the write voltage are the same between the present embodiment and the comparative example. In the comparative example, the thickness of the first silicon oxide film needs to be thinned in order to increase the hole injection efficiency during the erase operation. On the other hand, if the thickness of the first silicon oxide film is thinned, electrons stored in the first silicon nitride film during data retention tend to tunnel to the semiconductor substrate through the first silicon oxide film, and the retention characteristics deteriorate.

[0067] On the other hand, in this embodiment, Si-Si bonds are formed at the boundary BR between the first silicon oxide film OM1 and the first silicon nitride film NM1, and these act as hole-through points HTP. Specifically, as shown in FIG. 16, in the region where the hole-through point HTP consisting of the Si-Si bonds is formed at the boundary BR, the potential barrier against holes injected from the semiconductor substrate SUB to the first silicon nitride film NM1 during the erase operation is locally lower than in other regions. This is because, as shown in FIG. 17, the band gap near the interface of the first silicon oxide film OM1 is smaller than the band gap inside the first silicon oxide film OM1 due to the formation of the hole-through point HTP. As a result, in this embodiment, the hole injection efficiency during the erase operation is higher than that of the comparative example. That is, in this embodiment, the hole injection efficiency during the erase operation is increased without reducing the thickness of the first silicon oxide film OM1.

[0068] On the other hand, as shown in Fig. 18, the potential barrier against electrons stored in the first silicon nitride film NM1 during data retention has the same height between the region where the hole-through point HTP is formed and other regions. This is because, as shown in Fig. 19, the band gap in the vicinity of the interface of the first silicon oxide film OM1 is larger than the band gap of the first silicon nitride film NM1.

[0069] As described above, according to the semiconductor device MCP of this embodiment, the erasing time can be shortened and the deterioration of the retention characteristics can be suppressed.

[0070] <Modification> The gate insulating film GIM of the semiconductor device MCP according to this embodiment includes, but is not limited to, a third silicon oxide film OM3 and a second silicon nitride film NM2 in addition to the first silicon oxide film OM1, the first silicon nitride film NM1, and the second silicon oxide film OM2. The gate insulating film GIM may be configured as a laminate in which only the first silicon oxide film OM1, the first silicon nitride film NM1, and the second silicon oxide film OM2 are laminated in order. In this case, too, it is sufficient that Si-Si bonds are formed at the boundary between the first silicon oxide film OM1 and the first silicon nitride film NM1.

[0071] <Evaluation results of erasure time> 21 is a graph showing the evaluation results of the erasing time of two examples of the semiconductor device according to the present embodiment, which are different from each other only in the density of the Si-Si bonds at the boundary portion BR. The horizontal axis of FIG. 21 represents the density of the Si-Si bonds (unit: pieces / cm 2 ), and the vertical axis of FIG. 21 is the erase time (unit: milliseconds). The density of Si-Si bonds in the first embodiment is 6.30×10 12 pieces / cm 2 and the density of the Si-Si bonds in the second embodiment is 5.45×10 12 pieces / cm 2 The threshold voltage was set to -1.25V. As shown in Fig. 21, the erase time in the first embodiment was reduced to less than half of the erase time in the second embodiment. In other words, it was confirmed that the Si-Si bond formed at the boundary portion BR acts as the hole-through point HTP.

[0072] <Evaluation results of retention characteristics> When the amount of electrons stored in the first silicon nitride film and the second silicon nitride film varies, the threshold voltage Vth of the memory cell varies. In this experiment, the retention characteristics were evaluated based on the variation in threshold voltage when the semiconductor device was left in an environment of 90° C. FIG. 22 is a graph showing the evaluation results of the retention characteristics of the semiconductor device according to this embodiment and the comparative example, which differs from this embodiment only in that no Si-Si bond is formed at the boundary between the first silicon oxide film and the first silicon nitride film. The horizontal axis of FIG. 22 is the leaving time (unit: seconds), and the vertical axis of FIG. 22 is the threshold voltage (unit: V). In FIG. 22, the white plots show the evaluation results of this embodiment, and the black plots show the evaluation results of the comparative example. As shown in FIG. 22, the white plots overlap with the black plots, and the retention characteristics of the semiconductor device according to this embodiment were equivalent to those of the comparative example. In other words, it was confirmed that the Si-Si bond formed at the boundary BR does not deteriorate the retention characteristics.

[0073] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0074] BR boundary portion, CGE gate electrode, CNT1, CNT2 silicide, CPG contact plug, DR drain region, DR1 third portion, DR2 fourth portion, GIM gate insulating film, HTP hole-through point, IF insulating film, IL1, IL2 interlayer insulating film, IOC input / output circuit, ISR element isolation region, LOG logic circuit, MCP semiconductor device, ML wiring, MSF main surface, MT transistor, NM1 first silicon nitride film, NVM nonvolatile memory circuit, OM1 first silicon oxide film, OM3 third silicon oxide film, SR source region, SR1 first portion, SR2 second portion, SUB semiconductor substrate, SW sidewall spacer, WR well region.

Claims

1. a semiconductor substrate having a main surface; a gate insulating film formed on the main surface; a gate electrode formed on the gate insulating film, the gate insulating film includes a first silicon nitride film, and a silicon oxide film disposed between the main surface and the first silicon nitride film and in contact with the first silicon nitride film; a Si-Si bond is formed at a boundary between the silicon oxide film and the first silicon nitride film, In the boundary portion, the density of the Si--Si bonds is lower than the density of the O--Si bonds.

2. At the boundary, the density of the Si-Si bonds is 7×10 12 pieces / cm 2 2. The semiconductor device according to claim 1, wherein:

3. 2. The semiconductor device according to claim 1, wherein the gate insulating film is a film formed by sequentially stacking a bottom oxide film made of the silicon oxide film, the first silicon nitride film, an insulating film formed on the first silicon nitride film, a second silicon nitride film formed on the insulating film, and a top oxide film.

4. forming a gate insulating film on a main surface of a semiconductor substrate; forming a gate electrode on the gate insulating film; The step of forming a gate insulating film includes: forming a silicon oxide film on the main surface; forming a Si termination on a surface of the silicon oxide film; forming a silicon nitride film on the surface so that Si bonds to the Si termination.

5. The step of forming the Si termination includes a step of forming an OH termination on the surface, and a step of heating the surface after the step of forming the OH termination to remove H from the surface. ２ The method for manufacturing a semiconductor device according to claim 4 , further comprising the step of:

6. The H ２ 6. The method for manufacturing a semiconductor device according to claim 5, wherein in the step of desorbing O, the surface is heated to 430° C. or more and 520° C. or less.

7. 5. The method for manufacturing a semiconductor device according to claim 4, wherein after the step of forming the Si termination, the step of forming the silicon nitride film is performed without exposing the surface to an atmosphere containing oxygen.

8. 5. The method for manufacturing a semiconductor device according to claim 4, wherein in the step of forming the Si termination, the surface is exposed to at least one selected from the group consisting of a treatment solution containing hydrochloric acid / hydrogen peroxide (HPM), ammonia / hydrogen peroxide (APM), hydrofluoric acid (HF), water, hydrogen plasma, hydrogen peroxide gas, and water vapor.

9. 5. The method for manufacturing a semiconductor device according to claim 4, wherein in the step of forming the silicon oxide film, the silicon oxide film is formed by heating the main surface in an atmosphere containing oxygen.

Images