Memory Cells and Memory Devices

Abstract

Memory cells and memory devices for storing one or more bits of information are provided. The memory cell (10) includes a semiconductor substrate (18) having a source terminal (12), a drain terminal (14), and a channel (16) extending between the source terminal (12) and the drain terminal (14). The memory cell (10) further includes a control gate (24) and a floating gate (26). The floating gate (26) is disposed between the control gate (24) and the channel (16). The floating gate (26) is electrically insulated from the control gate (24) and the channel (16) by a charge barrier and is configured to allow charge carriers to selectively enter and exit the floating gate (26) during write and erase operations, thereby providing at least first and second occupation states of the floating gate (26).

Description

[Technical field]

[0001] The present invention relates to memory cells and memory devices, and in particular to electronic memory devices that utilize a floating gate to store charge and thus data.

[0002] In modern times, society has become increasingly dependent on access to, and the manipulation and storage of, ever-increasing amounts of data, at ever-increasing speeds. Indeed, the ability to access large amounts of robustly stored data at high speeds is crucial in many industries. It is also highly desirable for individuals, for example when accessing the Internet. Access to information can foster freedom of choice, improve efficiency, drive innovation and economic development, and overall lead to improved quality of life.

[0003] Memory devices are typically semiconductor-based integrated circuits used by computers or other electronic devices. There are many different types of memory, including random access memory (RAM), read-only memory (ROM), non-volatile floating gate NOR / NAND flash memory, and dynamic random access memory (DRAM).

[0004] Flash memory is a semiconductor device that utilizes an electrically isolated floating gate in which an electric charge is selectively stored. A conventional flash memory cell includes a semiconductor substrate (usually silicon) that is doped to form isolated source and drain terminals. A control gate terminal is also provided, and an electrically isolated floating gate is disposed between the control gate and the substrate. A voltage applied to the control gate, greater than a threshold voltage, allows current flow along a conductive channel, also known as an inversion layer, in the semiconductor substrate between the source and drain terminals.

[0005] When a charge is located in the floating gate, it partially shields the control gate from the channel, thereby increasing the magnitude of the threshold voltage, i.e. the voltage at the control gate required for current to flow through the channel. Thus, there are at least two states of the device: one in which charge is held on the floating gate and the device has a first threshold voltage, and one in which charge is not held on the floating gate and the device has a second, lower threshold voltage. The state can be determined by applying an intermediate voltage to the control gate, i.e. a voltage that lies between the first and second threshold voltages, and sensing the flow of current in the channel. The two states can be considered as bits, and thus the presence or absence of charge in the floating gate can provide the memory function of the device.

[0006] By electrically insulating the floating gate, which is usually achieved by placing an oxide layer between the channel and the floating gate, and between the control gate and the floating gate, charge can be held within the floating gate for a very long time without risk of being removed from the floating gate. Flash memory is thus a non-volatile form of memory that allows for robust storage of data. Summary of the Invention [Problem to be solved by the invention]

[0007] Flash memory devices can be configured as enhancement mode devices or depletion mode devices. In enhancement mode devices, a conductive channel is induced by applying a gate voltage to the device, whereas depletion mode devices already have a pre-existing conductive channel that can be made non-conductive by applying a gate voltage. Thus, enhancement mode devices remain insulating when no gate voltage is applied, whereas depletion mode devices are conductive when no gate voltage is applied and therefore have fewer useful applications. Enhancement mode devices preferably allow single-bit addressing within an array.

[0008] It is also desirable to maximize the enhancement of the channel conductivity in response to an applied gate voltage, thereby reducing the voltage required to operate the memory device. Conventionally, this is accomplished by spatially doping the channel laterally, i.e., to reduce the intrinsic conductivity of the channel before the gate voltage is applied. However, spatially doping the channel laterally is technically challenging.

[0009] SUMMARY OF THE DISCLOSURE A memory cell has now been devised that overcomes or substantially mitigates the above-referenced and / or other disadvantages associated with the prior art. [Means for solving the problem]

[0010] According to a first aspect of the invention, a memory cell is provided for storing one or more bits of information. The memory cell comprises a semiconductor substrate provided with a source terminal, a drain terminal, and a channel extending between the source terminal and the drain terminal. The memory cell further comprises a control gate and a floating gate. The floating gate is disposed between the control gate and the channel, electrically insulated from the control gate and the channel by a charge barrier, and configured to allow selective passage of charge carriers into and out of the floating gate during write and erase operations, providing at least first and second occupancy states of the floating gate. The channel is configured to provide a minimum threshold voltage applied between the control gate and the substrate to introduce charge carriers from the semiconductor substrate into the channel and make the channel conductive. The minimum threshold voltage depends on the occupancy state of the floating gate. A read voltage may be applied between the control gate and the substrate to provide a conductive channel for the first occupancy state of the floating gate and a non-conductive channel for the second occupancy state of the floating gate.

[0011] A memory cell according to the invention is advantageous primarily because the memory cell is arranged to provide a minimum threshold voltage applied between the control gate and the substrate that will introduce charge carriers from the substrate into the channel to make it conductive, which allows the channel to be made non-conductive with zero applied voltage without the need for lateral spatial doping, thus allowing single-bit addressing of the cells in the array.

[0012] The memory cell may have a heterojunction at the interface between the channel and the semiconductor substrate, where the lowest energy level at which charge carriers can exist in the conduction band of the channel has a higher energy than the valence band of the semiconductor substrate, and thus the channel may be unoccupied by charge carriers in the absence of an applied electric field.

[0013] The channel may include a well. The well may include one or more internal states to which and from which charge carriers may pass. The one or more internal states may be confined internal states. The one or more confined internal states may be discrete energy levels. The well may be formed by appropriate selection of bulk semiconductor material. For example, the well may be formed in indium gallium asphide (InGaAs) that has an intentionally higher gallium (Ga) composition.

[0014] The channel may include a quantum well. The quantum well may have discrete internal energy levels for accommodating charge carriers within the channel. The quantum well may be defined between a charge barrier and a semiconductor substrate. The quantum well of the channel may be formed by a layer of semiconductor that defines the channel, which may be thin enough that the energy levels of the charge carriers are quantized.

[0015] A quantum well can be formed by a channel having an offset conduction band and / or offset valence band to form a heterojunction at the interface between the channel and the charge barrier and / or between the channel and the semiconductor substrate. The offset conduction band and / or offset valence band of the channel can be achieved by selecting different semiconductors for the adjacent layers, thereby defining a quantum well in the conduction band and / or valence band. That is, the offset conduction band and / or offset valence band of the channel can be achieved by forming the channel in a semiconductor different from the semiconductor(s) used to form the charge barrier and the semiconductor substrate. When the charge barrier and / or the semiconductor substrate include two or more semiconductors, the offset conduction band and / or offset valence band of the channel may be achieved by forming the channel in a semiconductor different from the semiconductor used for the adjacent layers of the charge barrier and / or the semiconductor substrate.

[0016] Thus, the channel may be formed by placing a narrow bandgap semiconductor between two wide bandgap semiconductors, thereby providing a heterojunction structure. That is, the channel may be formed by the narrow bandgap semiconductor and the charge barrier and / or adjacent layers of the semiconductor substrate may be formed by the wide bandgap semiconductor. "Bandgap" means the energy gap between the valence band and the conduction band of a semiconductor.

[0017] The semiconductor of the channel may be formed of any semiconductor that provides the charge barrier and the necessary barrier potential relative to the semiconductor substrate, e.g., the necessary heterojunction. In a currently preferred embodiment, the semiconductor comprises a III-V semiconductor, or an alloy of III-V semiconductors. For example, the channel may be formed of a compound in which 50% or more of the group III atoms are In and 50% or more of the group V atoms are N or As, e.g., In where the substrate is GaSb. x Ga1- x It may contain As.

[0018] Between the channel and the charge barrier Between The heterojunction may be a type II heterojunction or a type III heterojunction. The heterojunction between the channel and the substrate is ,blood A type III heterojunction, i.e., a break-gap heterojunction, is one in which the bandgap of the channel does not overlap with the bandgap of the substrate, or at least does not overlap with the bandgap of an adjacent layer of the semiconductor substrate. Nevertheless, at zero applied bias, the lowest internal energy level of the channel may have a higher energy than the valence band of the substrate.

[0019] The channel may include one or more quantum dots, quantum wires, or quantum wells. nothing. However, conventional integrated devices are built in layers, and fabrication techniques exist that provide heterojunctions with smooth interfaces and very few defects, so the use of quantum wells results in less cell-to-cell variability.

[0020] The discrete energy levels of the channel may correspond to one or more confined internal states into which charge carriers can enter and exit. The lowest confined internal state of the channel may have an energy higher than the valence band energy of the semiconductor substrate at zero applied bias. The lowest confined internal state of the channel may have an energy higher than the Fermi energy of the semiconductor substrate at zero applied bias. Thus, the channel may be devoid of charge carriers at zero applied bias, i.e., unoccupied, since charge carriers do not flow into the quantum well. That is, the quantum well, i.e., the channel, may be non-conducting, i.e., insulating, at zero applied bias.

[0021] Applying an electric field across the memory cell can modify the morphology of the channel and / or the energy of the charge carriers in the semiconductor substrate, resulting in an increase in the transmission coefficient of the charge carriers in the semiconductor substrate. The shape and / or size of the potential barrier can be modified, for example, the potential barrier can become tilted across the applied electric field. In particular, the increase or decrease in the height of the potential barrier can be proportional to its distance across the applied electric field. This application of an electric field is commonly referred to as a lever voltage.

[0022] In response to the application of an electric field, i.e., an applied bias, the lowest confined internal state of the channel may have an energy lower than the valence band energy of at least a portion of the semiconductor substrate. Thus, charge carriers may flow into the channel from the semiconductor substrate in response to the application of an electric field. Thus, the channel may become occupied, i.e., conductive, in response to the application of an electric field. Charge carriers may move into the channel from the semiconductor substrate by tunneling.

[0023] At least one of the charge barriers may be a charge trapping barrier which, in use, allows selective passage of charge carriers into the floating gate to modify one or more bits of information stored by the memory cell. The charge barrier to one side of the floating gate may be a charge trapping barrier and the charge barrier to the other side of the floating gate may be a charge blocking barrier that does not allow passage of charge carriers therethrough. In a currently preferred embodiment, the charge trapping barrier is disposed between the channel and the floating gate such that, upon application of a write voltage, charge carriers introduced into the floating gate pass from the substrate through the channel and into the floating gate.

[0024] The charge trapping barrier may be adapted to selectively allow charge carriers to pass into the floating gate in use to modify one or more bits of information stored by the memory cell. The charge trapping barrier may be adapted to selectively allow charge carriers to pass into the floating gate in response to application of an electric field across the memory cell. The charge trapping barrier may have any form that allows charge carriers to selectively pass into the floating gate. The charge trapping barrier may include at least one potential barrier that allows charge carriers to selectively pass into the floating gate, for example by controlling the energy of the charge carriers and / or by controlling the shape and / or size of the at least one potential barrier. The selective passage of charge carriers into the floating gate may be made possible by exploitation of quantum mechanical effects. In particular, the energy of the charge carriers penetrating the at least one potential barrier may be less than the height of the at least one potential barrier. The passage of charge carriers into the floating gate may be by quantum tunneling, also called wave mechanical tunneling, and thus the charge trapping barrier may be a quantum tunneling barrier.

[0025] The charge trapping barrier may include at least one potential barrier having a resonance energy less than the potential barrier height, which allows the charge carriers to pass to the floating gate. The transmission coefficient of the charge carriers at the resonance energy may exhibit a peak compared to the transmission coefficients at adjacent energies. The transmission coefficient at the resonance energy may be orders of magnitude greater than the transmission coefficients at adjacent energies. The passage of the charge carriers to the floating gate may be by resonant tunneling, and thus the charge trapping barrier may be a resonant tunneling barrier.

[0026] Resonant tunneling allows for fast write and erase speeds, for example in the region of 1 ns, such as less than 10 μs, less than 1 μs, less than 500 ns, or less than 100 ns for each write and / or erase operation.

[0027] The charge trapping barrier may include at least one potential barrier that allows selective interband passage of charge carriers into the floating gate, for example between the conduction band and the valence band. Thus, the charge trapping barrier may include a pn junction, for example a highly doped pn junction. However, it is preferred that the charge trapping barrier includes at least one potential barrier that allows selective intraband passage of charge carriers into the floating gate, for example within the conduction band or within the valence band. The charge trapping barrier may include at least one potential barrier where the energy states are quantized. This leads to a reduction in the density of states inside the barrier. As a result, only certain energy levels are allowed to be filled. The charge trapping barrier may include one or more quantum dots, quantum wires or quantum wells.

[0028] Conventional integrated devices are formed in layers, and the use of quantum wells results in less cell-to-cell variability because fabrication techniques exist that provide heterojunctions with smooth interfaces and very few defects. The charge trapping barriers and floating gates are preferably formed epitaxially, for example by molecular beam epitaxy (MBE), liquid phase epitaxy (LPE) or chemical vapor deposition (CVD).

[0029] The charge carriers may be electrons or holes, however, in a presently preferred embodiment, the charge carriers are electrons and the charge trapping barrier comprises at least one potential barrier that allows intraband passage of the electrons to the floating gate.

[0030] The charge trapping barrier may include two or more potential barriers in a multiple barrier arrangement. For example, the charge trapping barrier may include two, three, four, five or more potential barriers. In a currently preferred embodiment, the charge trapping barrier includes two quantum wells defining three potential barriers.

[0031] The charge trapping barrier may include one or more semiconductors. The charge trapping barrier may include one or more quantum wells. The quantum well or wells may be formed by one or more layers of semiconductors, with adjacent layers having offset conduction bands and / or offset valence bands, forming a heterojunction at the interface between these adjacent layers. Offset conduction bands and / or valence bands of layers of semiconductors may be achieved by selecting different semiconductors for adjacent layers, thereby defining one or more quantum wells in the conduction bands and / or valence bands.

[0032] Each quantum well may thus be formed by placing a narrow bandgap semiconductor between two wide bandgap semiconductors, thereby providing a heterojunction structure. "Bandgap" means the energy gap between the valence band and the conduction band of a semiconductor. Thus, the charge trapping barrier may include multiple layers of two or more different semiconductors that together define one or more quantum wells.

[0033] The multiple layers of semiconductors in the charge trapping barrier may be formed from any semiconductor that provides the required barrier potential, e.g., any required heterojunction containing any resonant energy. The layers of semiconductors may alternate between two different semiconductors, e.g., different elemental or compound semiconductors. Alternatively, the layers of semiconductors may include semiconductor alloys, with different ratios of elements in adjacent or alternating layers.

[0034] The layer of the charge trapping barrier may have a conduction band offset and / or thickness that provides a transmission coefficient peak at the resonance energy. The layer of the charge trapping barrier may have a conduction band offset of at least 1.0 eV, at least 2.0 eV, or at least 3.0 eV. The charge trapping barrier may have a thickness of less than 50 nm, less than 30 nm, or less than 10 nm. For example, for non-volatile memories, the charge trapping barrier may have a thickness in the range of 10-20 nm, and for semi-volatile memories, the charge trapping barrier may have a thickness in the range of 5-15 nm.

[0035] Since the memory cell alters one or more bits of information stored by the memory cell by allowing selective passage of charge carriers to the floating gate, the charge trapping barrier may have a thickness sufficient to provide a desired resonant tunneling barrier without affecting the sensitivity of the memory cell's read operation. The charge trapping barrier may have a thickness substantially the same as the thickness of the charge blocking barrier. Alternatively, the charge trapping barrier may be thicker than the thickness of the charge blocking barrier. For example, the charge trapping barrier may have a thickness at least 30%, 50%, 100%, or 500% greater than the thickness of the charge blocking barrier.

[0036] A charge trapping barrier may include one or more confined internal states into which and from which charge carriers can pass, e.g., by quantum tunneling. The confined internal states may be formed by either quantum dots, quantum wires, or quantum wells. A charge trapping barrier may therefore be considered to be a "hollow" barrier. In contrast, a charge blocking barrier may not include confined internal states through which charge carriers can pass, such that charge carriers cannot pass through the charge blocking barrier, e.g., by quantum tunneling. A charge blocking barrier may therefore be considered to be a "solid" barrier.

[0037] The semiconductor of the charge trapping barrier may be a crystalline solid, such as a crystalline inorganic solid. The semiconductor may have high electron mobility for faster operation. The semiconductor may have a wide band gap for higher temperature operation and lower thermal noise.

[0038] In currently preferred embodiments, the semiconductor comprises a III-V semiconductor, or an alloy of III-V semiconductors. The layers of semiconductor may be substantially lattice matched to reduce defects and therefore errors. The layers may be substantially lattice matched. The layers of semiconductor within the charge trapping barrier may have a maximum lattice mismatch of 5%, 1% or 0.5%.

[0039] In a currently preferred embodiment, the channel is formed by indium gallium arenide (InGaAs). The semiconductor substrate may be formed from any suitable semiconductor, including indium antimonide (InSb), aluminum indium antimonide (AlInSb), gallium antimonide (GaSb), gallium arsenide (GaAs) and silicon (Si). The semiconductor substrate may be the same or similar to the material of the floating gate. In a currently preferred embodiment, the semiconductor substrate is defined by a layer of gallium antimonide (GaSb). Although not required, the source and drain terminals may be n or p doped.

[0040] The semiconductor of the charge trapping barrier may include any of boron nitride (BN), boron phosphide (BP), boron arsenide (BA), aluminum nitride (AlN), aluminum phosphide (AlP), aluminum arsenide (AlAs), aluminum antimonide (AlSb), gallium nitride (GaN), gallium phosphide (GaP), gallium arsenide (GaAs), gallium antimonide (GaSb), indium nitride (InN), indium arsenide (InAs), and indium antimonide (InSb).

[0041] The semiconductor of the charge trapping barrier may comprise an alloy of semiconductor materials. The semiconductor of the charge trapping barrier may also be aluminum gallium arsenide (AlGaAs), indium gallium arsenide (InGaAs), aluminum indium arsenide (AlInSb), gallium arsenide phosphide (GaAsP), gallium arsenide antimonide (GaAsSb), aluminum gallium nitride (AlGaN), indium gallium arsenide antimonide (InAsSb), aluminum gallium phosphide (AlGaInP), indium gallium arsenide phosphide (InGaAsP), indium gallium arsenide antimonide (In ...GaAsSb), aluminum gallium phosphide (AlGaInP), indium gallium arsenide phosphide (InGaAsP), indium gallium arsenide antimonide (InGaAsSb), indium gallium arsenide antimonide (InGaAsSb), indium gallium arsenide antimonide (InGaAsSb), indium gallium arsenide antimonide (InGaAsSb), indium gallium arsenide antimonide (InGaAsSb), indium gallium arsenide antimonide (InGaAsSb), indium gallium arsenide antimonide (InGaAsSb), indium gallium arsenide antimonide (InGaAsSb), indium gallium arsenide antimonide (InGa The nitride semiconductor layer may include any of indium gallium arsenide antimonide (InGaAsSb), indium arsenide phosphide (InAsSbP), aluminum gallium nitride (AlGaAsN), indium gallium arsenide nitride (InGaAsN), indium aluminum arsenide nitride (InAlAsN), gallium arsenide antimonide (GaAsSbN), gallium indium arsenide antimonide (GaInNAsSb), and gallium indium arsenide antimonide phosphide (GaInAsSbP).

[0042] When an alloy of two or more elements is referred to, it is understood that the alloying elements can be present in any relative ratio.

[0043] The use of III-V semiconductors can provide high carrier mobility for faster operation and wide bandgaps for operation at higher temperatures and with lower thermal noise. Carrier mobility at room temperature is at least 500 cm. 2 / Vs, at least 1,000 cm 2 / Vs, at least 5,000 cm 2 / Vs, at least 10,000 cm 2 / Vs, or at least 20,000 cm 2 / Vs. The semiconductor may comprise an alloy of semiconductor materials with selected ratios of elements that provide a desired band gap and / or a desired lattice constant for each layer.

[0044] The layer or layers of semiconductors in the charge trapping barrier may include narrow band gap semiconductors such as indium arsenide (InAs) or gallium antimonide (GaSb). The layer or layers of semiconductors in the charge trapping barrier may include wide band gap semiconductors such as aluminum gallium antimonide (AlGaSb) or aluminum gallium arsenide (AlGaAs). In a currently preferred embodiment, the charge trapping barrier may be formed from layers of indium arsenide (InAs) and aluminum gallium antimonide (AlGaSb). These III-V semiconductors have very high conduction band offsets and are nearly lattice matched. The layers of the charge trapping barrier may have a conduction band offset of at least 1.0 eV, at least 2.0 eV, or at least 3.0 eV. The layers of semiconductors in the charge trapping barrier may have a maximum lattice mismatch of 5%, 1%, or 0.5%.

[0045] Application of an electric field across the charge trapping barrier may modify the shape of one or more potential barriers and / or the shape of the energy of the charge carriers in the channel and / or floating gate, resulting in an increase in the transfer coefficient of the charge carriers in the channel or floating gate for each barrier potential. The shape and / or size of one or more potential barriers may be modified, e.g., one or more potential barriers may be tilted across the applied electric field. In particular, the increase or decrease in the height of one or more potential barriers may be proportional to their distance across the applied electric field. This application of an electric field is commonly referred to as a lever voltage.

[0046] The charge trapping barrier can be modeled such that the resonance energies of the potential barriers are substantially aligned when a predetermined electric field is applied across the charge trapping barrier. The predetermined electric field may be constant during a write or erase operation. Alternatively, the write or erase operation may be a multi-step process requiring multiple different electric fields to be applied in sequence across the charge trapping barrier to allow charge carriers to pass through the charge trapping barrier.

[0047] The memory cell has at least one write voltage, which when applied between the control gate and the source terminal, causes a flow of charge carriers, e.g., electrons, from the semiconductor substrate to the channel, through the charge trapping barrier, and to the floating gate. The number of charge carriers retained in the floating gate when the electric field is removed may depend on the formation of the floating gate. The memory cell has at least one erase voltage, which when applied between the control gate and the source terminal, causes a flow of charge carriers, e.g., electrons, from the floating gate, through the charge trapping barrier, and to the channel. When the at least one erase voltage is withdrawn, the charge carriers flow from the channel into the semiconductor substrate, causing the channel to become unoccupied, i.e., non-conductive.

[0048] The potential difference applied across the charge trapping barrier during a write or erase operation may be substantially lower than the conventional voltage required to move the charge carriers to the floating gate. In particular, the potential difference may be less than 7 V, less than 5 V, or less than 3 V. Thus, the charge carriers have low kinetic energy and, upon collision with the charge blocking barrier, may cause substantially less damage to the barrier than known in the prior art. Thus, the number of times data can be written to the memory cell may be increased compared to conventional flash memories. For example, the memory cell may have a lifetime of approximately 10 6 , 10 10 , 10 16 , or even more switching cycles may be allowed.

[0049] The charge trapping barrier may be provided to prevent charge carriers from entering the floating gate in the absence of an applied write voltage. Similarly, the charge trapping barrier may be provided to prevent charge carriers from leaving the floating gate in the absence of an applied erase voltage. The charge trapping barrier may have a thickness and / or height that substantially eliminates the probability of electrons traveling through the charge trapping barrier from the channel to the floating gate in the absence of an applied write voltage, or from the floating gate to the channel in the absence of an applied erase voltage. The charge trapping barrier may be provided to prevent less than 1 electron per 10,000 years, or less than 1 electron per 1,000 years, or less than 1 electron per 100 years, or less than 1 electron per decade, or less than 1 electron from leaving the floating gate in the absence of an applied electric field across the charge trapping barrier.

[0050] The floating gate may be adapted to hold charge carriers, e.g., electrons, within its boundaries and may be electrically isolated from the control gate by a charge blocking barrier.

[0051] The floating gate may contain potential traps with quantized energy states between the charge trapping barrier and the charge blocking barrier. This results in a reduced density of states inside the floating gate. As a result, only certain energy levels are allowed to be filled. The floating gate may contain one or more quantum dots, quantum wires or quantum wells. However, conventional integrated devices are formed in layers, and fabrication techniques exist that provide heterojunctions with smooth interfaces and very few defects, so the use of quantum wells results in less cell-to-cell variation.

[0052] The floating gate may include a quantum well defined between a charge trapping barrier and a charge blocking barrier. In particular, the charge trapping barrier and the charge blocking barrier may define walls of the quantum well of the floating gate.

[0053] The quantum well of the floating gate may be formed by a layer of semiconductor that defines the floating gate and a layer of semiconductor on each side of the floating gate. The layers of semiconductor on each side of the floating gate may define at least a portion of the charge trapping barrier and the charge blocking barrier. Adjacent layers may have a conduction band offset and / or a valence band offset that forms a heterojunction at the interface between the adjacent layers, thereby defining the floating gate. The conduction band offset and / or offset valence band of the layers of semiconductor may be achieved by selecting different semiconductors for adjacent layers, thereby defining a quantum well in the conduction band and / or valence band.

[0054] Thus, the quantum well of the floating gate may be formed by disposing a narrow bandgap semiconductor between two wide bandgap semiconductors, thereby providing a heterojunction structure. The charge blocking barrier may include a potential barrier substantially the same size as the potential barrier of the charge trapping barrier adjacent to the floating gate. Alternatively, the charge blocking barrier may include a potential barrier larger than the potential barrier of the charge trapping barrier adjacent to the floating gate. Thus, the layer of material defining that portion of the charge blocking barrier adjacent to the floating gate may be of a wider bandgap material than the layer of semiconductor defining that portion of the charge trapping barrier adjacent to the floating gate.

[0055] The floating gate and the charge trapping barrier layer may have a conduction band offset of at least 1.0 eV, at least 2.0 eV, or at least 3.0 eV. The floating gate and the charge blocking barrier layer may have a conduction band offset of at least 1 eV, at least 2 eV, or at least 3 eV.

[0056] The material defining the floating gate may be similar to, or indeed the same as, the material that provides the lower potential region of the charge trapping barrier.

[0057] The material defining the floating gate may thus be a semiconductor, for example one of the suitable semiconductors discussed above in connection with the charge trapping barrier. Most preferably, the floating gate is formed of a III-V semiconductor material. In a currently preferred embodiment, the floating gate is defined by a layer of indium arsenide (InAs) or indium gallium arsenide antimonide (InGaAsSb).

[0058] A charge blocking barrier may be provided to prevent charge carriers, e.g., electrons, from passing between the floating gate and the control gate, or, if charge carriers are allowed to pass between the floating gate and the control gate, the passage of the charge carriers does not change the bit or bits of information stored by the memory cell.

[0059] The charge blocking barrier may be a potential barrier having a height substantially equal to that of the charge trapping barrier. Alternatively, the charge blocking barrier may be a potential barrier having a height significantly greater than that of the charge trapping barrier. The charge blocking barrier may have a thickness of less than 20 nm, less than 10 nm, or less than 5 nm. For example, in the case of a non-volatile memory, the charge blocking barrier may have a thickness in the range of 10-20 nm, and in the case of a semi-volatile memory, the charge blocking barrier may have a thickness in the range of 5-15 nm.

[0060] The charge blocking barrier may be formed of an insulator, or a semiconductor material that defines a suitably large potential barrier to the floating gate. The charge blocking barrier may be formed of a semiconductor material. The charge blocking barrier may be formed of a III-V semiconductor material, such as aluminum antimonide (AlSb), or a suitable dielectric, such as silicon dioxide (SiO2) or aluminum oxide (Al2O3).

[0061] The charge blocking barrier may have a thickness that brings the floating gate and the channel into close proximity.

[0062] Although there are advantages to using III-V semiconductors in the semiconductor substrate, III-V semiconductors can be expensive to source and / or manufacture. In a currently preferred embodiment, the semiconductor substrate is formed on an additional base substrate of one or more other semiconductors, for example a layered base substrate. Indeed, if the layer of the base substrate is silicon, this brings advantages in terms of integration with conventional silicon devices. A particularly advantageous base substrate, where the semiconductor substrate is gallium antimonide (GaSb), is a layer of gallium arsenide (GaAs) and a layer of silicon. However, other combinations of III-V semiconductors may also be suitable.

[0063] The layers of material defining one or more of the charge trapping barrier, the floating gate, the charge blocking barrier, the channel, and the semiconductor substrate may be substantially lattice-matched. Thus, the heterostructure of the active device region of the memory cell may be substantially defect-free, ensuring high reliability. The lattice mismatch may be less than 5%, less than 3%, or less than 1%.

[0064] The memory cells may be formed by any conventional semiconductor structure fabrication means, however, preferably at least the charge trapping barrier and the floating gate are epitaxially formed, such as by molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or chemical vapor deposition (CVD).

[0065] Each terminal may be connectable to other parts of the device, for example to other parts of an integrated circuit. In addition to the control gate, source and drain terminals, the memory cell may have a base-gate terminal, as is typical in MOSFET type devices. The base-gate terminal may be connected, for example, to a source terminal or a drain terminal.

[0066] The memory cell may form part of an array of memory cells arranged to store a number of bits of information within the memory device. Thus, according to a further aspect of the invention, there is provided a memory device comprising a plurality of memory cells as described above, arranged to provide write, read and erase operations. The memory device may be either a NOR type memory device, in which the memory cells are connected in parallel, or a NAND type memory device, in which the memory cells are connected in series.

[0067] A memory cell may achieve a state "0" when there are stored charge carriers on the floating gate and a state "1" when there are few or no stored charge carriers on the floating gate. To read the state of a memory cell, a first threshold voltage (V th ) and a second lower threshold voltage (V th ) between the read voltage (V read ) can be applied to the control gate. read) may be applied between the control gate and the source terminal, for example, with the base gate terminal connected to the source terminal. However, to reduce the voltage between the control gate and the floating gate, and thus the risk of charge carrier transfer between them, a read voltage (V read ) may be applied.

[0068] Applied read voltage (V read ) can cause a first current to flow in the source and / or drain terminals when the memory cell is in state "1" and either a second, lower current or no current or negligible current when the memory cell is in state "0." Thus, the device may include arrangements for sensing or measuring current flow between the source and drain terminals of the memory cell.

[0069] In a write operation, a write potential (V write ), electrons can be pushed onto the floating gate. write ) can be applied, for example, between the control gate and source terminals with the base gate terminal shorted to the source terminal, allowing for a lower write voltage.

[0070] In the erase operation, the erase potential (V erase Electrons can be ejected from the floating gate to either the source or base terminal by applying an erase voltage (V erase ) can be applied, for example, between the control gate and source terminals with the base gate terminal connected to the source terminal, allowing for a lower erase voltage.

[0071] During storage, charge may be retained on the floating gate. In a currently preferred embodiment, no voltage is applied to the control gate with respect to the source terminal during storage.

[0072] According to a further aspect of the present invention there is provided a memory device comprising a plurality of memory cells as defined above.

[0073] According to a further aspect of the invention, a memory device is provided comprising a plurality of memory cells for storing one or more bits of information. Each memory cell comprises a semiconductor substrate including a source terminal, a drain terminal, and a channel extending between the source terminal and the drain terminal. The memory cell further comprises a control gate and a floating gate. The floating gate is disposed between the control gate and the channel and is electrically insulated from the control gate and the channel by a charge barrier. The floating gate is configured to allow selective passage of charge carriers to and from the floating gate by resonant tunneling during write and erase operations, providing at least first and second occupancy states of the floating gate. A read voltage may be applied between the control gate and the substrate to provide a conductive channel for the first occupancy state of the floating gate and a non-conductive channel for the second occupancy state of the floating gate.

[0074] The channel may include a quantum well having discrete internal energy levels for accommodating charge carriers within the channel, and is configured to provide a minimum threshold voltage applied between the control gate and the substrate to introduce charge carriers from the substrate into the channel to make the channel conductive.

[0075] The memory cells may be adapted such that their channels are conductive only upon application of an electric field across the memory cells. The memory device may be configured to provide write, read and erase operations with respect to each of the plurality of memory cells. The memory device may include means for sensing or measuring a current through a channel of each of the plurality of memory cells. The memory device may further include means for applying a read voltage to a control gate of the memory cell.

[0076] The plurality of memory cells may be arranged in an array. The array may include a plurality of columns and a plurality of rows. Each memory cell in a row may be electrically connected. Each memory cell in a column may be electrically connected. The memory device may comprise at least one first electrical contact arranged to provide a voltage to a control gate of each memory cell in a column of the array. The memory device may include at least one second electrical contact arranged to provide a voltage to a substrate of each memory cell in a row of the array via at least one of the source, drain or base gate terminals. The other two of the source, drain and base gate terminals may be connected to ground.

[0077] In use, the first electrical contact can apply a first portion of a required voltage to a desired column in the array, and the second electrical contact can apply a second portion of the required voltage to a desired row in the array, such that a target cell in the array receives all of the required voltages. The required voltages can be any of the read, write, and erase voltages described above. The first portion of the required voltages can be at least 10%, 20%, 30%, 40%, or 50% of the total required voltage. The second portion of the required voltages can be at least 50%, 60%, 70%, 80%, or 90% of the total required voltage.

[0078] This can be advantageous in that only the target memory cell receives the full voltage required to read, write, or erase from that memory cell, while the remaining memory cells in the same column or row receive only a portion of the full required voltage and are therefore unaffected.

[0079] The memory cells may be non-volatile. The memory cells may store one or more bits of information without requiring power. The memory cell may have a storage time of at least 10,000 years, thereby allowing the memory chip to store data for at least 10 years. In fact, storage times of at least 100,000 years, or at least 1,000,000 years, may be achieved.

[0080] While this application focuses primarily on non-volatile memory cells, it is recognized that the principles may also be more broadly applied to form semi-volatile memory cells. Such semi-volatile memory cells are suitable for use as DRAM type memories. When the memory cells are semi-volatile, the memory time of the memory cells may be at least one hour, at least one day, at least one week, or at least one year. This may provide a significant advantage over current DRAM type memories, in which the capacitors need to be refreshed approximately every 60 milliseconds. [Brief description of the drawings]

[0081] [Figure 1] 1 is a schematic cross-sectional view of a memory cell according to the present invention; [Diagram 2] 2 is a schematic conduction band energy level diagram for a memory cell according to the present invention; [Diagram 3] 2 is a schematic conduction and valence band energy level diagram at the channel-substrate interface of a memory cell according to the present invention; [Figure 4] 1 is a schematic diagram of an array of memory cells according to the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0082] 1 is a schematic cross-sectional view of a memory cell according to the present invention, generally designated 10. Memory cell 10 includes source and drain terminals 12 and 14, a channel 16 between source and drain terminals 12 and 14, a base-gate terminal 15 at the base of a semiconductor substrate 18, and a control gate 24 for inducing a change in conductivity of channel 16 in semiconductor substrate 18 between source and drain terminals 12 and 14. The memory cell also includes a floating gate 26 disposed between control gate 24 and semiconductor substrate 18.

[0083] The floating gate 26 is electrically insulated from the control gate 24 by a charge blocking barrier 30, and the floating gate 26 is electrically insulated from the semiconductor substrate 18, and thus the channel 16 within the semiconductor substrate 18, by a charge trapping barrier 28. The charge trapping barrier 28 is provided to selectively allow charge carriers to pass between the floating gate 26 and the channel 16 within the semiconductor substrate 18, in use, to modify one or more bits of information stored by the memory cell 10. In contrast, the charge blocking barrier 30 prevents charge carriers from passing between the control gate 24 and the floating gate 26.

[0084] The channel 16 differs from that of a conventional memory cell in that the channel 16 is formed of a different material grown on the material of a semiconductor substrate 18. The channel 16 is epitaxially grown on the semiconductor substrate 18, for example, by molecular beam epitaxy (MBE) or any other suitable process. The semiconductor substrate 18 is formed of gallium antimonide (GaSb) and disposed on a base structure 20, 22 that allows for the use of lower cost materials and may facilitate integration into silicon-based devices. In particular, the top base layer 20 of the base structure 20, 22 is formed of gallium arsenide (GaAs), and the semiconductor substrate 18 is disposed on the top base layer 20 using an interface misfit method (IMF). The top base layer 20 is disposed on the bottom base layer 22, which is formed of silicon (Si) or germanium (Ge) on silicon.

[0085] Alternatively, the semiconductor substrate 18 may be disposed on a top base layer 20 of GaAs that is thicker, i.e., without the addition of a bottom base layer. This may be advantageous since GaAs is a common compound semiconductor and is widely available.

[0086] Alternatively, the semiconductor substrate 18 may be disposed on a top base layer 20 of Si that is thicker, i.e., without the addition of a bottom base layer. This may be advantageous since Si is the most common semiconductor and is widely available. In such an embodiment, it may be advantageous to include, for example, a strain relief mechanism to mitigate the potentially deleterious effects of lattice mismatch between the semiconductor substrate 18 and the top base layer 20. One example of such a mechanism is the inclusion of one or more atomic monolayers provided between the semiconductor substrate 18 and the top base layer 20, although it is understood that this may be provided by any other known suitable means. The one or more atomic monolayers may include AlSb. The one or more atomic monolayers may include 10, 15, or 20 atomic monolayers.

[0087] Alternatively, the semiconductor substrate 18 may be thickened and formed entirely of gallium antimonide (GaSb) and the memory cell 10 may be more expensive to manufacture in this configuration, but does not require lattice matching with the base structure.

[0088] Charge trapping barrier 28 is formed from alternating layers of indium arsenide (InAs) and aluminum antimonide (AlSb) to create two narrow quantum wells (i.e., three resonant tunneling barriers) and is disposed on top of channel 16. The layers of charge trapping barrier 28 are substantially lattice matched and have a large conduction band offset.

[0089] The floating gate 26 is disposed on top of the charge trapping barrier 28 and is formed from indium arsenide (InAs) and its thickness is not critical but may typically be in the region of 10-50 nm. The floating gate 26 is an electrically isolated quantum well defined between the charge trapping barrier 28 and the charge blocking barrier 30 and is suitable for holding a finite number of charge carriers in quantized energy levels.

[0090] Above the floating gate 26 is a charge blocking barrier 30. The charge blocking barrier 30 may be formed by 15 nm of aluminum antimonide (AlSb). Such a charge blocking barrier 30 has a thickness substantially equal to that of the charge trapping barrier 28. Furthermore, the charge blocking barrier 30 has a potential barrier substantially equal to that of the charge trapping barrier 28. Alternatively, since the charge blocking barrier should have insulating properties and is disposed above the semiconductor layer of the device, it may be formed by a dielectric layer, for example an oxide such as silicon dioxide (SiO2) or aluminum oxide (Al2O3). Aluminum is often readily available in compound semiconductor epitaxy systems such as molecular beam epitaxy and vapor phase epitaxy, and therefore can be deposited in situ in the epitaxy reactor as a thin layer that naturally oxidizes ex situ to protect the semiconductor layer below, making aluminum oxide a convenient choice. In practice, an additional dielectric layer may be placed in situ to ensure protection of the semiconductor layer.

[0091] The control gate 24 is formed of any suitable conductive material, such as a metal, for example gold.

[0092] The charge trapping barrier 28, the floating gate 26, and the charge blocking barrier 30 may be formed on the semiconductor substrate 18, i.e., on the channel 16, by any suitable method, such as, for example, molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or chemical vapor deposition (CVD).

[0093] After growth, memory cell 10 is processed using standard semiconductor lithography techniques. Contacts are made to source terminal 12, drain terminal 14, control gate 24 and base gate terminal 15 for applying voltages and allowing the passage of current through memory cell 10.

[0094] As shown in Figure 2, the charge trapping barriers 28 define potential barriers that define a series of quantum wells that allow resonant tunneling. The quantum wells are formed of layers of different sizes, specifically 1.8 nm of AlSb, 2.4 nm of InAs, 1.2 nm of AlSb, 3.0 nm of InAs, and 1.8 nm of AlSb. The potential barriers of the charge trapping barriers 28 have resonant energies, shown by the dotted lines in Figure 3, that allow charge carriers to pass through each of the potential barriers at or substantially at those energies.

[0095] The charge trapping barrier 28 is modeled such that when no voltage is applied to the memory cell 10, the resonant energies of the potential barrier are not aligned, but when a predetermined electric field is applied across the charge trapping barrier 28, the resonant energies of the potential barrier are substantially aligned, allowing charge carriers to pass from the channel 16 to the floating gate 26, or vice versa.

[0096] When the memory cell 10 is not in use, no voltage should be applied. In this state, the large charge-blocking barrier 30 between the floating gate 26 and the control gate 24 prevents the passage of charge between them. Similarly, no charge should flow between the floating gate 26 and the channel 16 because the energies of the confined states in the two quantum wells within the charge-trapping barrier 28 are high and do not match each other.

[0097] To write to the memory cell 10, the drain terminal 14 is shorted to the base-gate terminal 15 contact (ground) and a voltage of approximately +2.5V is applied between the control gate 24 and the source terminal 12. This aligns the lowest quantum confinement states in the two quantum wells that form part of the charge trapping barrier 28, allowing electrons to rapidly pass into the floating gate 26 by the process of resonant tunneling.

[0098] To erase the memory cell 10, the drain terminal 14 is shorted to the base-gate terminal 15 contact (ground) and a voltage of approximately −2.5 V is applied between the control gate 24 and source terminal 12. This aligns the lowest confinement states in the floating gate 26 and the adjacent quantum well in the charge trapping barrier 28, allowing electrons to pass rapidly from the floating gate 26 to the other quantum well in the charge trapping barrier 28 (at a higher energy state) by a resonant tunneling process and then into the channel 16.

[0099] To read the memory cell 10 without applying any significant voltage between the closely spaced control gate 24 and floating gate 26, thereby avoiding charge flow between them, the source terminal should not be shorted to the base gate terminal 15. Instead, a voltage of approximately +0.5V should be applied between the control gate 24 and base gate terminal 15, so that in the absence of charge in the floating gate 26, carriers in the semiconductor substrate 18 are driven into the channel 16, which becomes more conductive and gives a reading of '1'. In the presence of charge in the floating gate 26, the conductivity of the channel 16 is not substantially increased, giving a reading of '0'.

[0100] This is generally consistent with the operation of conventional flash memories. However, unlike conventional flash memories, in the memory cell 10 of the present invention, the channel 16 in the semiconductor substrate 18 comprises a naturally non-conductive quantum well. This is shown in more detail in FIG.

[0101] 3, the channel 16 can be seen to include a quantum well defined by the potential barrier of the adjacent semiconductor substrate 18 and the adjacent charge trapping barrier 28. The potential barrier of the adjacent semiconductor substrate 18 is the conduction band 40 of the semiconductor substrate 18. The quantum well is particularly narrow, e.g., 15 nm, and quantum effects indicate that the quantum well has quantized energy levels known as confined energy levels, the lowest of which (i.e., the ground state energy level) is indicated by the dotted line 42. These confined energy levels represent energy levels that charge carriers must occupy within the quantum well.

[0102] It can be seen that at zero applied bias, the valence band 44 of the semiconductor substrate 18 has a lower energy than the quantized energy states 42 of the channel 16. Thus, under normal conditions, charge carriers do not move from the semiconductor substrate 18 into the channel 16, and as a result, the channel 16 is unoccupied, i.e., insulating or non-conducting.

[0103] However, it can be seen that the application of a bias, for example 0.3 V, between the control gate 24 and the base gate terminal 15 shifts the valence band energy 46 of the semiconductor substrate 18. The valence band energy 46 shifts so that a portion of the valence band 44 is above the ground state energy level 42 of the quantum well.

[0104] In response to an applied bias, a portion of the valence band 44 exceeds the ground state energy 42 of the quantum well, so that charge carriers in the valence band 44 migrate into the quantum well, i.e., the channel 16 becomes occupied and therefore conductive.

[0105] The memory cell 10 has a write voltage which, when applied between the control gate 24 and the source terminal 12, causes a flow of electrons to and from the channel 16, through the charge trapping barrier 28, to the floating gate 26. The electrons move through the charge trapping barrier 28 in the usual manner, i.e., by resonant tunneling, to write to the floating gate 26. The number of electrons retained in the floating gate 26 when the electric field is removed may depend on the shape of the floating gate 26. The memory cell 10 also has an erase voltage which, when applied between the control gate 24 and the source terminal 12, causes a flow of electrons from the floating gate 26, through the charge trapping barrier 28, into the channel 16, and then out of the channel 16 back to the semiconductor substrate 18. Similarly, electrons move in the opposite direction, through the charge trapping barrier 28, in the usual manner, i.e., by resonant tunneling, to erase from the floating gate 26. During storage, electrons are retained in the floating gate 26, and no bias needs to be applied to the control gate 24 for the memory cell to store one or more bits of information provided by the presence or absence of electrons in the floating gate 26.

[0106] In response to a smaller applied bias, the valence band energy of the semiconductor substrate 18 will shift less, i.e., not a portion of the valence band will be high enough to exceed the ground state energy level 42 of the quantum well, and the channel 16 will remain insulating. In response to a larger applied bias, the valence band will shift more, i.e., a larger portion of the valence band will shift high enough to exceed the ground state energy level 42 of the quantum well. It will thus be appreciated that the density of charge carriers in the channel 16, and therefore the conductivity of the channel 16, depends on the bias applied between the control gate and base gate terminals.

[0107] Thus, when a voltage is applied between the control gate 24 and the base gate terminal 15, or between the control gate 24 and the source terminal 12, a threshold voltage exists where the valence band of the adjacent semiconductor substrate material 18 is raised just above the ground state energy 42 of the quantum well, thereby causing the channel 16 to transition between an insulating and a conducting state.

[0108] Therefore, the threshold voltage of the memory cell 10 (V th ) can be defined as the value of the control gate-source voltage, or control gate-base gate terminal voltage, at which the conductivity of the conductive channel connecting the source terminal 12 and the drain terminal 14 of the memory cell 10 switches between a depleted state, i.e., a state depleted of charge and therefore insulating, allowing only an inherent leakage current, and a conductive state. The memory cell 10 is arranged to provide a change in threshold voltage when one or more charge carriers, e.g., electrons, are retained by the floating gate 26.

[0109] The memory cell 10 achieves a state "0" when there are stored charge carriers on the floating gate 26, a state "1" when there are few stored charge carriers on the floating gate 26, and a state "1" when there are no stored charge carriers on the floating gate 26. To read the state of the memory cell 10, a read voltage (V read ) is applied to the control gate 24, and a read voltage (V read ) is the first threshold voltage (V th ) and a second, lower, threshold voltage (V th ) between the applied read voltage (V read ) results in a first current flow at source terminal 12 and / or drain terminal 14 when memory cell 10 is in state "1," and no or negligible current flow when memory cell 10 is in state "0." Thus, the device in which the memory cell is incorporated includes arrangements for sensing or measuring the flow of current between the source and drain terminals of the memory cell.

[0110] While the memory cells are described above as having channels that include quantum wells, it is contemplated that the channel may alternatively include a semiconductor layer formed from a different semiconductor than the semiconductor substrate, provided that the conduction band of the channel layer is above the valence band of the semiconductor substrate and that application of a voltage raises at least a portion of the valence band of the semiconductor substrate above the conduction band of the channel.

[0111] The similarities between the memory cell 10 of the present invention and flash memory cells readily allow the memory cell 10 disclosed herein to be implemented in a flash architecture, such as a NAND-type architecture, in which multiple memory cells are connected in series in large strings.

[0112] The inventors have also discovered that the memory cells disclosed herein may be implemented in an active memory, or RAM, architecture that allows rapid access to individual memory cells within an array of memory cells, as desired by a user.

[0113] Such an architecture is possible by implementing the memory cells described above in an architecture such as that shown in Figure 4. Figure 4 shows a portion of a memory device 50 having a plurality of memory cells 10 arranged in an array. The array includes rows of memory cells 10 electrically connected by word lines 52A, 52B, 52C, 52D, and columns of memory cells 10 electrically connected by bit lines 54-1, 54-2, 54-3, 54-4.

[0114] Note that in FIG. 4, the drain terminals of the memory cells 10 are connected in pairs and are also commonly connected to the base-gate terminals of all cells in the array 50 .

[0115] Due to the nature of the resonant tunneling barrier 28 of the memory cell 10, the current peaks for the write and erase processes are particularly sharp, i.e., the voltages required to write or erase the memory cell 10 can be quantified very specifically. This allows the required voltages to be applied to the memory device 10 via two half-voltages.

[0116] In the example of FIG. 4, a first half voltage is applied to the target memory cell 56 via word line 52C, and a second half voltage is applied to the target memory cell 56 via bit line 54-1. This allows the target memory cell 56 to receive the full voltage required to write / erase the floating gate 26 of the memory cell 56. Meanwhile, it is ensured that none of the other memory cells 10 along word line 52C or bit line 54-1 receive enough voltage to intentionally affect the storage in their respective floating gates. For example, if it is known that a voltage between 0.8 and 1V is required to write to the floating gate of the target memory cell, a voltage of 0.5V can be applied to the associated word line and 0.5V can be applied to the associated bit line. Thus, the target memory cell is provided with 1V, while all remaining memory cells are provided with only 0.5V and remain unaffected. In a similar manner, a read operation can be performed by applying a read threshold voltage to the word line and testing the conductivity of the cells on the bit line.

[0117] This ability to target individual memory cells within a memory device makes it suitable for RAM applications because of the speed with which individual cells can be selectively addressed. However, unlike most RAM technologies, the memory devices described above are non-volatile. This method of memory access is also advantageous in that it reduces the number of electrical contacts required, since the drain terminals of all cells in the array connect to each other and to a common base-gate terminal, so that only electrical contacts to the respective bit lines and word lines are required. This allows the memory device to be much more compact than other devices with similar storage capacity. [Explanation of symbols]

[0118] 10 Memory Cells 12 Source terminal 14 Drain terminal 16 Channels 18 Semiconductor Substrate 20 Base structure, top base layer 22 Base structure, the lowest base layer 24 Control Gate 26 Floating Gate 28 Charge trapping barrier, resonant tunneling barrier 30 Charge Blocking Barrier 40 Conduction band 42 Ground state energy level, quantized energy state 44 Valence Band 46 Valence Band Energy 50 Memory Devices, Arrays 52 Word Line 54 bit lines 56 Target Memory Cell

Claims

1. A memory cell for storing one or more bits of information, comprising: a semiconductor substrate having a source terminal, a drain terminal, and a channel extending between the source terminal and the drain terminal; a control gate and a floating gate; the floating gate is disposed between the control gate and the channel and is electrically insulated from the control gate and the channel by a charge barrier configured to selectively allow charge carriers to move into and out of the floating gate during write and erase operations, providing at least first and second occupancy states of the floating gate; the channel is configured to provide a minimum threshold voltage applied between the control gate and the semiconductor substrate to induce the charge carriers from the semiconductor substrate into the channel and cause the channel to become conductive; the minimum threshold voltage depends on the occupancy state of the floating gate; a read voltage is applied between the control gate and the semiconductor substrate to provide a conductive channel in the first occupation state of the floating gate and a non-conductive channel in the second occupation state of the floating gate; the interface between the channel and the semiconductor substrate is a type III heterojunction; the channel comprises a quantum well, quantum dot, or quantum wire having discrete confined energy levels that accommodate the charge carriers within the channel; A memory cell wherein the lowest confined energy level of the quantum well, quantum dot or quantum wire has an energy higher than the valence band of the semiconductor substrate in the absence of an electric field applied across the memory cell.

2. The memory cell of claim 1 , wherein the quantum well, quantum dot or quantum wire is disposed between the charge barrier and the semiconductor substrate.

3. The memory cell of claim 2 , wherein the charge barrier and the semiconductor substrate define walls of the quantum well, quantum dot, or quantum wire.

4. In the absence of any applied bias across the channel, The memory cell of claim 1 , wherein the channel comprises a potential barrier at an interface between the channel and the charge barrier, and the potential barrier at an interface between the channel and the semiconductor substrate.

5. 5. The memory cell of claim 4, wherein the potential barrier at the interface between the channel and the semiconductor substrate allows the charge carriers to switch between a state in which they pass between the semiconductor substrate and the channel and a state in which they cannot pass in response to the application of an electric field.

6. 6. The memory cell of claim 1, wherein the channel comprises a conduction band offset and / or a valence band offset forming a heterojunction at an interface between the channel and the charge barrier and at an interface between the channel and the semiconductor substrate.

7. The memory cell of any one of claims 1 to 6, wherein the channel is formed by a narrow bandgap semiconductor disposed between two wide bandgap semiconductors.

8. The memory cell of any one of claims 1 to 7, wherein the channel is an InGaAs quantum well, quantum dot or quantum wire and one of the adjacent barrier materials is GaSb.

9. 9. The memory cell of claim 1, wherein the lowest confined energy level of the quantum well, quantum dot or quantum wire has an energy higher than the Fermi energy of the semiconductor substrate in the absence of an electric field applied across the memory cell.

10. 6. The memory cell of claim 5, wherein, in use, switching between a state in which charge carriers pass between the semiconductor substrate and the channel and a state in which they cannot pass is controllable by controlling the shape and / or size of the potential barrier at the interface between the channel and the semiconductor substrate.

11. The memory cell of claim 10 , wherein the passage of charge carriers between the semiconductor substrate and the channel is controllable by application of an electric field across the memory cell.

12. 12. The memory cell of claim 11, wherein in response to an application of an electric field, a lowest confined internal state of the quantum well, quantum dot or quantum wire has an energy lower than a valence band energy of at least a portion of the semiconductor substrate.

13. The memory cell of any one of claims 1 to 12, wherein the channel is not occupied by the charge carriers when no voltage is applied between the control gate and the semiconductor substrate in the absence of an applied electric field.

14. The memory cell of any one of claims 1 to 13, wherein the channel is non-conductive and / or insulating when no voltage is applied between the control gate and the semiconductor substrate in the absence of an applied electric field.

15. A memory device comprising a plurality of said memory cells according to any one of claims 1 to 14, A memory device, wherein the floating gate is configured to allow the charge carriers to selectively enter and exit the floating gate by resonant tunneling during write and erase operations.

16. a plurality of said memory cells arranged in an array including a plurality of columns and a plurality of rows; The memory device includes at least one first electrical contact arranged to supply a voltage to the control gate of each of the memory cells in a column of the array; at least one second electrical contact arranged to supply a voltage to at least one of the source terminal, the drain terminal, or the base-gate terminal; The memory device of claim 15 comprising:

17. the first electrical contacts are configured to apply a first portion of a required voltage to a desired column in the array; the second electrical contacts are configured to apply a second portion of the required voltage to a desired row in the array, the second portion being the remainder of the required voltage excluding the first portion; The memory device of claim 16 , wherein a target cell in the array receives all of the required voltages.

18. 20. The memory device of claim 17, wherein the required voltage is one of a read voltage, a write voltage, and an erase voltage.

19. The memory device of any one of claims 15 to 18, wherein either the source terminals of the plurality of memory cells or the drain terminals of the plurality of memory cells are electrically connected to a base gate terminal common to the plurality of memory cells.

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