Image sensor based on time delay integration (TDI) and imaging method thereof

Abstract

An image sensor based on time delay integration (TDI) and an imaging method thereof are disclosed. The image sensor based on time delay integration TDI includes a multi-stage linear array including a plurality of single-stage linears arranged along a scan direction of the image sensor, each single-stage linear including a plurality of pixels arranged along the linear direction, each single-stage linear entering a count mode in response to a first control signal and entering a transfer mode in response to a second control signal, in the count mode each single-stage linear counting optical signals incident on pixels to obtain count values, in the transfer mode each single-stage linear stopping counting, and each single-stage linear other than the last single-stage linear outputting the obtained current count value to the next single-stage linear, in which the last single-stage linear outputs the obtained current count value.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to Chinese patent application No. 202010971985.8 filed on September 16, 2020, and all contents disclosed in the above Chinese patent application are incorporated by reference as part of this application.

[0002] The present disclosure relates to an image sensor and imaging method based on time delay integration (TDI), and in particular to an image sensor and corresponding imaging method that employs a single photon avalanche diode (SPAD) to realize time delay integration. [Background technology]

[0003] Time delay integration is an imaging method that enhances the signal-to-noise ratio of an image in a fast scanning imaging mode, and is generally used in charge coupled device (CCD) technology, i.e., TDI-CCD image sensors. Figure 1 shows a schematic diagram of the use of a TDI image sensor in imaging. In a linear scanning system, the direction of increase in the number of stages of the TDI image sensor is the scanning direction of the camera, and the linear array of different stages can be used to perform multiple exposure imaging of the same scene, which can extend the equivalent integration time of imaging, and is more advantageous in increasing the signal-to-noise ratio. There is a positive correlation between the signal-to-noise ratio and the number of stages of the TDI sensor, and the more stages the TDI image sensor has, the higher the signal-to-noise ratio of the image that can be achieved under the same imaging conditions. In general, TDI technology is widely used in linear scanning applications, such as industrial pipeline scanning, scanning of low and medium-earth orbit satellites, and is particularly suitable for low-light and high-speed imaging systems, and can obtain images with high signal-to-noise ratios in a short time.

[0004] However, TDI-CCD image sensors have some disadvantages, such as high manufacturing cost and high operating voltage, and recently, the industry has proposed TDI image sensors based on CMOS process. TDI-CMOS technology is compatible with CMOS process and has low cost, but its conversion method usually performs analog domain accumulation or digital domain accumulation after matrix reading, which is prone to noise and requires complex control timing. Overall, the noise level and imaging quality of TDI-CMOS image sensors both have a certain difference compared to TDI-CCD. Summary of the Invention [Means for solving the problem]

[0005] Therefore, the image sensor and corresponding imaging method based on time delay integration disclosed herein specifically relates to an image sensor and corresponding imaging method that employs a single-photon avalanche diode to realize time delay integration, and is particularly suitable for low-illumination and high-speed scanning imaging systems.

[0006] According to one aspect of the present disclosure, a time delay integration (TDI) based image sensor is proposed, the time delay integration (TDI) based image sensor comprising: a multi-stage linear array including a plurality of single-stage linears arranged along a scan direction of an image sensor, the scan direction of the image sensor being a stage direction, each single-stage linear including a plurality of pixels arranged along the linear direction, the linear direction being perpendicular to the stage direction; The single-stage linear of each stage enters a count mode in response to a first control signal and enters a transfer mode in response to a second control signal, and in the count mode, the single-stage linear of each stage counts the optical signals incident on the pixel to obtain a count value, while in the transfer mode, the single-stage linear of each stage stops counting, and the single-stage linear of each stage other than the single-stage linear of the final stage outputs the obtained current count value to the single-stage linear of the next stage, and the single-stage linear of the final stage outputs the obtained current count value.

[0007] According to one example of the present disclosure, the optical signals are photons, and each pixel includes a pixel unit that detects the photons and outputs a pulse signal, the number of which is related to the number of photons, and a counter that receives the pulse signal output by the pixel unit, obtains the count value by counting the number of pulse signals in response to the first control signal, and stops counting in response to the second control signal and outputs the obtained current count value.

[0008] According to one example of the present disclosure, a pixel unit includes a single-photon avalanche diode SPAD, and the SPAD is operated in Geiger mode by connecting the SPAD to a reverse bias voltage.

[0009] According to one example of the present disclosure, each pixel has: The optical fiber further includes a quenching circuit connected to the SPAD, which quenches the avalanche by lowering the reverse bias voltage of the SPAD when the SPAD receives a single photon and avalanche multiplication occurs, and outputs a pulse signal.

[0010] According to one example of the present disclosure, each pixel further includes a pulse shaping circuit connected to the quench circuit, shaping the pulse signal output by the quench circuit, and outputting a digital pulse signal to the counter.

[0011] According to one example of the present disclosure, the image sensor further includes a latch circuit that latches the count value output by the final single-stage linear in response to the second control signal, and an address selection circuit that reads the count value latched by the latch circuit so that a downstream processing circuit generates image information based on the count value.

[0012] According to one example of the present disclosure, the image sensor further includes a timing control circuit that generates and provides the first control signal and the second control signal to each stage in a multi-stage linear array.

[0013] According to an example of the present disclosure, in each single-stage linear, the pixel units and the counters respectively form a pixel unit linear and a counter linear along the array direction.

[0014] According to one example of the present disclosure, the pixel unit linear and the counter linear are arranged alternately with each other in a multi-stage linear array and arranged in the same layer, or the pixel unit linear and the counter linear form a pixel unit array and a counter array, respectively, and the pixel unit array and the counter array are arranged in the same layer, and the pixel units in the pixel unit array are electrically connected to corresponding counters in the counter array.

[0015] According to an example of the present disclosure, the pixel unit linear and the counter linear form a pixel unit array and a counter array respectively, and the pixel unit array and the counter array are disposed in different layers.

[0016] According to an example of the present disclosure, the pixel unit array and the counter array are arranged in different layers according to a 3D stacking process, and the pixel units in the pixel unit array are electrically connected to corresponding counters in the counter array.

[0017] According to an example of the present disclosure, at least one of the quench circuit and the pulse shaping circuit is integrated into the pixel unit.

[0018] According to an example of the present disclosure, a counter includes trigger units that are cascaded in multiple stages, and in the multiple cascaded trigger units, the trigger unit in each stage includes a flip-flop, a first data selector and a second data selector connected to the flip-flop, and the flip-flop in each stage includes: a data input terminal connected to the output terminal of the first data selector; a clock input terminal connected to the output terminal of the second data selector; a first output terminal for outputting a count pulse; a second output terminal connected to the first input terminal of the first data selector; A first input terminal of the second data selector in each of the trigger units other than the first-stage trigger unit is connected to a second output terminal of the flip-flop in the previous-stage trigger unit, and a first input terminal of the second data selector in the first-stage trigger unit is connected to an output terminal of the pulse shaping circuit; The second input end of the second data selector in the trigger unit of each stage receives a second control signal.

[0019] According to an example of the present disclosure, the second input terminal of the first data selector in each of the single-stage linear pixels other than the first single-stage linear pixel is connected to the first output terminal of the corresponding flip-flop of the previous single-stage linear pixel; The second input terminal of the first data selector in the first single-stage linear pixel receives a first level signal; The first output terminal of the flip-flop in the last single-stage linear pixel is connected to the latch circuit.

[0020] According to an example of the present disclosure, the control ends of the first data selector and the second data selector in the trigger unit receive a first control signal.

[0021] According to one example of the present disclosure, the flip-flop is a D flip-flop.

[0022] According to one example of the present disclosure, the flip-flop is one of a JK flip-flop, an RS flip-flop, and a T flip-flop, and the trigger unit further includes a logic gate circuit connected to the flip-flop so as to realize the function of a D flip-flop using the JK flip-flop, the RS flip-flop, or the T flip-flop.

[0023] According to another aspect of the present disclosure, there is provided an imaging method based on time delay integration (TDI), which includes scanning an object to be imaged using a plurality of single-stage linears arranged along a scanning direction of an image sensor, wherein the scanning direction of the image sensor is a stage direction, each single-stage linear includes a plurality of pixels arranged along the linear direction, and the linear direction is perpendicular to the stage direction, and each single-stage linear enters a counting mode in response to a first control signal, and each single-stage linear enters a transfer mode in response to a second control signal, and in the counting mode, the single-stage linear of each stage is used to count optical signals incident on pixels to obtain count values, while in the transfer mode, the single-stage linear of each stage stops counting, and the current count values ​​obtained by each single-stage linear of other stages other than the single-stage linear of the final stage are transferred to the single-stage linear of the next stage, and the current count value obtained by the single-stage linear of the final stage is output.

[0024] According to one example of the present disclosure, the optical signal is a photon, and the imaging method includes: The method further includes using a pixel unit to detect photons and outputting a pulse signal, the number of which is related to the number of photons; using a counter to receive the pulse signal output by the pixel unit, and counting the number of the pulse signals in response to the first control signal to obtain the count value; and stopping the count and outputting the obtained current count value in response to the second control signal.

[0025] According to one example of the present disclosure, a single-photon avalanche diode SPAD is employed to detect photons and output a pulse signal, and the SPAD is operated in Geiger mode by connecting the SPAD to a reverse bias voltage.

[0026] According to one example of the present disclosure, the imaging method further includes latching the count value output by the final single-stage linear in response to the second control signal, and reading the count value of the latch so as to generate image information based on the count value. Effect of the Invention

[0027] The time delay integration type SPAD image sensor proposed in this disclosure has fully digitalized imaging and transfer processes, low noise introduction levels, and small impact of the number of transfers on the MTF. Compared to conventional TDI-CCD image sensor technology, this sensor has advantages such as low readout noise, low transfer noise, fewer limitations on the MTF for the number of TDI stages, and low cost. [Brief description of the drawings]

[0028] [Figure 1] FIG. 1 is a schematic diagram of imaging using a time delay and integration image sensor based on a linear scan system. [Diagram 2] 1 is a schematic diagram of a linear array arrangement embodiment of a time delay integration type image sensor proposed in accordance with the principles of the present disclosure; [Diagram 3] FIG. 2 is a schematic diagram of the circuit structure of a single pixel included in a time delay integration type image sensor proposed according to the principles of the present disclosure. [Figure 4] 1 is a schematic diagram of a circuit structure of a transferable counter proposed according to the principles of the present disclosure; [Diagram 5] 2 is a schematic diagram of the operation timing of a forwardable counter proposed in accordance with the principles of the present disclosure; [Figure 6] FIG. 1 is a schematic diagram of employing a JK flip-flop in a forwardable counter to realize a trigger unit according to the principles of the present disclosure. [Figure 7] 1 is a schematic diagram of another linear array arrangement embodiment of a time delay integration image sensor according to the principles of the present disclosure; FIG. [Figure 8] 1 is a schematic diagram of another linear array arrangement embodiment of a time delay integration image sensor according to the principles of the present disclosure; FIG. [Figure 9] A method for imaging with a time delay integration (TDI) based image sensor is proposed according to the principles of the present disclosure. [Figure 10]1 shows a comparison of transfer efficiency versus number of TDI stages when imaging an image sensor based on the principles of the present disclosure and a conventional TDI-CCD. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] The present disclosure will be described in detail below in conjunction with the accompanying drawings and specific embodiments. The described specific embodiments are only used to interpret and explain the principles of the present disclosure, and are not intended to limit the scope of the technical solution of the present disclosure. In this specification, various elements may be described using terms such as first and second, but it should be understood that these elements should not be limited by these terms. These terms are only used to distinguish one element from another element.

[0030] FIG. 1 is a schematic diagram of imaging using a time delay integration image sensor based on a linear scan system. As shown in FIG. 1, when imaging based on a linear scan system, the time delay integration image sensor is composed of a linear array, the step direction is the relative motion direction, that is, the scan direction of the camera, and the direction perpendicular to the step direction is the linear direction, and the pixels arranged in this direction form a single-step linear. During scanning, different single-step linears sequentially perform exposure imaging on the same scene, transmit the obtained photoelectric signal to the subsequent stage, and superimpose the signal transmitted to the subsequent stage and the photoelectric signal obtained by the exposure of the next stage, and then transmit it to the subsequent stage again. Therefore, it is more advantageous to perform multiple exposure imaging and superimposition on the scene at the same location by different single-step linears, which actually extends the equivalent integration time of imaging and increases the signal-to-noise ratio. There is a positive correlation between the signal-to-noise ratio and the number of stages of the line array, and the more stages of the linear array included in the TDI sensor, the higher the signal-to-noise ratio of the corresponding image acquired under the same imaging conditions.

[0031] As mentioned above, there are two types of TDI image sensors currently available. One is a TDI-CCD image sensor, which has some disadvantages such as high manufacturing costs and high operating voltage. The other is a TDI image sensor based on a CMOS process. However, the transfer method of the TDI-CMOS image sensor between each stage of the linear array usually involves reading out the matrix and then performing analog domain accumulation or digital domain accumulation, which is prone to noise and requires complex control timing. Therefore, the noise level and imaging quality of the TDI-CMOS image sensor are different from those of the TDI-CCD.

[0032] This disclosure proposes that by adopting a transferable counter, a function of transferring a digital signal output by a stage to a subsequent stage is realized, and an accumulation function is realized by the count of the counter. The image sensor based on the transferable counter between the linear elements of each single stage proposed in this disclosure has advantages such as low read noise, low transfer noise, small restrictions on the modulation transfer function (MTF) for the number of TDI stages, and low cost because there is no analog-to-digital conversion process and a full digital circuit is adopted.

[0033] 2 is a schematic diagram of a linear array arrangement embodiment of a time delay integration image sensor proposed according to the principles of the present disclosure. As shown in FIG. 2, the time delay integration image sensor includes a plurality of single-line linear arrays 200 and related functional circuits, such as a timing control circuit 204, a latch and address selection circuit 205, etc. The multi-stage linear array 200 includes a plurality of single-stage linears arranged along the scanning direction of the image sensor, such as a first single-stage linear, a second single-stage linear, ... an Nth single-stage linear, and the scanning direction of the image sensor is the direction of the stages of the multi-stage single-line linears. Each single-stage linear includes a plurality of pixels 201 arranged along a linear direction perpendicular to the stage direction, and each pixel 201 includes a pixel unit 202 and a corresponding transferable counter 203.

[0034] The single-stage linear of each stage enters a count mode in response to a first control signal and enters a transfer mode in response to a second control signal. In the count mode, the single-stage linear of each stage counts optical signals incident on the pixel to obtain a count value, while in the transfer mode, the single-stage linear of each stage stops counting, and the single-stage linear of each stage other than the single-stage linear of the last stage outputs the obtained current count value to the single-stage linear of the next stage, and the single-stage linear of the last stage outputs the obtained current count value.

[0035] As shown in FIG. 2, the timing control circuit 204 generates a first control signal and a second control signal, and provides the first control signal and the second control signal to each stage of the multi-stage linear array 200 .

[0036] 2, the output of the single-stage linear at the last stage is shown to be connected to a latch and an address selection circuit. For example, the output of the single-stage linear at the last stage of the multi-stage linear array 200 is connected to a latch circuit, and the latch circuit is connected to the address selection circuit. For example, the latch circuit latches the count value output by the single-stage linear at the last stage in response to a second control signal. The address selection circuit reads the count value latched in the latch circuit so that a downstream processing circuit generates image information based on the count value.

[0037] In practice, based on the principles of the present disclosure, the timing control circuit, the latch circuit and the address selection circuit are used to respectively realize the control of transfer timing, the caching of the linear count value of the final single stage and the read control of the count value.

[0038] According to an embodiment of the present disclosure, the pixel unit adopts a single photon avalanche diode (SPAD) to realize imaging based on TDI, that is, adopts TDI-SPAD technology to realize imaging. Specifically, the SPAD is an avalanche photodiode operating in Geiger mode. When a single photon is incident on the SPAD active area, sustained avalanche multiplication occurs with a certain probability. After the avalanche multiplication is quenched by a quenching circuit, it is shaped by a pulse shaping circuit to output a digital pulse signal to the outside. Therefore, the signal output in response to a series of photons being incident on the SPAD appears as a discrete pulse signal on the time axis. The number of pulses can be counted by a counter to reflect the intensity of the incident light, thereby restoring image gray scale information. When a single-stage linear array is formed by using a plurality of SPAD pixel units and a counter for scanning, if the exposure time is not long, the signal acquired by the single-stage linear array is limited, and it is necessary to form a multi-stage linear array with the single-stage linear array to realize an improved signal-to-noise ratio. Therefore, the present disclosure proposes to adopt a transferable counter between each single-stage linear array to realize a transfer accumulation function, thereby improving the signal-to-noise ratio.

[0039] Specifically, FIG. 3 shows a schematic diagram of the circuit structure of a single pixel included in the time delay integration image sensor proposed according to the principles of the present disclosure. As shown in FIG. 3, the pixel unit includes a single photon avalanche diode (SPAD) 301, which is connected to a corresponding quench circuit 302 and a pulse shaping circuit 303. The single photon avalanche diode 301 is connected to a reverse bias voltage Vbias to operate in Geiger mode. When a single photon is incident on the active area of ​​the single photon avalanche diode 301, sustained avalanche multiplication occurs with a certain probability. After the avalanche multiplication is quenched by the quench circuit 302, it is shaped by the pulse shaping circuit 303 to output a digital pulse signal to the outside. Thus, when a series of photons are incident on the single photon avalanche diode 301, the signal output through the pulse shaping circuit appears as a discrete pulse signal on the time axis. By using a counter to count the number of pulses, the intensity of the incident light can be reflected, and image information can be restored.

[0040] According to one example of the present disclosure, each pixel includes a pixel unit that detects photons and outputs pulse signals, the number of which is related to the number of photons, and a counter that receives the pulse signals output by the pixel unit, counts the number of pulse signals in response to the first control signal to obtain the count value, and stops counting in response to the second control signal and outputs the obtained current count value.

[0041] As an example, the pixel unit may include a single photon avalanche diode SPAD, and the SPAD may be operated in Geiger mode by connecting the SPAD to a reverse bias voltage.

[0042] As an example, each pixel further includes a quench circuit connected to the SPAD that, when the SPAD receives a single photon and avalanche multiplication occurs, quenches the avalanche by reducing the reverse bias voltage of the SPAD and outputs a pulse signal.

[0043] As an example, each pixel further includes a pulse shaping circuit connected to the quenching circuit, for shaping the pulse signal output by the quenching circuit, and outputting a digital pulse signal to the counter.

[0044] According to the above example of the present disclosure, the pixel unit mainly includes a single-photon avalanche diode, the pixel unit is correspondingly connected to a counter, and the counter outputs a digital pulse signal. In the present disclosure, the counter is a transferable counter, i.e. a counter with pulse counting ability and digital transfer ability, which is used to receive the digital pulse signal output by the corresponding pixel unit, record the number of pulses, and transmit the current count value of the transferable counter at the first stage to the transferable counter at the second stage under a certain timing control.

[0045] Specifically, the present disclosure proposes to count the number of photons using an N-bit transferable counter as a counter in each pixel, the specific structure and working principle of which are described with reference to FIG. 4 and FIG.

[0046] FIG. 4 shows a schematic diagram of a circuit structure using D flip-flops to form a transferable counter. As shown in FIG. 4, the horizontal direction shows an N-bit transferable counter formed by D flip-flops corresponding to a pixel unit, the left-to-right direction is the direction from the lower to the higher count value, and the vertical direction shows an N-bit transferable counter corresponding to adjacent pixels in the direction of increasing number of stages of the linear array. Taking FIG. 4 as an example, the first row shows an N-bit transferable counter corresponding to a single-stage linear pixel unit in the first stage, and the second row shows an N-bit transferable counter corresponding to a single-stage linear pixel unit in the second stage. As an example, the two pixel units belong to two adjacent stages of pixel units in the same row in the arrangement mode of the linear array shown in FIG. 2.

[0047] Specifically, as shown in FIG. 4, for pixel units having the same position in a single-stage linear with different stages, the outputs of the pixel units of each stage are all connected to one transferable counter. For example, as shown in FIG. 4, the input end of the transferable counter 401 is called the input end corresponding to the pixel unit of the first stage, and the input end of the transferable counter 402 is called the input end corresponding to the pixel unit of the second stage, and so on. Taking the transferable counter 401 as an example, it includes multiple stages of trigger units, each stage of the trigger unit includes a flip-flop and a corresponding logic gate unit, each stage of the trigger unit corresponds to one bit of the count value, the trigger unit closer to the input end of the counter outputs the lower part of the count value, and the trigger unit farther from the input end of the counter outputs the upper part of the count value, and the number of bits of the count value increases in order from left to right. As shown in FIG. 4, the trigger unit of each stage includes one D flip-flop 403 and two data selectors 404 and 405 which are logic gate units. In the circuit shown in Fig. 4, an alternative dual line selector is used as an example of a data selector. Specifically, the D terminal of the data input terminal of the D flip-flop 403 is connected to the output terminal of the first alternative dual line selector 404, the clk terminal of the clock input terminal of the D flip-flop 403 is connected to the output terminal of the second alternative dual line selector 405, and the Q terminal of the D flip-flop 403 outputs one bit (1 bit) of the count value to the outside as a data output terminal and is connected to the first input terminal 1 of the first alternative dual line selector 404 of the trigger unit at the same position in the single-stage linear of the next stage. The Qn terminal of the D flip-flop 403 is connected to the second input terminal 2 of the first alternative dual line selector 404 of the trigger unit at the position where it is located, and is connected to the first input terminal 1' of the second alternative dual line selector 405 of the trigger unit of the next stage.

[0048] According to an example of the present disclosure, the first input terminal 1 of the first alternative dual line selector 404 of the first stage transferable counter corresponding to the pixel unit in the first stage single stage linear is both connected to the first level. For example, the first level is the zero level, which makes it easy to realize a reset operation for the counter during transfer.

[0049] In Fig. 4, the second input terminal 2' of the second alternative dual line selector 405 in the trigger unit of each stage receives a second control signal trans_sig for triggering a process of transferring count values ​​between the linear elements of the single stages of each stage. The gating control terminals 3 of the first alternative dual line selector 404 and the second alternative dual line selector 405 receive a first control signal trans_sel. According to one example, when the first control signal trans_sel signal is "0", it triggers a count mode of the transferable counter, and when the trans_sel signal is "1", it triggers a transfer mode of the transferable counter. Specifically, when the first control signal trans_sel is “0”, the signal input to the second input terminal 2 of the first alternative dual line selector 404 is gated to be connected to the D terminal of the D flip-flop, and the signal input to the first input terminal 1′ of the second alternative dual line selector 405 is gated to be connected to the clock input terminal clk of the D flip-flop, that is, the two middle data lines of the four data lines are gated, and at this time the transferable counter operates in the normal “count mode”. When the level of the first control signal trans_sel signal is “1”, the signal input to the first input terminal 1 of the first alternative dual line selector 404 is gated to be connected to the D terminal of the D flip-flop, and the signal input to the second input terminal 2′ of the second alternative dual line selector 405 is gated to be connected to the clock input terminal clk of the D flip-flop, that is, the two outer data lines of the four data lines are gated, and at this time the transferable counter operates in “transfer mode”.

[0050] Hereinafter, the operation principle of the transferable counter shown in FIG. 4 will be described in combination with the operation timing diagram of the transferable counter shown in FIG. 5. As shown in FIG. 5, the signal pulse represents the signal input by the single-stage linear pixel unit of each stage to the corresponding transferable counter, and when the level of the first control signal trans_sel is "0", the transferable counter operates in "count mode". At this time, when the rising edge of one pulse of the signal pulse reaches the input end of the trigger unit of the first stage of the transferable counter, the count value of the counter is incremented, and Stage N-2, Stage N-1, and Stage N respectively represent the count values ​​of the transferable counter of the N-2th stage, the N-1th stage, and the Nth stage. When the level of the first control signal trans_sel is "1", the transferable counter is triggered to operate in "transfer mode". As described above, the two alternative dual line selectors gate the two outer data lines of the four data lines, that is, they gate the signal input to the first input terminal 1 of the first alternative dual line selector 404 to be connected to the D terminal of the D flip-flop, and gate the signal input to the second input terminal 2' of the second alternative dual line selector 405 to be connected to the clock input terminal clk of the D flip-flop. At this time, when the rising edge of the second control signal trans_sig arrives, it triggers all the D flip-flops to output the signal input from the first input terminal 1 of the first alternative dual line selector 404 to their Q terminals, thereby transferring the count value of the previous stage counter to the next stage counter, thereby completing the overall transfer of the count value. It should be particularly noted that all the Q terminals of the first stage transferable counters output the reset signal "0", and the value of the last stage transferable counter is transferred to the latch. Thereafter, the level of the first control signal trans_sel changes to "0" again, causing the transferable counter to switch from the "transfer mode" to the "count mode".

[0051] In addition, in FIG. 4, the realization of the transferable counter is described by taking the D flip-flop as an example. For example, the basic constituent units of the transferable counter shown in FIG. 4 include a D flip-flop and a two-way dual line selector, but the actual circuit design is not limited to this. As is well known to those skilled in the art, other types of flip-flops may be adopted to realize the transferable counter. For example, flip-flops such as JK flip-flops, SR flip-flops, and T flip-flops can be adopted and combined with the necessary logic gate circuits to realize similar functions.

[0052] Figure 6 shows a schematic diagram of a JK flip-flop combined with the necessary logic gate circuit to convert it into a D flip-flop. The conversion formula of the two input terminals J and K of the JK flip-flop 601 is:

number

[0053] Similarly, similar trigger units and corresponding forward counter circuits may be implemented by circuits such as T flip-flops, SR flip-flops, etc., and will not be described further here.

[0054] As described above, based on the principles of the present disclosure, the counter includes trigger units cascaded in multiple stages, and in the trigger units cascaded in multiple stages, the trigger unit of each stage includes a flip-flop, a first data selector and a second data selector connected to the flip-flop, and the flip-flop of each stage includes a data input terminal connected to the output terminal of the first data selector, a clock input terminal connected to the output terminal of the second data selector, a first output terminal for outputting a count pulse, and a second output terminal connected to the first input terminal of the first data selector, the first input terminal of the second data selector in the trigger units of each stage other than the first stage trigger unit is connected to the second output terminal of the flip-flop in the previous stage, the first input terminal of the second data selector in the first stage trigger unit is connected to the output terminal of the pulse shaping circuit, and the second input terminal of the second data selector in the trigger unit of each stage receives a second control signal.

[0055] According to one example of the present disclosure, the second input terminal of the first data selector in each single-stage linear pixel other than the first stage single-stage linear pixel is connected to the first output terminal of the flip-flop in the corresponding pixel of the previous stage single-stage linear pixel, the second input terminal of the first data selector in the first stage single-stage linear pixel receives a first level signal, and the first output terminal of the flip-flop in the last stage single-stage linear pixel is connected to a latch circuit.

[0056] According to an example of the present disclosure, the control ends of the first data selector and the second data selector in the trigger unit receive a first control signal.

[0057] According to one example of the present disclosure, the flip-flop may be a D flip-flop.

[0058] According to one example of the present disclosure, the flip-flop may be one of a JK flip-flop, an RS flip-flop, and a T flip-flop, and the trigger unit further includes a logic gate circuit connected to the flip-flop so as to realize the function of a D flip-flop using the JK flip-flop, the RS flip-flop, or the T flip-flop.

[0059] Based on the principles of the present disclosure, the TDI image sensor may adopt other types of linear array arrangements in addition to the arrangement shown in FIG. 2 in which pixel unit linear and counter linear are alternately arranged in a multi-stage linear array and arranged in the same layer.

[0060] For example, according to another embodiment of the present disclosure, the pixel unit linear and the counter linear form a pixel unit array and a counter array, respectively, and the pixel unit array and the counter array are arranged on the same layer, and the pixel units in the pixel unit array are electrically connected to corresponding counters in the counter array. For example, as shown in Fig. 7, the pixel unit array and the counter array are independently designed and arranged in the form of two independent arrays, respectively, and the pixel units and the counters are connected in one-to-one correspondence by metal lines, and related functional circuits such as timing control circuits, latch circuits, and address selection circuits are arranged on the periphery.

[0061] According to another embodiment of the present disclosure, the following arrangement of the linear array may be further adopted. The pixel unit linear and the counter linear form a pixel unit array and a counter array, respectively, and the pixel unit array and the counter array are arranged in different layers. For example, the pixel unit array and the counter array are arranged in different layers according to a 3D stacking process, and the pixel units in the pixel unit array are electrically connected to corresponding counters in the counter array. For example, the pixel unit array and the counter array may be electrically connected by a through silicon via TSV method. Specifically, as shown in FIG. 8, by adopting a 3D stacking process, the pixel unit array, the counter array and related functional circuits are designed in different layers, and the pixel units and the counters are electrically connected between the two layers in one-to-one correspondence. For example, the through silicon via (TSV) technology may be adopted to realize the electrical connection between the pixel units and the counters in one-to-one correspondence.

[0062] In a linear array arrangement, the quenching circuit and / or the shaping circuit may be integrated in the pixel unit together with the single photon avalanche diode SPAD, or, depending on needs, the quenching circuit and / or the shaping circuit may not be integrated in the pixel unit together with the SPAD, but may be arranged outside the pixel unit and even in a different layer from the pixel unit array.

[0063] According to another aspect of the present disclosure, there is further provided an imaging method based on time delay integration (TDI). As shown in Fig. 9, the method includes: S910, scanning an object to be imaged using a plurality of single-stage linears arranged along a scanning direction of an image sensor, the scanning direction of the image sensor is a stage direction, each single-stage linear includes a plurality of pixels arranged along a linear direction, the linear direction is perpendicular to the stage direction, and in response to a first control signal, each single-stage linear enters a counting mode, and in response to a second control signal, each single-stage linear enters a transfer mode, in the counting mode, each single-stage linear is used to count optical signals incident on pixels and obtain count values, while in the transfer mode, each single-stage linear stops counting, and transfers the obtained current count values ​​of each single-stage linear of the other stages except the last single-stage linear to the next single-stage linear, and outputs the obtained current count value of the last single-stage linear.

[0064] As an example, in the method, the optical signals are photons, and the method includes: using a pixel unit to detect the photons and output pulse signals, the number of which is related to the number of photons; using a counter to receive the pulse signals output by the pixel unit, count the number of pulse signals in response to the first control signal, obtain the count value, and in response to the second control signal, stop counting and output the obtained current count value.

[0065] As an example, the method employs a single-photon avalanche diode SPAD to detect photons and output a pulse signal, and operates the SPAD in Geiger mode by connecting the SPAD to a reverse bias voltage.

[0066] For example, the method further includes latching a count value output by the final single-stage linear in response to the second control signal, and reading the count value of the latch so as to generate image information based on the count value.

[0067] The time delay integration type image sensor proposed according to the present disclosure has a fully digitalized imaging process and transfer process, and has a low noise introduction level and a small impact of the number of transfers on the MTF. As shown in Figure 10, the MTF is related to the transfer efficiency and the number of stages of the array, and since there is residual charge during the conventional TDI-CCD transfer and the transfer efficiency is less than 1, the MTF decreases with the increase in the number of stages. On the contrary, the time integration type image sensor with transferable counter adopted in the present disclosure can achieve a transfer efficiency p=1 and is not limited by the number of stages, so it has the advantages of lower read noise, lower transfer noise, less restriction on the MTF for the number of TDI stages, and lower cost compared to the technology of the conventional TDI-CCD image sensor.

[0068] The embodiments described herein may be implemented, for example, as a method or process, an apparatus, a software program, a data stream, or a signal. Even if discussed in the context of a single embodiment (e.g., discussed only as a method or an apparatus), the embodiments of the discussed features may be implemented in other forms (e.g., a program). The apparatus may be implemented, for example, using appropriate hardware, software, and firmware. The methods may be implemented, for example, in an apparatus of a processor, which generally refers to processing equipment including, for example, a computer, a microprocessor, an integrated circuit, or a programmable logic device. Processors further include communication equipment, for example, computers, mobile phones, portable / personal digital assistants, and other equipment that facilitates communication of information between terminal users.

[0069] While a number of embodiments have been described, it should be understood that various modifications are possible. For example, elements of different embodiments can be combined, supplemented, modified, or removed to produce other embodiments. Moreover, those skilled in the art will appreciate that the disclosed structures and processes can be substituted with other structures and processes such that the resulting embodiments can perform at least substantially the same function in at least substantially the same way as the disclosed embodiments to achieve at least substantially the same results. Thus, this application contemplates these and other embodiments. [Explanation of symbols]

[0070] 200 Linear Array 201 pixels 202 pixel unit 203 Transferable Counter 204 Timing control circuit 205 Latch and address selection circuit 301 Single-photon avalanche diode 302 Quench Circuit 303 Pulse Shaping Circuit 401 Transferable Counter 402 Transferable Counter 403 D Flip Flop 404 1st Alternative Dual Line Selector 405 2nd Alternative Dual Line Selector 601 JK Flip Flop

Claims

1. 1. A time delay integration (TDI) based image sensor, comprising: a multi-stage linear array including a plurality of single-stage linears arranged along a scan direction of an image sensor, the scan direction of the image sensor being a stage direction, each single-stage linear including a plurality of pixels arranged along the linear direction, the linear direction being perpendicular to the stage direction; The single-stage linear of each stage enters a count mode in response to a first control signal, and enters a transfer mode in response to a second control signal, and in the count mode, the single-stage linear of each stage counts optical signals incident on pixels to obtain count values, while in the transfer mode, the single-stage linear of each stage stops counting, and the single-stage linear of each stage other than the single-stage linear of the last stage outputs the obtained current count value to the single-stage linear of the next stage, and the single-stage linear of the last stage outputs the obtained current count value; The time delay integration (TDI) based image sensor comprises: a latch circuit for latching a count value output by a final single-stage linear in response to the second control signal; an address selection circuit for reading the count value latched by the latch circuit so that a subsequent processing circuit generates image information based on the count value; The pixel includes a pixel unit and a counter; The counter includes trigger units that are cascaded in multiple stages, and in the multiple cascaded trigger units, the trigger units in each stage include a flip-flop, a first data selector and a second data selector that are connected to the flip-flop, and the flip-flop in each stage includes: a data input connected to the output of the first data selector; a clock input connected to the output of the second data selector; a first output terminal for outputting a count pulse; a second output terminal connected to the second input terminal of the first data selector; A first input terminal of the second data selector in each of the trigger units other than the first-stage trigger unit is connected to a second output terminal of the flip-flop in the previous-stage trigger unit, and a first input terminal of the second data selector in the first-stage trigger unit is connected to an output terminal of the pulse shaping circuit; A second input of the second data selector in the trigger unit of each stage receives a second control signal.

2. the optical signal is a photon; The pixel unit detects the photons and outputs a pulse signal whose number is related to the number of photons; 2. The image sensor according to claim 1, wherein the counter receives a pulse signal output by a pixel unit, obtains the count value by counting the number of pulse signals in response to the first control signal, and stops counting and outputs the obtained current count value in response to the second control signal.

3. The image sensor of claim 2 , wherein the pixel unit includes a single-photon avalanche diode SPAD, and the SPAD is operated in Geiger mode by connecting the SPAD to a reverse bias voltage.

4. Each pixel is 4. The image sensor according to claim 3, further comprising a quenching circuit connected to the SPAD, which, when the SPAD receives a single photon and avalanche multiplication occurs, quenches the avalanche by reducing a reverse bias voltage of the SPAD and outputs a pulse signal.

5. Each pixel is 5. The image sensor of claim 4, further comprising a pulse shaping circuit coupled to the quench circuit for shaping the pulse signal output by the quench circuit and outputting a digital pulse signal to the counter.

6. 6. The image sensor of claim 1, further comprising a timing control circuit that generates and provides the first and second control signals to each stage in a multi-stage linear array.

7. The image sensor according to any one of claims 2 to 5, wherein in each single stage linear, the pixel units and the counters respectively form a pixel unit linear and a counter linear along the array direction.

8. The pixel unit linear and the counter linear are arranged alternately with each other in a multi-stage linear array and are arranged in the same layer; or 8. The image sensor of claim 7, wherein the pixel unit linear and the counter linear form a pixel unit array and a counter array, respectively, and the pixel unit array and the counter array are disposed in the same layer, and the pixel units in the pixel unit array are electrically connected to corresponding counters in the counter array.

9. The image sensor according to claim 7 , wherein the pixel unit linear and the counter linear form a pixel unit array and a counter array, respectively, and the pixel unit array and the counter array are disposed on different layers.

10. The image sensor of claim 9 , wherein the pixel unit array and the counter array are arranged in different layers according to a 3D stacking process, and a pixel unit in the pixel unit array is electrically connected to a corresponding counter in the counter array.

11. The image sensor of claim 5 , wherein at least one of the quench circuit and the pulse shaping circuit is integrated into the pixel unit.

12. The second input terminal of the first data selector in each of the single-stage linear pixels other than the first single-stage linear pixel is connected to the first output terminal of the corresponding flip-flop in the previous single-stage linear pixel; The second input terminal of the first data selector in the first single-stage linear pixel receives a first level signal; 2. The image sensor according to claim 1, wherein a first output terminal of the flip-flop in the last single-stage linear pixel is connected to a latch circuit.

13. The image sensor according to claim 1 , wherein the control ends of the first data selector and the second data selector in the trigger unit receive a first control signal.

14. The image sensor of claim 1 , wherein the flip-flop is a D flip-flop.

15. 2. The image sensor of claim 1, wherein the flip-flop is one of a JK flip-flop, an RS flip-flop, and a T flip-flop, and the trigger unit further includes a logic gate circuit connected to the flip-flop to realize a function of a D flip-flop using the JK flip-flop, the RS flip-flop, or the T flip-flop.

16. 1. A time delay integration (TDI) based imaging method, comprising: Scanning the object to be imaged using a plurality of single-stage linears arranged along a scan direction of the image sensor, the scan direction of the image sensor being a stage direction, each single-stage linear includes a plurality of pixels arranged along the linear direction, the linear direction being perpendicular to the stage direction; responsive to a first control signal, causing each single-stage linear to enter a count mode, and responsive to a second control signal, causing each single-stage linear to enter a transfer mode; In the count mode, the single-stage linear of each stage is used to count the optical signal incident on the pixel to obtain a count value, while in the transfer mode, the single-stage linear of each stage is made to stop counting, and the current count value obtained by the single-stage linear of each stage other than the single-stage linear of the last stage is transferred to the single-stage linear of the next stage, and the current count value obtained by the single-stage linear of the last stage is output; The time delay integration (TDI) based image sensor comprises: a latch circuit for latching a count value output by a final single-stage linear in response to the second control signal; an address selection circuit for reading the count value latched by the latch circuit so that a subsequent processing circuit generates image information based on the count value; The pixel includes a pixel unit and a counter; The counter includes trigger units that are cascaded in multiple stages, and in the multiple cascaded trigger units, the trigger units in each stage include a flip-flop, a first data selector and a second data selector that are connected to the flip-flop, and the flip-flop in each stage includes: a data input connected to the output of the first data selector; a clock input connected to the output of the second data selector; a first output terminal for outputting a count pulse; a second output terminal connected to the second input terminal of the first data selector; A first input terminal of the second data selector in each of the trigger units other than the first-stage trigger unit is connected to a second output terminal of the flip-flop in the previous-stage trigger unit, and a first input terminal of the second data selector in the first-stage trigger unit is connected to an output terminal of the pulse shaping circuit; A second input of the second data selector in the trigger unit of each stage receives a second control signal.

17. the optical signal is a photon, and the imaging method comprises: Detecting photons using the pixel units and outputting pulse signals whose number is related to the number of photons; 17. The imaging method of claim 16, further comprising: using the counter to receive pulse signals output by pixel units; counting a number of the pulse signals in response to the first control signal to obtain the count value; and stopping counting and outputting the obtained current count value in response to the second control signal.

18. 20. The imaging method of claim 17, further comprising employing a single-photon avalanche diode SPAD to detect photons and output a pulse signal, and operating the SPAD in Geiger mode by connecting the SPAD to a reverse bias voltage.

19. latching the count value output by the final single-stage linear in response to the second control signal; The method of imaging according to any one of claims 16 to 18, further comprising: reading the count value of the latch to generate image information based on the count value.

Images