Packaging substrate and manufacturing method thereof

Abstract

To provide a packaging substrate and a method for manufacturing the same applicable to high-speed circuits by greatly improving electrical characteristics such as signal transmission speed and making the insulating film treatment process simpler by virtually preventing the generation of parasitic elements.SOLUTION: A semiconductor device 100 includes a semiconductor element section 30 including semiconductor elements 32 to 36 and a packaging substrate 20 electrically connected to the semiconductor element section, and by applying a glass substrate as a core to the packaging substrate, the semiconductor elements and a motherboard 10 are more closely connected so that electrical signals are transmitted over a maximum short distance.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The embodiment relates to a packaging substrate and a manufacturing method thereof. [CROSS REFERENCE TO RELATED APPLICATIONS]

[0002] This application claims the benefit of priority from U.S. Provisional Patent Application No. 62 / 816,984, filed March 12, 2019, U.S. Provisional Patent Application No. 62 / 816,972, filed March 12, 2019, U.S. Provisional Patent Application No. 62 / 825,966, filed March 29, 2019, and U.S. Provisional Patent Application No. 62 / 825,945, filed March 29, 2019, the contents of which are incorporated herein by reference in their entirety. [Background technology]

[0003] In manufacturing electronic components, the process of forming circuits on a semiconductor wafer is called the front-end process (FE), and the process of assembling the wafer so that it can be used in an actual product is called the back-end process (BE), which includes the packaging process.

[0004] The four core technologies of the semiconductor industry that have enabled the rapid development of electronic products in recent years are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology has evolved into various forms, such as nano-level line widths below microns, more than 10 million cells, high-speed operation, and large amounts of heat dissipation, but the technology to perfectly package these has not been supported. Therefore, the electrical performance of semiconductors is sometimes determined by packaging technology and the resulting electrical connections rather than the performance of the semiconductor technology itself.

[0005] The packaging substrate is made of ceramic or resin. Since the ceramic substrate has a high resistance or a high dielectric constant, it is not easy to mount high-performance, high-frequency semiconductor elements on it. In the case of a resin substrate, it is possible to mount relatively high-performance, high-frequency semiconductor elements, but there is a limit to how much the wiring pitch can be reduced.

[0006] In recent years, research is underway into the application of silicon and glass to high-end packaging substrates. By forming through holes in silicon or glass substrates and applying conductive materials to the through holes, the length of the wiring between the device and the motherboard can be shortened, resulting in excellent electrical characteristics.

[0007] Related prior literature includes: Korean Patent Publication No. 10-2019-0008103, Korean Patent Publication No. 10-2016-0114710, Korean Patent Registration No. 10-1468680, etc. Summary of the Invention [Problem to be solved by the invention]

[0008] An object of the embodiment is to provide a more integrated packaging substrate and a semiconductor device including the same by applying a glass substrate.

[0009] An object of the embodiment is to provide a substrate for semiconductor packaging including a glass substrate having a core seed layer formed inside a core via, and a manufacturing method thereof. [Means for solving the problem]

[0010] To achieve the above object, a packaging substrate according to an embodiment includes: i) a glass substrate having a first surface and a second surface facing each other; ii) a number of core vias penetrating the thickness of the glass substrate; and iii) a core layer located on a surface of the core via and including a core seed layer serving as a seed for forming an electrically conductive layer. The core via includes a first opening in contact with the first surface, a second opening in contact with the second surface, and a minimum inner diameter portion that is an area in the entire core via that connects the first opening and the second opening and has the narrowest inner diameter. The ratio of the larger of the diameter of the first opening, which is the diameter of the first surface opening, and the diameter of the second opening, which is the diameter of the second opening, to the diameter of the minimum inner diameter portion is 1:0.65 to 0.99.

[0011] The ratio (thickness ratio) of a first thickness and a second thickness, which are thicknesses of the core seed layer measured at two positions facing each other on the inner diameter surface of the core via, is 1:0.4 to 4.5.

[0012] The thickness deviation rate of the core seed layer, represented by the following formula 1, is 83% or less. [Formula 1] Thickness deviation rate = ((maximum thickness of core seed layer - minimum thickness of core seed layer) / average thickness of core seed layer) x 100%

[0013] The core via includes a first opening in contact with the first surface; a second opening in contact with the second surface; and a minimum inner diameter portion that is the area of ​​the entire core via whose inner diameter is narrowest, connecting the first opening and the second opening.

[0014] The ratio of the larger of the diameter of the first opening, which is the diameter of the first surface opening, and the diameter of the second opening, which is the diameter of the second opening, to the diameter of the minimum inner diameter portion is 1:0.65 to 0.99.

[0015] The larger of an angle (Ca1) of an inner diameter surface connecting the minimum inner diameter portion and the first opening and an angle (Ca2) of an inner diameter surface connecting the minimum inner diameter portion and the second opening may be 0.5 degrees to 6.5 degrees.

[0016] The minimum inner diameter portion may be located at a point that is 40% to 60% of the total length of the core via, based on the first opening.

[0017] The ratio of the larger of the diameter of the first opening, which is the diameter of the first side opening, and the diameter of the second opening, which is the diameter of the second opening, to the thickness of the glass substrate may be 1:2-4.

[0018] In one embodiment, the core seed layer may have an average thickness of 30 nm to 200 nm.

[0019] The ratio of the diameter of the minimum inner diameter portion to the thickness of the glass substrate may be 1:2.5-6.

[0020] The diameter of the minimum inner diameter portion may be 50% to 99% of the diameter of the first opening or the second opening, whichever has the larger diameter.

[0021] The core distribution layer may include an electrically conductive layer, at least a portion of which electrically couples the electrically conductive layer on the first side and the electrically conductive layer on the second side through the core via.

[0022] The thickness of the thinner of the electrically conductive layers of the core distribution layer may be the same as or greater than the thickness of the thinner of the electrically conductive layers of the top layer.

[0023] In order to achieve the above object, a method for manufacturing a substrate for semiconductor packaging according to another embodiment includes: A preparation step of providing a pre-processed substrate having a glass substrate having a first surface and a second surface facing each other, and a number of core vias penetrating the glass substrate in a thickness direction; and The method may include a sputtering step of sputtering at a predetermined angle with respect to a reference line perpendicular to the first surface to form a core seed layer on an inner diameter surface of the core via.

[0024] The ratio (thickness ratio) of a first thickness and a second thickness, which are thicknesses of the core seed layer measured at two positions facing each other on the inner diameter surface of the core via, is 1:0.4 to 4.5.

[0025] The thickness deviation rate of the core seed layer, represented by the following formula 1, is 83% or less. [Formula 1] Thickness deviation rate = ((maximum thickness of core seed layer - minimum thickness of core seed layer) / average thickness of core seed layer) x 100%

[0026] The core via includes a first opening in contact with the first surface; a second opening in contact with the second surface; and a minimum inner diameter portion that is the area of ​​the entire core via whose inner diameter is narrowest, connecting the first opening and the second opening.

[0027] The ratio of the larger of the diameter of the first opening, which is the diameter of the first surface opening, and the diameter of the second opening, which is the diameter of the second opening, to the diameter of the minimum inner diameter portion is 1:0.65 to 0.99.

[0028] The packaging substrate is the packaging substrate of the above embodiment. Effect of the Invention

[0029] The packaging substrate and the semiconductor device including the same of the embodied example can connect the semiconductor element and the motherboard more closely, allowing electrical signals to be transmitted over the shortest possible distance, thereby significantly improving electrical characteristics such as signal transmission speed.

[0030] In addition, the glass substrate used as the core of the substrate is itself an insulator, so there is almost no risk of parasitic elements occurring compared to existing silicon cores, the insulating film processing process can be simplified, and it can be applied to high-speed circuits.

[0031] In addition, unlike silicon manufactured in the form of round wafers, glass substrates are manufactured in the form of large panels, making mass production relatively easy and further improving economic efficiency. [Brief description of the drawings]

[0032] [Figure 1] 1 is a conceptual diagram illustrating a cross section of a semiconductor device according to an embodiment; [Diagram 2] 1 is a conceptual diagram illustrating a cross section of a packaging substrate according to an embodiment; [Diagram 3]1A shows a state in which a glass substrate in which a core via is formed is viewed from above, and FIG. 1B is a conceptual diagram illustrating a cross section taken along the line aa' in FIG. [Figure 4] 1A and 1B are schematic diagrams illustrating the cross-sectional shape of a core via applied in an embodiment. [Diagram 5] FIG. 4(b) is a conceptual diagram illustrating a cross section of the state in which a core insulating layer has been further formed. [Figure 6] 1 is a detailed conceptual diagram illustrating a portion of a cross section of a packaging substrate according to an embodiment; [Figure 7] 1 is a detailed conceptual diagram illustrating a portion of a cross section of a packaging substrate according to an embodiment; [Figure 8] 1 is a flowchart illustrating a cross-sectional view of a manufacturing process of a packaging substrate according to an embodiment. [Figure 9] 1 is a flowchart illustrating a cross-sectional view of a manufacturing process of a packaging substrate according to an embodiment. [Figure 10] 1 is a flowchart illustrating a cross-sectional view of a manufacturing process of a packaging substrate according to an embodiment. [Figure 11] 1A illustrates a glass substrate having a core via according to an embodiment as viewed from above, and FIG. 1B is a conceptual diagram illustrating a cross section of the core via. [Figure 12] 11 is a cross-sectional conceptual diagram of a core via for explaining measurement points applied when evaluating a thickness deviation in an embodiment; FIG. [Figure 13] 4 is a photograph showing an example of thickness measurement of a core seed layer measured according to an embodiment. [Figure 14] 1A illustrates a glass substrate having a core via according to another embodiment as viewed from above, and FIG. 1B is a conceptual diagram illustrating a cross section of the core via. [Figure 15] 13 is a cross-sectional conceptual diagram of a core via for explaining measurement points applied when evaluating a thickness deviation in another embodiment; FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily understand the embodiments. However, the embodiments may be embodied in various different forms and are not limited to the embodiments described herein. The same reference numerals are used throughout the specification to refer to similar parts.

[0034] Throughout this specification, the term "combinations thereof" contained in a Markush form expression means a mixture or combination of one or more selected from the group consisting of each of the components described in the Markush form expression, and is meant to include one or more selected from the group consisting of each of the components.

[0035] Throughout this specification, terms such as "first", "second", "A", "B", etc. are used to distinguish identical terms from one another. Furthermore, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0036] In this specification, the term "based on ~" may mean that the compound includes "a compound corresponding to ~" or "a derivative of ~".

[0037] In this specification, "B is located on A" means that B is located on A in direct contact with A, or that B is located on A with another layer located therebetween, and is not to be interpreted as being limited to B being located in contact with the surface of A.

[0038] In this specification, B being linked to A means that A and B are directly linked or that A and B are linked via another component therebetween, and unless otherwise specified, it is not to be interpreted as being limited to A and B being directly linked.

[0039] In this specification, the term "singular" is intended to include the singular or plural as the context requires, unless otherwise specified.

[0040] In the process of developing a semiconductor device that is more integrated and can exhibit high performance with a thin thickness, the inventors recognized that not only the element itself but also the packaging part is an important factor in improving performance, and in the course of research into this, they confirmed that, unlike the case where two or more layers of cores are applied to a motherboard as a packaging substrate like the existing interposer and organic substrate, the packaging substrate can be made thinner and electrical characteristics of the semiconductor device can be improved by applying a method of applying a glass core in a single layer and controlling the shape of the through via and the electrically conductive layer formed thereon. In the process of realizing such a packaging substrate, in order to form an electrically conductive layer having a relatively uniform thickness inside the core via of the glass substrate so that problems such as short circuits do not occur, it is necessary to form a uniform buffer layer on the inner diameter surface of the core via. In the embodiment, a core seed layer is applied through sputtering as described below.

[0041]

[0042] FIG 1 is a conceptual diagram illustrating a cross section of a semiconductor device according to an embodiment, FIG 2 is a conceptual diagram illustrating a cross section of a packaging substrate according to an embodiment, FIG 3(a) shows a state in which a core via is formed in a glass substrate as viewed from above, and FIG 3(b) is a conceptual diagram illustrating a cross section taken along a-a' line in FIG 3(a). FIG 4(a) and FIG 4(b) are conceptual diagrams illustrating the cross section of a core via applied in an embodiment, FIG 5 is a conceptual diagram illustrating a cross section of FIG 4(b) in which a core insulating layer is further formed, FIG 6 is a detailed conceptual diagram illustrating a part of a cross section of a packaging substrate according to an embodiment, and FIG 7 is a detailed conceptual diagram illustrating a part of a cross section of a packaging substrate according to an embodiment. Hereinafter, the embodiment will be described in more detail with reference to FIG 1 to FIG 7.

[0043]

[0044] Semiconductor device 100

[0045] To achieve the above objective, the semiconductor device 100 of the embodiment includes a semiconductor device part 30 in which one or more semiconductor devices 32, 34, 36 are located; a packaging substrate 20 electrically connected to the semiconductor devices; and a motherboard 10 electrically connected to the packaging substrate, transmitting external electrical signals to the semiconductor devices and connecting the semiconductor devices to each other.

[0046] The packaging substrate 20 according to another embodiment includes a core layer 22 and a top layer 26.

[0047] The semiconductor element section 30 means each element mounted on a semiconductor device, and is mounted on the packaging substrate 20 by connection electrodes or the like. Specifically, the semiconductor element section 30 may be, for example, a computing element such as a CPU or a GPU (first element: 32, second element: 34), a storage element such as a memory chip (third element, 36), or the like, but may be any semiconductor element mounted on a semiconductor device without any restrictions.

[0048] The motherboard 10 may be a motherboard such as a printed circuit board or a printed wiring board.

[0049] The packaging substrate 20 includes a core layer 22 and a top layer 26 disposed on one side of the core layer.

[0050] The packaging substrate 20 may optionally further include a lower layer 29 located below the core layer.

[0051] The core layer 22 includes a glass substrate 21; a number of core vias 23 penetrating the glass substrate in the thickness direction; and a core distribution layer 24 in which an electrically conductive layer is located on a surface of the glass substrate or the core vias, at least a portion of which electrically connects the electrically conductive layers on the first surface and the second surface through the core vias.

[0052] The glass substrate 21 has a first surface 213 and a second surface 214 facing each other, the two surfaces being generally parallel to each other, and has a constant thickness throughout the glass substrate.

[0053] The glass substrate 21 has a core via 23 that penetrates the first surface and the second surface.

[0054] Conventionally, packaging substrates for semiconductor devices are formed by stacking a silicon substrate and an organic substrate. In the case of silicon substrates, due to the characteristics of semiconductors, there is a risk of parasitic elements occurring when applied to high-speed circuits, and there is a disadvantage in that power loss is relatively large. In addition, in the case of organic substrates, a large area is required to form more complex distribution patterns, which does not match with the trend of manufacturing electronic devices that are becoming ultra-miniaturized. In order to form a complex distribution pattern within a set size, it is necessary to substantially fine the pattern, but there is a substantial limit to the fine pattern due to the characteristics of materials such as polymers applied to organic substrates.

[0055] In the embodiment, to solve this problem, a glass substrate 21 is used as a support for a core layer 22. In addition, by using a core via 23 formed through the glass substrate together with the glass substrate, the length of electrical flow is shortened, providing a packaging substrate 20 that is more compact, has faster response, and has less loss characteristics.

[0056] The glass substrate 21 is preferably a glass substrate used in semiconductors, and examples of glass substrates that may be used include, but are not limited to, borosilicate glass substrates and non-alkali glass substrates.

[0057] The thickness of the glass substrate 21 may be 1,000 μm or less, 100 μm to 1,000 μm, or 100 μm to 700 μm. More specifically, the thickness of the glass substrate 21 may be 100 μm to 500 μm. Forming a thinner packaging substrate is advantageous in that electrical signals can be transmitted more efficiently, but since the substrate must also function as a support, it is preferable to use a glass substrate 21 having the above thickness. Here, the thickness of the glass substrate means the thickness of the glass substrate itself excluding the thickness of the electrically conductive layer located on the glass substrate.

[0058] The core via 23 may be formed by removing a predetermined area of ​​the glass substrate 21, specifically, by etching a plate-shaped glass by physical and / or chemical methods.

[0059] Specifically, when forming the core via 23, a defect (groove) may be formed on the surface of the glass substrate using a laser or the like, and then chemical etching, laser etching, etc. may be applied, but is not limited thereto.

[0060] The core via 23 includes a first opening 233 in contact with the first surface; a second opening 234 in contact with the second surface; and a minimum inner diameter portion 235 which is the area whose inner diameter is narrowest in the entire core via connecting the first opening and the second opening.

[0061] The diameter of the first opening (CV1) and the diameter of the second opening (CV2) may be substantially different or may be substantially the same.

[0062] The minimum inner diameter portion may be located at the first opening or the second opening, and the core via may be a cylindrical or (truncated) pyramidal core via. In this case, the diameter (CV3) of the minimum inner diameter portion corresponds to the smaller diameter of the first opening or the second opening.

[0063] The minimum inner diameter portion may be located between the first opening and the second opening, and the core via may be a barrel-type core via. In this case, the diameter (CV3) of the minimum inner diameter portion may be smaller than the larger of the diameters of the first opening and the second opening.

[0064] Specifically, the average diameter of the minimum inner diameter portion may be 50 μm to 95 μm.

[0065] The minimum inner diameter portion can satisfy the condition of the following formula 1.

[0066] [Formula 1]

[0067] JPEG0007599518000001.jpg12131

[0068] In the above formula 1, D 50 is the value that corresponds to 50% of the diameter distribution of the smallest inner diameter, D 90 is the value that corresponds to 90% of the diameter distribution of the smallest inner diameter, D 10 is the value that corresponds to 10% of the diameter distribution of the smallest inner diameter part.

[0069] The average diameter of the minimum inner diameter portion may be 55 μm to 85 μm, or may be 60 μm to 70 μm.

[0070] More specifically, the minimum inner diameter portion can satisfy the condition of the following formula 1-1.

[0071] [Formula 1-1]

[0072] JPEG0007599518000002.jpg12142

[0073] In the above formula 1-1, D 50 is the value that corresponds to 50% of the diameter distribution of the smallest inner diameter, D 90 is the value that corresponds to 90% of the diameter distribution of the smallest inner diameter, D 10 is the value that corresponds to 10% of the diameter distribution of the smallest inner diameter part.

[0074] Specifically, the target opening, which is the larger of the diameter of the first opening and the diameter of the second opening, may have an average diameter of 70 μm to 120 μm.

[0075] Specifically, the target opening, which is the larger of the diameter of the first opening and the diameter of the second opening, can satisfy the condition of the following formula 2.

[0076] [Formula 2]

[0077] JPEG0007599518000003.jpg14154

[0078] In the above formula 2, D 50 is the value that corresponds to 50% of the diameter distribution of the target opening, and D 90 is the value that corresponds to 90% of the diameter distribution of the target openings, and D 10 is the value that corresponds to 10% of the diameter distribution of the target openings.

[0079] Specifically, the target opening, which is the larger of the diameter of the first opening and the diameter of the second opening, may have an average diameter of 80 μm to 105 μm.

[0080] Specifically, the target opening, which is the larger of the diameter of the first opening and the diameter of the second opening, can satisfy the condition of the following formula 2-1.

[0081] [Formula 2-1]

[0082] JPEG0007599518000004.jpg14165

[0083] In the above formula 2-1, D 50 is the value that corresponds to 50% of the diameter distribution of the target opening, and D 90 is the value that corresponds to 90% of the diameter distribution of the target openings, and D 10 is the value that corresponds to 10% of the diameter distribution of the target openings.

[0084] The core via has a diameter of a first opening, which is a diameter at an opening in contact with the first surface, and a diameter of a second opening, which is a diameter at an opening in contact with the second surface, and the average diameter of the target openings, which is the larger of these, is a value corresponding to 50% of the diameter distribution of the target openings. 50 It can have a larger value.

[0085] The diameter distribution described above was evaluated based on the diameters measured by dividing the prepared sample into nine sections (3×3) and taking samples from the top left, bottom left, center, top right, and bottom right regions, cutting the samples, and observing the cross sections under a microscope.

[0086] The thickness of the electrically conductive layer measured over the larger of the diameter of the first opening (CV1) and the diameter of the second opening (CV2) may be the same as or thicker than the thickness of the electrically conductive layer formed on the portion of the core via having the smallest inner diameter (CV3).

[0087] The core vias 23 may be positioned in an amount of 100 to 3000, 100 to 2500, or 225 to 1024 per unit area (1 cm×1 cm) of the glass substrate 21. When such pitch conditions are satisfied, the formation of an electrical conductive layer and the performance of the packaging substrate can be improved.

[0088] The core vias 23 may be positioned at a pitch of 1.2 mm or less, at a pitch of 0.12 mm to 1.2 mm, or at a pitch of 0.3 mm to 0.9 mm on the glass substrate 21. In this case, it is advantageous to form an electrically conductive layer while maintaining the mechanical properties of the glass substrate at a certain level or higher.

[0089] The core distribution layer 24 includes a core distribution pattern 241, which is an electrically conductive layer that electrically connects the first and second surfaces of the glass substrate through a through via, and a core insulating layer 223 that covers the core distribution pattern.

[0090] The core layer 22 has an electrically conductive layer formed therein through a core via, and serves as an electrical path across the glass substrate 21, connecting the upper and lower parts of the glass substrate over a relatively short distance, thereby enabling faster electrical signal transmission and low loss.

[0091] The core distribution pattern 241 is a pattern that electrically connects the first surface 213 and the second surface 214 of the glass substrate through the core vias 23, and specifically includes a first surface distribution pattern 241a which is an electrically conductive layer located on at least a portion of the first surface 213, a second surface distribution pattern 241c which is an electrically conductive layer located on at least a portion of the second surface 214, and a core via distribution pattern 241b which is an electrically conductive layer that electrically connects the first surface distribution pattern and the second surface distribution pattern to each other through the core vias 23. Each of the electrically conductive layers may be, for example, a copper plating layer, but is not limited thereto.

[0092] The core via 23 includes a first opening 233 in contact with the first surface; a second opening 234 in contact with the second surface; and a minimum inner diameter portion 235 which is the area of ​​the entire core via whose inner diameter is narrowest, connecting the first opening and the second opening.

[0093] The glass substrate 21 acts as an intermediate connecting the semiconductor device part 30 and the motherboard 10 at the upper and lower parts, respectively, and the core vias 23 act as paths for transmitting electrical signals, facilitating the transmission of the signals.

[0094] The cross-sectional shape of the core via 23 may be such that one opening has a larger diameter and the other opening has a smaller diameter based on the thickness of the glass substrate (see FIG. 4(a) and photo), or the core via may be generally barrel-shaped with the inner diameter of the core via being somewhat narrower in the center (see FIG. 4(b) and photo).

[0095] The core via 23 has a first surface opening diameter (CV1) which is the diameter at the first opening, a second surface opening diameter (CV2) which is the diameter at the second opening, and a minimum inner diameter diameter (CV3) which is the diameter at the minimum inner diameter portion.

[0096] The core via 23 may have a diameter (CV1) of the first surface opening and a diameter (CV2) of the second surface opening that are substantially the same as each other, or may be substantially different from each other.

[0097] The core via 23 may have an inner diameter smaller than other portions at one location of an inner diameter surface connecting the first opening and the second opening, and this is called a minimum inner diameter (portion).

[0098] When the core via 23 has a narrowed area at least in a portion of the via, the size of the minimum inner diameter (CV3) may be 50% to 99% or 70% to 95% of the larger of the diameter of the first surface opening (CV1) and the diameter of the second surface opening (CV2). When the narrowed size is within such a range, an electrically conductive layer can be formed more smoothly.

[0099] The minimum inner diameter portion may be located at a point (G23) that is 40% to 60% of the total length (G21) of the core via, or may be located at a point (G25) that is 45% to 55% of the total length of the core via, based on the first opening. When the minimum inner diameter portion is located at the above-described position based on the total length of the core via, the design of the electrical conductive layer of the packaging substrate and the process of forming the electrical conductive layer may be facilitated.

[0100] The ratio of the larger of the diameter (CV1) of the first opening which is the diameter at the first opening and the diameter (CV2) of the second opening which is the diameter at the second opening to the size (CV3) of the minimum inner diameter portion may be 1:0.65 to 0.99, or 1:0.72 to 0.95. When the inner diameter is narrowed within such a range, an electrically conductive layer, etc., can be formed more smoothly.

[0101] The core via 23 may have an angle of 8 degrees or less when observed in a cross section of the core via from the opening in contact with the first surface to the part of the core via having the smallest inner diameter at the opening having the larger diameter between the opening in contact with the first surface and the opening in contact with the second surface, based on the thickness direction perpendicular to the first surface.

[0102] The angle (Ca1) of the inner diameter surface connecting the minimum inner diameter portion and the first opening and the angle (Ca2) of the inner diameter surface connecting the minimum inner diameter portion and the second opening may have a ratio of 1:0.7 to 1.3. In this case, the difference in angle between the inner diameter surface of the core via starting from the first opening and the inner diameter surface of the core via starting from the second opening becomes negligible, and the subsequent plating process and the like may proceed more smoothly.

[0103] The angle is evaluated as an angle with a virtual reference line perpendicular to the first surface or the second surface, and is evaluated as an absolute value regardless of the direction (hereinafter the same).

[0104] The larger of the angle (Ca1) of the inner diameter surface connecting the minimum inner diameter portion and the first opening and the angle (Ca2) of the inner diameter surface connecting the minimum inner diameter portion and the second opening may be 8 degrees or less, may be 0.1 degrees to 8 degrees, or may be 0.5 degrees to 6.5 degrees. When the angle is such, subsequent steps such as plating can proceed more smoothly, and it becomes easier to form an electrically conductive layer having an intended pattern.

[0105] The thickness of the electrically conductive layer measured at the larger of the diameter of the first side opening (CV1) and the diameter of the second side opening (CV2) may be the same as or thicker than the thickness of the electrically conductive layer formed on the portion of the core via having the smallest inner diameter (CV3).

[0106] The core distribution layer 24 is an electrically conductive layer formed on a glass substrate, and may have a cross cut adhesion test value of 4B or more, specifically 5B or more, according to ASTM D3359. In addition, the electrically conductive layer, which is the core distribution layer 24, may have an adhesive strength of 3N / cm or more to the glass substrate, and may have a bonding strength of 4.5N / cm or more. If such a bonding strength is satisfied, the bonding strength between the substrate and the electrically conductive layer is sufficient for use as a packaging substrate.

[0107] A top layer 26 is positioned on the first surface 213 .

[0108] The upper layer 26 includes an upper distribution layer 25 and an upper surface connection layer 27 located on the upper distribution layer, and the top surface of the upper layer 26 can be protected by a cover layer 60 having an opening formed therein to which a connection electrode of a semiconductor element portion can directly abut.

[0109] The upper distribution layer 25 includes an upper insulating layer 253 located on the first surface, and an upper distribution pattern 251 having a predetermined pattern and embedded in the upper insulating layer as an electrically conductive layer to which at least a portion of the core distribution layer 24 is electrically connected.

[0110] The upper insulating layer 253 may be any material that can be used as an insulating layer for a semiconductor device or a packaging substrate, such as, but not limited to, an epoxy resin containing a filler.

[0111] The insulator layer may be formed by forming a coating layer and curing it, or may be formed by laminating an insulator film in an uncured or semi-cured state to the core layer and curing it. In this case, if a pressure-sensitive lamination method is applied, the insulator is embedded even in the space inside the core via, allowing for efficient process progress. In addition, even when multiple insulator layers are applied by laminating them, it may be difficult to substantially distinguish between the insulator layers, and the multiple insulator layers are collectively referred to as upper insulating layers. In addition, the same insulating material may be applied to the core insulating layer 223 and the upper insulating layer 253, and in this case, the boundary between them may not be substantially distinguished.

[0112] The upper distribution pattern 251 refers to an electrically conductive layer located in the upper insulating layer 253 in a predetermined shape. For example, the upper distribution pattern 251 may be formed by a build-up layer method. In particular, an insulating layer is formed, unnecessary parts of the insulating layer are removed, an electrically conductive layer is formed by a method such as copper plating, unnecessary parts of the electrically conductive layer are removed, an insulating layer is formed again on the electrically conductive layer, unnecessary parts are removed again, and an electrically conductive layer is formed by a method such as plating, and the like. By repeating these methods, the upper distribution pattern 251 having an electrically conductive layer formed vertically or horizontally in a desired pattern may be formed.

[0113] The upper distribution pattern 251 is located between the core layer 22 and the semiconductor device part 30, and is formed to include a fine pattern in at least a part thereof so that electrical signals can be smoothly transmitted to the semiconductor device part 30 and the intended complex pattern can be fully accommodated. In this case, the width and interval of the fine pattern may be less than 4 μm, 3.5 μm or less, 3 μm or less, 2.5 μm or less, or 1 μm to 2.3 μm, respectively. The interval may be the interval between adjacent fine patterns (the same applies to the explanation of the fine pattern below).

[0114] In order to form the upper distribution pattern 251 to include a fine pattern, at least two methods are used in the embodiment.

[0115] One of the methods is to use a glass substrate 21 as the glass substrate of the packaging substrate. The glass substrate 21 may have a surface illuminance (Ra) of 10 angstroms or less and a fairly flat surface characteristic, so that the influence of the surface morphology of the support substrate on the formation of the fine pattern may be minimized.

[0116] Another method is based on the characteristics of the insulator. In the case of the insulator, a filler component is often applied together with the resin, and inorganic particles such as silica particles can be applied as the filler. When inorganic particles are applied to the insulator as a filler, the size of the inorganic particles can affect whether or not a fine pattern is formed. The insulator applied in the embodiment includes a particulate filler having an average diameter of 150 nm or less, specifically, a particulate filler having an average diameter of 1 nm to 100 nm. This characteristic minimizes the effect of the insulator itself on the formation of an electrically conductive layer having a width of several micrometers while maintaining the physical properties required for the insulator at a certain level or higher, and promotes the formation of a fine pattern having excellent adhesion on the surface due to the fine surface morphology.

[0117] The upper connection layer 27 includes an upper connection pattern 272, at least a portion of which is electrically connected to the upper distribution pattern 251 and located on the upper insulating layer 253, and an upper connection electrode 271 that electrically connects the semiconductor device unit 30 and the upper connection pattern 272. The upper connection pattern 272 may be located on one surface of the upper insulating layer 253, or at least a portion of which may be embedded and exposed on the upper insulating layer. For example, when the upper connection pattern is located on one surface of the upper insulating layer, the upper insulating layer may be formed by plating, etc., and when a portion of the upper connection pattern is embedded and exposed on the upper insulating layer, a copper plating layer, etc. may be formed, and then a portion of the insulating layer or the electrically conductive layer may be removed by surface polishing, surface etching, etc.

[0118] The upper connection pattern 272 may include a fine pattern at least in a portion thereof, like the above-described upper distribution pattern 251. The upper connection pattern 272 including such a fine pattern can electrically connect more devices in a small area, facilitate the connection of electrical signals between devices or with the outside, and enable more integrated packaging.

[0119] The upper connection electrodes 271 may be directly connected to the semiconductor device part 30 using terminals or the like, or may be connected to the semiconductor device part 30 using device connectors 51 such as solder balls.

[0120] The packaging substrate 20 is also connected to the motherboard 10. The motherboard 10 may be directly connected to a second surface distribution pattern 241c, which is a core distribution layer located on at least a portion of the second surface 214 of the core layer 22, through a terminal of the motherboard, or may be electrically connected to the second surface distribution pattern 241c through a board connection part such as a solder ball. In addition, the second surface distribution pattern 241c may be connected to the motherboard 10 through a lower layer 29 located at the bottom of the core layer 22.

[0121] The lower layer 29 includes a lower distribution layer 291 and a lower connection layer 292 .

[0122] The lower distribution layer 291 includes: i) a lower insulating layer 291b, at least a portion of which contacts the second surface 214; and ii) a lower distribution pattern 291a, which is embedded in the lower insulating layer and has a predetermined pattern, and at least a portion of which is electrically connected to the core distribution layer.

[0123] The lower connection layer 292 may include i) a lower connection electrode 292a electrically connected to the lower connection pattern, and ii) a lower connection pattern 292b electrically connected to at least a portion of the lower distribution pattern and at least a portion of which is exposed on one surface of the lower insulating layer.

[0124] The bottom connection pattern 292b is a portion that is connected to the motherboard 10, and unlike the top connection pattern 272, may be formed of a non-fine pattern that is wider than a fine pattern for more efficient transmission of electrical signals.

[0125] One of the features of the present invention is that the packaging substrate 20 located between the semiconductor element part 30 and the motherboard 10 does not substantially include any additional substrate other than the glass substrate 21 .

[0126] In the past, an interposer and an organic substrate were laminated together between a device and a motherboard. It is understood that such a multi-layer structure was adopted for at least two reasons. One reason is that there is a scale problem in directly bonding a fine pattern of a device to a motherboard, and the other reason is that a problem of wiring damage due to a difference in thermal expansion coefficient may occur during the bonding process or during the operation of the semiconductor device. In the present embodiment, this problem is solved by applying a glass substrate having a thermal expansion coefficient similar to that of a semiconductor device, and forming a fine pattern having a fine scale sufficient for mounting a device on a first surface of the glass substrate and an upper layer thereof.

[0127] In an embodiment, the thickness of the thinner one of the electrical conductive layers of the core distribution layer 24 may be the same as or thicker than the thickness (Tus) of the thinner one of the electrical conductive layers of the upper layer 26. In this way, when the thickness of the thinner one of the electrical conductive layers of the core distribution layer 24 is the same as or thicker than the thickness of the thinner one of the electrical conductive layers of the upper layer 26, electrical signals can be transmitted more efficiently between the device and the motherboard.

[0128] In an embodiment, the thickness (Tsc) of the thinner one of the second surface distribution patterns 241 c may be thicker than the thickness (Tus) of the thinner one of the top surface connection patterns 272 .

[0129] In an embodiment, the thickness (Tds) of the thicker one of the bottom connection electrodes 292a may be greater than the thickness (Tsc) of the thinner one of the second distribution patterns 241c.

[0130] Since the semiconductor device 100 has a packaging substrate 20 having a relatively thin thickness, the overall thickness of the semiconductor device can be reduced, and a desired electrical connection pattern can be arranged in a smaller area by applying a fine pattern. Specifically, the thickness of the packaging substrate may be about 2000 μm or less, about 1500 μm or less, or about 900 μm. Also, the thickness of the packaging substrate may be about 120 μm or more, or about 150 μm or more. Due to the characteristics described above, the packaging substrate can stably connect the element and the motherboard electrically and structurally even with a relatively thin thickness, thereby contributing to the miniaturization and thinning of the semiconductor device.

[0131] 8 to 10 are flow charts illustrating a cross-sectional view of a method for manufacturing a packaging substrate according to an embodiment of the present invention. Hereinafter, a method for manufacturing a packaging substrate according to another embodiment of the present invention will be described with reference to FIGS.

[0132] Manufacturing method of packaging substrate

[0133] A method for manufacturing a packaging substrate according to an embodiment includes a preparation step of forming defects at predetermined positions on a first surface and a second surface of a glass substrate; an etching step of applying an etching solution to the glass substrate on which the defects are formed to provide a glass substrate on which a core via is formed; a core layer fabrication step of forming a core distribution layer, which is an electrically conductive layer, by plating a surface of the glass substrate on which the core via is formed, to manufacture a core layer; and an upper layer fabrication step of forming an upper distribution layer, which is an electrically conductive layer covered with an insulating layer, on one surface of the core layer, to manufacture the packaging substrate described above.

[0134] The core layer manufacturing step may include a pretreatment process of forming an organic-inorganic composite primer layer containing nanoparticles having an amine group on the surface of the glass substrate in which the core vias are formed, and providing the pretreated glass substrate; and a plating process of plating a metal layer on the pretreated glass substrate.

[0135] The core layer manufacturing step may include a pretreatment process of forming a metal-containing primer layer on a surface of the glass substrate in which the core via is formed by sputtering to provide a pretreated glass substrate; and a plating process of plating a metal layer on the pretreated glass substrate.

[0136] An insulating layer may be formed between the core layer and the upper layer.

[0137] The insulating layer forming step may be a step of forming a core insulating layer by positioning an insulating film on the core layer and then performing pressure-sensitive lamination.

[0138] The manufacturing method of the packaging substrate will be described in more detail below.

[0139] 1) Preparation step (glass defect formation process): A glass substrate 21a having flat first and second surfaces is prepared, and defects (grooves, 21b) are formed on the glass surface at predetermined positions for the formation of core vias. The glass substrate may be a glass substrate used for electronic device substrates, for example, but is not limited to, an alkali-free glass substrate. As commercially available products, products manufactured by manufacturers such as Corning, Schott, and AGC may be used. When forming the defects (grooves), methods such as mechanical etching and laser irradiation may be used.

[0140] 2) Etching step (core via forming step): The glass substrate 21a having the defect (groove, 21b) is subjected to a physical or chemical etching process to form a core via 23. In the etching process, a via is formed in the defective portion of the glass substrate, and the surface of the glass substrate 21a may be etched at the same time. In order to prevent such etching of the glass surface, a masking film or the like may be applied, but taking into consideration the complication of the process of applying and removing the masking film, the glass substrate having the defect itself may be etched. In this case, the thickness of the glass substrate having the core via may be somewhat thinner than the thickness of the initial glass substrate.

[0141] 3-1) Core layer preparation step: An electrically conductive layer 21d is formed on a glass substrate. The electrically conductive layer is typically a metal layer containing copper metal, but is not limited thereto.

[0142] The adhesion between the glass surface (including the glass substrate surface and the core via surface) and the copper metal surface is poor due to their different properties. In the present embodiment, the adhesion between the glass surface and the metal is improved by two methods, a dry method and a wet method.

[0143] The dry method is a method of applying sputtering, that is, a method of forming a seed layer 21c on the glass surface and the inner diameter of the core via by metal sputtering. When forming the seed layer, a different metal such as titanium, chromium, nickel, etc. may be sputtered together with copper, etc., and in this case, it is considered that the glass-metal adhesion is improved by the anchor effect caused by the interaction between the glass surface morphology and the metal particles.

[0144] The wet method is a method of performing a primer treatment, and a primer layer 21c is formed by pretreating with a compound having a functional group such as an amine. Depending on the intended degree of adhesion, the primer treatment may be performed with a compound or particles having an amine functional group after pretreating with a silane coupling agent. As mentioned above, the support substrate of the embodiment needs to have high performance to be able to form a fine pattern, and this must be maintained even after the primer treatment. Therefore, when such a primer includes nanoparticles, it is preferable to apply nanoparticles having an average diameter of 150 nm or less, and for example, it is preferable to apply nanoparticles as particles having an amine group. The primer layer may be formed by applying an adhesion improver, for example, manufactured by MEC's ​​CZ series.

[0145] In the seed layer / primer layer 21c, the electrically conductive layer may selectively form a metal layer in a state where a portion where no electrically conductive layer is required is removed or not removed. In addition, the seed layer / primer layer 21c may selectively be treated in a state where a portion where an electrically conductive layer is required or not required is activated or deactivated for metal plating, and the subsequent steps may be carried out. For example, the activation or deactivation treatment may be a light irradiation treatment using a laser having a certain wavelength, a chemical treatment, or the like. When forming a metal layer, a copper plating method applied to the manufacture of semiconductor devices may be applied, but is not limited thereto.

[0146] During the metal plating, the thickness of the electroconductive layer formed can be controlled by adjusting various variables such as the concentration of the plating solution, the plating time, and the type of additives applied.

[0147] If a portion of the core distribution layer is unnecessary, it may be removed, and after a portion of the seed layer is removed or passivated, metal plating may be carried out to form an electrically conductive layer in a predetermined pattern, thereby forming an etched layer 21e of the core distribution layer.

[0148] 3-2) Insulation layer formation step: After the formation of the core distribution layer, which is the electrically conductive layer, the core via may undergo an insulation layer formation step in which the empty space is filled with an insulation layer. In this case, the insulation layer may be applied in the form of a film, for example, an insulation layer in the form of a film formed by a pressure-sensitive lamination method or the like. By carrying out the pressure-sensitive lamination in this manner, the insulation layer is sufficiently filled into the empty space inside the core via, and a core insulation layer without the formation of voids can be formed.

[0149] 4) Upper layer manufacturing step: This is a step of forming an upper distribution layer including an upper insulating layer and an upper distribution pattern on the core layer. The upper insulating layer may be formed by coating a resin composition forming the insulating layer 23a or laminating an insulating film, and is preferably formed by laminating an insulating film. The lamination of the insulating film may be performed by laminating and curing the insulating film, and if a pressure-sensitive lamination method is applied, the insulating resin may be sufficiently embedded in layers in which no electrically conductive layer is formed inside the core via. The upper insulating layer is also applied to have at least a portion of the glass substrate directly abutting thereon and thus having sufficient adhesion. Specifically, the glass substrate and the upper insulating layer preferably have a property of satisfying an adhesion test value of 4B or more according to ASTM D3359.

[0150] The upper distribution pattern may be formed by repeating the process of forming the insulating layer 23a, forming the electrically conductive layer 23c in a predetermined pattern, etching unnecessary portions, and then forming an etching layer 23d of the electrically conductive layer, or in the case of electrically conductive layers formed adjacent to each other with an insulating layer in between, the upper distribution pattern may be formed by forming blind vias 23b in the insulating layer and then proceeding with a plating process. When forming the blind vias, dry etching methods such as laser etching and plasma etching, wet etching methods using a masking layer and an etchant, etc. may be used.

[0151] 5) Upper surface connection layer and cover layer forming step: The upper surface connection pattern and the upper surface connection electrode may also be formed in a similar process to that of forming the upper distribution layer. Specifically, the upper surface connection pattern and the upper surface connection electrode may be formed by forming an insulating layer 23f on the insulating layer 23e, forming an electrically conductive layer 23g thereon, and then forming an electrically conductive layer 23h thereon, or may be formed by selectively forming only the electrically conductive layer without applying an etching method. The cover layer may be formed such that the upper surface connection electrode is exposed by forming an opening (not shown) at a position corresponding to the upper surface connection electrode, and can be directly connected to the element connection part or the terminal of the element.

[0152] 6) Lower connection layer and cover layer formation step: A lower distribution layer and / or a lower connection layer may be formed in a manner similar to the upper connection layer and cover layer formation steps described above, and a cover layer (not shown) may be optionally formed.

[0153] 11(a) shows a top view of a glass substrate having a core via according to another embodiment, and (b) is a conceptual diagram illustrating a cross section of the core via. Hereinafter, a packaging substrate including a glass substrate and a manufacturing method thereof will be described with reference to FIGS. 1 and 11.

[0154] Semiconductor packaging substrate 215 and its manufacturing method

[0155] According to another embodiment, the semiconductor packaging substrate 215 includes:

[0156] The glass substrate 21 includes: i) a glass substrate 21 having a first surface 213 and a second surface 214 facing each other; ii) a number of core vias 23 penetrating the glass substrate in the thickness direction; and iii) a core layer located on a surface of the core vias and having a core seed layer 225 that serves as a seed for forming an electrically conductive layer.

[0157] The semiconductor packaging substrate 215 can be applied as a component of the packaging substrate 20 of the semiconductor device 100 described above.

[0158] The glass substrate 21 is preferably a glass substrate used in semiconductors, and examples of glass substrates that may be used include, but are not limited to, borosilicate glass substrates and non-alkali glass substrates.

[0159] The thickness of the glass substrate 21 may be 1,000 μm or less, 100 μm to 1,000 μm, or 100 μm to 700 μm. More specifically, the thickness of the glass substrate 21 may be 100 μm to 500 μm. Forming a thinner packaging substrate is advantageous in that electrical signals can be transmitted more efficiently, but since the substrate must also function as a support, it is preferable to use a glass substrate 21 having the above thickness. Here, the thickness of the glass substrate means the thickness of the glass substrate itself excluding the thickness of the electrically conductive layer located on the glass substrate.

[0160] The core via 23 may be formed by removing a predetermined area of ​​the glass substrate 21, specifically, by etching a plate-shaped glass by physical and / or chemical methods.

[0161] Specifically, when forming the core via 23, a defect (groove) may be formed on the surface of the glass substrate using a laser or the like, and then chemical etching, laser etching, etc. may be applied, but is not limited thereto.

[0162] The core via 23 includes a first opening 233 in contact with the first surface; a second opening 234 in contact with the second surface; and a minimum inner diameter portion 235 which is the area whose inner diameter is narrowest in the entire core via connecting the first opening and the second opening.

[0163] The diameter of the first opening (CV1) and the diameter of the second opening (CV2) may be substantially different or substantially the same.

[0164] The minimum inner diameter portion may be located at the first opening or the second opening, and the core via may be a cylindrical or (truncated) pyramidal core via. In this case, the diameter (CV3) of the minimum inner diameter portion corresponds to the smaller diameter of the first opening or the second opening.

[0165] The minimum inner diameter portion may be located between the first opening and the second opening, and the core via may be a barrel-type core via. In this case, the diameter (CV3) of the minimum inner diameter portion may be smaller than the larger of the diameters of the first opening and the second opening.

[0166] The core via 23 includes an opening in contact with the first surface, an opening in contact with the second surface, and a portion of the core via having a minimum inner diameter, and the minimum inner diameter portion may be located at a point less than 40% or more than 60% of the first opening when the entire length of the core via is taken as 100%. A core via having such a shape may be more advantageous in having a value for the thickness ratio described below.

[0167] The core via 23 may have an opening-to-thickness ratio, meaning the ratio of the inner diameter at the opening (the larger of the first surface opening and the second surface opening) to the thickness of the glass substrate, of 1:2 to 4. The core via 23 may have a minimum inner diameter-to-thickness ratio, meaning the ratio of the inner diameter at the minimum inner diameter to the thickness of the glass substrate, of 1:2.5 to 6. A core via having such a ratio is more advantageous for forming a core seed layer having the characteristics described later.

[0168] When the core seed layer 225 is formed by sputtering, due to the shape characteristics of the narrow and long core via, the core seed layer may not be sufficiently formed in some parts, or the core seed layer may be formed with different thicknesses. Such a core seed layer serves as a base for forming an electrically conductive layer such as a copper layer by a method such as plating, and the thickness distribution of such an electrically conductive layer may affect the speed and efficiency of electrical signal transmission, so it is necessary to control it.

[0169] In an embodiment, the first and second thicknesses of the core seed layer 225 are measured at opposing positions on the inner diameter surface of the core via 23, and the ratio between them is used to determine whether a core seed layer of uniform thickness has been formed overall.

[0170] Specifically, the core via 23, on whose inner diameter surface the core seed layer 225 is located, is observed in cross section, and the thickness of the core seed layer 225 is measured at a certain position. Since the core seed layer itself may have a curved surface, the sample values ​​measured three to five times or more while changing the position slightly at one point are averaged, and this is evaluated as a thickness value.

[0171] In the core seed layer 225, the thickness deviation rate represented by the following formula 1 may be 90% or less, 83% or less, or 67% or less. When the thickness deviation rate is as described above, a core seed layer having a relatively uniform thickness can be provided.

[0172] [Formula 1] Thickness deviation rate = ((maximum thickness of core seed layer - minimum thickness of core seed layer) / average thickness of core seed layer) x 100%

[0173] In Equation 1, the maximum thickness is the thickness having the maximum value in the measured core seed layer thickness sample, the minimum thickness is the thickness having the smallest value in the thickness sample, and the average thickness is the average value of the thickness sample.

[0174] The average thickness of the core seed layer 225 may be 30 nm to 200 nm, or 50 nm to 170 nm. The core seed layer having such a thickness range can form a relatively uniform electrical conductivity as intended by the present invention.

[0175] The core seed layer 225 may also have the following characteristics:

[0176] When observing the cross section of the core seed layer, there are positions facing each other at the same height, which are matched as 1-1 and 2-1, and 1-2 and 2-2 in Figure 12. Since the core seed layer itself may have a curved surface, the values ​​measured at one point are changed slightly in position and then averaged 3 to 5 times or more, and this is evaluated as the thickness value.

[0177] In addition, the thicknesses of the core seed layers facing each other are matched to a first thickness and a second thickness, such as 1-1 and 1-2, and the ratio of the first thickness to the second thickness is calculated, which is called the thickness ratio.

[0178] The thickness ratio may be 1:0.4 to 4.5, 1:0.5 to 3.0, or 1:0.7 to 2.0. When the thickness ratio is such, the core seed layers 225 have a relatively uniform thickness at positions facing each other.

[0179] The standard deviation of the thickness ratio measured at three or five positions having different heights on the inner diameter surface of the core via 23 may be 1.5 or less, 1 or less, or 0.8 or less. This means that the three or five positions having different heights have a relatively constant thickness. In this case, the three or five positions having different heights refer to positions designated at relatively constant intervals in consideration of the overall length of the core via, and the intervals between the positions do not need to be completely uniform.

[0180] Specifically, the inner diameter surface of the core via may have different thicknesses depending on its height when the second surface is used as a reference, and such thickness differences are likely to occur due to the characteristics of a narrow and long core via. However, the core seed layer 225 having the above-mentioned characteristics controls the unevenness in thickness and provides a core seed layer having constant characteristics at an appropriate level or higher.

[0181] The core seed layer 225 specifically includes a first surface core seed layer 225a located on the first surface, a core via seed layer 225b located on the inner diameter surface above the core via, and a second surface core seed layer 225c located on the second surface, which are sequentially connected to each other.

[0182] The specific features of the core seed layer 225 mentioned above apply to the core via seed layer 225b.

[0183] As shown in Figure 13, the measured core seed layer thickness, thickness ratio, and standard deviation are presented as follows: The photograph presented in Figure 13 is the data of Sample 1.

[0184] [Table 1]

[0185] *Thickness is evaluated by the average of 5 points. *Thickness ratio is calculated as (1-1 / 2-1).

[0186] A method for producing the core seed layer will now be described.

[0187] The method for manufacturing the core seed layer includes a preparation step and a sputtering step.

[0188] The preparation step is a step of preparing a pre-processed substrate having a glass substrate having a first surface and a second surface facing each other, and a number of core vias penetrating the glass substrate in a thickness direction. A detailed description of the glass substrate and the core vias will be omitted since they overlap with the above description. In addition, a detailed description of a method for forming core vias in a glass substrate will be omitted since they overlap with the above description of the packaging substrate.

[0189] The sputtering step is a step of forming a core seed layer on the inner diameter surface of the core via by sputtering at a gun angle (As) of 10 degrees to 90 degrees with respect to a reference line perpendicular to the first surface. The gun angle may be 10 degrees to 65 degrees. The gun angle may be 15 degrees to 55 degrees, or 15 degrees to 45 degrees. The gun angle may be 10 degrees to 35 degrees. When sputtering is performed by applying such a gun angle, a core seed layer having a certain level or more of thickness uniformity up to the inside of the core via can be more efficiently formed.

[0190] The present invention will be described in more detail with reference to the following specific examples. The following examples are merely illustrative for the purpose of facilitating understanding of the present invention, and are not intended to limit the scope of the present invention.

[0191] <Example 1 - Manufacturing of substrate for semiconductor packaging>

[0192] 1) Preparation step (glass defect formation process): A glass substrate 21a having flat first and second surfaces was prepared, and defects (grooves, 21b) were formed on the glass surface at predetermined positions for the formation of core vias. Borosilicate glass (Corning) was used as the glass. Mechanical etching and laser irradiation methods were used to form the defects (grooves).

[0193] 2) Etching step (core via forming step): A core via 23 was formed in the glass substrate 21a having defects (grooves, 21b) through a physical or chemical etching process. The core via was formed to have a first opening in contact with the first surface; a second opening in contact with the second surface; and a minimum inner diameter portion which is an area with the narrowest inner diameter in the entire core via connecting the first opening and the second opening. The minimum inner diameter portion was positioned at a point 40% to 60% of the length of the core via based on the first opening, assuming that the entire length of the core via is 100%. In addition, the angle of the inner diameter surface observed in the cross section of the core via up to the minimum inner diameter portion in the largest opening of the first and second openings was set to 8 degrees or less based on the thickness direction perpendicular to the second surface.

[0194] 3-1) Core layer manufacturing step: An electrically conductive layer 21d was formed on a glass substrate. A metal layer containing copper metal was applied as the electrically conductive layer. A dry method was used to improve adhesion between the surface of the glass substrate and the metal layer. The dry method is a method of applying sputtering, i.e., a method of forming a seed layer 21c on the glass surface and the inner diameter of the core via by metal sputtering. When forming the seed layer, at least one dissimilar metal selected from titanium, chromium, and nickel was sputtered together with copper. At this time, the sputtering was performed at a gun angle (As) of 45 degrees with respect to a reference line perpendicular to the first surface.

[0195] Thereafter, when forming the metal layer, a copper plating method that is applied to the manufacture of semiconductor devices was applied.

[0196] <Example 2 - Manufacturing of substrate for semiconductor packaging>

[0197] A packaging substrate was manufactured by following the same procedure as in Example 1, except that in Example 1, the position of the minimum inner diameter portion in 2) was set to be less than 40% based on the first opening, and the sputtering angle in 3-1) was changed to 55 degrees.

[0198] <Example 3 - Manufacturing of substrate for semiconductor packaging>

[0199] A packaging substrate was manufactured in the same manner as in Example 1, except that the angle during sputtering in 3-1) in Example 1 was changed to 65 degrees.

[0200] <Example 4 - Manufacturing of substrate for semiconductor packaging>

[0201] A packaging substrate was manufactured by following the same procedure as in Example 1, except that in Example 1, the position of the minimum inner diameter portion in 2) was set to be less than 40% based on the first opening, and the angle during sputtering in 3-1) was changed to 90 degrees.

[0202] <Comparative Example 1 - Manufacturing of Substrate for Semiconductor Packaging>

[0203] A packaging substrate was manufactured in the same manner as in Example 1, except that the angle of the inner diameter surface of 2) in Example 1 was changed to exceed 8 degrees.

[0204] <Comparative Example 2 - Manufacturing of Substrate for Semiconductor Packaging>

[0205] A packaging substrate was manufactured by following the same procedure as in Example 1, except that in Example 1, the angle of the inner diameter surface in 2) was more than 8 degrees, the position of the minimum inner diameter portion was less than 40% based on the first opening, and the angle during sputtering in 3-1) was changed to 65 degrees.

[0206] <Comparative Example 3 - Manufacturing of Substrate for Semiconductor Packaging>

[0207] A packaging substrate was manufactured by following the same procedure as in Example 1, except that in Example 1, the angle of the inner diameter surface in 2) was more than 8 degrees, the position of the minimum inner diameter portion was less than 40% based on the first opening, and the angle during sputtering in 3-1) was changed to 90 degrees.

[0208] <Experimental example - Measurement of the ratio of the first thickness to the second thickness, and the thickness deviation>

[0209] The thickness of the core seed layer of the packaging substrate manufactured in the examples and comparative examples was measured five times, including one point and its surrounding area, and five times, including another point opposite the one point and its surrounding area, and the ratio of the first thickness to the second thickness and the thickness deviation results are shown in Table 1.

[0210] [Table 2]

[0211] Ca: The angle of the inner diameter surface observed in the cross section of the core via up to the minimum inner diameter portion in the larger of the first and second openings, based on the thickness direction perpendicular to the first surface. 1-n:2-n: Ratio of the first thickness to the second thickness of the core seed layer measured at two positions facing each other on the inner diameter surface of the core via

[0212] Thickness deviation rate: ((maximum thickness of core seed layer - minimum thickness of core seed layer) / average thickness of core seed layer) x 100%

[0213] Position of minimum inner diameter part: When the entire length of the core via is taken as 100%, this is a relative position based on the first opening.

[0214] Referring to Table 1, in Examples 1 to 4 in which the Ca value is 8 degrees or less, the thickness deviation rate is 90 or less, and the 1-n:2-n ratio is 1:0.4 to 4.5, showing a relatively uniform core seed layer thickness. It is considered that a packaging substrate having such characteristics can sufficiently smoothly transmit an electrical signal to an element disposed on the upper or lower side thereof.

[0215] The packaging substrate of the embodiment utilizes excellent properties such as being able to act as a substrate support that is thin and has sufficient strength without forming parasitic elements, which is characteristic of a glass substrate, as well as excellent properties such as forming an electrically conductive layer with a thickness that is a suitable ratio to the thickness of the glass substrate to induce efficient signal transmission.

[0216] Glass substrates are considered to have poor bonding properties with electrically conductive layers such as copper layers, and in order to form an electrically conductive layer of sufficient thickness by a method such as plating, it is necessary to form a seed layer or primer layer between the glass surface and the electrically conductive layer. However, if such a seed layer or primer layer is formed too thick or unevenly, it may be difficult to form a sufficient electrically conductive layer within a specified core via diameter, which may have a negative effect on the electrical signal transmission speed between the upper and lower parts of the packaging substrate.

[0217] Considering these characteristics, for efficient transmission of electrical signals, it is preferable that the thickness of the seed layer or primer layer is applied as uniformly and thinly as possible while satisfying a specific ratio, and it is considered preferable that the sputtering angle is 15 degrees to 90 degrees and the Ca is 8 degrees or less.

[0218] Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and many variations and improvements made by those skilled in the art using the basic concept of the present invention defined in the following claims also fall within the scope of the present invention. [Explanation of symbols]

[0219] 100: Semiconductor device 10: Motherboard 30: Semiconductor element section 32: First semiconductor element 34: Second semiconductor element 36: Third semiconductor element 20: Packaging substrate 22: Core layer 223: Core insulating layer 21, 21a: Glass substrate 213: 1st side 214: 2nd side 23: Core via 233: First opening 234: Second opening 235: Minimum inner diameter portion 24: Core distribution layer 241: Core distribution pattern 241a: first surface distribution pattern 241b: core via distribution pattern 241c: 2nd surface distribution pattern 26: Upper layer 25: Upper distribution layer 251: Upper distribution pattern 252: Blind via 253: Top insulating layer 27: Top connection layer 271: Top connection electrode 272: Top connection pattern 29: Bottom layer 291: Lower distribution layer 291a: Lower distribution pattern 291b: Lower insulating layer 292: Lower connection layer 292a: Bottom connection electrode 292b: Bottom connection pattern 50: Connection portion 51: Element connection portion 52: Board connection part 60: Cover layer 21b: Glass defect 21c: Seed layer, primer layer 21d: Core distribution layer 21e: Etching layer of the core distribution layer 23a: insulating layer 23b: etched layer of the insulating layer 23c: Electrically conductive layer 23d: Etching layer of the electrically conductive layer 23e: Insulating layer 23f: Etching layer of insulating layer 23g: Electrically conductive layer 23h: Etching layer of the electrically conductive layer

Claims

1. i) a glass substrate having a first surface and a second surface facing each other; ii) a number of core vias penetrating the thickness of the glass substrate; and iii) a core layer located on a surface of the core via and a core seed layer serving as a seed for the formation of an electrically conductive layer; a ratio (thickness ratio) of a first thickness and a second thickness of the core seed layer measured at two positions facing each other on an inner diameter surface of the core via is 1:0.4 to 4.5; The thickness deviation rate of the core seed layer represented by the following formula 1 is 83% or less, the core via includes a first opening in contact with the first surface; a second opening in contact with the second surface; and a minimum inner diameter portion that is a region in the entire core via connecting the first opening and the second opening, the minimum inner diameter portion being a region in which the inner diameter is narrowest; a ratio of the diameter of the smallest inner diameter portion to the thickness of the glass substrate is 1:2.5 to 6; a ratio of the larger of the diameter of the first side opening, which is the diameter at the first opening, and the diameter of the second side opening, which is the diameter at the second opening, to the diameter of the minimum inner diameter portion is 1:0.65 to 0.

99. [Formula 1] Thickness deviation rate=((maximum thickness of core seed layer−minimum thickness of core seed layer) / average thickness of core seed layer)×100%

2. The semiconductor packaging substrate of claim 1, wherein the larger of the angle (Ca1) of the inner diameter surface connecting the minimum inner diameter portion and the first opening and the angle (Ca2) of the inner diameter surface connecting the minimum inner diameter portion and the second opening is 0.5 degrees to 6.5 degrees.

3. 2. The substrate for semiconductor packaging according to claim 1, wherein the minimum inner diameter portion is located at a point between 40% and 60% of the length of the core via based on the first opening, when the entire length of the core via is taken as 100%.

4. 2. The substrate for semiconductor packaging according to claim 1, wherein a ratio of the larger of the diameter of the first side opening, which is the diameter at the first opening, and the diameter of the second side opening, which is the diameter at the second opening, to a thickness of the glass substrate is 1:2 to 4.

5. The packaging substrate of claim 4 , wherein the diameter of the minimum inner diameter portion is 50% to 99% of the diameter of the first opening or the second opening, whichever has a larger diameter.

6. a top layer overlying the core layer; The core layer includes a core distribution layer located on a surface of the glass substrate or a core via; the core distribution layer includes an electrically conductive layer, at least a portion of which electrically connects the electrically conductive layer on the first side and the electrically conductive layer on the second side through the core via; 2. The semiconductor packaging substrate of claim 1, wherein the thinner of the electrically conductive layers of the core distribution layer has a thickness equal to or greater than a thickness of the thinner of the electrically conductive layers of the top layer.

7. A preparation step of providing a pre-processed substrate having a glass substrate having a first surface and a second surface facing each other, and a number of core vias extending through the glass substrate in a thickness direction; and a sputtering step of sputtering at a predetermined angle with respect to a reference line perpendicular to the first surface to form a core seed layer on an inner diameter surface of the core via; a ratio (thickness ratio) of a first thickness and a second thickness of the core seed layer measured at two positions facing each other on an inner diameter surface of the core via is 1:0.4 to 4.5; The thickness deviation rate of the core seed layer represented by the following formula 1 is 83% or less, the core via includes a first opening in contact with the first surface; a second opening in contact with the second surface; and a minimum inner diameter portion that is a region in the entire core via connecting the first opening and the second opening, the minimum inner diameter portion being a region in which the inner diameter is narrowest; a ratio of the diameter of the smallest inner diameter portion to the thickness of the glass substrate is 1:2.5 to 6; a ratio of the larger of the diameter of the first side opening which is the diameter at the first opening and the diameter of the second side opening which is the diameter at the second opening to the diameter of the minimum inner diameter portion is 1:0.65 to 0.

99. [Formula 1] Thickness deviation rate=((maximum thickness of core seed layer−minimum thickness of core seed layer) / average thickness of core seed layer)×100%

8. A semiconductor device comprising: an element portion including a semiconductor element; and a packaging substrate electrically connected to the element portion, the packaging substrate being the packaging substrate according to claim 1 .

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