Bandgap Voltage Apparatus

Abstract

To generate a stable reference voltage at low voltage.SOLUTION: A bandgap voltage device is comprised of: a first current source operably connected to a bandgap input node and a bandgap output node, which is capable of outputting a first proportional absolute temperature (PTAT) current; a first bandgap transistor and a second bandgap transistor; a current mirror operably connected to the bandgap output node; and a second current source which is operably connected to the current mirror and can output a second PTAT current.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED PATENT APPLICATIONS This application claims priority to U.S. Provisional Patent Application No. 62 / 895,365, filed September 3, 2019, entitled "Low Voltage Collector Free Bandgap Voltage Reference," the contents of which are incorporated herein by reference in their entirety and for all purposes as if fully and completely set forth herein.

[0002] The present embodiments relate generally to power conversion, and more particularly to a low voltage collector-free bandgap voltage generator. [Background technology]

[0003] Providing a stable voltage reference for an electrical or electronic system is a key building block in most analog and mixed-signal integrated circuits, including voltage regulators and data converters. Summary of the Invention [Problem to be solved by the invention]

[0004] It is desirable for a voltage reference to be stable over process, voltage, and temperature variations. Low voltage operation of an electrical or electronic system is particularly desirable for embedded, mobile, and similar devices. However, conventional systems may not be able to effectively generate a stable voltage reference at a sufficiently low voltage. Thus, a technical solution for generating a stable reference voltage at low voltage is desirable. [Means for solving the problem]

[0005] An embodiment includes a bandgap voltage device having a first current source operatively coupled to a bandgap input node and a bandgap output node and operable to output a first Proportional to Absolute Temperature (PTAT) current, a current mirror including a first bandgap transistor and a second bandgap transistor, and a second current source operatively coupled to the bandgap output node, operatively coupled to the current mirror and operable to output a second PTAT current.

[0006] An embodiment also includes a system including a proportional to absolute temperature (PTAT) current generator, a bandgap voltage device operably coupled to the PTAT current generator, a bandgap input node and a bandgap output node, a current mirror including a first bandgap transistor and a second bandgap transistor, and a current mirror operably coupled to the PTAT current generator and the bandgap output node.

[0007] Embodiments also include a bandgap transistor device having a first P+ layer proximate a center of a planar surface of the transistor device, a first N+ layer at least partially surrounding the first P+ layer along the planar surface, a second P+ layer at least partially surrounding the first N+ layer along the planar surface, a second N+ layer at least partially surrounding the second P+ layer along the planar surface, and a third P+ layer at least partially surrounding the second N+ layer along the planar surface.

[0008] These and other aspects and features of the present embodiments will become apparent to those of ordinary skill in the art upon review of the following description of illustrative embodiments in conjunction with the accompanying drawings. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 illustrates an exemplary system according to this embodiment. [Diagram 2] FIG. 2 is a diagram illustrating an exemplary current generating device proportional to absolute temperature, according to an embodiment. [Diagram 3]FIG. 3 is a diagram showing an exemplary bandgap voltage generator according to this embodiment. [Figure 4] FIG. 4 illustrates an exemplary thermal shutdown controller device according to this embodiment. [Figure 5A] FIG. 5A illustrates a plan view of an exemplary transistor device operable in accordance with the system of FIG. 1 and one of the devices of FIGS. [Figure 5B] FIG. 5B illustrates a cross-sectional view of the exemplary transistor device of FIG. 5A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] The present embodiment will now be described in detail in conjunction with the drawings, which are provided as illustrative examples of the present embodiment, to enable those skilled in the art to implement embodiments and alternatives that are apparent to those skilled in the art. In particular, the following drawings and examples are not meant to limit the scope of the present embodiment to a single embodiment, and other embodiments can be made by replacing some or all of the elements described or illustrated. Furthermore, where some elements of the present embodiment can be implemented partially or fully using known components, only the portions of such known components that are essential to understanding the present embodiment will be described, and the details for implementing the invention of other portions of such known components will be omitted so as not to obscure the present embodiment. An embodiment described as being implemented in software should not be so limited, and may include embodiments implemented in hardware, or combinations of software and hardware, as will be apparent to those skilled in the art, unless otherwise specified herein. An embodiment showing a singular component should not be considered as limiting herein, but rather, unless otherwise specified herein, the present invention is intended to encompass other embodiments including multiple identical components, and vice versa. Furthermore, the applicant does not intend any term in the specification or claims to be attributed an unusual or special meaning unless expressly described as such. Additionally, the present embodiments encompass present and future known equivalents to the known components referenced herein by way of example.

[0011] The implementations are directed to a low voltage bandgap voltage generator. In some implementations, low supply voltage operation is achieved with the bandgap voltage combined with the bias transistor bias voltage. In some implementations, low supply voltage operation is achieved at 1.3V or higher, advantageously enabling a stable bandgap at a low operating voltage. In some implementations, the exemplary system provides a self-buffered output to which the bandgap generator can source current. In this manner, no additional buffer is required, and additional or external buffers may reduce the accuracy of the desired bandgap voltage. In some implementations, the exemplary system is self-starting, and therefore does not require a dedicated start-up circuit. In some implementations, the exemplary system enables low current operation and has a collector-less design. In the exemplary collector-less design, one or more n-wells or N-buried layer pockets are connected to the power supply. In this exemplary implementation, the exemplary system or device is resistant to minority carrier injection, which can further reduce the accuracy of the desired bandgap potential. It should be understood that any reference to a collector terminal with respect to a collector-free transistor device, device configuration, or the like, is a brief reference to a transistor diagram, representation, or the like, and is not limited to any transistor requiring a terminal connector to a collector region, layer, or the like.

[0012] [Embodiment 1] (Configuration of Semiconductor Device) FIG. 1 illustrates an exemplary system according to the present embodiment. As shown in FIG. 1, the exemplary system 100 includes a Voltage Input 110, a Current Generator 120, a Bandgap Generator 130, a Bandgap Voltage Output 140, a Thermal Shutdown Controller 150, and a TSD Control Output 160. In some implementations, the exemplary system 100 is operable between -40°C and +175°C. The input voltage 110 is operable to provide input power to one or more of the current generator 120, the bandgap generator 130, and the TSD controller 150. In some implementations, the input voltage 110 includes or provides at least one DC voltage to the exemplary system 100. In some implementations, the input voltage 110 is in the range of 1.5V to 5.5V. The current generator 120 is operable to generate at least one constant or substantially constant current source to one or more of the bandgap generator 130 and the TSD controller 150. In some implementations, the current generator 120 provides a supply current equal to or proportional to a current generated by the current generator. In some implementations, one or more of the bandgap generator 130 and the TSD controller 150 receive the supply current. The bandgap generator 130 is operable to generate at least one constant or substantially constant bandgap voltage. In some implementations, the exemplary system 100 generates a bandgap output voltage 140 that is substantially constant within one percent (±1%) of a predetermined bandgap voltage. In some implementations, the bandgap generator 130 is operable to generate an output of at least 10 μA. The TSD controller 150 is operable to generate a TSD control output 160 when operation of the exemplary system 100 is outside a predetermined shutdown range. In some implementations, the TSD controller has a shutdown range of 151°C to 165°C.In some implementations, the TSD control output 160 includes a logic high or logic low component generated from the TSD controller 150. In some implementations, the TSD control output is an inverted logic value indicating a shutdown activation control output during a logic low state of the TSD control output 160 and normal operation during a logic high state of the TSD control output.

[0013] 2 is a diagram illustrating an exemplary current generating device proportional to absolute temperature according to the present embodiment. As shown in FIG. 2, an exemplary circuit 200 corresponds to the current generator 120 and includes an input section, a current mirror section, a current source section, and a current output section.

[0014] The input section includes an input node 202 and resistors 204 and 206. In some implementations, the input node 202 is operable to receive at least an input voltage from the voltage input 110 and provide the input voltage to the resistors 204 and 206. In some implementations, the resistors 204 and 206 are operably coupled to the input node 202 in parallel with each other. In some implementations, each of the resistors 204 and 206 is operably coupled to a current mirror section and a current output section.

[0015] The current mirror portion includes transistors 210 and 212. In some implementations, each of the transistors 210 and 212 is operably coupled to a resistor 204 and a resistor 206, respectively. In some implementations, the transistors 210 and 212 are PNP transistors. In some implementations, the transistors 210 and 212 correspond to the example transistors of FIGS. 5A and 5B. In some implementations, the resistors 204 and 206 are operably coupled to respective emitter terminals of the transistors 210 and 212. In some implementations, respective base terminals of the transistors 210 and 212 are operably coupled to each other. In some implementations, a collector terminal of at least one of the transistors 210 and 212 is operably coupled to respective base terminals of the transistors 210 and 212. In some implementations, the transistors 210 and 212 are operably coupled to a current source portion. The current source portion includes current sources 216 and 218. In some implementations, the current sources 216 and 218 include one or more electric, electronic, or similar devices that provide a predetermined constant current, including one or more of a constant direct current and an alternating current. In some implementations, each of the current sources 216 and 218 is operably coupled to a corresponding collector terminal of each of the transistors 210 and 212, respectively.

[0016] The current output portion includes a transistor 214 and a current output node 222. In some implementations, the transistor 214 is a PNP transistor. In some implementations, the transistor 214 corresponds to the example transistor of FIGS. 5A and 5B. In some implementations, an emitter terminal of the transistor 214 is operably coupled to an emitter node of at least one of the transistors 210 and 212. In some implementations, a base terminal of the transistor 214 is operably coupled to a collector node of at least one of the transistors 210 and 212. In some implementations, the collector node of the transistor 214 is operably coupled to a current output node 222. In some implementations, the current output node 222 is operable to output a Proportional Absolute Temperature (PTAT) current as the current output 220.

[0017] 3 is a diagram illustrating an exemplary bandgap voltage generator according to this embodiment. As shown in FIG. 3, an exemplary circuit 300 includes an input section, a current mirror section, a bias section, and an output section.

[0018] The input section includes a bandgap input node 302, a transistor 304, a current source 330, a capacitor 334, and a resistor 336. In some implementations, the bandgap input node 302 is operable to receive at least an input voltage from the voltage input 110 and provide the input voltage to the transistor 304 and the current source 330. In some implementations, the transistor 304 is a field effect transistor (FET). In some implementations, a source terminal of the transistor 304 is operably coupled to one or more of the bandgap input node 302 and the current source 330. In some implementations, a gate terminal of the transistor 304 is operably coupled to the current source 330. In some implementations, a drain terminal of the transistor 304 is operably coupled to one or more of the current mirror section, the bias section, and the output section. In some implementations, the current source 300 is operable to output a current equal to, substantially equal to, or corresponding to the proportional absolute temperature (PTAT) current output by the exemplary circuit 200. In some implementations, the capacitor 334 and the resistor 336 are operatively coupled in series with each other and in parallel with the current source 330. In some implementations, the capacitor 334 and the resistor 336 comprise a compensation circuit.

[0019] The current mirror portion includes transistors 310 and 312, and resistors 320, 322, 324, and 326. In some implementations, each of the transistors 310 and 312 is operably coupled to the transistor 304, the current source 330, the bias portion, and the output portion. In some implementations, the transistors 310 and 312 are PNP transistors. In some implementations, the transistors 310 and 312 correspond to the example transistors of FIGS. 5A and 5B. In some implementations, the resistors 320 and 324 are each operably coupled to a respective collector terminal of each of the transistors 310 and 312. In some implementations, the collector terminal of the transistor 310 is operably coupled to the base terminal of the transistor 312. In some implementations, the base terminal of the transistor 312 is operably coupled to the collector terminal of the transistor 310. In some implementations, resistors 320 and 322 are disposed in series with a collector terminal of transistor 310, and a base terminal of transistor 310 is operably coupled to a node disposed between resistors 320 and 322. In some implementations, resistors 320 and 322 comprise a voltage divider. In some implementations, resistors 322, 324, and 326 are operably coupled to one another, and resistors 322 and 324 are in parallel with one another and in series with resistor 326. In some implementations, resistor 326 is a variable resistor. In some implementations, resistor 326 is operable to configure, calibrate, or the like, the exemplary circuit 300 to output a predetermined bandgap output voltage. In some implementations, resistor 326 is operable to configure, calibrate, or the like, the exemplary circuit 300 by compensating for electrical characteristics of one or more components of the exemplary circuit 300.

[0020] The bias portion includes transistor 306, transistor 314, and current source 332. In some implementations, transistor 306 is a field effect transistor (FET). In some implementations, transistor 306 is operably coupled to bias node 308 and operable to receive a bias voltage therefrom. In some implementations, a source terminal of transistor 306 is operably coupled to current source 332 and transistor 314. In some implementations, a drain terminal of transistor 306 is operably coupled to one or more of an output of current source 330 and a gate terminal of transistor 304. In some implementations, transistor 314 is a PNP transistor. In some embodiments, transistor 314 corresponds to the exemplary transistor of FIGS. 5A and 5B. In some implementations, a collector terminal of transistor 314 is operably coupled to one or more of an input of current source 332 and a source terminal device of transistor 306. In some implementations, a base terminal of transistor 314 is operably coupled to one or more of the collector terminals of transistor 312 and resistor 324. In some implementations, an emitter node of transistor 314 is operably coupled to the emitter nodes of one or more of transistors 310 and 312 and to an output portion. The output portion includes a bandgap voltage output node 340 operable to provide a bandgap voltage output 140. In some implementations, current source 332 is operable to output a current that is twice or substantially twice the proportional to absolute temperature (PTAT) current output by example circuit 200.

[0021] In some implementations, one or more of the current sources 330 and 332 are operable to generate, provide, or the like a current in accordance with the current output 220. In some implementations, one or more of the current sources 330 and 332 include one or more electric, electronic, or similar devices operable to receive the current output 220 and provide the current output 220 to the example circuit 300. Alternatively, in some implementations, one or more of the current sources 330 and 332 include one or more electric, electronic, or similar devices operable to generate a current based on one or more characteristics of the current output 220 and provide the generated current to the example circuit 300.

[0022] 4 is a diagram illustrating an exemplary thermal shutdown controller apparatus according to the present embodiment. As shown in FIG. 4, the exemplary circuit 400 includes a TSD input section, a TSD signal generator section, and a TSD output section. The TSD input section includes a TSD input node 402 and a current source 420. In some implementations, the TSD input node 402 is operable to receive the voltage input 110. In some implementations, the current source 420 is operably coupled at its input to the TSD input node 402 and operable to receive the voltage input 110 at its input.

[0023] The TSD signal generator portion includes a bandgap voltage input node 404, resistors 412 and 414, a transistor 410, and a current source 416. In some implementations, the bandgap voltage input node is operable to receive the bandgap voltage output 140. In some implementations, the bandgap voltage input node 404 is operably coupled to the bandgap voltage output node 340 of the exemplary circuit 300. In some implementations, the bandgap voltage input node 404 is operably coupled to one or more of the resistor 412 and the transistor 410. In some implementations, the transistor 410 is a PNP transistor. In some embodiments, the transistor 410 corresponds to the exemplary transistor of FIGS. 5A and 5B. In some implementations, an emitter terminal of the transistor 410 is operably coupled to the bandgap voltage input node 404 and the resistor 412. In some implementations, a collector terminal of the transistor 410 is operably coupled to the current source 416. In some implementations, current source 416 is operable to output a current equal to, substantially equal to, or corresponding to the proportional absolute temperature (PTAT) current output by example circuit 200. In some implementations, a base terminal of transistor 410 is operably coupled to resistors 412 and 414. In some implementations, resistors 412 and 414 include a voltage divider circuit.

[0024] The TSD output section includes a transistor 422 and a TSD output node 406. In some implementations, the transistor 422 is a field effect transistor (FET). In some implementations, a gate terminal of the transistor 422 is operably coupled to a collector terminal of the transistor 410 and an input terminal of the current source 416. In some implementations, a source terminal of the transistor 422 is operably coupled to an output of the current source 416 and the resistor 414. In some implementations, the TSD output node 406 is operably coupled to one or more of an output node of the current source 420 and a drain terminal of the transistor 422. In some implementations, the TSD output node 406 provides the TSD control output 160.

[0025] In some implementations, one or more of the current sources 416 and 420 are operable to generate, provide, or the like a current in accordance with the current output 220. In some implementations, one or more of the current sources 416 and 420 include one or more electric, electronic, or similar devices operable to receive the current output 220 and provide the current output 220 to the example circuit 400. Alternatively, in some implementations, one or more of the current sources 416 and 420 include one or more electric, electronic, or similar devices operable to generate a current based on one or more characteristics of the current output 220 and provide the generated current to the example circuit 400.

[0026] FIG. 5A illustrates a plan view of an exemplary transistor device operable in accordance with the system of FIG. 1 and one of the devices of FIGS. 2-4. As illustrated in plan view 500A of FIG. 5A, the exemplary transistor device includes an emitter region, a base region, a collector region, an outer N-type region, an outer P-type region, and a device wall region. In some implementations, the exemplary transistor device is a PNP transistor. In some implementations, the exemplary transistor is a bipolar junction transistor, or the like. In some implementations, the exemplary transistor can be connected to one or more electrode pads that include one or more conductive layers, insulating layers, semiconductive layers, or the like. In some implementations, one or more bandgap transistors are configured in accordance with the exemplary transistors of FIGS. 5A and 5B. Thus, the exemplary transistors may be included in at least one or more of the current generator 120, the bandgap generator 130, and the TSD controller 150. In some implementations, one or more transistors of one or more of the current generator 120, the bandgap generator 130, and the TSD controller 150 are configured in accordance with the exemplary transistors of FIGS. 5A and 5B. Thus, in some implementations, advantages of the present implementations are achieved by integrating the example transistors of FIGS. 5A and 5B with system 100 and one or more of devices 200, 300, and 400.

[0027] The emitter region may include one or more emitter layers 510. In some implementations, the emitter layer is formed on or over a semiconductor substrate by one or more semiconductor or polymer layers. In some implementations, the emitter region is located at or near the center of a plane of the transistor device. As an example, the planar surface of the semiconductor device may include a surface of a semiconductor wafer or a portion thereof following slicing thereof. In some implementations, the emitter layer is formed on a top surface of an exemplary semiconductor device that includes a planar surface. In some embodiments, the emitter region 510 may be contactable with at least one emitter electrode pad, lead, or the like to comprise an emitter electrode terminal of the semiconductor device.

[0028] The base region can include a base layer 512, which is at least partially surrounded by a first shallow trench (ST) layer 520. In some implementations, the base region 512 includes at least one N+ doped semiconductor layer material. In some implementations, the base region 512 at least partially surrounds the emitter layer 510 along a planar surface. In some implementations, the base layer 512 is proximate to the emitter layer 510 along a planar surface of the exemplary device. In some implementations, the base region 512 can contact at least one base electrode pad, lead, or the like to form a base electrode terminal of the semiconductor device. In some implementations, the first ST layer 520 partially surrounds the base layer 512 and at least partially electrically insulates the base layer 512 from one or more layers proximate thereto.

[0029] The collector region can include a collector layer 514, which is at least partially surrounded by a second ST layer 520. In some implementations, the collector layer 514 includes at least one P+ doped semiconductor layer material. In some implementations, the collector layer 514 at least partially surrounds the base layer 512 and the first ST layer 520 along a planar surface. In some implementations, the first ST layer 520 at least partially electrically insulates the base layer 512 from the collector layer 514. In some embodiments, the collector layer 514 is proximate to the first ST layer 520 along a plane of the exemplary device. In some implementations, the collector layer 514 can contact at least one collector electrode pad, lead, or the like to comprise a collector electrode terminal of the semiconductor device. In some implementations, the second ST layer 520 partially surrounds the collector layer 514 and at least partially electrically insulates the collector layer 514 from one or more layers proximate thereto.

[0030] The outer N-type region can include an outer N-type doped layer 516, which is at least partially surrounded by a third ST layer 520. In some implementations, the outer N-type doped layer 516 includes at least one N+ doped semiconductor layer material. In some implementations, the outer N-type doped layer 516 at least partially surrounds the collector layer 514 and the second ST layer 520 along a planar surface. In some implementations, the second ST layer 520 at least partially electrically insulates the collector layer 514 from the outer N-type doped layer 516. In some implementations, the outer N-type doped layer 516 is adjacent to the second ST layer 520 along a plane of the exemplary device. In some implementations, the outer N-type doped layer 516 can be contacted with at least one N-type electrode pad, lead, or the like to constitute an N-type electrode terminal of the semiconductor device. In some implementations, one or more N-type electrode pads are operably coupled to one or more of the emitter layer 510, the base layer 512, and the collector layer 516. In some implementations, a third ST layer 520 partially surrounds the outer N-type doped layer 516 and at least partially electrically insulates the outer N-type doped layer 516 from one or more layers adjacent to it.

[0031] The outer P-type region may include an outer P-type doped layer 518, which is at least partially surrounded by a fourth ST layer 520. In some implementations, the outer P-type doped layer 518 includes at least one P+ doped semiconductor layer material. In some implementations, the outer P-type doped layer 518 at least partially surrounds the outer N-type doped layer 516 and the third ST layer 520 along the planar surface. In some implementations, the third ST layer 520 at least partially electrically insulates the outer N-type doped layer 516 from the outer P-type doped layer 518. In some implementations, the outer P-type doped layer 518 is adjacent to the third ST layer 520 along the plane of the exemplary device. In some implementations, the outer P-type doped layer 518 can be in contact with at least one P-type electrode pad, lead, or the like to constitute a P-type electrode terminal of the semiconductor device. In some implementations, one or more P-type electrode pads are operably coupled to one or more of the emitter layer 510, the base layer 512, and the collector layer 516. In some implementations, a fourth ST layer 520 partially surrounds the outer P-type doped layer 518 and at least partially electrically insulates the outer P-type doped layer 518 from one or more device boundaries, including device wall regions.

[0032] The device wall region can include a substrate material 522. In some implementations, the substrate material 522 includes at least one epitaxial (epi) semiconductor layer material. In some implementations, the substrate material is formed as a semiconductor wafer and sliced ​​or otherwise separated into a plurality of semiconductor device elongate planes through a plane through the substrate material perpendicular to the plane of 500A parallel to the plane of the exemplary semiconductor device.

[0033] Figure 5B is a diagram illustrating a cross-sectional view of the example transistor device of Figure 5 A. As illustrated in cross-sectional view 500B of Figure 5B, the example transistor device includes an emitter region, a base region, a collector region, an outer N-type region, an outer P-type region, a device wall region, and a substrate region.

[0034] The emitter region may further include a plurality of contact portions including the emitter layer 510. In some implementations, the plurality of contact portions of the emitter layer 510 include a buried emitter layer and an emitter layer structure. In some implementations, the buried emitter layer includes at least one P+ doped semiconductor layer material. In some implementations, the buried emitter layer is disposed at or near the center of a plane of the transistor device. In some implementations, the emitter layer structure includes at least one polymer or semiconductor layer material. In some implementations, the emitter layer structure at least partially surrounds the buried emitter along a planar surface. In some implementations, the emitter layer structure is disposed substantially on the plane of the semiconductor device and the buried emitter layer. In some implementations, the buried emitter layer and the emitter layer structure are formed by one or more interdependent or independent semiconductor fabrication steps as known or as may become known.

[0035] The base region may further include a high voltage N-type diffused drain (HVNDD) layer 560. In some implementations, the HVNDD layer 560 is disposed within the semiconductor device and at least partially disposed below the emitter layer 510 and the base layer 512. In some implementations, one or more of the buried emitter layer and base layer 512 of the emitter layer 510 are at least partially embedded within the HVNDD layer 560. In some implementations, the emitter layer structure of the emitter layer 510 is disposed at least partially above and in contact with the HVNDD layer 560. It is understood that the HVNDD layer 560 may include additional materials therein. It is further understood that the HVNDD layer 560 may include any material or materials having at least one high voltage N-type diffused drain characteristic, property, or the like.

[0036] The collector region may further include a first p-well layer 540. In some implementations, the first p-well layer 540 is disposed in the semiconductor device and at least partially below the collector layer 514. In some implementations, the collector layer 514 is at least partially embedded in the first p-well layer 540. In some implementations, the first ST layer 520 further at least partially electrically insulates the HVNDD layer 560 from the first p-well layer 540. It should be understood that the first p-well layer 540 may include additional materials therein. Additionally, it should be understood that the first p-well layer 540 may include any material or materials having at least one p-well characteristic, property, or the like.

[0037] The external N-type region may further include an n-well layer 550 and a high voltage n-well (HVNW) layer 552. In some implementations, the n-well layer 550 is disposed within the semiconductor device at least partially below the outer N-type doped layer 516. In some implementations, the outer N-type doped layer 516 is at least partially embedded within the n-well layer 550. In some implementations, the second ST layer 520 further electrically insulates the first p-well layer 540 at least partially from the n-well layer 550. It should be understood that the n-well layer 550 may include additional materials therein. It should be further understood that the n-well layer 550 may include any material or materials having at least one n-well characteristic, property, or the like. In some implementations, the HVNW layer 552 is disposed within the semiconductor device and at least partially below the n-well layer 550. In some implementations, the n-well layer 550 is at least partially embedded within the HVNW layer 552. It should be understood that the HVNW layer 552 may include additional materials therein. Further, it should be appreciated that the HVNW layer 552 may include any material or materials having at least one n-well characteristic, property, or the like.

[0038] The outer P-type region may further include a second p-type well layer 540 and an outer high voltage p-type well (HVPW) layer 542. In some implementations, a second p-well layer 540 is disposed within the semiconductor device and at least partially above the outer HVPW layer 542. In some implementations, the second p-well layer 540 is at least partially embedded within the outer HVPW layer 542. In some implementations, the third ST layer 520 further electrically insulates the n-well layer 550 at least partially from the second p-well layer 540. It should be appreciated that the second p-well layer 540 may include additional materials therein. Additionally, it should be appreciated that the second p-well layer 540 may include any material or materials having at least one p-well characteristic, property, or the like. In some implementations, the outer HVPW layer 542 is disposed within the semiconductor device and at least partially below the second p-well layer 540. In some implementations, the second p-well layer 540 is at least partially embedded within the outer HVPW layer 542. It should be understood that the outer HVPW layer 542 can include additional materials therein. Further, it should be understood that the outer HVPW layer 542 can include any material or materials having at least one p-well characteristic, property, or the like.

[0039] The substrate region can include the substrate material 522 of the device wall region, the inner high voltage p-well (HVPW) layer 542, and the N-buried layer (NBL) 530. In some implementations, the substrate material 522 includes the device wall extending along the height of the exemplary transistor device of FIGS. 500A and 500B. In some implementations, the inner HVPW layer 542 includes a doped region formed simultaneously with the outer doped region 542. In some implementations, the HVNW layer 552 is formed within the intermediate HVPW layer including the inner HVPW layer and the outer HVPW layer 542, and then forms the separate inner and outer HVPW layers 542. It should be understood that the inner HVPW layer 542 can include additional materials therein. Additionally, it should be understood that the inner HVPW layer 542 can include any material or materials having at least one p-well characteristic, characteristic, or the like. In some implementations, the NBL 530 is integrated into one or more of the substrate material 522, the inner HVPW layer 542, and the HVNW layer 552. The NBL 530 may be doped according to at least one of N+, N?, or the like. However, it is understood that the NBL 530 may include additional materials therein. Additionally, it is understood that the NBL 530 may include any material or materials having at least one n-type characteristic, property, or the like.

[0040] The subject matter described herein may depict different components contained within or connected to different other components. It should be understood that the architectures depicted are exemplary, and that in fact many other architectures that achieve the same functionality may be implemented. In a conceptual sense, any arrangement of components to achieve the same functionality is effectively "associated" such that the desired functionality is achieved; thus, any two components combined herein to achieve a particular functionality may be considered to be "associated" with one another such that the desired functionality is achieved, regardless of architecture or intermediate components. Similarly, any two components so associated may also be considered to be "operably connected" or "operably coupled" with one another to achieve the desired functionality, and any two components that may be so associated may be "operably coupled" with one another to achieve the desired functionality. Specific examples of operably coupleable include, but are not limited to, physically coupleable and / or physically interacting components, and / or wirelessly interactable and / or wirelessly interacting components, and / or logically interactable and / or logically interacting components.

[0041] With respect to the use of plural and / or singular terms herein, those of skill in the art may translate from plural to singular and / or from singular to plural as appropriate to the context and / or application. Various singular / plural permutations may be expressly set forth herein for clarity.

[0042] Those of ordinary skill in the art will generally understand that the clauses used in this specification, and in particular the appended claims (e.g., the body of the appended claims), are generally intended as "open" clauses (e.g., a "including" clause should be interpreted as "including but not limited to," a "having" clause should be interpreted as "having at least," a "including" clause should be interpreted as "including but not limited to," etc.).

[0043] Although the figures and description may show a particular order of method steps, the order of such steps may differ from that shown and described unless otherwise specified above. Also, two or more steps may be performed simultaneously or with partial concurrence unless otherwise specified above. Such variations may depend, for example, on the software and hardware systems selected, as well as designer choice. All such variations are within the scope of this disclosure. Similarly, software implementations of the described methods may be accomplished by standard programming techniques with rule-based logic and other logic to accomplish the various connecting, processing, comparing, and deciding steps.

[0044] It will be further understood by those skilled in the art that where the recitation of a particular number of introduced claims is intended, such intent will be expressly recited in the claim, and that in the absence of such recitation, no such intent exists. For example, as an aid to understanding, the following appended claims may contain the use of the introductory phrases "at least one" and "one or more" to introduce the recitation of a claim, but the use of such phrases should not be construed as meaning that the introduction of a claim reference by the indefinite article "a" or "an" limits a particular claim that includes such an introduced claim reference to an invention that includes only one such reference, even if the same claim includes the introductory phrases "one or more" or "at least one" and the indefinite article "a" or "an." (For example, "a" and / or "an" are typically interpreted to mean "at least one" or "one or more." Moreover, even if a specific number of introduced claim references are explicitly recited, one of ordinary skill in the art will recognize that such references should typically be interpreted to mean at least the recited number (e.g., a bare reference of "two references," without other modifiers, typically means at least two references, or more than two references).

[0045] Furthermore, when a convention similar to "at least one of A, B, and C, etc." is used, it is generally intended that such a structure would be understood by one of ordinary skill in the art (e.g., "a system having at least one of A, B, and C" includes, but is not limited to, systems having A alone, B alone, C alone, A and B alone, A and B alone, A and C alone, A and C alone, B and C alone, and / or A, B and C alone, etc.). When a convention similar to "at least one of A, B, or C, etc." is used, it is generally intended that such a structure would be understood by one of ordinary skill in the art (e.g., "a system having at least one of A, B, or C" includes, but is not limited to, systems having A alone, B alone, C alone, A and B together, A and C together, B and C together, and / or A, B and C together, etc.). Moreover, it will be further understood by those skilled in the art that virtually any disjunctive word and / or phrase presenting two or more alternative terms, either in the description, claims, or drawings, should be understood to contemplate the possibility of including one of the terms, either of the terms, or both of the terms. For example, the phrase "A or B" is understood to include the possibilities of "A" or "B" or "A and B."

[0046] Further, unless otherwise specified, use of the terms "approximately," "about," "approximately," "substantially," and the like means plus or minus ten percent.

[0047] The foregoing description of the illustrative embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or to be limiting with respect to the precise form disclosed, and modifications and variations are possible in light of the above teachings or may be acquired from practice of the disclosed embodiments. It is intended that the scope of the present invention be defined by the appended claims and their equivalents. [Explanation of symbols]

[0048] 100 Systems 110 Input voltage 120 Current Generator 130 Bandgap Generator 140 Bandgap voltage output 150 Thermal Shutdown Controller 160 TSD control output 202 Input Node 204, 206 resistor 210, 212, 214 Transistors 216, 218 current source 220 Current Output 222 Current Output Node 330, 332 current source 302 Bandgap Input Node 304, 306, 310, 312, 314 transistors 308 Bias Node 320, 322, 324, 326, 336 resistor 334 Capacitor 340 Bandgap voltage output node 402 TSD input node 404 Bandgap voltage input node 406 TSD output node 410, 422 Transistors 412, 414 resistor 416, 420 current source 510 Emitter layer 512 Base Layer 514 Collector Layer 516 N-type doped layer 518 P-type doped layer 520 Trench Layer 522 Substrate Materials 530 N-embedding layer 540 p-well layer 542 High voltage p-well layer 550 n-well layer 552 High voltage n-well layer 560 High voltage N-type diffused drain layer

Claims

1. a first current source operatively connected to the bandgap input node and the bandgap output node and capable of outputting a first Proportional Absolute Temperature (PTAT) current; a current mirror including a first bandgap transistor and a second bandgap transistor operatively connected to the bandgap output node; a second current source operatively connected to the current mirror and capable of outputting a second PTAT current; a third bandgap transistor operatively connected to the bandgap output node and to the current mirror; Bandgap voltage device.

2. the third bandgap transistor operatively connects the second current source to the current mirror; 2. The bandgap voltage device of claim 1.

3. A first current source operatively connected to the bandgap input node and the bandgap output node, the first current source capable of outputting a first proportional to absolute temperature (PTAT) current; a current mirror including a first bandgap transistor and a second bandgap transistor operatively connected to the bandgap output node; a second current source operatively connected to the current mirror and capable of outputting a second PTAT current; a voltage divider operably connected to the first bandgap transistor and the second bandgap transistor. Bandgap voltage device.

4. A first current source operatively connected to the bandgap input node and the bandgap output node, the first current source capable of outputting a first proportional to absolute temperature (PTAT) current; a current mirror including a first bandgap transistor and a second bandgap transistor operatively connected to the bandgap output node; a second current source operatively connected to the current mirror and capable of outputting a second PTAT current; a first bias transistor operatively connected to the bandgap input node, the first current source, the current mirror, and the bandgap output node. Bandgap voltage device.

5. a second bias transistor operably connected to the first current source, the second current source, and the first bias transistor.

5. The bandgap voltage device of claim 4.

6. the first current source and the second current source comprise at least a PTAT current generator; 2. The bandgap voltage device of claim 1.

7. each of the first bandgap transistor, the second bandgap transistor, and the third bandgap transistor comprises a bipolar junction transistor; 2. The bandgap voltage device of claim 1.

8. the bipolar junction transistor has a first P+ layer adjacent to a center of a formation region of the bipolar junction transistor when viewed in a plane; 8. The bandgap voltage device of claim 7.

9. the bipolar junction transistor further comprising a first N+ layer at least partially surrounding the plurality of emitter layers, and a second P+ layer at least partially surrounding the first N+ layer.

9. The bandgap voltage device of claim 8.

10. The bipolar junction transistor further includes a second N+ layer at least partially surrounding the second P+ layer, and a third P+ layer at least partially surrounding the second N+ layer. Have 10. The bandgap voltage device of claim 9.

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