Vector multiplication and addition with zero skip instructions and logic

Abstract

To provide an instruction and associated logic to enable a vector multiply add instructions with automatic zero skipping for sparse input.SOLUTION: One embodiment provides a general-purpose graphics processor comprising logic to perform operations comprising fetching a hardware macro instruction having a predicate mask, a repeat count, and a set of initial operands, where the initial operands include a destination operand and multiple source operands. The hardware macro instruction is configured to perform one or more multiply / add operations on input data associated with a set of matrices.SELECTED DRAWING: Figure 20

Description

[Technical field]

[0001] This application relates to vector multiply add instructions and logic with zero skip. [Background technology]

[0002] Matrix multiplication is one of the most common operations performed in high performance computing (HPC) and machine learning (ML) workloads. Matrix multiplication operations are often performed in processor functional units using a variant of a fused multiply-add instruction. Because matrices used in these workloads are often sparse, there is a high probability that the multiplier or multiplicand provided to the instruction is zero, resulting in the accumulation of zero values. Therefore, such operations can be bypassed without affecting the final result. [Brief description of the drawings]

[0003] So that the above-mentioned features of the present embodiments can be understood in detail, a more particular description of the above briefly summarized embodiments can be made by reference to embodiments, some of which are illustrated in the accompanying drawings, it being noted, however, that the accompanying drawings depict only typical embodiments and therefore should not be considered as limiting the scope thereof. [Figure 1] FIG. 1 is a block diagram of a processing system according to one embodiment. [Figure 2A] FIG. 1 illustrates a computer system and a graphics processor provided by embodiments described herein. [Figure 2B] FIG. 1 illustrates a computer system and a graphics processor provided by embodiments described herein. [Figure 2C] FIG. 1 illustrates a computer system and a graphics processor provided by embodiments described herein. [Figure 2D]FIG. 1 illustrates a computer system and a graphics processor provided by embodiments described herein. [Figure 3A] FIG. 2 is a block diagram of an additional graphics processor and computational accelerator architecture provided by embodiments described herein. [Figure 3B] FIG. 2 is a block diagram of an additional graphics processor and computational accelerator architecture provided by embodiments described herein. [Figure 3C] FIG. 2 is a block diagram of an additional graphics processor and computational accelerator architecture provided by embodiments described herein. [Figure 4] FIG. 4 is a block diagram of a graphics processing engine 410 of a graphics processor according to some embodiments. [Figure 5A] FIG. 2 illustrates thread execution logic including an array of processing elements used in a graphics processor core according to embodiments described herein. [Figure 5B] FIG. 2 illustrates thread execution logic including an array of processing elements used in a graphics processor core according to embodiments described herein. [Figure 6] FIG. 2 illustrates an additional execution unit according to one embodiment. [Figure 7] FIG. 2 is a block diagram illustrating a graphics processor instruction format according to some embodiments. [Figure 8] FIG. 2 is a block diagram of a graphics processor according to another embodiment. [Figure 9A] FIG. 2 illustrates a command format and command sequence for a graphics processor according to some embodiments. [Figure 9B] FIG. 2 illustrates a command format and command sequence for a graphics processor according to some embodiments. [Figure 10] FIG. 1 illustrates an exemplary graphics software architecture for a data processing system according to some embodiments. [Figure 11A] FIG. 1 is a block diagram illustrating an IP core development system according to one embodiment. [Figure 11B] 1 is a cross-sectional side view of an integrated circuit package assembly according to certain embodiments described herein. [Figure 11C] FIG. 2 illustrates a package assembly including multiple units of hardware logic chiplets connected to a substrate. [Figure 11D] FIG. 2 illustrates a package assembly including replaceable chiplets, according to one embodiment. [Figure 12] FIG. 1 illustrates an example integrated circuit and associated graphics processor that may be manufactured using one or more IP cores in accordance with various embodiments described herein. [Figure 13A] FIG. 1 illustrates an example integrated circuit and associated graphics processor that may be manufactured using one or more IP cores in accordance with various embodiments described herein. [Figure 13B] FIG. 1 illustrates an example integrated circuit and associated graphics processor that may be manufactured using one or more IP cores in accordance with various embodiments described herein. [Figure 14] FIG. 1 illustrates a machine learning software stack according to one embodiment. [Figure 15A] FIG. 1 illustrates layers of an exemplary deep neural network. [Figure 15B] FIG. 1 illustrates layers of an exemplary deep neural network. [Figure 16] FIG. 1 illustrates an exemplary recurrent neural network. [Figure 17] FIG. 1 illustrates training and deployment of a deep neural network. [Figure 18] FIG. 2 is a block diagram illustrating distributed learning. [Figure 19] FIG. 1 is a block diagram of a data processing system according to one embodiment. [Figure 20] FIG. 2 illustrates a general matrix multiplication operation on a source matrix and a destination matrix. [Figure 21A] FIG. 1 illustrates an instruction and associated hardware logic for enabling multiply-add vector operations with zero skip on sparse inputs. [Figure 21B] FIG. 1 illustrates an instruction and associated hardware logic for enabling multiply-add vector operations with zero skip on sparse inputs. [Figure 21C] FIG. 1 illustrates an instruction and associated hardware logic for enabling multiply-add vector operations with zero skip on sparse inputs. [Figure 22] FIG. 1 illustrates instruction expansion and skipping of sparse input according to one embodiment. [Diagram 23] FIG. 1 illustrates a method for facilitating execution of a multiply / add / vector instruction, according to one embodiment. [Figure 24] FIG. 1 is a block diagram of a computing device including a graphics processor, according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0004] The embodiments described herein generally provide a new instruction (madv) that compresses multiple multiply-add instructions found in a general matrix multiplication (GEMM) kernel. When the instruction is executed, the functional units of the graphics processor can compare zero values ​​of the broadcast source to create a skipMask bitmap that is sent as a predicate to the madv instruction. The predicate is used to skip individual multiply-add instructions during the expansion of the madv instruction. Skipping instruction instances is particularly useful for sparse matrix multiplication. The number of instruction iterations that can be skipped during expansion is related to the sparsity of the input. In the HPC / ML computational domain, matrix sparsity can exceed 50%, allowing more than half of the dynamic multiply-add instructions to be bypassed, resulting in a speedup of more than 2x for such workloads. Furthermore, the instruction fetch and decode bandwidth consumed by such workloads decreases with the amount of operating power consumed by the graphics processor. In general, a direct correlation can be seen between the benefits provided by the madv instruction and the number of zeros in a given input matrix.

[0005] For purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various embodiments described below. However, it will be apparent to one skilled in the art that the embodiments may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the underlying principles and to provide a more thorough understanding of the embodiments. Although some of the following embodiments are described with reference to a graphics processor, the techniques and teachings described herein may be applied to various types of circuits or semiconductor devices, including general-purpose or graphics processing devices. References herein to "one embodiment" or "an embodiment" indicate that a particular feature, structure, or characteristic described with respect to or in connection with an embodiment may be included in at least one of such embodiments. However, the appearance of the phrase "in one embodiment" in various places in the specification does not necessarily all refer to the same embodiment.

[0006] In the following description and claims, the terms "coupled" and "connected," along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. "Coupled" is used to indicate that two or more elements, which may or may not be in direct physical or electrical contact with each other, co-operate or interact with each other. "Connected" is used to indicate the establishment of communication between two or more elements that are coupled with each other.

[0007] In the following description, Figures 1-13 provide an overview of an exemplary data processing system and graphic processor logic incorporating or related to various embodiments. Figures 14-19 provide an overview of machine learning and the applicability of graphic processors and parallel processors to machine learning. Figures 20-24 provide specific details of various embodiments. Some aspects of the following embodiments are described with respect to a graphic processor, while other aspects are described with respect to a general-purpose processor, such as a central processing unit (CPU). Similar techniques and teachings can be applied to other types of circuits or semiconductor devices, including, but not limited to, one or more instances of many integrated core processors, GPU clusters, or field programmable gate arrays (FPGAs). In general, the teachings can be applied to any processor or machine that manipulates or processes images (e.g., samples, pixels), vertex data, or geometry data, or performs parallel processing operations for machine learning and high performance computer applications.

[0008] System Overview

[0009] 1 is a block diagram of a processing system 100 according to one embodiment. System 100 may be used in a single processor desktop system, a multiprocessor workstation system, or a server system having multiple processors 102 or processor cores 107. In one embodiment, system 100 is a processing platform embedded in a system-on-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices, such as in Internet of Things (IoT) devices with wired or wireless connections to local or wide area networks.

[0010] In one embodiment, the system 100 may include, be coupled to, or be integrated within a server-based gaming platform, a game console and media console including games, a mobile game console, a handheld game console, or an online game console. In some embodiments, the system 100 is part of a mobile Internet-connected device, such as a mobile phone, a smart phone, a tablet computing device, or a laptop with low internal storage capacity. The processing system 100 may also include, be coupled to, or be integrated within a wearable device, such as a smart watch wearable device; smart eyewear or clothing enhanced with augmented reality (AR) or virtual reality (VR) capabilities that provide visual, audio, or haptic output to complement a real-world visual, audio, or haptic experience, or that otherwise provides text, audio, graphics, video, holographic images or videos, or haptic feedback; other augmented reality (AR) devices; or other virtual reality (VR) devices. In some embodiments, the processing system 100 may include, be part of, a television or a set-top box device. In one embodiment, system 100 may include, be coupled to, or be integrated within an autonomous vehicle, such as a bus, a tractor trailer, an automobile, a motorcycle or power cycle, an airplane or glider (or any combination thereof), etc. The autonomous vehicle may use system 100 to process the sensed environment around the vehicle.

[0011] In some embodiments, the one or more processors 102 each include one or more processor cores 107 for processing instructions that, when executed, perform operations of system or user software. In some embodiments, at least one of the one or more processor cores 107 is configured to process a particular instruction set 109. In some embodiments, the instruction set 109 may facilitate computation via complex instruction set computing (CISC), reduced instruction set computing (RISC), or very long instruction words (VLIW). The one or more processor cores 107 may process different instruction sets 109, which may include instructions to facilitate emulation of other instruction sets. The processor cores 107 may also include other processing devices, such as digital signal processors (DSPs).

[0012] In some embodiments, the processor 102 includes a cache memory 104. Depending on the architecture, the processor 102 may have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among various components of the processor 102. In some embodiments, the processor 102 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which may be shared among the processor cores 107 using known cache coherency techniques. A register file 106 may also be included in the processor 102 and may include different types of registers (e.g., integer registers, floating point registers, status registers, and an instruction pointer register) for storing different types of data. Some registers may be general purpose registers, while other registers may be specific to the design of the processor 102.

[0013] In some embodiments, the one or more processors 102 are coupled to one or more interface buses 110 to transmit communication signals, such as address, data, or control signals, between the processors 102 and other components in the system 100. In one embodiment, the interface bus 110 may be a processor bus, such as a version of a Direct Media Interface (DMI) bus. However, the processor bus is not limited to a DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In one embodiment, the processor 102 includes an integrated memory controller 116 and a platform controller hub 130. The memory controller 116 facilitates communication between memory devices and other components of the system 100, while the platform controller hub (PCH) 130 provides connectivity to I / O devices via a local I / O bus.

[0014] The memory device 120 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or any other memory device with suitable performance to function as a process memory. In one embodiment, the memory device 120 may operate as a system memory of the system 100 to store data 122 and instructions 121 used by the one or more processors 102 when executing applications or processes. The memory controller 116 also couples to an optional external graphics processor 118 that may communicate with one or more graphics processors 108 in the processor 102 to perform graphics and media processing. In some embodiments, graphics, media, or computational processing may be assisted by an accelerator 112, which is a co-processor that may be configured to perform a specialized set of graphics, media, or computational processing. For example, in one embodiment, the accelerator 112 is a matrix multiplication accelerator used to optimize machine learning or computational processing. In one embodiment, accelerator 112 is a ray-tracing accelerator that can be used to perform ray-tracing operations in conjunction with graphics processor 108. In one embodiment, external accelerator 119 can be used instead of or in conjunction with accelerator 112.

[0015] In some embodiments, a display device 111 may be connected to the processor 102. The display device 111 may be one or more internal display devices, such as a mobile electronic or laptop device, or an external display device attached via a display interface (e.g., DisplayPort, etc.). In one embodiment, the display device 111 may be a head mounted display (HMD), such as a stereoscopic display device for use in virtual reality (VR) or augmented reality (AR) applications.

[0016] In some embodiments, the platform controller hub 130 allows peripherals to be connected to the memory device 120 and the processor 102 via a high-speed I / O bus. The I / O peripherals include, but are not limited to, an audio controller 146, a network controller 134, a firmware interface 128, a wireless transceiver 126, a touch sensor 125, and a data storage device 124 (e.g., non-volatile memory, volatile memory, hard disk drive, flash memory, NAND, 3D NAND, 3D XPoint, etc.). The data storage device 124 can be connected via a storage interface (e.g., SATA) or via a peripheral bus such as a peripheral component interconnect bus (e.g., PCI, PCI Express). The touch sensor 125 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. The wireless transceiver 126 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, 5G, or Long-Term Evolution (LTE) transceiver. Firmware interface 128 allows for communication with system firmware and may be, for example, a unified extensible firmware interface (UEFI). Network controller 134 may allow for network connectivity to a wired network. In some embodiments, a high performance network controller (not shown) couples to interface bus 110. In one embodiment, audio controller 146 is a multi-channel high definition audio controller. In one embodiment, system 100 includes an optional legacy I / O controller 140 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. Platform controller hub 130 may also connect to one or more universal serial bus (USB) controllers 142 for connecting input devices such as a keyboard and mouse 143 combination, a camera 144, or other USB input devices.

[0017] It should be understood that the illustrated system 100 is exemplary and not limiting, as other types of data processing systems configured differently may be used. For example, instances of memory controller 116 and platform controller hub 130 may be integrated into a separate external graphics processor, such as external graphics processor 118. In one embodiment, platform controller hub 130 and / or memory controller 116 may be external to one or more processors 102. For example, system 100 may include external memory controller 116 and platform controller hub 130, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with processor 102.

[0018] For example, a circuit board (sled) may be used on which components such as CPUs, memory, and other components are placed and designed to enhance thermal performance. In some examples, processing components such as processors are placed on the top surface of the sled, while near memory such as DIMMs are placed on the bottom surface of the sled. As a result of the enhanced airflow from this design, the components can operate at higher frequencies and power levels than typical systems, thereby improving performance. Additionally, the sled is configured to blindly mate with power and data communication cables in the rack, thereby enhancing the ability to be quickly removed, upgraded, reinstalled, and / or replaced. Similarly, the individual components, such as processors, accelerators, memory, data storage drives, etc., placed on the sled are configured to be easily upgraded due to the increased spacing between each other. In an exemplary embodiment, the components further include hardware authentication features to attest to their authenticity.

[0019] Data centers can utilize a single network architecture (fabric) that supports multiple other network architectures, including Ethernet and Omnipath. The threads can be connected to the switches via optical fiber, which provides higher bandwidth and lower latency than typical twisted pair cabling (e.g., Cat5, Cat5E, Cat6, etc.). The high bandwidth, low latency interconnect and network architecture allows the data center to pool resources such as memory, accelerators (e.g., GPUs, graphic accelerators, FPGAs, ASICs, neural network and / or artificial intelligence accelerators, etc.), and physically disaggregated data storage drives, when in use, and provide them to computer resources (e.g., processors) as needed, allowing the computer resources to access the pooled resources as if they were local.

[0020] A power source or power source can provide voltage and / or current to system 100 or any component or system described herein. In one example, the power source includes an AC to DC (alternating current to direct current) adapter for plugging into a wall outlet. Such AC power can be a renewable energy (e.g., solar power) source. In one example, the power source includes a DC power source, such as an external AC-DC converter. In one example, the power source or power source includes wireless charging hardware that charges by proximity to a charging field. In one example, the power source can include an internal battery, an AC power source, a motion-based power source, a solar power source, or a fuel cell power source.

[0021] Figures 2A-2D illustrate a computer system and a graphics processor provided by embodiments described herein. Elements of Figures 2A-2D having the same reference numbers (or names) as elements of other figures herein may operate or function in a similar manner as described elsewhere herein, but are not limited to such.

[0022] 2A is a block diagram of an embodiment of a processor 200 having one or more processor cores 202A-202N, an integrated memory controller 214, and an integrated graphics processor 208. The processor 200 may include additional cores up to additional core 202N, represented by a dashed box. Each of the processor cores 202A-202N includes one or more internal cache units 204A-204N. In some embodiments, each processor core also has access to one or more shared cache units 206. The internal cache units 204A-204N and the shared cache unit 206 represent a cache memory hierarchy within the processor 200. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core, and one or more levels of shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, with the highest level of cache before external memory classified as an LLC. In some embodiments, cache coherency logic maintains coherency between the various cache units 206 and 204A-204N.

[0023] In some embodiments, processor 200 may also include a set of one or more bus controller units 216 and a system agent core 210. The one or more bus controller units 216 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. The system agent core 210 provides management functions for various processor components. In some embodiments, system agent core 210 includes one or more integrated memory controllers 214 for managing access to various external memory devices (not shown).

[0024] In some embodiments, one or more of the processor cores 202A-202N include support for simultaneous multithreading. In such embodiments, the system agent core 210 includes components for coordinating and operating the cores 202A-202N during multithreaded processing. The system agent core 210 may further include a power control unit (PCU) that includes logic and components for coordinating the power state of the processor cores 202A-202N and the graphics processor 208.

[0025] In some embodiments, processor 200 further includes a graphics processor 208 for performing graphics processing operations. In some embodiments, graphics processor 208 couples to a system agent core 210 that includes a set of shared cache units 206 and one or more integrated memory controllers 214. In some embodiments, system agent core 210 also includes a display controller 211 that drives the output of the graphics processor to one or more coupled displays. In some embodiments, display controller 211 may also be a separate module coupled to the graphics processor via at least one interconnect or may be integrated within graphics processor 208.

[0026] In some embodiments, a ring-based interconnect unit 212 is used to couple the internal components of processor 200. However, alternative interconnect units may be used, such as a point-to-point interconnect, a switched interconnect, or other technologies, including technologies known in the art. In some embodiments, graphics processor 208 couples to ring interconnect 212 via I / O link 213.

[0027] The exemplary I / O link 213 represents at least one of several types of I / O interconnects, including on-package I / O interconnects that facilitate communication between various processor components and a high-performance embedded memory module 218, such as an eDRAM module. In some embodiments, each of the processor cores 202A-202N and the graphics processor 208 may use the embedded memory module 218 as a shared last-level cache.

[0028] In some embodiments, the processor cores 202A-202N are homogeneous cores that execute the same instruction set architecture. In another embodiment, the processor cores 202A-202N are heterogeneous with respect to instruction set architecture (ISA), where one or more of the processor cores 202A-202N execute a first instruction set while at least one of the other cores executes a subset of the first instruction set or another instruction set. In one embodiment, the processor cores 202A-202N are heterogeneous with respect to microarchitecture, where one or more cores with relatively high power consumption are combined with one or more cores with low power consumption. In one embodiment, the processor cores 202A-202N are heterogeneous with respect to computational capabilities. Additionally, the processor 200 can be implemented on one or more chips or as a SoC integrated circuit having the illustrated components in addition to other components.

[0029] FIG. 2B is a block diagram of hardware logic of a graphics processor core 219 according to some embodiments described herein. Elements of FIG. 2B having the same reference numbers (or names) as elements of other figures herein may operate or function in a similar manner as described elsewhere herein, but are not limited to such. The graphics processor core 219, sometimes referred to as a core slice, may be one or more graphics cores in a modular graphics processor. The graphics processor core 219 is an example of one graphics core slice, and the graphics processors described herein may include multiple graphics core slices based on target power and performance envelopes. Each graphics processor core 219 may include a fixed function block 230 coupled with multiple sub-cores 221A-221F, also referred to as sub-slices, that include modular blocks of general purpose and fixed function logic.

[0030] In some embodiments, fixed function block 230 includes a geometry / fixed function pipeline 231 that may be shared by all sub-cores of graphics processor core 219, e.g., in lower performance and / or lower power graphics processor implementations. In various embodiments, geometry / fixed function pipeline 231 includes a 3D fixed function pipeline (e.g., 3D pipeline 312 in FIGS. 3 and 4 described below), a video front end unit, a thread spawner and thread dispatcher, a unified return buffer manager that manages a unified return buffer manager (e.g., unified return buffer 418 in FIG. 4, described below).

[0031] In one embodiment, the fixed function block 230 also includes a graphics SoC interface 232, a graphics microcontroller 233, and a media pipeline 234. The graphics SoC interface 232 provides an interface between the graphics processor core 219 and other processor cores in the system-on-chip integrated circuit. The graphics microcontroller 233 is a programmable sub-processor that can be configured to manage various functions of the graphics processor core 219, including thread dispatch, scheduling, and pre-emption. The media pipeline 234 (e.g., media pipeline 316 of FIGS. 3 and 4) includes logic that facilitates decoding, encoding, pre-processing, and / or post-processing of multimedia data, including image and video data. The media pipeline 234 performs media processing via requests to computation or sampling logic in the sub-cores 221-212F.

[0032] In one embodiment, the SoC interface 232 enables the graphics processor core 219 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components in the SoC, including memory hierarchy elements such as shared last-level cache memory, system RAM, embedded on-chip or on-package DRAM, etc. The SoC interface 232 also enables communication with fixed function devices in the SoC, such as a camera imaging pipeline, and enables the use and / or implementation of global memory atomics that may be shared between the graphics processor core 219 and the CPUs in the SoC. The SoC interface 232 also implements power management control for the graphics processor core 219 and enables an interface between the clock domain of the graphics core 219 and other clock domains in the SoC. In one embodiment, the SoC interface 232 enables receipt of command buffers from a command streamer and a global thread dispatcher configured to provide commands and instructions to each of one or more graphics cores in the graphics processor. Commands and instructions can be dispatched to the media pipeline 234 if media processing is to be performed, or to the geometry and fixed function pipelines (e.g., geometry and fixed function pipelines 231, geometry and fixed function pipelines 237) if graphics processing operations are to be performed.

[0033] Graphics microcontroller 233 can be configured to perform various scheduling and management tasks for graphics processor core 219. In one embodiment, graphics microcontroller 233 can perform graphics and / or compute workload scheduling to various graphics parallel engines in execution unit (EU) arrays 222A-222F, 224A-224F within sub-cores 221A-221F. In this scheduling model, host software executing on a CPU core of a SoC including graphics processor core 219 can send a workload to one of multiple graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. Scheduling operations include determining which workload to run next, sending the workload to a command streamer, pre-empting existing workloads running on the engines, monitoring the progress of the workload, and notifying host software when the workload is completed. In one embodiment, graphics microcontroller 233 may also facilitate low power or idle states for graphics processor core 219, providing graphics processor core 219 with the ability to save and restore registers within graphics processor core 219 on low power state transitions independent of the operating system and / or graphics driver software on the system.

[0034] Graphics processor core 219 may have up to N modular sub-cores, more or less than the illustrated sub-cores 221A-221F. For each set of N sub-cores, graphics processor core 219 may include shared function logic 235, shared and / or cache memory 236, geometry / fixed function pipeline 237, as well as additional fixed function logic 238 that accelerates various graphics and computation operations. Shared function logic 235 may include logic units that can be shared by each of the N sub-cores in graphics processor core 219, associated with shared function logic 420 of FIG. 4 (e.g., sampler, math, and / or inter-thread communication logic). Shared and / or cache memory 236 may be a last-level cache for the set of N sub-cores 221A-221F in graphics processor core 219, and may also function as a shared memory accessible by multiple sub-cores. Geometry / fixed function pipeline 237 may be included in place of geometry / fixed function pipeline 231 in fixed function block 230 and may include the same or similar logical units.

[0035] In one embodiment, graphics processor core 219 includes additional fixed function logic 238 that can include various fixed function acceleration logic used by graphics processor core 219. In one embodiment, additional fixed function logic 238 includes an additional geometry pipeline for use with position-only shading. In position-only shading, there are two geometry pipelines: a full geometry pipeline in geometry / fixed function pipeline 238, 231, and an additional geometry pipeline, the cull pipeline, that can be included in additional fixed function logic 238. In one embodiment, the cull pipeline is a fragmented version of the full geometry pipeline. The full pipeline and the cull pipeline can run different instances of the same application, with each instance having a separate context. Position-only shading can hide long cull runs of discarded triangles, allowing shading to complete faster in some cases. For example, in one embodiment, the cull pipeline logic in additional fixed function logic 238 can execute position shaders in parallel with the main application and can generally generate significant results faster than the full pipeline because the cull pipeline only fetches and shades position attributes of vertices without performing rasterization and rendering of pixels to the frame buffer. The cull pipeline can use the significant results generated to calculate visibility information for all triangles, regardless of whether they are culled or not. The full pipeline (which may be called a reconstructed pipeline in this example) can consume the visibility information, skip over culled triangles, and shade only the visible triangles that are ultimately passed to the rasterization phase.

[0036] In one embodiment, the additional fixed function logic 238 may also include machine learning acceleration logic, such as fixed function matrix multiplication logic, for implementations that include optimizations for machine learning training or inference.

[0037] Within each graphics sub-core 221A-221F is a set of execution resources that can be used to perform graphics, media, and computational processing in response to requests by the graphics pipeline, media pipeline, or shader programs. The graphics sub-cores 221A-221F include multiple EU arrays 222A-222F, 224A-224F, thread dispatch and inter-thread communication (TD / IC) logic 223A-223F, 3D (e.g., texture) samplers 225A-225F, media samplers 206A-206F, shader processors 227A-227F, and shared local memory (SLM) 228A-228F. Each EU array 222A-222F, 224A-224F includes multiple execution units, which are general-purpose graphics processing units capable of performing floating point and integer / fixed point logical operations in service of graphics, media, or computational processing, including graphics, media, or computational shader programs. The TD / IC logic 223A-223F performs local thread dispatch and thread control operations for the execution units in the sub-cores and facilitates communication between threads executing on the execution units of the sub-cores. The 3D samplers 225A-225F can read textures or other 3D graphics related data into memory. The 3D samplers can read texture data differently based on the configured sample state and texture format associated with a given texture. The media samplers 206A-206F can perform similar read operations based on the type and format associated with the media data. In one embodiment, each graphics sub-core 221A-221F can alternatively include an integrated 3D and media sampler. The threads executing on the execution units in each sub-core 221A-221F utilize a shared local memory 228A-228F in each sub-core to allow threads executing in a thread group to execute using a common pool of on-chip memory.

[0038] 2C illustrates a graphics processing unit (GPU) 239 that includes a dedicated set of graphics processing resources arranged into multi-core groups 240A-240N. Although details of only a single multi-core group 240A are presented, it will be understood that the other multi-core groups 240B-240N may be equipped with the same or similar sets of graphics processing resources.

[0039] As shown, multi-core group 240A may include a set of graphics cores 243, a set of tensor cores 244, and a set of ray tracing cores 245. Scheduler / dispatcher 241 schedules and dispatches graphics threads for execution to the various cores 243, 244, 245. A set of register files 242 store operand values ​​used by cores 243, 244, 245 when executing graphics threads. These include, for example, integer registers for storing integer values, floating point registers for storing floating point values, vector registers for storing packed data elements (integer and / or floating point data elements), and tile registers for storing tensor / matrix values. In one embodiment, the tile registers are implemented as a combined set of vector registers.

[0040] One or more combined level 1 (L1) cache and shared memory units 247 store graphics data, such as texture data, vertex data, pixel data, ray data, bounding volume data, etc., locally within each multicore group 240A. One or more texture units 247 may also be used to perform texturing operations, such as texture mapping and sampling. A level 2 (L2) cache 253, shared by all or a subset of the multicore groups 240A-240N, stores graphics data and / or instructions for multiple simultaneous graphics threads. As shown, the L2 cache 253 may be shared across multiple multicore groups 240A-240N. One or more memory controllers 248 couple the GPU 239 to memory 249, which may be system memory (e.g., DRAM) and / or dedicated graphics memory (e.g., GDDR6 memory).

[0041] Input / output (I / O) circuitry 250 couples GPU 239 to one or more I / O devices 252, such as a digital signal processor (DSP), a network controller, or a user input device. An on-chip interconnect may be used to couple I / O device 252 to GPU 239 and memory 249. One or more I / O memory management units (IOMMUs) 251 of I / O circuitry 250 directly couple I / O device 252 to system memory 249. In one embodiment, IOMMU 251 manages multiple sets of page tables to map virtual addresses to physical addresses in system memory 249. In this embodiment, I / O device 252, CPU 246, and GPU(s) 239 may share the same virtual address space.

[0042] In one embodiment, IOMMU 251 supports virtualization. In this case, IOMMU 251 manages a first set of page tables for mapping guest / graphics virtual addresses to guest / graphics physical addresses and a second set of page tables for mapping guest / graphics physical addresses to system / host physical addresses (e.g., in system memory 249). The base addresses of each of the first and second sets of page tables are stored in control registers and swapped out on context switches (e.g., to provide a new context with access to the associated set of page tables). Although not shown in FIG. 2C, each of cores 243, 244, 245 and / or multicore groups 240A-240N may include a translation lookaside buffer (TLB) for caching virtual guest to physical guest translations, physical guest to physical host translations, and virtual guest to physical host translations.

[0043] In one embodiment, CPU 246, GPU 239, and I / O devices 252 are integrated into a single semiconductor chip and / or chip package. The illustrated memory 249 may be integrated on the same chip or may be coupled to memory controller 248 via an off-chip interface. In one implementation, memory 249 includes GDDR6 memory that shares the same virtual address space as other physical system-level memory, although the underlying principles of the invention are not limited to this particular implementation.

[0044] In one embodiment, tensor cores 244 include multiple execution units specifically designed to perform matrix operations, which are fundamental computational processes used to perform deep learning operations. For example, simultaneous matrix multiplication operations can be used for training and inference of neural networks. Tensor cores 244 can perform matrix operations using a variety of operand precisions, including single-precision floating point (e.g., 32-bit), half-precision floating point (e.g., 16-bit), integer word (16-bit), byte (8-bit), and half-byte (4-bit). In one embodiment, the neural network implementation extracts features of each rendered scene and potentially combines details from multiple frames to construct a high-quality final image.

[0045] In a deep learning implementation, parallel matrix multiplication operations may be scheduled for execution on tensor cores 244. In particular, training a neural network requires a significant number of matrix dot product operations. To process the inner product formulation of N×N×N matrix multiplication, tensor cores 244 may include at least N dot product processing elements. Before the matrix multiplication begins, an entire matrix is ​​loaded into a tile register, and at least one column of a second matrix is ​​loaded each of the N cycles. In each cycle, N dot products are processed.

[0046] Matrix elements may be stored in different precisions depending on the particular implementation, including 16-bit words, 8-bit bytes (e.g., INT8), and 4-bit half-bytes (e.g., INT4). Different precision modes can be specified for tensor cores 244 to ensure that the most efficient precision is used for various workloads (e.g., inference workloads that can tolerate quantization to bytes and half-bytes, etc.).

[0047] In one embodiment, ray tracing core 245 accelerates ray tracing processing for both real-time ray tracing and non-real-time ray tracing implementations. In particular, ray tracing core 245 includes ray traversal / intersection circuitry for performing ray traversals using a bounding volume hierarchy (BVH) and identifying intersections between rays and primitives enclosed within the BVH volume. Ray tracing core 245 may also include circuitry for performing depth testing and culling (e.g., using a Z-buffer or similar construct). In one implementation, ray tracing core 245 performs traversal and intersection processing in coordination with image denoising techniques described herein, at least a portion of which may be executed on tensor core 244. For example, in one embodiment, tensor core 244 implements a deep learning neural network to denoise frames generated by ray tracing core 245. However, the CPU 246, graphics core 243, and / or ray tracing core 245 may also implement all or part of the denoising and / or deep learning algorithms.

[0048] Additionally, as discussed above, a distributed approach to denoising can be used, in which the GPU 239 is in a computing device that is coupled to other computing devices via a network or high speed interconnect. In this embodiment, the interconnected computing devices share neural network learning / training data to improve the speed at which the entire system learns to denoise different types of image frames and / or different graphics applications.

[0049] In one embodiment, the ray tracing core 245 handles all BVH traversals and ray primitive intersections, preventing the graphics core 243 from being overloaded with thousands of instructions per ray. In one embodiment, each ray tracing core 245 includes a first set of dedicated circuitry for performing bounding box tests (e.g., traversal operations) and a second set of dedicated circuitry for performing ray triangle intersection tests (e.g., intersecting rays are traversed). Thus, in one embodiment, the multi-core group 240A only needs to launch ray probes, and the ray tracing core 245 independently performs ray traversals and intersections and returns hit data (e.g., hit, no hit, multiple hits, etc.) to the thread context. The other cores 243, 244 are freed to perform other graphics or computational work while the ray tracing core 245 performs traversal and intersection processing.

[0050] In one embodiment, each ray tracing core 245 includes a traversal unit that performs BVH test operations and an intersection unit that performs ray-primitive intersection tests. The intersection unit generates a "hit," "no hit," or "multiple hits" response and provides the response to the appropriate thread. During traversal and intersection processing, the execution resources of other cores (e.g., graphics core 243 and tensor core 244) are freed to perform other forms of graphics work.

[0051] In one particular embodiment described below, a hybrid rasterization / ray tracing approach is used in which work is distributed between the graphics core 243 and the ray tracing core 245.

[0052] In one embodiment, the ray tracing core 245 (and / or other cores 243, 244) includes hardware support for a ray tracing instruction set, such as Microsoft's DirectX Ray Tracing (DXR), which includes dispatch ray commands as well as ray generation, nearest hit, any hit, and miss shaders (each object can be assigned its own set of shaders and textures). Another ray tracing platform that may be supported by the ray tracing core 245, graphics core 243, and tensor core 244 is Vulkan 1.1.85. However, it should be noted that the underlying principles of the present invention are not limited to any particular ray tracing ISA.

[0053] In general, the various cores 245, 244, 243 may support a ray tracing instruction set that includes instructions / functions for ray generation, nearest hit, any hit, ray-primitive intersection, per-primitive and hierarchical bounding box construction, misses, visits, and exceptions. More specifically, one embodiment includes ray tracing instructions for performing the following functions:

[0054] ray generation Ray generation instructions can be executed for each pixel, sample, or other user-defined work allocation.

[0055] Nearest Hits A nearest hit instruction may be executed to find the nearest intersection point between a ray and a primitive in a scene.

[0056] any hit Any hit command identifies multiple intersections between the ray and primitives in the scene, and potentially identifies a new closest intersection point.

[0057] Intersection The intersection commands perform ray-primitive intersection tests and output the results.

[0058] Per-primitive bounding box constructionThis instruction builds a bounding box around a given primitive or group of primitives (eg, when building a new BVH or other acceleration data structure).

[0059] Miss Indicates that the ray does not hit any geometry in the scene, or a specified region of the scene.

[0060] visit Shows the children volumes that the ray traverses.

[0061] exception Contains different types of exception handlers (e.g., called for different error conditions).

[0062] 2D is a block diagram of a general purpose graphics processing unit (GPGPU) 270 that may be configured as a graphics processor and / or computational accelerator, according to embodiments described herein. GPGPU 270 may be interconnected with a host processor (e.g., one or more CPUs 246) and memories 271, 272 via one or more system and / or memory buses. In one embodiment, memory 271 is a system memory that may be shared with one or more CPUs 246, and memory 272 is a device memory dedicated to GPGPU 270. In one embodiment, components within GPGPU 270 and device memory 272 may be mapped to memory addresses accessible by one or more CPUs 246. Access to memories 271 and 272 may be facilitated via memory controller 268. In one embodiment, memory controller 268 may include an internal direct memory access (DMA) controller 269, or may include logic for performing operations otherwise performed by a DMA controller.

[0063] GPGPU 270 includes multiple cache memories, including L2 cache 253, L1 cache 254, instruction cache 255, and shared memory 256, at least some of which may be partitioned as cache memories. GPGPU 270 also includes multiple computation units 260A-260N. Each computation unit 260A-260N includes a set of vector registers 261, scalar registers 262, vector logic unit 263, and scalar logic unit 264. Computation units 260A-260N may also include local shared memory 265 and program counter 266. Computation units 260A-260N may be coupled with constant cache 267, which may be used to store constant data, which is data that does not change during execution of a kernel or shader program executing on GPGPU 270. In one embodiment, constant cache 267 is a scalar data cache, and cached data may be fetched directly into scalar registers 262.

[0064] During operation, one or more CPUs 246 may write commands to registers or memory within GPGPU 270 that are mapped into an accessible address space. Command processor 257 may read commands from registers or memory and determine how those commands are to be processed within GPGPU 270. Thread dispatcher 258 may then be used to dispatch threads to computation units 260A-260N for execution of those commands. Each computation unit 260A-260N may execute threads independently of the other computation units. Additionally, each computation unit 260A-260N may be independently configured for conditional computation and may conditionally output the results of the computation to memory. Command processor 257 may interrupt one or more CPUs 246 upon completion of a submitted command.

[0065] Figures 3A-3C show block diagrams of additional graphics processor and computational accelerator architectures provided by embodiments described herein. Elements of Figures 3A-3C having the same reference numbers (or names) as elements of any other figure herein can operate or function in any manner similar to, but not limited to, as described elsewhere herein.

[0066] 3A is a block diagram of a graphics processor 300, which may be a separate graphics processing unit or may be a graphics processor integrated with multiple processing cores or other semiconductor devices such as, but not limited to, memory devices or network interfaces. In some embodiments, the graphics processor communicates with registers on the graphics processor and commands placed in the processor memory via a memory-mapped I / O interface. In some embodiments, the graphics processor 300 includes a memory interface 314 for accessing memory. The memory interface 314 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or system memory.

[0067] In some embodiments, the graphics processor 300 also includes a display controller 302 that drives display output data to a display device 318. The display controller 302 includes hardware for one or more overlay planes for the display and composition of multiple layers of video or user interface elements. The display device 318 can be an internal or external display device. In one embodiment, the display device 318 is a head-mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. In some embodiments, graphics processor 300 includes a video codec engine 306 that encodes, decodes, or transcodes media to, from, or between one or more media encoding formats, including but not limited to Motion Picture Experts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formats such as H.264 / MPEG-4 AVC, H.265 / HEVC, Alliance for Open Media (AOMedia) VP8, VP9, ​​as well as Society of Motion Picture & Television Engineers (SMPTE) 421 M / VC-1, and Joint Photographic Experts Group (JPEG) formats such as JPEG, and Motion JPEG (MJPEG) formats.

[0068] In some embodiments, graphics processor 300 includes a block image transfer (BLIT) engine 304 for performing two-dimensional (2D) rasterizer processing, including, for example, bit-boundary block transfer. However, in one embodiment, 2D graphics processing is performed using one or more components of a graphics processing engine (GPE) 310. In some embodiments, GPE 310 is a computational engine for performing graphics processing, including three-dimensional (3D) graphics processing and media processing.

[0069] In some embodiments, GPE 310 includes a 3D pipeline 312 for performing 3D processing such as rendering three-dimensional images and scenes using processing functions that operate on 3D primitive shapes (e.g., rectangles, triangles, etc.). 3D pipeline 312 includes programmable fixed-function elements that perform various tasks within the elements and / or spawn execution threads into 3D / media subsystem 315. While 3D pipeline 312 can be used to perform media processing, embodiments of GPE 310 also include a media pipeline 316 that is used specifically to perform media processing such as video post-processing and image enhancement.

[0070] In some embodiments, the media pipeline 316 includes fixed function or programmable logic units that perform one or more specialized media processing, such as video decode acceleration, video deinterlacing, and video encode acceleration, in place of or on behalf of the video codec engine 306. In some embodiments, the media pipeline 316 further includes a thread spawning unit that spawns threads for execution in the 3D / media subsystem 315. The spawned threads perform media processing calculations on one or more graphics execution units included in the 3D / media subsystem 315.

[0071] In some embodiments, the 3D / Media subsystem 315 includes logic for executing threads generated by the 3D pipeline 312 and the media pipeline 316. In one embodiment, the pipelines send thread execution requests to the 3D / Media subsystem 315, which includes thread dispatch logic for arbitrating and dispatching the various requests to available thread execution resources. The execution resources include an array of graphics execution units that process the 3D and media threads. In some embodiments, the 3D / Media subsystem 315 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory, including registers and addressable memory, for sharing data between threads and storing output data.

[0072] FIG. 3B illustrates a graphics processor 320 having a tiled architecture, according to an embodiment described herein. In one embodiment, the graphics processor 320 includes a graphics processing engine cluster 322 having multiple instances of the graphics processing engine 310 of FIG. 3A in the graphics engine tiles 310A-310D. Each of the graphics engine tiles 310A-310D can be interconnected via a set of tile interconnects 323A-323F. Each of the graphics engine tiles 310A-310D can also be connected to a memory module or memory device 326A-326D via memory interconnects 325A-325D. The memory devices 326A-326D can use any graphics memory technology. For example, the memory devices 326A-326D can be graphics double data rate (GDDR) memory. In one embodiment, the memory devices 326A-326D are high bandwidth memory (HBM) modules that can be on-die with the respective graphics engine tiles 310A-310D. In one embodiment, memory devices 326A-326D are stacked memory devices that can be stacked on top of each of the graphics engine tiles 310A-310D. In one embodiment, each graphics engine tile 310A-310D and associated memory 326A-326D resides on a separate chiplet that is coupled to a base die or base substrate, as described in further detail in Figures 11B-11D.

[0073] The graphics processing engine cluster 322 may be connected to an on-chip or on-package fabric interconnect 324. The fabric interconnect 324 allows communication between the graphics engine tiles 310A-310D and components such as the video codec 306 and one or more copy engines 304. The copy engines 304 may be used to move data between the memory devices 326A-326D and memory external to the graphics processor 320 (e.g., system memory). The fabric interconnect 324 may also be used to interconnect the graphics engine tiles 310A-310D. The graphics processor 320 optionally includes a display controller 302 that allows connection to an external display device 318. The graphics processor may also be configured as a graphics or computation accelerator. In an accelerator configuration, the display controller 302 and the display device 318 may be omitted.

[0074] Graphics processor 320 may be connected to a host system via host interface 328. Host interface 328 allows communication between graphics processor 320, system memory, and / or other system components. Host interface 328 may be, for example, a PCI Express bus or another type of host system interface.

[0075] FIG. 3C illustrates a computation accelerator 330 according to an embodiment described herein. The computation accelerator 330 may include architectural similarities to the graphics processor 320 of FIG. 3B and is optimized for computation acceleration. The computation engine cluster 332 may include a set of computation engine tiles 340A-340D that include execution logic optimized for parallel or vector-based general-purpose computation processing. In some embodiments, the computation engine tiles 340A-340D do not include fixed-function graphics processing logic, but in one embodiment, one or more of the computation engine tiles 340A-340D may include logic to perform media acceleration. The computation engine tiles 340A-340D may be connected to memories 326A-326D via memory interconnects 325A-325D. The memories 326A-326D and memory interconnects 325A-325D may be of similar technology to the graphics processor 320 or may be different. The graphics computation engine tiles 340A-340D may also be interconnected via a set of tile interconnects 323A-323F, which may connect to and / or be interconnected by the fabric interconnect 324. In one embodiment, the computation accelerator 330 includes a large L3 cache 336, which may be configured as a device-wide cache. The computation accelerator 330 may also be connected to a host processor and memory via a host interface 328, in a manner similar to the graphics processor 320 of FIG. 3B.

[0076] Graphics Processing Engine

[0077] FIG. 4 is a block diagram of a graphics processing engine 410 of a graphics processor according to some embodiments. In one embodiment, the graphics processing engine (GPE) 410 is a version of the GPE 310 shown in FIG. 3A and may represent the graphics engine tiles 310A-310D of FIG. 3B. Elements of FIG. 4 having the same reference numbers (or names) as elements of other figures herein may operate or function in a similar manner as described elsewhere herein, but are not limited to such. For example, the 3D pipeline 312 and media pipeline 316 of FIG. 3A are shown. The media pipeline 316 is optional in some embodiments of the GPE 410 and may not be explicitly included within the GPE 410. For example, in at least one embodiment, a separate media and / or image processor is coupled to the GPE 410.

[0078] In some embodiments, the GPE 410 is coupled to or includes a command streamer 403 that provides a command stream to the 3D pipeline 312 and / or the media pipeline 316. In some embodiments, the command streamer 403 is coupled to a memory, which may be a system memory or one or more of an internal cache memory and a shared cache memory. In some embodiments, the command streamer 403 receives commands from the memory and sends the commands to the 3D pipeline 312 and / or the media pipeline 316. The commands are instructions fetched from a ring buffer that stores commands for the 3D pipeline 312 and the media pipeline 316. In one embodiment, the ring buffer may further include a batch command buffer that stores a batch of multiple commands. Commands for the 3D pipeline 312 may also include references to data stored in memory, such as, but not limited to, vertex and geometry data for the 3D pipeline 312 and / or image data and memory objects for the media pipeline 316. The 3D pipeline 312 and the media pipeline 316 process commands and data by performing operations through logic within the respective pipelines or by dispatching one or more execution threads to the graphics core array 414. In one embodiment, the graphics core array 414 includes one or more blocks of graphics cores (e.g., graphics core(s) 415A, graphics core(s) 415B), each block including one or more graphics cores. Each graphics core includes a set of graphics execution resources, such as general-purpose and graphics-specific execution logic for performing graphics and computational processing, as well as fixed-function texture processing and / or machine learning and artificial intelligence acceleration logic.

[0079] In various embodiments, the 3D pipeline 312 may include fixed function and programmable logic to process one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 414. The graphics core array 414 provides a unified block of execution resources for use in processing these shader programs. General purpose execution logic (e.g., execution units) within the graphics cores 415A-414B of the graphics core array 414 includes support for a variety of 3D API shader languages ​​and can execute multiple concurrent threads of execution associated with multiple shaders.

[0080] In some embodiments, graphics core array 414 includes execution logic to perform media functions such as video and / or image processing. In one embodiment, the execution units include general purpose logic that is programmable to perform parallel general purpose computing operations in addition to graphics processing operations. The general purpose logic can perform processing operations in parallel or in cooperation with general purpose logic in processor core 107 of FIG. 1 or cores 202A-202N of FIG. 2A.

[0081] Output data generated by threads executing on the graphics core array 414 may output data to memory in a unified return buffer (URB) 418. The URB 418 may store data for multiple threads. In some embodiments, the URB 418 may be used to transmit data between different threads executing on the graphics core array 414. In some embodiments, the URB 418 may further be used for synchronization between threads on the graphics core array and fixed function logic in the shared function logic 420.

[0082] In some embodiments, graphics core array 414 is scalable such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance levels of GPE 410. In one embodiment, execution resources are dynamically scalable, allowing execution resources to be enabled or disabled as needed.

[0083] The graphics core array 414 couples to shared function logic 420, which includes multiple resources shared among the graphics cores in the graphics core array. The shared functions in the shared function logic 420 are hardware logic units that provide specialized auxiliary functions to the graphics core array 414. In various embodiments, the shared function logic 420 includes, but is not limited to, sampler 421, math 422, and inter-thread communication (ITC) 423 logic. Additionally, some embodiments implement one or more caches 425 in the shared function logic 420.

[0084] Shared functions are implemented at least when the demand for a given specialized function is insufficient for inclusion within the graphics core array 414. Instead, a single instantiation of that specialized function is implemented as a standalone entity within the shared function logic 420 and shared among the execution resources within the graphics core array 414. The exact set of functions shared among and included within the graphics core array 414 varies by embodiment. In some embodiments, certain shared functions within the shared function logic 420 that are used extensively by the graphics core array 414 may be included within the shared function logic 416 within the graphics core array 414. In various embodiments, the shared function logic 416 within the graphics core array 414 may include some or all of the logic within the shared function logic 420. In one embodiment, all of the logical elements within the shared function logic 420 may be duplicated within the shared function logic 416 of the graphics core array 414. In one embodiment, the shared function logic 420 is omitted in favor of the shared function logic 416 within the graphics core array 414.

[0085] Execution Unit

[0086] 5A-5B illustrate thread execution logic 500 including an array of processing elements for use in a graphics processor core, according to embodiments described herein. Elements of FIG. 5A-5B having the same reference numbers (or names) as elements of other figures herein may operate or function in a similar manner as described elsewhere herein, but are not limited to such. FIG. 5A-5B illustrates an overview of thread execution logic 500 that may represent the hardware logic shown in each of sub-cores 221A-221F of FIG. 2B. FIG. 5A illustrates an execution unit in a general-purpose graphics processor, and FIG. 5B illustrates an execution unit that may be used in a computational accelerator.

[0087] 5A, in some embodiments, thread execution logic 500 includes a shader processor 502, a thread dispatcher 504, an instruction cache 506, a scalable execution unit array including multiple execution units 508A-508N, a sampler 510, a shared local memory 511, a data cache 512, and a data port 514. In one embodiment, the scalable execution unit array can be dynamically scalable by enabling or disabling one or more execution units (e.g., any of execution units 508A, 508B, 508C, 508D through 508N-1, and 508N) based on the computational requirements of a workload. In one embodiment, the included components are interconnected via an interconnect fabric that links each component. In some embodiments, the thread execution logic 500 includes one or more connections to memory, such as system memory or cache memory, via one or more of an instruction cache 506, a data port 514, a sampler 510, and execution units 508A-508N. In some embodiments, each execution unit (e.g., 508A) is a standalone programmable general-purpose computational unit capable of executing multiple simultaneous hardware threads, processing multiple data elements in parallel for each thread. In various embodiments, the array of execution units 508A-508N is scalable to include any number of individual execution units.

[0088] In some embodiments, execution units 508A-508N are primarily used to execute shader programs. Shader processor 502 can process various shader programs and dispatch execution threads associated with the shader programs via thread dispatcher 504. In one embodiment, the thread dispatcher includes logic to arbitrate thread initiation requests from the graphics and media pipelines and instantiate the requested threads on one or more execution units within execution units 508A-508N. For example, a geometry pipeline can dispatch vertex, tessellation, or geometry shaders to thread execution logic for processing. In some embodiments, thread dispatcher 504 can also handle run-time thread creation requests from running shader programs.

[0089] In some embodiments, the execution units 508A-508N support an instruction set that includes native support for many standard 3D graphics shader instructions, allowing shader programs from graphics libraries (e.g., Direct3D and OpenGL) to be executed with minimal translation. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel operations (e.g., pixel shaders, fragment shaders), and general-purpose operations (e.g., compute shaders and media shaders). Each of the execution units 508A-508N is capable of multi-issue single instruction multiple data (SIMD) execution, allowing for multi-threaded operation to enable an efficient execution environment in the face of longer latency memory accesses. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread state. Execution is multi-issue per clock into a pipeline capable of integer, single and double precision floating point operations, SIMD branch functions, logical operations, transcendental operations, and a variety of other operations. While waiting for data from memory or one of the shared functions, dependency logic within the execution units 508A-508N puts the waiting thread to sleep until the requested data is returned. While the waiting thread is asleep, hardware resources may be devoted to processing other threads. For example, during a delay associated with vertex shader processing, the execution unit may process another type of shader program, including a pixel shader, a fragment shader, or a different vertex shader. Various embodiments may apply to execution use with the use of single instruction multithreading (SIMT) as an alternative to or in addition to the use of SIMD. Reference to a SIMD core or processing may also apply to SIMT or to SIMD in combination with SIMT.

[0090] Each execution unit of execution units 508A-508N operates on an array of data elements. The number of data elements is the "execution size", or the number of channels of an instruction. An execution channel is a logical unit of execution for accessing data elements, masking, and flow control within an instruction. The number of channels may be independent of the number of physical arithmetic logic units (ALUs) or floating point units (FPUs) of a particular graphics processor. In some embodiments, execution units 508A-508N support integer and floating point data types.

[0091] The execution unit instruction set includes SIMD instructions. Various data elements can be stored in registers as packed data types, and the execution unit processes the various elements based on the data size of the elements. For example, when manipulating a 256-bit wide vector, the 256 bits of the vector are stored in a register, and the execution unit manipulates the vector as four individual 54-bit packed data elements (quadword (QW) sized data elements), eight individual 32-bit packed data elements (doubleword (DW) sized data elements), sixteen individual 16-bit packed data elements (word (W) sized data elements), or thirty-two individual 8-bit data elements (byte (B) sized data elements). However, different vector widths and register sizes are possible.

[0092] In one embodiment, one or more execution units can be combined into fused execution units 509A-509N with thread control logic (507A-507N) common to the fused EUs. Multiple EUs can be fused into an EU group. Each EU in a fused EU group can be configured to execute a separate SIMD hardware thread. The number of EUs in a fused EU group can vary depending on the embodiment. Furthermore, various SIMD widths can be executed per EU, including but not limited to SIMD8, SIMD16, and SIMD32. Each fused graphics execution unit 509A-509N includes at least two execution units. For example, fused execution unit 509A includes a first EU 508A, a second EU 508B, and thread control logic 507A common to the first EU 508A and the second EU 508B. The thread control logic 507A controls the threads executed in the fused graphic execution unit 509A, and enables each EU in the fused execution units 509A-509N to execute using a common instruction pointer register.

[0093] One or more internal instruction caches (e.g., 506) are included in the thread execution logic 500 for caching thread instructions for the execution units. In some embodiments, one or more data caches (e.g., 512) are included for caching thread data during thread execution. Threads executing on the execution logic 500 may also store explicitly managed data in shared local memory 511. In some embodiments, a sampler 510 is included to provide texture sampling for 3D processing and media sampling for media processing. In some embodiments, the sampler 510 includes specialized texture or media sampling functionality for processing texture or media data during the sampling process before providing the sampled data to the execution units.

[0094] During execution, the graphics and media pipelines send thread start requests to the thread execution logic 500 via thread creation and dispatch logic. Once a group of geometric objects has been processed and rasterized into pixel data, pixel processor logic (such as pixel shader logic, fragment shader logic, etc.) in the shader processor 502 is invoked to further compute output information and write the results to an output surface (such as a color buffer, depth buffer, stencil buffer, etc.). In some embodiments, a pixel shader or fragment shader computes values ​​for various vertex attributes that are interpolated across the rasterized objects. In some embodiments, the pixel processor logic in the shader processor 502 then executes pixel or fragment shader programs provided by an application programming interface (API). To execute the shader programs, the shader processor 502 dispatches threads to the execution units (e.g., 508A) via the thread dispatcher 504. In some embodiments, the shader processor 502 uses texture sampling logic in the sampler 510 to access texture data from texture maps stored in memory. Arithmetic operations on the texture data and the input geometry data compute pixel color data for each geometry fragment or discard one or more pixels from further processing.

[0095] In some embodiments, the data port 514 provides a memory access mechanism for the thread execution logic 500 to output processed data to memory for further processing in the graphics processor output pipeline. In some embodiments, the data port 514 includes or is coupled to one or more cache memories (e.g., data cache 512) for caching data for memory access via the data port.

[0096] In one embodiment, the execution logic 500 may also include a ray tracer 505 that may provide ray tracing acceleration functionality. The ray tracer 505 may support a ray tracing instruction set that includes instructions / functions for ray generation. The ray tracing instruction set may be similar to or different from the ray tracing instruction set supported by the ray tracing core 245 of FIG. 2C.

[0097] 5B illustrates exemplary internal details of execution unit 508, according to an embodiment. Graphics execution unit 508 may include an instruction fetch unit 537, a general purpose register file array (GRF) 524, an architectural register file array (ARF) 526, a thread arbiter 522, a send unit 530, a branch unit 532, a set of SIMD floating point units (FPUs) 534, and, in one embodiment, a set of dedicated integer SIMD ALUs 535. GRF 524 and ARF 526 include a general purpose register file and a set of architectural register files associated with each concurrent hardware thread that may be active in graphics execution unit 508. In one embodiment, per-thread architectural state is maintained in ARF 526, while data used during thread execution is stored in GRF 524. The execution state of each thread, including each thread's instruction pointer, may be held in thread-specific registers in ARF 526.

[0098] In one embodiment, the graphics execution unit 508 has an architecture that is a combination of simultaneous multithreading (SMT) and fine-grained interleaved multithreading (IMT). The architecture has a modular structure that can be tuned at design time based on the target number of concurrently executing threads and the number of registers per execution unit, and the resources of the execution unit are divided across the logic used to execute multiple concurrent threads. The number of logical threads that can be executed by the graphics execution unit 508 is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread.

[0099] In one embodiment, the graphics execution unit 508 can issue multiple instructions simultaneously, each of which can be a different instruction. The thread arbiter 522 of the graphics execution unit thread 508 can dispatch the instruction to one of the send unit 530, the branch unit 532, or the SIMD FPU 534 for execution. Each execution thread can access 128 general purpose registers in the GRF 524, each of which can store 32 bytes and can be accessed as a SIMD 8-element vector of 32-bit data elements. In one embodiment, each execution unit thread has access to 4K bytes in the GRF 524, although the embodiment is not so limited and more or less register resources can be provided in other embodiments. In one embodiment, the graphics execution unit 508 is divided into seven hardware threads that can independently perform computational operations, although the number of threads per execution unit can also vary depending on the embodiment. For example, in one embodiment, a maximum of 16 hardware threads are supported. In an embodiment where the seven threads can access 4K bytes, the GRF 524 can store a total of 28K bytes. With 16 threads each having access to 4K bytes, the GRF524 can store a total of 64K bytes. In flexible addressing mode, registers can be addressed together to effectively build wider registers, or to represent strided rectangular block data structures.

[0100] In one embodiment, memory operations, sampler operations, and other longer latency system communications are dispatched via "send" instructions executed by a message passing send unit 530. In one embodiment, branch instructions are dispatched to a dedicated branch unit 532 to facilitate SIMD divergence and eventual convergence.

[0101] In one embodiment, the graphics execution unit 508 includes one or more SIMD floating point units (FPUs) 534 to perform floating point operations. In one embodiment, the FPUs 534 also support integer calculations. In one embodiment, the FPUs 534 can SIMD execute up to M 32-bit floating point (or integer) operations, or SIMD execute up to 2M 16-bit integer or 16-bit floating point operations. In one embodiment, at least one of the FPUs provides extended math capabilities supporting high throughput transcendental math functions and double precision 54-bit floating point. In some embodiments, there is also a set of 8-bit integer SIMD ALUs 535, which can be specifically optimized to perform operations related to machine learning calculations.

[0102] In one embodiment, an array of multiple instances of the graphics execution unit 508 can be instantiated into a graphics sub-core group (e.g., a sub-slices). For scalability, the multiplication architect can select the exact number of execution units per sub-core group. In one embodiment, the execution unit 508 can execute instructions across multiple execution channels. In a further embodiment, each thread executing on the graphics execution unit 508 executes on a different channel.

[0103] FIG. 6 illustrates an additional execution unit 600 according to one embodiment. The execution unit 600 may be, for example but not limited to, a compute-optimized execution unit for use in the compute engine tiles 340A-340D as in FIG. 3C. A variation of the execution unit 600 may be used in the graphics engine tiles 310A-310D as in FIG. 3B. In one embodiment, the execution unit 600 includes a thread control unit 601, a thread state unit 602, an instruction fetch / prefetch unit 603, and an instruction decode unit 604. The execution unit 600 further includes a register file 606 that stores registers that can be allocated to hardware threads within the execution unit. The execution unit 600 further includes a send unit 607 and a branch unit 608. In one embodiment, the send unit 607 and the branch unit 608 may operate similarly to the send unit 530 and the branch unit 532 of the graphics execution unit 508 of FIG. 5B.

[0104] The execution unit 600 also includes a computation unit 610 that includes multiple different types of functional units. In one embodiment, the computation unit 610 includes an ALU unit 611 that includes an array of arithmetic logic units. The ALU unit 611 can be configured to perform 64-bit, 32-bit, and 16-bit integer and floating point operations. The integer and floating point operations can be performed simultaneously. The computation unit 610 can also include a systolic array 612 and a math unit 613. The systolic array 612 includes a W-wide and D-deep network of data processing units that can be used to perform vector or other data parallel processing in a systolic manner. In one embodiment, the systolic array 612 can be configured to perform matrix operations such as matrix dot product operations. In one embodiment, the systolic array 612 supports 8-bit and 4-bit integer operations as well as 16-bit floating point operations. In one embodiment, the systolic array 612 can be configured to accelerate machine learning operations. In such an embodiment, systolic array 612 may be configured to support the bfloat 16-bit floating point format. In one embodiment, math unit 613 may be included to perform a particular subset of math operations in a more efficient and lower power manner than ALU unit 611. Math unit 613 may include a variation of math logic that may be found in the shared function logic of a graphics processing engine provided by other embodiments (e.g., math logic 422 of shared function logic 420 of FIG. 4). In one embodiment, math unit 613 may be configured to perform 32-bit and 64-bit floating point operations.

[0105] The thread control unit 601 includes logic to control the execution of threads in the execution units. The thread control unit 601 may include thread arbitration logic to start, stop, and pre-empt (pre-empt) the execution of threads in the execution units 600. The thread state unit 602 may be used to store thread states for threads assigned to execute in the execution units 600. Storing thread states in the execution units 600 allows for quick pre-emption (pre-emption) of threads when they become blocked or idle. The instruction fetch / pre-fetch unit 603 may fetch instructions from an instruction cache of a higher level of execution logic (e.g., instruction cache 506 as in FIG. 5A). The instruction fetch / pre-fetch unit 603 may also issue pre-fetch requests for instructions to be loaded into the instruction cache based on analysis of currently executing threads. The instruction decode unit 604 may be used to decode instructions to be executed by the computation units. In one embodiment, the instruction decode unit 604 may be used as a secondary decoder to decode complex instructions into constituent micro-operations.

[0106] The execution unit 600 further includes a register file 606 that can be used by hardware threads executing on the execution unit 600. The registers in the register file 606 can be divided across logic used to execute multiple simultaneous threads in the compute units 610 of the execution unit 600. The number of logical threads that can be executed by the graphics execution unit 600 is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread. The size of the register file 606 can vary between embodiments based on the number of hardware threads supported. In one embodiment, register renaming can be used to dynamically assign registers to hardware threads.

[0107] 7 is a block diagram illustrating a graphics processor instruction format 700 according to some embodiments. In one or more embodiments, a graphics processor execution unit supports an instruction set having instructions in multiple formats. Solid lined boxes indicate components that are typically included in the execution unit's instructions, while dashed lines indicate optional components or components that are only included in a subset of the instructions. In some embodiments, the instruction format 700 described and illustrated is a macro-instruction, in that it is an instruction that is provided to the execution unit as opposed to a micro-operation that results from instruction decode once the instruction is processed.

[0108] In some embodiments, the graphics processor execution units natively support instructions in a 128-bit instruction format 710. A 64-bit compacted instruction format 730 is available for some instructions based on the selected instruction, instruction options, and number of operands. The native 128-bit instruction format 710 provides access to all instruction options, but some options and operations are restricted to the 64-bit format 730. The native instructions available in the 64-bit format 730 vary depending on the embodiment. In some embodiments, the instructions are partially compressed using a set of index values ​​in an index field 713. The execution unit hardware looks up a set of compression tables based on the index values, and uses the output of the compression tables to reconstruct the native instruction into the 128-bit instruction format 710. Other sizes and formats of instructions can be used.

[0109] For each format, the instruction opcode 712 specifies the operation that the execution unit will perform. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs an add operation simultaneously across each color channel representing a texture or image element. By default, the execution unit executes each instruction across all data channels of an operand. In some embodiments, the instruction control field 714 allows control over certain execution options such as channel selection (e.g., prediction) and data channel order (e.g., swizzle). For instructions in the 128-bit instruction format 710, the execution size field 716 limits the number of data channels that are executed in parallel. In some embodiments, the execution size field 716 is not available for use with the 64-bit compressed instruction format 730.

[0110] Some execution unit instructions have up to three operands, including two source operands, src0 720, src1 722, and one destination 718. In some embodiments, the execution units support dual destination instructions where one of the destinations is implicit. Data manipulation instructions may have a third source operand (e.g., SRC2 724), and the instruction opcode 712 determines the number of source operands. The last source operand of an instruction may be an immediate value (e.g., hard-coded) passed with the instruction.

[0111] In some embodiments, the 128-bit instruction format 710 includes an access / address mode field 726 that specifies, for example, whether a direct register addressing mode or an indirect register addressing mode is used. When using the direct register addressing mode, the register addresses of one or more operands are provided directly by bits of the instruction.

[0112] In some embodiments, the 128-bit instruction format 710 includes an access / address mode field 726 that specifies the address mode and / or access mode of the instruction. In one embodiment, the access mode is used to define the data access alignment of the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, where the byte alignment of the access mode determines the access alignment of the instruction operands. For example, in a first mode, the instruction can use byte-aligned addressing for source and destination operands, and in a second mode, the instruction can use 16-byte aligned addressing for all source and destination operands.

[0113] In one embodiment, the address mode portion of the access / address mode field 726 determines whether the instruction uses direct or indirect addressing. When using the direct register addressing mode, bits of the instruction directly provide the register address of one or more operands. When using the indirect register addressing mode, the register address of one or more operands can be calculated based on the address register value and the address immediate field of the instruction.

[0114] In some embodiments, instructions are grouped based on a bit field of the opcode 712 to simplify opcode decode 740. In the case of an 8-bit opcode, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The exact opcode groupings shown are merely examples. In some embodiments, the move and logical opcode group 742 includes data movement and logical instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logical group 742 shares the five most significant bits (MSBs), with move (mov) instructions being of the form 0000xxxb and logical instructions being of the form 0001xxxb. The flow control instruction group 744 (e.g., call, jump (jmp)) includes instructions of the form 0010xxxb (e.g., 0x20). Other instruction group 746 includes a mix of instructions, including synchronization instructions (e.g., wait, send) of the form 0011xxxb (e.g., 0x30). The parallel math instruction group 748 includes component-related arithmetic instructions (e.g., add, multiply (mul)) in the format of 0100xxxb (e.g., 0x40). The parallel math group 748 performs arithmetic operations in parallel across data channels. The vector math group 750 includes arithmetic instructions (e.g., dp4) in the format of 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic such as dot product calculations on vector operands. The illustrated opcode decode 740, in one embodiment, can be used to determine which portion of the execution units to use to execute the decoded instruction. For example, some instructions may be designated as systolic instructions to be executed by a systolic array. Other instructions, such as ray tracing instructions (not shown), can be routed to a ray tracing core or ray tracing logic within a slice or partition of the execution logic.

[0115] Graphics Pipeline

[0116] Figure 8 is a block diagram of another embodiment of a graphics processor 800. Elements of Figure 8 having the same reference numbers (or names) as elements of other figures herein may operate or function similarly to, but are not limited to, those described elsewhere herein.

[0117] In some embodiments, graphics processor 800 includes a geometry pipeline 820, a media pipeline 830, a display engine 840, thread execution logic 850, and a rendering output pipeline 870. In some embodiments, graphics processor 800 is a graphics processor in a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or via commands issued to graphics processor 800 via a ring interconnect 802. In some embodiments, ring interconnect 802 couples graphics processor 800 to other processing components, such as other graphics processors or general-purpose processors. Commands from ring interconnect 802 are interpreted by command streamer 803, which provides instructions to individual components of geometry pipeline 820 or media pipeline 830.

[0118] In some embodiments, command streamer 803 directs the operation of vertex fetcher 805, which reads vertex data from memory and executes vertex processing commands provided by command streamer 803. In some embodiments, vertex fetcher 805 provides the vertex data to vertex shader 807, which performs coordinate space transformations and lighting operations on each vertex. In some embodiments, vertex fetcher 805 and vertex shader 807 execute the vertex processing instructions by dispatching execution threads to execution units 852A-852B via thread dispatcher 831.

[0119] In some embodiments, the execution units 852A-852B are an array of vector processors with an instruction set for performing graphics and media processing. In some embodiments, the execution units 852A-852B have an associated L1 cache 851 that is local to each array or shared between the arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

[0120] In some embodiments, the geometry pipeline 820 includes a tessellation component that performs hardware accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader 811 configures the tessellation operations. A programmable domain shader 817 provides back-end evaluation of the tessellation output. A tessellator 813 operates at the direction of the hull shader 811 and includes special purpose logic that generates a set of detailed geometric objects based on a coarse geometric model provided as input to the geometry pipeline 820. In some embodiments, the tessellation components (e.g., hull shader 811, tessellator 813, domain shader 817) can be bypassed when tessellation is not used.

[0121] In some embodiments, a complete geometric object can be processed by the geometry shader 819 via one or more threads dispatched to the execution units 852A-852B, or can proceed directly to the clipper 829. In some embodiments, the geometry shader operates on entire geometric objects, rather than vertices or patches of vertices like previous stages of the graphics pipeline. The geometry shader 819 receives input from the vertex shader 807 when tessellation is disabled. In some embodiments, the geometry shader 819 is programmable by the geometry shader program to perform geometry tessellation when the tessellation unit is disabled.

[0122] Prior to rasterization, a clipper 829 processes the vertex data. The clipper 829 can be a fixed-function clipper or a programmable clipper with clipping and geometry shader functions. In some embodiments, a rasterizer and depth test component 873 of the rendering output pipeline 870 dispatches pixel shaders to convert geometric objects into per-pixel representations. In some embodiments, pixel shader logic is included in the thread execution logic 850. In some embodiments, an application can bypass the rasterizer and depth test component 873 and access non-rasterized vertex data via the stream-out unit 823.

[0123] Graphics processor 800 has an interconnect bus, interconnect fabric, or some other interconnect mechanism that allows data and message passing between major components of the processor. In some embodiments, execution units 852A-852B and associated logic units (e.g., L1 cache 851, sampler 854, texture cache 858, etc.) interconnect via data port 856 to perform memory accesses and communicate with the processor's rendering output pipeline components. In some embodiments, sampler 854, caches 851, 858, and execution units 852A-852B each have a separate memory access path. In one embodiment, texture cache 858 may also be configured as a sampler cache.

[0124] In some embodiments, the rendering output pipeline 870 includes a rasterizer and depth test component 873 that converts vertex-based objects into an associated pixel-based representation. In some embodiments, the rasterizer logic includes a windower / masker unit to perform fixed function triangle and line rasterization. In some embodiments, associated rendering caches 878 and depth caches 879 are also available. A pixel manipulation component 877 performs pixel-based manipulations on the data, although in some cases pixel operations associated with 2D processing (e.g., bit-block image transfers including blending) are performed by the 2D engine 841 or replaced at display time by the controller 843 using an overlay display surface. In some embodiments, a shared L3 cache 875 is available to all graphics components, allowing data to be shared without using main system memory.

[0125] In some embodiments, the graphics processor media pipeline 830 includes a media engine 837 and a video front end 834. In some embodiments, the video front end 834 receives pipeline commands from the command streamer 803. In some embodiments, the media pipeline 830 includes a separate command streamer. In some embodiments, the video front end 834 processes the media commands before sending the commands to the media engine 837. In some embodiments, the media engine 837 includes a thread generation function that generates threads for dispatch to the thread execution logic 850 via the thread dispatcher 831.

[0126] In some embodiments, graphics processor 800 includes a display engine 840. In some embodiments, display engine 840 is external to processor 800 and couples to the graphics processor via ring interconnect 802 or some other interconnect bus or fabric. In some embodiments, display engine 840 includes a 2D engine 841 and a display controller 843. In some embodiments, display engine 840 includes dedicated logic that can operate independently from the 3D pipeline. In some embodiments, display controller 843 couples to a display device (not shown), which may be a system integrated display device, such as a laptop computer, or an external display device attached via a display connector.

[0127] In some embodiments, the geometry pipeline 820 and the media pipeline 830 are configurable to operate based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In some embodiments, the graphics processor's driver software translates API calls specific to a particular graphics or media library into commands that the graphics processor can process. In some embodiments, support is provided for the Open Graphics Library (OpenGL), Open Computer Language (OpenCL), and / or Vulkan graphics and computation APIs, all from the Khronos Group. In some embodiments, support may also be provided for Microsoft's Direct3D library. In some embodiments, a combination of these libraries may be supported. Support is also provided for the open source computer vision library (OpenCV). Future APIs, including compatible 3D pipelines, are also supported if a mapping can be made from the future API's pipeline to the graphics processor's pipeline.

[0128] Graphics Pipeline Programming

[0129] Figure 9A is a block diagram illustrating a graphics processor command format 900 according to some embodiments. Figure 9B is a block diagram illustrating a graphics processor command sequence 910 according to one embodiment. The solid lined boxes in Figure 9A indicate components that are typically included in a graphics command, while the dashed lines include components that are optional or that are included in only a subset of the graphics commands. The example graphics processor command format 900 of Figure 9A includes data fields to identify a client 902, a command operation code (opcode) 904, and data 906 for the command. Sub-opcodes 905 and command size 908 are also included in some commands.

[0130] In some embodiments, the client 902 specifies which client units of the graphics device will process the command data. In some embodiments, a command parser in the graphics processor examines the client field of each command to condition further processing of the command and route the command data to the appropriate client unit. In some embodiments, the graphics processor client units include a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline that processes the command. When a client unit receives a command, the client unit reads the opcode 904 and, if present, the sub-opcode 905 to determine the operation to perform. The client unit executes the command using the information in the data field 906. For some commands, an explicit command size 908 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands based on the command opcode. In some embodiments, the commands are aligned via multiples of doublewords. Other command formats can be used.

[0131] The flow diagram of FIG. 9B illustrates an exemplary graphics processor command sequence 910. In some embodiments, software or firmware of a data processing system featuring an embodiment of a graphics processor uses versions of the illustrated command sequences to set up, execute, and terminate a set of graphics operations. The sample command sequence is shown and described for illustrative purposes only, as embodiments are not limited to these particular commands or this command sequence. Furthermore, commands may be issued as a batch of commands in the command sequence, whereby the graphics processor processes the sequence of commands at least partially concurrently.

[0132] In some embodiments, the graphics processor command sequence 910 begins with a pipeline flush command 912, which causes the active graphics pipeline to complete any commands currently pending in the pipeline. In some embodiments, the 3D pipeline 922 and the media pipeline 924 do not operate simultaneously. A pipeline flush is executed, causing the active graphics pipeline to complete any pending commands. In response to the pipeline flush, the graphics processor's command parser pauses command processing until the active drawing engine completes pending operations and the associated read cache is invalidated. Optionally, data in the rendering cache that is marked as "dirty" may be flushed to memory. In some embodiments, the pipeline flush command 912 may be used for pipeline synchronization or before placing the graphics processor in a low power state.

[0133] In some embodiments, the pipeline select command 913 is used when a command sequence requests the graphics processor to explicitly switch pipelines. In some embodiments, the pipeline select command 913 is only required once in an execution context before issuing any pipeline commands, unless the execution context issues commands for both pipelines. In some embodiments, a pipeline flush command 912 is required immediately before switching pipelines via the pipeline select command 913.

[0134] In some embodiments, pipeline control commands 914 are used to configure the graphics pipeline for operation and to program the 3D pipeline 922 and the media pipeline 924. In some embodiments, pipeline control commands 914 configure the pipeline state of the active pipeline. In one embodiment, pipeline control commands 914 are used for pipeline synchronization and to clear data from one or more cache memories in the active pipeline before processing a batch of commands.

[0135] In some embodiments, the return buffer state command 916 is used to configure a set of return buffers for each pipeline to write data to. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers in which the operation writes intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and for inter-thread communication. In some embodiments, the return buffer state 916 includes selecting the size and number of return buffers to use for a set of pipeline operations.

[0136] The remaining commands in the command sequence differ based on the active pipeline for the operation. Based on a pipeline decision 920, the command sequence is tailored for either the 3D pipeline 922, starting at a 3D pipeline state 930, or the media pipeline 924, starting at a media pipeline state 940.

[0137] The commands that configure the 3D pipeline state 930 include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables that are configured before processing 3D primitive commands. The values ​​of these commands are determined at least in part based on the particular 3D API that is being used. In some embodiments, the 3D pipeline state 930 commands can also selectively disable or bypass certain pipeline elements if those particular pipeline elements are not being used.

[0138] In some embodiments, the 3D primitive 932 command is used to submit a 3D primitive to be processed by the 3D pipeline. The command and associated parameters passed to the graphics processor via the 3D primitive 932 command are forwarded to a vertex fetch function of the graphics pipeline. The vertex fetch function uses the 3D primitive 932 command data to generate a vertex data structure. The vertex data structure is stored in one or more return buffers. In some embodiments, the 3D primitive 932 command is used to perform vertex operations on the 3D primitive via a vertex shader. To process the vertex shader, the 3D pipeline 922 dispatches shader execution threads to the graphics processor execution units.

[0139] In some embodiments, the 3D pipeline 922 is triggered via an execute 934 command or event. In some embodiments, a register write triggers command execution. In some embodiments, execution is triggered via a "go" or "kick" command in the command sequence. In one embodiment, command execution is triggered using a pipeline synchronization command to flush the command sequence through the graphics pipeline. The 3D pipeline performs geometric processing of the 3D primitives. Once processing is complete, the resulting geometric objects are rasterized and a pixel engine colors the resulting pixels. Additional commands that control pixel shading and pixel backend processing may also be included in these operations.

[0140] In some embodiments, the graphics processor command sequence 910 follows the path of the media pipeline 924 when performing media processing. In general, the specific use and manner of programming the media pipeline 924 depends on the media or computational processing being performed. Certain media decode operations may be offloaded to the media pipeline during media decoding. In some embodiments, the media pipeline may be bypassed and media decoding may be performed in whole or in part using resources provided by one or more general purpose processing cores. In one embodiment, the media pipeline also includes elements for general purpose graphics processor unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using computational shader programs that are not explicitly related to rendering graphics primitives.

[0141] In some embodiments, the media pipeline 924 is configured in a similar manner to the 3D pipeline 922. A set of commands that configure the media pipeline state 940 are dispatched or placed in a command queue before the media object commands 942. In some embodiments, the commands for the media pipeline state 940 contain data for configuring the media pipeline elements that will be used to process the media object. This includes data for configuring the video decode and video encode logic in the media pipeline, such as the encode or decode format. In some embodiments, the commands for the media pipeline state 940 also support the use of one or more pointers to "indirect" state elements that contain a batch of state settings.

[0142] In some embodiments, the media object command 942 provides a pointer to a media object for processing by the media pipeline. The media object includes a memory buffer that contains the video data to be processed. In some embodiments, all media pipeline state must be valid before issuing the media object command 942. Once the pipeline state is configured and the media object command 942 is queued, the media pipeline 924 is triggered via an execute command 944 or equivalent execute event (e.g., a register write). The output from the media pipeline 924 can then be post-processed by operations provided by the 3D pipeline 922 or the media pipeline 924. In some embodiments, GPGPU operations are configured and executed in a similar manner to media processing.

[0143] Graphics Software Architecture

[0144] 10 illustrates an exemplary graphics software architecture for a data processing system 1000, according to some embodiments. In some embodiments, the software architecture includes a 3D graphics application 1010, an operating system 1020, and at least one processor 1030. In some embodiments, the processor 1030 includes a graphics processor 1032 and one or more general-purpose processor cores 1034. The graphics application 1010 and the operating system 1020 each execute in the system memory 1050 of the data processing system.

[0145] In some embodiments, the 3D graphics application 1010 includes one or more shader programs that include shader instructions 1012. The shader language instructions may be in a high-level shader language such as Direct3D's High Level Shader Language (HLSL), OpenGL Shader Language (GLSL), etc. The application also includes executable instructions 1014 in a machine language suitable for execution by a general-purpose processor core 1034. The application also includes graphics objects 1016 that are defined by vertex data.

[0146] In some embodiments, the operating system 1020 is a Microsoft Windows operating system from Microsoft Corporation, a proprietary UNIX-like operating system, or an open source UNIX-like operating system that uses a variation of the Linux kernel. The operating system 1020 can support a graphics API 1022, such as the Direct3D API, the OpenGL API, or the Vulkan API. If the Direct3D API is used, the operating system 1020 compiles any shader instructions 1012 in HLSL into a lower level shader language using a front-end shader compiler 1024. The compilation can be a just-in-time (JIT) compilation, or the application can perform shader pre-compilation. In some embodiments, the high-level shaders are compiled into low-level shaders during compilation of the 3D graphics application 1010. In some embodiments, the shader instructions 1012 are provided in an intermediate format, such as a version of the standard portable intermediate representation (SPIR) used by the Vulkan API.

[0147] In some embodiments, the user mode graphics driver 1026 includes a back-end shader compiler 1027 for converting the shader instructions 1012 into a hardware-specific representation. When the OpenGL API is used, the shader instructions 1012 in the GLSL high-level language are passed to the user mode graphics driver 1026 for compilation. In some embodiments, the user mode graphics driver 1026 communicates with a kernel mode graphics driver 1029 using operating system kernel mode functions 1028. In some embodiments, the kernel mode graphics driver 1029 communicates with the graphics processor 1032 to dispatch commands and instructions.

[0148] IP Core Implementation

[0149] One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit, such as a processor. For example, the machine-readable medium may include instructions that represent various logic within a processor. When read by a machine, the instructions can cause the machine to create logic to perform the techniques described herein. Such representations, known as "IP cores," are reusable logical units of an integrated circuit that may be stored on a tangible machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model is provided to various customers or manufacturing facilities, which load the hardware model into manufacturing machines that produce the integrated circuit. The integrated circuit may be manufactured such that the circuit performs the processing described in connection with any of the embodiments described herein.

[0150] FIG. 11A is a block diagram illustrating an IP core development system 1100 that may be used to fabricate an integrated circuit for processing, according to one embodiment. The IP core development system 1100 may be used to generate modular, reusable designs that may be incorporated into a larger design or used to build an entire integrated circuit (e.g., a SOC integrated circuit). The design facility 1130 may generate a software simulation 1110 of the IP core design in a high-level programming language (e.g., C / C++). The software simulation 1110 may be used to design, test, and verify the operation of the IP core using a simulation model 1112. The simulation model 1112 may include functional, behavioral, and / or timing simulation. A register transfer level (RTL) design 1115 may then be created or synthesized from the simulation model 1112. The RTL design 1115 is an abstraction of the operation of the integrated circuit that models the flow of digital signals between hardware registers, including associated logic that is implemented using the modeled digital signals. In addition to the RTL design 1115, lower level designs at the logic level or transistor level may also be created, designed, or synthesized. Thus, the specific details of the initial design and simulation may vary.

[0151] The RTL design 1115 or equivalent may be further synthesized by a design facility into a hardware model 1120, which may be a hardware description language (HDL) or some other representation of physical design data. The HDL may be further simulated or tested to verify the design of the IP core. The IP core design may be stored using a non-volatile memory 1140 (e.g., a hard disk, a flash memory, or any non-volatile storage medium) for delivery to a third-party manufacturing facility 1165. Alternatively, the IP core design may be transmitted via a wired connection 1150 or a wireless connection 1160 (e.g., via the Internet). The manufacturing facility 1165 may then manufacture an integrated circuit based at least in part on the IP core design. The manufactured integrated circuit may be configured to process according to at least one embodiment described herein.

[0152] 11B illustrates a cross-sectional side view of an integrated circuit package assembly 1170 according to some embodiments described herein. The integrated circuit package assembly 1170 illustrates an implementation of one or more processors or accelerator devices as described herein. The package assembly 1170 includes multiple units of hardware logic 1172, 1174 coupled to a substrate 1180. The logic 1172, 1174 may be at least partially implemented with configurable logic or fixed function logic hardware and may include one or more portions of any of the processor cores, graphic processors, or other accelerator devices described herein. Each unit of logic 1172, 1174 may be implemented in a semiconductor die and coupled to the substrate 1180 via an interconnect structure 1173. The interconnect structure 1173 may be configured to route electrical signals between the logic 1172, 1174 and the substrate 1180 and may include interconnects such as, but not limited to, bumps or pillars. In some embodiments, the interconnect structure 1173 may be configured to route electrical signals, such as, for example, input / output (I / O) signals and / or power or ground signals associated with the processing of the logic 1172, 1174. In some embodiments, the substrate 1180 is an epoxy-based laminate substrate. In other embodiments, the substrate 1180 may include other suitable types of substrates. The package assembly 1170 may be connected to other electrical devices via the package interconnect 1183. The package interconnect 1183 may be coupled to a surface of the substrate 1180 to route electrical signals to other electrical devices, such as a motherboard, another chipset, or a multi-chip module.

[0153] In some embodiments, the units of logic 1172, 1174 are electrically coupled to a bridge 1182 configured to route electrical signals between the logic 1172, 1174. The bridge 1182 may be a high density interconnect structure that provides paths for the electrical signals. The bridge 1182 may include a bridge substrate comprised of glass or a suitable semiconductor material. Electrical routing features may be formed on the bridge substrate to provide chip-to-chip connections between the logic 1172, 1174.

[0154] Although two units of logic 1172, 1174 and a bridge 1182 are shown, the embodiments described herein may include more or fewer logic units on one or more dies. If logic is included on a single die, bridge 1182 may be omitted, and thus one or more dies may be connected by zero or more bridges. Alternatively, multiple dies or units of logic may be connected by one or more bridges. Additionally, multiple logic units, dies, and bridges may be connected together in other possible configurations, including three-dimensional configurations.

[0155] FIG. 11C illustrates a package assembly 1190 including multiple units of hardware logic chiplets connected to a substrate 1180 (e.g., a base die). Graphics processing units, parallel processors, and / or computational accelerators as described herein can be composed of multiple silicon chiplets that are manufactured separately. In this context, a chiplet is an at least partially packaged integrated circuit that includes individual units of logic that can be assembled into a larger package with other chiplets. A multiple set of chiplets including different IP core logic can be assembled into a single device. Additionally, active interposer technology can be used to integrate chiplets into a base die or base chiplet. The concepts described herein enable interconnection and communication between various forms of IP within a GPU. IP cores can be manufactured using various process technologies and configured during manufacturing, thus avoiding the complexity of aggregating multiple IPs into the same manufacturing process, especially in large SoCs that include multiple flavors of IP. Enabling the use of multiple process technologies can reduce time to market and provide a cost-effective way to create multiple product SKUs. Additionally, disaggregated IP can be more easily power gated independently, allowing components not being used for a given workload to be powered off, reducing overall power consumption.

[0156] The hardware logic chiplets may include dedicated hardware logic chiplets 1172, logic or I / O chiplets 1174, and / or memory chiplets 1175. The hardware logic chiplets 1172 and logic or I / O chiplets 1174 may be implemented at least in part in configurable logic or fixed function logic hardware, and may include one or more portions of any of the processor cores, graphics processors, parallel processors, or other accelerator devices described herein. The memory chiplets 1175 may be DRAM (e.g., GDDR, HBM) memory or cache (SRAM) memory.

[0157] Each chiplet may be fabricated as a separate semiconductor die and coupled to substrate 1180 via interconnect structures 1173. Interconnect structures 1173 may be configured to route electrical signals between the various chiplets and logic in substrate 1180. Interconnect structures 1173 may include interconnects such as, but not limited to, bumps or pillars. In some embodiments, interconnect structures 1173 may be configured to route electrical signals such as, for example, input / output (I / O) signals and / or power or ground signals associated with the processing of logic, I / O, and memory chiplets.

[0158] In some embodiments, the substrate 1180 is an epoxy-based laminate substrate. In other embodiments, the substrate 1180 may include other suitable types of substrates. The package assembly 1190 may be connected to other electrical devices via the package interconnect 1183. The package interconnect 1183 may be bonded to a surface of the substrate 1180 to route electrical signals to other electrical devices, such as a motherboard, another chipset, or a multi-chip module.

[0159] In some embodiments, the logic or I / O chiplets 1174 and the memory chiplets 1175 may be electrically coupled through a bridge 1187 configured to route electrical signals between the logic or I / O chiplets 1174 and the memory chiplets 1175. The bridge 1187 may be a high density interconnect structure that provides a path for the electrical signals. The bridge 1187 may include a bridge substrate comprised of glass or a suitable semiconductor material. Electrical routing functions may be formed on the bridge substrate to provide chip-to-chip connections between the logic or I / O chiplets 1174 and the memory chiplets 1175. The bridge 1187 may also be referred to as a silicon bridge or an interconnect bridge. For example, in some embodiments, the bridge 1187 is an embedded multi-die interconnect bridge (EMIB). In some embodiments, the bridge 1187 may simply be a direct connection from one chiplet to another.

[0160] Substrate 1180 can include hardware components for I / O 1191, cache memory 1192, and other hardware logic 1193. Fabric 1185 is embedded in substrate 1180 to enable communication between various logic chiplets and logic 1191, 1193 within substrate 1180. In one embodiment, I / O 1191, fabric 1185, cache, bridges, and other hardware logic 1193 can be integrated into a base die that is stacked on top of substrate 1180.

[0161] In various embodiments, the package assembly 1190 can include fewer or more components and chiplets interconnected by the fabric 1185 or one or more bridges 1187. The chiplets in the package assembly 1190 can be arranged in a 3D or 2.5D configuration. In general, the bridge structure 1187 can be used to facilitate point-to-point interconnections between, for example, logic or I / O chiplets and memory chiplets. The fabric 1185 can be used to interconnect various logic and / or I / O chiplets (e.g., chiplets 1172, 1174, 1191, 1193) with other logic and / or I / O chiplets. In one embodiment, the cache memory 1192 in the substrate can function as a global cache for the package assembly 1190, part of a distributed global cache, or a dedicated cache for the fabric 1185.

[0162] 11D illustrates a package assembly 1194 including a replaceable chiplet 1195, according to one embodiment. The replaceable chiplet 1195 can be assembled into a standardized slot of one or more base chiplets 1196, 1198. The base chiplets 1196, 1198 can be coupled via a bridge interconnect 1197, which can be similar to other bridge interconnects described herein or can be, for example, an EMIB. Memory chiplets can also be connected to logic or I / O chiplets via a bridge interconnect. I / O and logic chiplets can communicate via an interconnect fabric. Each base chiplet can support one or more slots in a standardized format for either logic or I / O or memory / cache.

[0163] In one embodiment, the SRAM and power delivery circuitry can be fabricated in one or more base chiplets 1196, 1198, which can be fabricated using a different process technology than the replaceable chiplets 1195 stacked on top of the base chiplets. For example, the base chiplets 1196, 1198 can be fabricated using a larger process technology, while the replaceable chiplets can be fabricated using a smaller process technology. One or more of the replaceable chiplets 1195 can be memory (e.g., DRAM) chiplets. Different memory densities can be selected for the package assembly 1194 based on the power and / or performance targeted for the product using the package assembly 1194. Furthermore, logic chiplets containing different types and numbers of functional units can be selected at assembly time based on the power and / or capabilities targeted for the product. Furthermore, chiplets containing different types of IP logic cores can be inserted into the slots of the replaceable chiplets, allowing hybrid processor designs that can use a mix and match of IP blocks of different technologies.

[0164] Exemplary System of Chip Integrated Circuits

[0165] 12-13 illustrate an exemplary integrated circuit and associated graphics processor that may be manufactured using one or more IP cores according to various embodiments described herein. In addition to what is illustrated, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general purpose processor cores.

[0166] 12 is a block diagram illustrating an exemplary system on a chip integrated circuit 1200 that may be manufactured using one or more IP cores, according to one embodiment. The exemplary integrated circuit 1200 includes one or more application processors 1205 (e.g., CPU), at least one graphics processor 1210, and may further include an image processor 1215 and / or a video processor 1220, any of which may be modular IP cores from the same or multiple different design facilities. The integrated circuit 1200 includes a USB controller 1225, a UART controller 1230, an SPI / SDIO controller 1235, and an I / O controller 1236. 2 S / I 2 The integrated circuit may further include peripheral or bus logic including a C controller 1240. Additionally, the integrated circuit may include a display device 1245 coupled to one or more of a High Definition Multimedia Interface (HDMI®) controller 1250 and a Mobile Industry Processor Interface (MIPI) display interface 1255. Storage may be provided by a flash memory subsystem 1260 including a flash memory and a flash memory controller. A memory interface may be provided for accessing an SDRAM or SRAM memory device via a memory controller 1265. Some integrated circuits further include an embedded security engine 1270.

[0167] 13A-13B are block diagrams illustrating an example graphics processor for use in an SoC, according to embodiments described herein. FIG. 13A illustrates an example graphics processor 1310 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores, according to one embodiment. FIG. 13B illustrates an additional example graphics processor 1340 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores, according to one embodiment. The graphics processor 1310 of FIG. 13A is an example of a low-power graphics processor core. The graphics processor 1340 of FIG. 13B is an example of a high-performance graphics processor core. Each of the graphics processors 1310, 1340 may be a variation of the graphics processor 1210 of FIG. 12.

[0168] As shown in FIG. 13A, the graphics processor 1310 includes a vertex processor 1305 and one or more fragment processors 1315A-1315N (e.g., 1315A, 1315B, 1315C, 1315D through 1315N-1, and 1315N). The graphics processor 1310 can execute different shader programs through separate logic, so that the vertex processor 1305 is optimized to perform the operations of a vertex shader program, while the one or more fragment processors 1315A-1315N perform the fragment (e.g., pixel) shading operations of a fragment or pixel shader program. The vertex processor 1305 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. The fragment processors 1315A-1315N use the primitive and vertex data generated by the vertex processor 1305 to generate a frame buffer that is displayed on the display device. In one embodiment, the fragment processors 1315A-1315N are optimized to execute fragment shader programs such as those provided in the OpenGL API, which can be used to perform similar processing as pixel shader programs such as those provided in the Direct3D API.

[0169] Graphics processor 1310 further includes one or more memory management units (MMUs) 1320A-1320B, caches 1325A-1325B, and circuit interconnects 1330A-1330B. The one or more MMUs 1320A-1320B provide virtual to physical address mapping for graphics processor 1310, including vertex processors 1305 and / or fragment processors 1315A-1315N, which can reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more caches 1325A-1325B. In one embodiment, one or more MMUs 1320A-1320B may be synchronized with other MMUs in the system, including one or more MMUs associated with one or more application processors 1205, image processor 1215, and / or video processor 1220 of Figure 12, allowing each processor 1205-1220 to participate in a shared or unified virtual memory system. According to an embodiment, one or more circuit interconnects 1330A-1330B may enable graphics processor 1310 to interface with other IP cores in the SoC via an internal bus of the SoC or via a direct connection.

[0170] As shown in Figure 13B, the graphics processor 1340 includes one or more MMUs 1320A-1320B, caches 1325A-1325B, and circuit interconnects 1330A-1330B of the graphics processor 1310 of Figure 13A. The graphics processor 1340 includes one or more shader cores 1355A-1355N (e.g., 1355A, 1355B, 1355C, 1355D, 1355E, 1355F through 1355N-1, 1355N) that provide a unified shader core architecture in which a single core or type or cores can execute all types of programmable shader code, including shader program code implementing vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores present may vary depending on the embodiment and implementation. Additionally, graphics processor 1340 includes an inter-core task manager 1345 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1355A-1355N and tiling unit 1358 to accelerate the tiling process for tile-based rendering, where the rendering process of a scene is subdivided in image space, for example to exploit local spatial coherence within the scene or to optimize the use of internal caches.

[0171] Machine Learning Overview

[0172] Machine learning algorithms are algorithms that can learn based on a set of data. Machine learning algorithm embodiments can be designed to model high-level abstractions within a dataset. For example, image recognition algorithms can be used to determine which of several categories a given input belongs to. Regression algorithms can output a numerical value given an input. Pattern recognition algorithms can be used to generate converted text or convert text to speech and / or perform speech recognition.

[0173] An exemplary type of machine learning algorithm is a neural network. There are many types of neural networks, and a simple type of neural network is a feedforward network. A feedforward network can be implemented as an acyclic graph with nodes arranged in layers. Typically, a feedforward network topology includes an input layer and an output layer separated by at least one hidden layer. The hidden layer converts the input received by the input layer into a representation that helps generate the output at the output layer. The network nodes are fully connected to the nodes of adjacent layers via edges, but there are no edges between the nodes within each layer. Data received at the nodes of the input layer of a feedforward network is propagated (i.e., "feed forward") to the nodes of the output layer via an activation function that calculates the state of the nodes of each successive layer in the network based on the coefficients (weights) associated with each edge connecting the layers. Depending on the particular model represented by the algorithm being executed, the output from a neural network algorithm can take a variety of forms.

[0174] Before a machine learning algorithm is used to model a particular problem, the algorithm is trained using a training dataset. Training a neural network involves selecting a network topology, using a set of training data that represents the problem being modeled by the network, and adjusting the weights until the network model runs with minimal error for all instances of the training dataset. For example, during the supervised learning training process of a neural network, the outputs generated by the network in response to inputs that represent instances in the training dataset are compared with the "correct" labeled outputs for the instances, an error signal representing the difference between the outputs and the labeled outputs is calculated, and the weights associated with the connections are adjusted to minimize the error as the error signal propagates backwards through the layers of the network. The network is considered "trained" when the error for each output generated from an instance of the training dataset is minimized.

[0175] The accuracy of machine learning algorithms can be significantly affected by the quality of the data set used to train the algorithm. The training process can be computationally intensive and can take a significant amount of time on a conventional general-purpose processor. Thus, parallel processing hardware is used to train many types of machine learning algorithms. This is particularly useful for optimizing the training of neural networks, since the calculations performed in adjusting the coefficients of the neural network themselves naturally lend themselves to parallel implementation. In particular, many machine learning algorithms and software applications have been adapted to take advantage of parallel processing hardware in general-purpose graphics processing units.

[0176] 14 is a generalized diagram of a machine learning software stack 1400. A machine learning application 1402 may be configured to train a neural network with a training dataset or to implement machine intelligence using a trained deep neural network. The machine learning application 1402 may include training and inference capabilities for the neural network and / or specialized software that may be used to train the neural network prior to deployment. The machine learning application 1402 may implement any type of machine intelligence, including but not limited to image recognition, mapping and localization, autonomous navigation, speech synthesis, medical image processing, or language translation.

[0177] Hardware acceleration of the machine learning application 1402 can be enabled through the machine learning framework 1404. The machine learning framework 1404 can provide a library of machine learning primitives. Machine learning primitives are basic operations typically performed by machine learning algorithms. Without the machine learning framework 1404, developers of machine learning algorithms would need to create and optimize the main computation logic associated with the machine learning algorithm, and then reoptimize the computation logic as new parallel processors are developed. Instead, machine learning applications can be configured to perform the necessary computations using primitives provided by the machine learning framework 1404. Exemplary primitives include tensor convolutions, activation functions, and pooling, which are computational operations performed during training of a convolutional neural network (CNN). The machine learning framework 1404 can also provide primitives for implementing basic linear algebra subprograms performed by many machine learning algorithms, such as matrix and vector operations.

[0178] The machine learning framework 1404 can process input data received from the machine learning application 1402 and generate appropriate inputs to the computation framework 1406. The computation framework 1406 abstracts the underlying instructions provided to the GPGPU driver 1408, allowing the machine learning framework 1404 to take advantage of hardware acceleration via the GPGPU hardware 1410 without the machine learning framework 1404 having to be familiar with the architecture of the GPGPU hardware 1410. Furthermore, the computation framework 1406 can enable hardware acceleration of the machine learning framework 1404 across different types and generations of GPGPU hardware 1410.

[0179] Implementing machine learning neural networks

[0180] The computing architecture provided by the embodiments described herein can be configured to perform a type of parallel processing that is particularly suitable for training and deploying neural networks for machine learning. A neural network can be generalized as a network of functions with graph relationships. As known in the art, there are various types of neural network implementations used in machine learning. One exemplary type of neural network is a feedforward network, as previously described.

[0181] A second exemplary type of neural network is the Convolutional Neural Network (CNN). CNNs are specialized feed-forward neural networks for processing data with a known grid-like topology, such as image data. Thus, CNNs are commonly used for visual computation and image recognition applications, but can also be used for other types of pattern recognition, such as speech and language processing. The nodes of a CNN input layer are organized into a set of "filters" (feature detectors inspired by receptive fields in the retina), and the output of each set of filters is propagated to the nodes of successive layers of the network. A CNN's computation involves applying a convolution mathematical operation to each filter to generate the output of that filter. Convolution is a specialized mathematical operation performed by two functions to generate a third function that is a modified version of one of the two original functions. In convolutional network terminology, the first function of a convolution is called the input, while the second function is called the convolution kernel. The output may be called a feature map. For example, the input to a convolutional layer can be a multidimensional array of data that defines the various color components of the input image. The convolution kernel can be a multidimensional array of parameters, which are adapted by the training process of the neural network.

[0182] Recurrent neural networks (RNNs) are a family of feed-forward neural networks that contain feedback connections between layers. RNNs allow for the modeling of sequential data by sharing parameter data across various parts of the neural network. The architecture of an RNN contains cycles. A cycle represents the effect of a variable's current value at a future time on its own value, as at least a portion of the output data from the RNN is used as feedback to process subsequent inputs in the sequence. This feature makes RNNs particularly useful for language processing due to the nature of the variables that can constitute linguistic data.

[0183] The figures described below present exemplary feedforward, CNN, and RNN networks and explain the general process for training and deploying each of these types of networks, respectively. It will be understood that these descriptions are exemplary and non-limiting with respect to the specific embodiments described herein, and that the illustrated concepts are generally applicable to deep neural networks and machine learning techniques.

[0184] The above exemplary neural network can be used to perform deep learning. Deep learning is machine learning using deep neural networks. Deep neural networks used in deep learning are artificial neural networks that are composed of multiple hidden layers, as opposed to shallow neural networks that contain only a single hidden layer. Deeper (deep) neural networks are generally more computationally intensive to train. However, the additional hidden layers of the network enable multi-stage pattern recognition that reduces output error compared to shallow machine learning techniques.

[0185] A deep neural network used in deep learning typically includes a front-end network that performs feature recognition coupled to a back-end network that represents a mathematical model that can perform operations (e.g., object classification, speech recognition, etc.) based on feature representations provided to the model. Deep learning allows machine learning to be performed without the need to perform hand-crafted feature engineering on the model. Instead, a deep neural network can learn features based on statistical structures or correlations in the input data. The learned features can be provided to a mathematical model that can map the detected features to an output. The mathematical model used in the network is typically specialized for the particular task being performed, with different models being used to perform different tasks.

[0186] Once a neural network is constructed, a learning model can be applied to the network to train the network to perform a specific task. The learning model describes how to adjust the weights in the model to reduce the network's output error. Backpropagation of errors is a common method used to train neural networks. An input vector is presented to the network for processing. The output of the network is compared to the desired output using a loss function, and an error value is calculated for each neuron in the output layer. The error values ​​are then propagated backwards until each neuron has an associated error value that roughly represents its contribution to the original output. The network can then learn from these errors using algorithms such as the stochastic gradient descent algorithm to update the neural network weights.

[0187] 15A-15B show an exemplary convolutional neural network. FIG. 15A shows various layers within a CNN. As shown in FIG. 15A, an exemplary CNN used to model image processing can receive an input 1502 representing red, green, and blue (RGB) components of an input image. The input 1502 can be processed by multiple convolutional layers (e.g., a first convolutional layer 1504, a second convolutional layer 1506). The output from the multiple convolutional layers is optionally processed by a set of fully connected layers 1508. The neurons in the fully connected layers fully connect to all activations of the previous layer, as described above with respect to feedforward networks. The output from the fully connected layers 1508 can be used to generate an output result from the network. The activations in the fully connected layers 1508 can be calculated using matrix multiplication instead of convolutions. Not all CNN implementations utilize the fully connected layers 1508. For example, in some implementations, the second convolutional layer 1506 can generate the output of the CNN.

[0188] Convolutional layers are sparsely connected, which differs from traditional neural network configurations found in fully connected layers 1508. Traditional neural network layers are fully connected, whereby every output unit interacts with every input unit. However, as shown, convolutional layers are sparsely connected because the output of the convolution of the field (rather than each state value of each node in the field) is input to the nodes of the subsequent layer. The kernels associated with the convolutional layers perform the convolution operation, and the output is sent to the next layer. The dimensionality reduction performed within the convolutional layers is one aspect that allows CNNs to scale to process large images.

[0189] 15B illustrates exemplary computational steps within a convolutional layer of a CNN. An input to the convolutional layer 1512 of a CNN can be processed in three stages in the convolutional layer 1514. The three stages can include a convolution stage 1516, a detector stage 1518, and a pooling stage 1520. The convolutional layer 1514 can then output data to a successive convolutional layer. The final convolutional layer of the network can generate output feature map data or provide input to a fully connected layer to generate, for example, a classification value for the input to the CNN.

[0190] The convolution stage 1516 performs several convolutions in parallel to generate a set of linear activations. The convolution stage 1516 can include an affine transformation, which is any transformation that can be specified as a linear transformation plus a translation. Affine transformations include rotation, translation, scaling, and combinations of these transformations. The convolution stage calculates the output of a function (such as a neuron) that is connected to a particular region of the input, which can be determined as a local region associated with the neuron. The neuron calculates the dot product between the neuron's weight and the region of the local input to which the neuron is connected. The output from the convolution stage 1516 defines a set of linear activations that are processed by successive stages of the convolution layer 1514.

[0191] The linear activations may be processed by a detector stage 1518. In the detector stage 1518, each linear activation is processed by a nonlinear activation function. The nonlinear activation function enhances the nonlinear characteristics of the entire network without affecting the receptive fields of the convolutional layers. Several types of nonlinear activation functions can be used. One specific type is the rectified linear unit (ReLU), which uses an activation function defined as f(x)=max(0,x) to achieve an activation threshold of zero.

[0192] The pooling stage 1520 uses a pooling function that replaces the output of the second convolutional layer 1506 with summary statistics of nearby outputs. Pooling functions can be used to introduce translation invariance into the neural network, whereby small translations to the input do not change the pooled output. Invariance to local translations can be useful in scenarios where the presence of a feature in the input data is more important than the exact location of the feature. Various types of pooling functions can be used during the pooling stage 1520, such as max pooling, average pooling, l2-norm pooling, etc. Furthermore, some CNN implementations do not include a pooling stage. Instead, such implementations are replaced with an additional convolution stage with an increased stride compared to the previous convolution stage.

[0193] The output from the convolutional layer 1514 may then be processed by a next layer 1522, which may be an additional convolutional layer or one of the fully connected layers 1508. For example, the first convolutional layer 1504 in FIG. 15A may output to a second convolutional layer, which may in turn output to the first layer of the fully connected layers 1508.

[0194] FIG. 16 illustrates an exemplary recurrent neural network. In a recurrent neural network (RNN), the previous state of the network influences the output of the current state of the network. RNNs can be constructed in a variety of ways with a variety of functions. The use of RNNs typically revolves around using mathematical models to predict the future based on previous input sequences. For example, RNNs can be used to perform statistical language modeling to predict the next word given a series of previous words. The illustrated RNN 1600 can be described as having an input layer 1602 that receives input vectors, a hidden layer 1604 to implement a recurrent function, a feedback mechanism 1605 to allow for a "memory" of previous states, and an output layer 1606 to output the results. The RNN 1600 operates based on time steps. The state of the RNN at a given time step is influenced based on previous time steps via the feedback mechanism 1605. At a given time step, the state of the hidden layer 1604 is dictated by the previous state and the input of the current time step. An initial input (x1) at the first time step can be processed by the hidden layer 1604. The second input (x2) can be processed by the hidden layer 1604 using state information determined during processing of the initial input (x1). t =f(Ux t +Ws t-1 ), where U and W are parameter matrices. The function f is typically a nonlinearity, such as a variant of the hyperbolic tangent function (Tanh) or a rectified linear function f(x)=max(0,x). However, the particular mathematical functions used in the hidden layer 1604 may vary depending on the details of the particular implementation of the RNN 1600.

[0195] In addition to the basic CNN and RNN networks described, variations of these networks can be enabled. One example of a variant of an RNN is the long short-term memory (LSTM) RNN. LSTM RNNs can learn long-term dependencies that may be necessary to process longer language sequences. A variant of a CNN is the convolutional deep belief network, which has a structure similar to a CNN and is trained in a similar manner to a deep belief network. A deep belief network (DBN) is a generative neural network that consists of multiple layers of random variables. DBNs can be trained layer-by-layer using greedy unsupervised learning. The learned weights of the DBN can then be used to provide a pre-trained neural network by determining an optimal initial set of weights for the neural network.

[0196] FIG. 17 illustrates the training and deployment of deep neural networks. Once a network is constructed for a given task, it is trained using a training dataset 1702. To enable hardware acceleration of the training process, various training frameworks have been developed. For example, the machine learning framework 1404 of FIG. 14 may be configured as a training framework 1704. The training framework 1704 may hook into an untrained neural network 1706 and enable training the untrained neural net using parallel processing resources as described herein to generate a trained neural network 1708. To start the training process, initial weights may be selected randomly or by pre-training with a deep belief network. Then, the training cycle is performed in either a supervised or unsupervised manner.

[0197] Supervised learning is a learning method in which training is performed as a mediated operation, such as when the training data set 1702 includes inputs that are paired with desired outputs for the inputs, or when the training data set includes inputs with known outputs and the neural network's output is manually graded. The network processes the inputs and compares the resulting output to a set of expected or desired outputs. Errors are then back-propagated through the system. The training framework 1704 can be tuned to adjust the weights that control the untrained neural network 1706. The training framework 1704 can provide tools to monitor how well the untrained neural network 1706 has converged toward a model suitable for generating correct answers based on known input data. The training process occurs iteratively as the network weights are adjusted to fine-tune the outputs generated by the neural network. The training process can continue until the neural network reaches a statistically desired accuracy associated with the trained neural network 1708. The trained neural network 1708 can then be deployed to perform any number of machine learning operations and generate inference results 1714 based on the input of new data 1712.

[0198] Unsupervised learning is a learning method in which a network attempts to train itself with unlabeled data. Thus, in the case of unsupervised learning, a training data set 1702 includes input data without associated output data. The untrained neural network 1706 can learn groups in the unlabeled inputs and determine how each individual input is associated with the entire data set. Unsupervised training can be used to generate a self-organizing map, which is a type of trained neural network 1708 that can perform processing that helps reduce the dimensionality of the data. Unsupervised training can also be used for anomaly detection, which can identify data points in an input data set that deviate from normal patterns in the data.

[0199] Variations of supervised and unsupervised training may also be used. Semi-supervised learning is a technique in which the training data set 1702 contains a mixture of labeled and unlabeled data of the same distribution. Incremental learning is a variant of supervised learning in which input data is continually used to further train the model. Incremental learning allows the trained neural network 1708 to adapt to new data 1712 without forgetting the knowledge pumped into the network during initial training.

[0200] The training process, especially of deep neural networks, whether supervised or unsupervised, can be computationally intensive for a single computing node. Instead of using a single computing node, a distributed network of computing nodes can be used to accelerate the training process.

[0201] 18 is a block diagram illustrating distributed learning. Distributed learning is a training model that uses multiple distributed computing nodes to perform supervised or unsupervised training of neural networks. Each distributed computing node may include one or more host processors and one or more general-purpose processing nodes. As shown, distributed learning may perform a combination of model parallelism 1802, data parallelism 1804, and model and data parallelism 1806.

[0202] In model parallelism 1802, different computational nodes in a distributed system can perform training computations on different parts of a single network. For example, each layer of a neural network can be trained by a different processing node of the distributed system. An advantage of model parallelism is that it scales especially to large models. Splitting up the computations associated with different layers of a neural network allows the training of very large neural networks where the weights of all layers do not fit into the memory of a single computational node. In some cases, model parallelism can be particularly useful in performing unsupervised training of large neural networks.

[0203] In data parallelism 1804, different nodes in the distributed network have a complete instance of the model, with each node receiving a different portion of the data. The results from the different nodes are then combined. Various approaches to data parallelism are possible, but all data parallel training approaches require a technique to combine the results and synchronize the model parameters between each node. Exemplary approaches to combined (combined) data include parameter averaging and update-based data parallelism. Parameter averaging trains each node on a subset of the training data and sets the global parameters (e.g., weights, biases) to the average of the parameters from each node. Parameter averaging uses a central parameter server that maintains the parameter data. Update-based data parallelism is similar to parameter averaging, except that instead of transferring parameters from the nodes to the parameter server, updates to the model are transferred. Additionally, update-based data parallelism can be performed in a decentralized manner, where updates are compressed and transferred between nodes.

[0204] The combined model and data parallel processing 1806 can be implemented, for example, in a distributed system where each compute node contains multiple GPUs. Each node may have a complete instance of the model, and individual GPUs within each node are used to train different parts of the model.

[0205] Distributed training incurs increased overhead compared to training on a single machine, however the parallel processors and GPGPUs described herein each can implement various techniques to reduce the overhead of distributed training, including techniques that enable high-bandwidth GPU-to-GPU data transfers and high-speed remote data synchronization.

[0206] Example Machine Learning Applications

[0207] Machine learning can be applied to solve a variety of technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. Applications of computer vision range from replicating human visual capabilities, such as recognizing faces, to creating new categories of visual capabilities. For example, computer vision applications can be configured to recognize sound waves from vibrations occurring on an object displayed in a video. Accelerated machine learning on parallel processors allows computer vision applications to be trained with significantly larger training datasets than was previously possible, and allows inference systems to be deployed using low-power parallel processors.

[0208] Accelerated machine learning on parallel processors has autonomous driving applications including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train driving models based on data sets that specify appropriate responses to specific training inputs. The parallel processors described herein enable rapid training of increasingly complex neural networks used in autonomous driving solutions and enable the deployment of low-power inference processors on mobile platforms suitable for integration into autonomous vehicles.

[0209] Parallel processor accelerated deep neural networks have enabled a machine learning approach to automatic speech recognition (ASR). ASR involves creating a function that computes the most likely language sequence given an input acoustic sequence. Accelerated machine learning using deep neural networks has enabled the replacement of hidden Markov models (HMMs) and Gaussian mixture models (GMMs) previously used for ASR.

[0210] Parallel processor-accelerated machine learning can also be used to accelerate natural language processing. Automated learning procedures can utilize statistical inference algorithms to generate models that are robust to erroneous or unfamiliar input. Exemplary natural language processor applications include automatic machine translation between human languages.

[0211] Parallel processing platforms used for machine learning can be divided into training platforms and deployment platforms. Training platforms are typically highly parallelized and include optimizations to accelerate multi-GPU single-node training and multi-node, multi-GPU training, while deployed machine learning (e.g., inference) platforms typically include low-power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

[0212] GPGPU with matrix acceleration logic

[0213] 19 is a block diagram of a data processing system 1900 according to one embodiment. The data processing system 1900 is a heterogeneous processing system having a processor 1902, a unified memory 1910, and a GPGPU 1920 including machine learning acceleration logic. The processor 1902 and the GPGPU 1920 may be any of the processors and GPGPUs / parallel processors as described herein. The processor 1902 may execute instructions for a compiler 1915 stored in a system memory 1912. The compiler 1915 runs on the processor 1902 and compiles source code 1914A into compiled code 1914B. The compiled code 1914B may include instructions that may be executed by the processor 1902 and / or instructions that may be executed by the GPGPU 1920. During compilation, compiler 1915 may perform operations to insert metadata including hints regarding the level of data parallelism present in compiled code 1914B and / or hints regarding data locality associated with threads dispatched based on compiled code 1914B. Compiler 1915 may include information necessary to perform such operations, or operations may be performed with the aid of runtime library 1916. Runtime library 1916 also assists compiler 1915 in compiling source code 1914A, and may also include instructions that are linked at runtime with compiled code 1914B to facilitate execution of the compiled instructions on GPGPU 1920.

[0214] Unified memory 1910 represents a unified address space that may be accessed by processor 1902 and GPGPU 1920. The unified memory may include system memory 1912 as well as GPGPU memory 1918. GPGPU memory 1918 is memory within the address space of GPGPU 1920 and may include some or all of system memory 1912. In one embodiment, GPGPU memory 1918 may also include at least a portion of any memory dedicated for exclusive use by GPGPU 1920. In one embodiment, compiled code 1914B stored in system memory 1912 may be mapped into GPGPU memory 1918 for access by GPGPU 1920.

[0215] The GPGPU 1920 includes multiple computation blocks 1924A-1924N, which may include one or more of the various computation units or execution elements described herein. In one embodiment, the GPGPU 1920 further includes a matrix accelerator 1923, which may include one or more special function computation units designed to accelerate a subset of matrix operations (e.g., dot products, multiplication / addition, etc.). The GPGPU 1920 may also include a set of resources that may be shared by the computation blocks 1924A-1924N and the matrix accelerator 1923, including, but not limited to, a set of registers 1925, a power and performance module 1926, and a cache 1927. In one embodiment, the registers 1925 include directly and indirectly accessible registers, where the indirectly accessible registers are optimized for use by the matrix accelerator 1923. The power and performance module 1926 can be configured to adjust the power supply and clock frequency for the compute blocks 1924A-1924N to power gated idle components within the compute blocks 1924A-1924N. In various embodiments, the cache 1927 can include an instruction cache and / or a lower level data cache.

[0216] The GPGPU 1920 may further include an L3 data cache 1930 that may be used to cache data accessed from the unified memory 1910 by the computational elements in the matrix accelerator 1923 and / or the computational blocks 1924A-1924N. In one embodiment, the L3 data cache 1930 includes a shared local memory 1932 that may be shared by the computational elements in the computational blocks 1924A-1924N and the matrix accelerator 1923.

[0217] In one embodiment, the GPGPU 1920 includes instruction processing logic such as a fetch and decode unit 1921 and a scheduler controller 1922. The fetch and decode unit 1921 includes a fetch unit and a decode unit that fetch and decode instructions to be executed by one or more of the computation blocks 1924A-1924N or the matrix accelerator 1923. Instructions can be scheduled to appropriate functional units within the computation blocks 1924A-1924N or the matrix accelerator via the scheduler controller 1922. In one embodiment, the scheduler controller 1922 is an ASIC that can be configured to perform advanced scheduling operations. In one embodiment, the scheduler controller 1922 is a microcontroller or low energy per instruction processing core that can execute scheduler instructions loaded from a firmware module.

[0218] In one embodiment, some functions performed by the computation blocks 1924A-1924N may be scheduled directly or offloaded to the matrix accelerator 1923. In various embodiments, the matrix accelerator 1923 includes processing element logic configured to efficiently perform matrix computation operations, such as multiplication and addition operations and dot product operations used in 3D graphics or computation shader programs. In one embodiment, the matrix accelerator 1923 may be configured to accelerate operations used by machine learning frameworks. In one embodiment, the matrix accelerator 1923 is an application specific integrated circuit explicitly configured to perform a specific set of parallel matrix multiplication and / or addition operations. In one embodiment, the matrix accelerator 1923 is a field programmable gate array (FPGA) that provides fixed function logic that can be updated between workloads. The set of matrix operations that can be performed by the matrix accelerator 1923 may be limited to the operations that can be performed by the computation blocks 1924A-1924N. However, the matrix accelerator 1923 may be able to perform these operations with significantly higher throughput compared to the computation blocks 1924A-1924N.

[0219] GEMM calculation example

[0220] Graphics, vector, and parallel processors typically include one or more instructions that accelerate general matrix multiplication (GEMM) operations. A matrix multiplication can be performed with an M×K matrix and a K×N matrix to generate an M×N matrix. Large matrix multiplication can be performed by dividing the large matrix into blocks, where a block is a rectangular portion of the large matrix. The blocks can then be fetched to a processing resource for processing. In one embodiment, a multi-threaded processing resource, such as an execution unit, a graphics core, or a computation unit as described herein, can assign tasks to hardware threads to process each set of blocks and generate outputs to be stored in an output matrix. Each thread can traverse the matrix along the K dimension and accumulate the output of the product. Multiple blocks can be processed within a single thread based on the availability of registers in the processing resource.

[0221] FIG. 20 illustrates a general matrix multiplication operation on source and destination matrices. A single precision GEMM operation (e.g., SGEMM) is shown in which an M×K matrix (A matrix 2002) is multiplied by a K×N matrix (B matrix 2004) to produce an M×N output matrix (C matrix 2006). The illustrated matrices may be blocks of a larger matrix. The size of the blocks may vary depending on the SIMD width (e.g., simd width×simd width) of the machine. For example, in a SIMD8 processing element, A, B, and C may be 8×8 blocks of matrix elements. In one embodiment, A matrix 2002 is stored in the shared local memory of the processing element, while B matrix 2004 is stored in the L3 cache and C matrix 2006 is stored in a register in the general purpose register file of the processing resource, although other embodiments may be configured differently. Exemplary registers (e.g., rxx) and channels (e.g., 0 to 7) for the elements of the matrices are shown. During operation, matrix elements may be fetched from the indicated sources and stored in the illustrated registers and channels of the matrix elements. <src1>Without exploiting any sparsity present in the data (B matrix), <src2>Handle sparsity on the data (A matrix). In such an embodiment, <src2>Used for sparse inputs (e.g. matrices).

[0222] In one embodiment, SGEMM operations may be implemented via instructions having the format shown in Table 1. Table 1 Graphics processor instruction formats [Table 1]

[0223] The instruction formats in Table 1 are versions of the instruction formats 710 and 730 shown in FIG. 7. For the instruction formats in Table 1, <opcode>specifies the operation to be performed, <dst>is the operand that stores the result produced by the operation, <src0> 、 <src1>, and <src2>are three source operands, optionally followed by two modifiers ( <pred> 、 <cmod>) can be used. <pred>is a predicate that uses the flags register (f0.0) as a bitmask to mask off certain channels. <dst>and <cmod>is commonly used with the cmp (compare) instruction to generate a bit mask in the flags register based on the comparison results generated from the source operands. For example, <src0>and <src1>The instruction cmp(ne)f0.0 sets a bit in a flag register (f0.0) if the channels are not equal.

[0224] Some instruction sequences for SGEMM operations are shown in Table 2. Table 2 SGEMM operation sequence for k=0 [Table 2]

[0225] Table 2 shows an exemplary instruction sequence for operating on the matrix of FIG. 20, where k=0. A similar sequence is repeated for k=1 through 7. A higher loop loads the next set of elements from the A and B matrices and accumulates them into the same C matrix, which is also stored in the general register file. The mad opcodes shown are the operations: <dst> = <src0> + <src1> * <src2>Each operand consists of a register address, a range specification option, and a data type. The first instruction (line 00) multiplies the SIMD wide register r10 by the broadcast SIMD channel of register r76.0. The result is added to the SIMD wide register r34. <dst>For example, r34.0 <1> For :f, r34 is the register address (regnum) and .0 is the offset within the register (subregnum) in units of the data type. <1> is a range specification option indicating packed stride for writing, and :f indicates a float data type. <src0>or <src1>For example, r10.0<1,0>:f, where r10 is the register address (regnum), .0 is the offset within the register (subregnum) in units of the data type, <1,0> is a range specification option indicating the packed stride of the read, and :f indicates the data type. <src2>For example, r76.0 <0> For :f, r76 is the register address (regnum) and .0 is the offset within the register (subregnum) in units of the data type. <0> is a range specification option indicating broadcast of a single SIMD channel for reading, and :f indicates a float data type. The instructions in lines 01-07 perform a similar operation, proceeding across different SIMD channels in r76 and accumulating the results in consecutive registers (e.g., r77, r78).

[0226] Multiply-add vector instruction

[0227] Analysis of the instruction sequence in Table 2 shows that across the eight mad instructions used in the SGEMM operation, <src1>and <src2>The operand register addresses are the same, but <src0>and <dst>The operands indicate sequential increments. <src0>and <dst>are the same for a particular mad instruction, so the accumulation is done in the same register. Using this analysis, we can use the format: <pred>madv.rcount <dst> <src0> <src1> <src2>A graphics processing resource may be enabled that supports a hardware-implemented multiply-add vector (madv) instruction having:

[0228] Figures 21A-C show instructions and associated hardware logic for enabling multiply-add vector operations with zero skip for sparse inputs. Figure 21A shows the format of a multiply-add vector instruction 2100. Figure 21B shows hardware logic 2110 that enables decoding of the arithmetic-add vector instruction 2100. Figure 21C shows execution logic 2120 configured to enable decoding and execution of the multiply / add / vector instruction 2100 described herein.

[0229] As shown in FIG. 21A, one embodiment provides hardware support where a multiply-add vector instruction (madv instruction 2100) executes a sequence of multiply-add instructions with automatic zero skip on one or more input vectors. The format of the madv instruction 2100 includes a predicate (pred 2102), an instruction opcode supplemented with a repeat count 2104 (madv.rcount), a destination operand (dst 2106), and multiple source operands (src0 2107, src1 2108, src2 2109). In one embodiment, the predicate value is determined based on a flags register, and the bits of the predicate mask apply the predicate to the array of the individual mad instruction, rather than to the array of channels. Thus, the predicate mask can be used to enable or disable generation of certain instructions within the set of instructions represented by the madv instruction 2100.

[0230] In one embodiment, the madv instruction 2100 is implemented as a hardware macro instruction that is expanded into multiple additional instructions during decoding. In such an embodiment, the value of the iteration count 2104 indicates the number of instructions that are expanded in the execution resources at one time. For example, the madv.8 instruction shown in Table 3 below can be expanded in the execution resources into the SGEMM instruction sequence shown in Table 2. Table 3. Examples of multiply-add vector instructions [Table 3]

[0231] For the instructions in Table 3 above, the iteration count 2104 is 8. The supplied operand represents the initial operand of the first instruction in the set of expanded instructions. Operands for subsequent instructions are generated during expansion. In operand expansion: <dst>2106 and <src0>2107 consecutive registers, <src2>A block of 2109 consecutive sub-registers is used, with the number of consecutive registers / sub-registers determined based on the value of the iteration count 2104. Based on the value of the flags register, the expansion of certain instructions in the instruction set can be bypassed, for example when zero skipping is performed for sparse inputs.

[0232] As shown in Figure 21B, in one embodiment, instruction expansion is performed during decoding of the madv instruction, although other implementation techniques may be used in other embodiments, such as by direct execution of the instruction by an execute stage of the instruction execution pipeline. In one embodiment, the instruction decode logic 2110 in the processing resource may include a counter / state machine 2111, a priority encoder 2112, an instruction generator 2113, and an operand generator 2114 in addition to conventional instruction decode logic. The counter / state machine 2111 stores counter values ​​and decode states for use during expansion of the madv instruction. The priority encoder 2112 is used to scan the predicate to determine a first activated bit indicating a first mad instruction to be generated.

[0233] The proposed madv instruction can be implemented in the execution unit by adding a counter / state machine to the decode stage of the ALU pipe and generating a sequence of mad instructions. The priority encoder 2112 scans the predicate mask to find the first set bit. A mad instruction is generated by the instruction generator 2113 if the corresponding bit of that instruction is set in the predicate bit field. The operand generator 2114 then generates the corresponding operand value based on the initial operand register and sub-register values ​​and the bit positions set in the predicate mask. The execution of the madv instruction can be performed as shown in the pseudocode in Table 4 below. [Table 4]

[0234] The operand generator 2114 may generate the regnum and subregnum values ​​for the operands in a manner similar to that shown in the pseudocode of Table 4.

[0235] As shown in FIG. 21C, execution logic 2120 in a multithreaded processing resource may be configured to unpack and execute the madv instruction as described herein. The execution logic 2120 may be found in a multithreaded processing resource such as an execution unit, a compute unit, or a streaming multiprocessor as described herein. In one embodiment, a set of instruction queues 2122A-N may store a set of N instructions pending execution by the N threads of the execution logic 2120. Each thread has an associated pre-decode stage 2124A-N that halts execution of the thread until current instruction dependencies are cleared. A thread is marked as ready when no current instruction dependencies remain. Once cleared, the thread may participate in an arbitration process that selects the thread for dispatch to the execution pipeline of one of the ALUs.

[0236] Each ALU's respective arbiter 2126A-2126M may select one or more ready threads based on the availability of execution resources within the ALU. Instructions of the selected threads are then dispatched to the execution pipeline of the selected ALU. The illustrated ALU execution pipeline stages include decode stages 2128A-2128M, register read stages 2130A-2130M, execute stages 2132A-2132M, and writeback (WB) stages 2134A-2134M. In one embodiment, a single madv instruction may be expanded into multiple mad instructions within the decode stages 2128A-2128M of the ALU that receives the instruction.

[0237] In one embodiment, the number of ALUs in the execution logic 2120 is less than the number of threads that may be executed by the execution logic 2120. In one embodiment, multiple instructions may be issued to a single ALU. In one embodiment, only a subset of the available ALUs may be configured for madv instruction expansion, and such instructions are executed by those particular ALUs. The total number of clocks that the execution logic 2120 consumes to execute madv instructions depends on the number of clocks per mad instruction, the number of iterations, and the number of skipped instructions. In one embodiment, the ALUs of the execution logic may execute one mad instruction per clock. In such an embodiment, a madv.8 instruction takes 8 clocks to execute, minus 1 clock per skipped instruction when processing sparse input values.

[0238] 22 illustrates instruction expansion and skipping of sparse inputs according to one embodiment. In one embodiment, a compare instruction 2201 is used to: <src2>The register data used as input is compared to zero to generate the prediction mask used in the madv instruction 2202. In one embodiment, the expansion of the madv instruction is <src0>and <dst>Note the use of consecutive registers for the operands. During compilation of a shader program using the madv instruction, if not enough consecutive registers are available, the shader compiler can output multiple instructions 2203 with split iterations. For example, <src0>and <dst>Use different register starting points for the operands to output two instructions with a repeat count of 4, rather than one with a repeat count of 8. If multiple instructions are used, the instructions are <src1>and <src2>It can be performed as an atomic operation that allows for register reuse. <src2>Given 2109, instruction 2202, or instruction 2203, a set of mad instructions 2204 can be generated. <src2>It is possible to bypass instruction generation for sparse elements in 2109, thereby <src2>Not only is the execution of the mad instructions involving the elements bypassed, but the generation of the corresponding instructions is also bypassed, reducing the instruction fetch and decode bandwidth consumed by sparse matrix workloads.

[0239] In some cases, the SIMD size of a madv instruction may be larger than the register size, such that the result is written to multiple registers. In such cases, the expansion of the madv macro instruction results in the individual mad instructions being <dst>and <src0>is incremented by multiple registers. For example, when SIMD instruction=32, data type=4 bytes, and register width=64 bytes, <dst>and <src0>is incremented by (SIMD*data type / register width)=2 registers. Although the operations are generally described herein as SIMD operations, the techniques described herein may also be adapted to other parallel processing architectures, such as SIMD-based architectures.

[0240] For graphics processor architectures that include a dedicated accumulator register (the accX register), the madv instruction as described herein may be <src0>and <dst>Note that operands can use accumulator registers explicitly or implicitly. Accumulator registers can be larger and / or higher precision registers used to accumulate multiple floating-point operations. Using accumulator registers can produce more precise results depending on the precision of the input or output data types. If the number of accumulators in an architecture is limited, the results of one or more madv instructions can be stored in accumulators while others can be stored in general purpose registers.

[0241] Figure 23 illustrates a method 2300 for facilitating execution of a multiply / add / vector instruction, according to one embodiment. The method 2300 may be performed by logic of a computational or graphics processor pipeline of a graphics processor or parallel processor described herein. For example, the method 2300 may be performed by the execution logic 2120 of Figure 21C using the hardware logic 2110 of Figure 21B. The method 2300 may be used to facilitate execution of a hardware macro instruction, such as the madv instruction 2100 of Figure 21A, and / or as described herein.

[0242] In one embodiment, the method 2300 includes performing an operation of fetching a hardware macro instruction through hardware logic of a graphics or parallel processor (block 2301). The hardware macro instruction includes a predicate mask, an iteration count, and a set of initial operands ( <dst> 、 <src0> 、 <src1> 、 <src2>) in the instruction execution pipeline. The hardware macro instruction is configured to perform one or more multiply / add operations on input data associated with the set of matrices. The method 2300 further includes performing operations to decode the hardware macro instruction (block 2302). In one embodiment, the fetched hardware macro instruction may be stored in an instruction queue until logic in a pre-decode stage (e.g., pre-decode stages 2124A-2124N) of the instruction execution pipeline determines that a dependency, such as an associated load or compare instruction, has been satisfied. Once the dependency has been satisfied, the instruction may be automatically sent for decoding by decode logic of a processing resource as described herein.

[0243] The decoding process may at least partially include or include determining a set of hardware instructions to generate for execution. For example, a mad instruction may be generated for each activated bit of a predicate mask. The predicate mask may be, as shown in FIG. 22, <src2>It can be generated based on inputs stored in the operand subregisters. For example, using a compare instruction: <src2>A bit in a flags register can be set by comparing the data used as input with zero. The flags register can then be used as a predicate mask. The predicate mask and the iteration count can then be used to generate a set of hardware instructions for execution (block 2303). The instructions can be generated by the instruction generator 2113, as in FIG. 21B. The maximum number of instructions to be generated can be determined based on the iteration count. Generation of a particular hardware instruction is bypassed if disabled by an associated bit in the predicate mask.

[0244] The particular operands used by the generated instruction in the set of instructions may be determined based on the predicate mask and the set of initial operands (block 2304). The operands for the instruction may be generated by the operand generator 2114, as in FIG. <dst>and <src0>Consecutive consecutive registers are used for the operands, <src2>Consecutive sub-registers are used for the operands. No operands are generated for the bypassed instructions. The instruction execution pipeline of the graphics or parallel processor may then atomically execute the set of hardware instructions (block 2305). Atomic execution indicates that one or more operations performed during execution of the set of instructions are performed atomically, whereby the instructions in the set of instructions are considered as a single instruction. The specific number of clock cycles consumed by execution of the hardware macro-instruction may vary based on the number of cycles to perform a single multiply-add operation, the number of iterations associated with the instruction, and the number of instructions or operations bypassed due to sparse input data. The instruction execution pipeline of the graphics or parallel processor may then retire the hardware macro-instruction as each instruction in the set of hardware instructions is completed (block 2306).

[0245] Note that the number of execution cycles may vary depending on the sparsity of the input to the madv instruction. Thus, the latency of an instruction may not be determinable at compile time to allow for the scheduling of the next dependent instruction. Thus, the multiple instructions or operations performed by a madv instruction are viewed by the compiler and scheduling hardware as a single atomic instruction. Thus, for a set of consecutive dependent madv instructions, the instructions are executed in order such that the first madv instruction completes before the subsequent dependent instruction enters the execution pipeline.

[0246] Additional Exemplary Computing Devices

[0247] FIG. 24 is a block diagram of a computing device 2400 including a graphics processor 2404, according to one embodiment. The computing device 2400 may be a computing device such as the data processing system 100 as in FIG. 1 and may include the components shown in FIG. 14. The computing device 2400 may also be or be included in a communications device such as a set-top box (e.g., an Internet-based cable television set-top box, etc.), a global positioning system (GPS)-based device, etc. The computing device 2400 may also be or be included in a mobile computing device such as a mobile phone, a smartphone, a personal digital assistant (PDA), a tablet computer, a laptop computer, an e-reader, a smart television, a television platform, a wearable device (glasses, watches, bracelets, smart cards, jewelry, clothing, etc.), a media player, etc. For example, in one embodiment, the computing device 2400 includes a mobile computing device that uses an integrated circuit (IC), such as a system-on-chip (SoC or SOC), integrating various hardware and / or software components of the computing device 2400 on a single chip.

[0248] The computing device 2400 includes a graphics processor 2404. The graphics processor 2404 represents any of the graphics processors described herein. The graphics processor includes one or more graphics engines, graphics processor cores, and other graphics execution resources described herein. Such graphics execution resources may be represented in forms including, but not limited to, execution units, shader engines, fragment processors, vertex processors, streaming multiprocessors, graphics processor clusters, or any collection of computer resources suitable for processing graphics or image resources, or for general purpose computational processing on heterogeneous processors.

[0249] In one embodiment, the graphics processor 2404 includes a cache 2414, which may be divided into a single cache or multiple segments of cache memory, including, but not limited to, any number of L1, L2, L3, or L4 caches, rendering caches, depth caches, sampler caches, and / or shader unit caches. In some embodiments, the graphics processor 2404 includes a GPGPU engine 2444 that includes a shared local memory (SLM 2434), as well as a register file 2424 that includes registers used by the GPGPU engine 2444. The register file 2424 may include general purpose registers, architectural registers, configuration registers, and other types of registers. The general purpose register file (GRF) and / or architectural register file (ARF) may also reside within processing resources within one or more blocks of compute units (e.g., compute 2450, compute 2455) within the GPGPU engine 2444. Exemplary components may be used to provide the techniques of various embodiments described herein, including those that enable decoding and execution of the multiply-add-vector (madv) instructions described herein. In one embodiment, execution of madv instructions is facilitated via hardware-based decode / expand logic 2442 that expands madv instructions into multiple multiply-add (mad) instructions, although other embodiments may use different implementation techniques.

[0250] As shown, in one embodiment, in addition to the graphics processor 2404, the computing device 2400 may further include any number and type of hardware and / or software components, including, but not limited to, an application processor 2406, memory 2408, and input / output (I / O) sources 2410. The application processor 2406 may interact with a hardware graphics pipeline to share graphics pipeline functions, as shown with reference to FIG. 3. Processed data is stored in buffers of the hardware graphics pipeline, and state information is stored in memory 2408. The resulting data may be transferred to a display controller for output via a display device, such as the display device 318 of FIG. 3A. The display device may be of various types, such as a cathode ray tube (CRT), thin film transistor (TFT), liquid crystal display (LCD), organic light emitting diode (OLED) array, etc., and may be configured to display information to a user via a graphical user interface.

[0251] 1 and may be a central processing unit (CPU) used at least in part to execute an operating system (OS) 2402 of computing device 2400. OS 2402 may act as an interface between the hardware and / or physical resources of computing device 2400 and one or more users. OS 2402 may include driver logic for various hardware devices within computing device 2400, including graphics driver logic 2422, such as user mode graphics driver 1026 and / or kernel mode graphics driver 1029 of FIG. 10.

[0252] In some embodiments, the graphics processor 2404 may be part of the application processor 2406 (e.g., part of a physical CPU package), in which case at least a portion of the memory 2408 may be shared by the application processor 2406 and the graphics processor 2404, but at least a portion of the memory 2408 may be dedicated to the graphics processor 2404 or the graphics processor 2404 may have a separate memory store. The memory 2408 may include a pre-allocated area of ​​a buffer (e.g., a frame buffer). However, one skilled in the art should understand that the embodiments are not so limited and may use any memory accessible to the lower graphics pipeline. The memory 2408 may include various forms of random access memory (RAM) (e.g., SDRAM, SRAM, etc.), including applications that utilize the graphics processor 2404 to render desktop or 3D graphics scenes. A memory controller hub, such as the memory controller 116 of FIG. 1, may access data in the memory 2408 and transfer the data to the graphics processor 2404 for graphics pipeline processing. Memory 2408 may be made available to other components within computing device 2400. For example, any data received from various I / O sources 2410 of computing device 2400 (e.g., input graphics data) may be temporarily queued in memory 2408 before being processed by one or more processors (e.g., application processor 2406) in the implementation of a software program or application. Similarly, data that a software program determines needs to be transmitted from computing device 2400 to an external entity via one of the computer system interfaces or stored in an internal storage element is often temporarily queued in memory 2408 before being transmitted or stored.

[0253] The I / O sources may include devices such as a touch screen, touch panel, touch pad, virtual or conventional keyboard, virtual or conventional mouse, port, connector, network device, etc., and may be attached via a platform controller hub with reference to FIG. 1. Additionally, the I / O sources 2410 may include one or more I / O devices implemented to transfer data to and from the computing device 2400 (e.g., a networking adapter) or implemented for large scale non-volatile storage within the computing device 2400 (e.g., a hard disk drive). User input devices including alphanumeric and other keys may be used to communicate information and command selections to the graphics processor 2404. Another type of user input device is a cursor control such as a mouse, trackball, touch screen, touch pad, cursor direction keys, etc., which communicates directional information and command selections to the GPU and controls cursor movement on a display device. The camera and microphone array of the computing device 2400 may be used to observe gestures, record audio and video, and send and receive visual and voice commands.

[0254] An I / O source 2410 configured as a network interface may provide access to a network, such as a LAN, a wide area network (WAN), a metropolitan area network (MAN), a personal area network (PAN), Bluetooth, a cloud network, a cellular or mobile network (e.g., third generation (3G), fourth generation (4G), etc.), an intranet, the Internet, etc. A network interface may include, for example, a wireless network interface including one or more antennas. A network interface may also include a wired network interface that communicates with a remote device via a network cable, which may be, for example, an Ethernet cable, a coaxial cable, a fiber optic cable, a serial cable, or a parallel cable.

[0255] The network interface may provide access to a LAN, for example, by conforming to the IEEE 802.11 standard, and / or the wireless network interface may provide access to a personal area network, for example, by conforming to the Bluetooth standard. Other wireless network interfaces and / or protocols, including earlier and later standard versions, are also supported. In addition to or instead of communicating via a wireless LAN standard, the network interface may provide wireless communication using, for example, a time division multiple access (TDMA) protocol, a Global Systems for Mobile Communications (GSM) protocol, a code division, multiple access (CDMA) protocol, and / or other types of wireless communication protocols.

[0256] It should be understood that a lesser or more equipped system than the above examples may be preferred for a particular implementation. Thus, the configuration of computing device 2400 may vary from implementation to implementation depending on a number of factors, such as price constraints, performance requirements, technological improvements, or other circumstances. Examples include (but are not limited to) a mobile device, a personal digital assistant, a mobile computing device, a smart phone, a mobile phone, a handset, a one-way pager, a two-way pager, a messaging device, a computer, a personal computer (PC), a desktop computer, a laptop computer, a notebook computer, a handheld computer, a tablet computer, a server, a server array or server farm, a web server, a network server, an Internet server, a workstation, a minicomputer, a mainframe computer, a supercomputer, a network appliance, a web appliance, a distributed computing system, a multiprocessor system, a processor-based system, a consumer electronics product, a programmable consumer electronics product, a television, a digital television, a set-top box, a wireless access point, a base station, a subscriber station, a mobile subscriber center, a radio network controller, a router, a hub, a gateway, a bridge, a switch, a machine, or a combination thereof.

[0257] The embodiments may be implemented as any one or combination of a parent-board, hardwired logic, software stored by a memory device and executed by a microprocessor, firmware, one or more microchips or integrated circuits interconnected using an application specific integrated circuit (ASIC), and / or a field programmable gate array (FPGA). The term "logic" may include, by way of example, software or hardware, and / or a combination of software and hardware.

[0258] The embodiments may be provided, for example, as a computer program product that may include one or more machine-readable media having machine-executable instructions stored thereon, which when executed by one or more machines, such as a computer, a network of computers, or other electronic devices, may result in one or more machines performing operations according to the embodiments described herein. Machine-readable media include, but are not limited to, floppy disks, optical disks, CD-ROMs (compact disk read-only memory), and magneto-optical disks, ROMs, RAMs, EPROMs (erasable programmable read-only memory), EEPROMs (electrically erasable, programmable read-only memory), magnetic or optical cards, flash memories, or other types of non-transitory machine-readable media suitable for storing machine-executable instructions.

[0259] Additionally, embodiments may be downloaded as a computer program product, and the program may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) via a communications link (e.g., a modem and / or network connection) by one or more data signals embodied and / or modulated by a carrier wave or other propagation medium.

[0260] References in this specification to "one embodiment" or "embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the invention. The appearance of the phrase "in one embodiment" in various places in this specification does not necessarily all refer to the same embodiment. The processes illustrated in the following figures can be performed by processing logic including hardware (e.g., circuits, dedicated logic, etc.), software (as instructions in a non-transitory machine-readable storage medium), or a combination of both hardware and software. Reference will be made in detail to various embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art that the invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, circuits, and networks have not been described in detail so as not to unnecessarily obscure aspects of the embodiments.

[0261] It will also be understood that although terms such as first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first contact can be called a second contact, and similarly, a second contact can be called a first contact, without departing from the scope of the present invention. A first contact and a second contact are both contacts, but are not the same contact.

[0262] The terms used herein are intended to describe certain embodiments only and are not intended to be limiting with respect to all embodiments. When used in the description of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural, unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms "comprises," "having," "comprises," "comprising," "comprises ...

[0263] As used herein, the term "if" may be interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "upon determining" or "when (specified condition or event) is detected" may be interpreted to mean "upon determining" or "in response to determining" or "upon detecting (specified condition or event)" or "in response to detecting (specified condition or event)," depending on the context.

[0264] The embodiments described herein provide instructions and associated logic to enable a vector multiply-add instruction with automatic zero skip for sparse inputs. The following sections and / or examples relate to specific embodiments or examples thereof. Details of the examples may be used anywhere in one or more embodiments. Various features of different embodiments or examples may be combined in various ways with some features included and other features excluded to suit a variety of different applications. The examples may include subject matter such as a method, a means for performing the operations of the method, at least one machine-readable medium including instructions that, when executed by a machine, cause the machine to perform the operations of the method or the apparatus or system according to the embodiments and examples described herein. Various components may be means for performing the described operations or functions.

[0265] One embodiment provides a general purpose graphics processor including logic to perform a method including fetching a hardware macro instruction having a predicate mask, an iteration count, and a set of initial operands, the initial operand being a destination operand and a number of source operands (e.g., <src0> 、 <src1> 、 <src2>). The iteration count indicates the maximum number of hardware instructions to generate for the set of hardware instructions. The predicate mask indicates which instructions in the instruction set to generate or bypass. The predicate mask is a combination of zero and source input operands (e.g., <src2>) for each element associated with the set of matrices. The hardware macro instruction is configured to perform one or more multiplication and addition operations on input data associated with the set of matrices.

[0266] The method further includes decoding the hardware macro-instruction via the instruction decode logic. The step of decoding the hardware macro-instruction includes determining a set of hardware instructions to generate for execution and generating instructions within the set of instructions. The number of instructions and the particular instructions to generate can be determined based on the iteration count and a predicate mask. Unless the predicate mask indicates that generation of a particular instruction iteration should be skipped, a hardware instruction is generated for each specified iteration of the iteration count. The method further includes generating operands used by the generated instructions. The generated operands can specify simply successive and regularly consecutive registers or sub-registers within a block of registers or sub-registers, and the strides of the registers and sub-registers are determined based on the SIMD size of the instruction and the size of the register. The method further includes atomically executing the set of instructions and retiring the hardware macro-instruction when execution of each instruction in the set of instructions is completed. In one embodiment, the set of hardware instructions includes one or more hardware instructions, each of which causes the processing resource to perform a multiply and add operation in a single cycle, each of which performs a multiply and add operation on multiple data elements in a single cycle.

[0267] Additional embodiments provide graphics processing logic for performing the above methods. Additional embodiments also include data processing systems including the above graphics processing logic. The above techniques may be integrated or adapted into any of the graphics or parallel processor architectures described herein. Those skilled in the art will appreciate from the foregoing description that the broad techniques of the embodiments may be embodied in a variety of forms. Thus, although the embodiments have been described with reference to specific examples thereof, the true scope of the embodiments should not be so limited, as other modifications will become apparent to those skilled in the art upon review of the drawings, specification, and following claims. < / src1> < / src0> < / dst> < / src1> < / src0> < / dst> < / dst> < / dst> < / dst> < / dst> < / dst> < / dst> < / src1> < / src0> < / dst> < / pred> < / dst> < / dst> < / dst> < / src1> < / src0> < / dst> < / cmod> < / dst> < / pred> < / cmod> < / pred> < / src0> < / dst> < / opcode>

Claims

1. A graphics processor, comprising: an instruction fetcher for fetching a hardware macro-instruction having a predicate mask, an iteration count, and a set of initial operands, the hardware macro-instruction being an instruction for performing one or more multiplication and addition operations on inputs associated with a set of matrices; an instruction decoder that decodes the hardware macro instruction and generates a set of hardware instructions for performing one or more multiplication and addition operations, the set of hardware instructions being generated based on a predicate mask and the iteration count; a processing resource for executing the set of hardware instructions, the hardware macro-instructions being retired upon completion of the set of hardware instructions; Graphics processor.

2. The graphics processor of claim 1 , wherein the set of initial operands includes a destination operand and a plurality of source operands.

3. 3. The graphics processor of claim 2, wherein the set of hardware instructions includes one or more hardware instructions, each of the one or more hardware instructions being an instruction for causing the processing resource to perform a multiplication and addition operation in a single cycle.

4. 4. The graphics processor of claim 3, wherein each of the one or more hardware instructions is an instruction to perform the multiplication and addition operations on multiple data elements in the single cycle.

5. The graphics processor of claim 4 , wherein the number of iterations indicates a maximum number of hardware instructions to generate for the set of hardware instructions.

6. To generate the set of hardware instructions, the instruction decoder comprises: generating a first hardware instruction for an active bit in the predicate mask; 6. The graphics processor of claim 5, further comprising: a processor operable to bypass generation of the second hardware instruction for inactive bits in the predicate mask.

7. To generate the set of hardware instructions, the instruction decoder further comprises:

7. The graphics processor of claim 6, further comprising: generating a first set of operands for the first hardware instruction, the first set of operands indicating a destination register and a number of source registers used in the first hardware instruction, the first set of operands being generated based on the set of initial operands and an operand offset.

8. A graphics processor as claimed in any preceding claim, wherein the predicate mask comprises an active bit for each non-zero element associated with the source operand.

9. 1. A method of executing instructions on a graphics processor, the method comprising: fetching a hardware macro instruction having a predicate mask, an iteration count, and a set of initial operands, the hardware macro instruction being an instruction for performing one or more multiplication and addition operations on inputs associated with a set of matrices; decoding the hardware macro instruction into a decoded hardware macro instruction; generating, based on the decoded hardware macro instruction, a set of hardware instructions for performing one or more multiplication and addition operations, the set of hardware instructions being generated based on the predicate mask and the iteration count; executing the set of hardware instructions via processing resources of a graphics processor; and retiring the hardware macro-instruction when the set of hardware instructions is completed. method.

10. 10. The method of claim 9, wherein the set of initial operands includes a destination operand and a plurality of source operands.

11. 11. The method of claim 10, wherein the set of hardware instructions comprises one or more hardware instructions, each of the one or more hardware instructions causing the processing resource to perform a multiply and add operation in a single cycle.

12. 12. The method of claim 11, wherein each of the one or more hardware instructions performs the multiply and add operations on multiple data elements in the single cycle.

13. The method of claim 12 , wherein the iteration count indicates a maximum number of hardware instructions to generate for the set of hardware instructions.

14. The step of generating a set of hardware instructions comprises: generating a first hardware instruction for an active bit in the predicate mask; and bypassing generation of the second hardware instruction for inactive bits in the predicate mask.

15. The step of generating a set of hardware instructions further comprises:

15. The method of claim 14, further comprising generating a first set of operands for the first hardware instruction, the first set of operands indicating a destination register and a number of source registers used in the first hardware instruction, the first set of operands being generated based on the set of initial operands and an operand offset.

16. 16. A method as claimed in any one of claims 9 to 15, wherein the predicate mask comprises an active bit for each non-zero element associated with the source operand.

17. 1. A data processing system, comprising: a memory coupled to the bus; a graphics processor connected to the bus; The graphics processor includes: an instruction fetcher for fetching a hardware macro-instruction having a predicate mask, an iteration count, and a set of initial operands including a destination operand and a plurality of source operands, the hardware macro-instruction being an instruction for performing one or more multiplication and addition operations on inputs associated with a set of matrices; an instruction decoder that decodes the hardware macro instruction and generates a set of hardware instructions for performing one or more multiplication and addition operations, the set of hardware instructions being generated based on a predicate mask and the iteration count; a processing resource for executing the set of hardware instructions, the hardware macro-instructions being retired upon completion of the set of hardware instructions; Data processing system.

18. 20. The data processing system of claim 17, wherein the set of hardware instructions comprises one or more hardware instructions, each of the one or more hardware instructions being an instruction for causing the processing resource to perform a multiply and add operation in a single cycle.

19. 20. The data processing system of claim 18, wherein each of said one or more hardware instructions is an instruction to perform said multiply and add operations on multiple data elements in said single cycle.

20. 20. The data processing system of claim 19, wherein the iteration count indicates a maximum number of hardware instructions to generate for the set of hardware instructions.

21. To generate the set of hardware instructions, the instruction decoder comprises: generating a first hardware instruction for an active bit in the predicate mask; 21. The data processing system of claim 20, further comprising: bypassing generation of the second hardware instruction for inactive bits in the predicate mask.

22. To generate the set of hardware instructions, the instruction decoder further comprises:

22. The data processing system of claim 21, further comprising: generating a first set of operands for the first hardware instruction, the first set of operands indicating a destination register and a number of source registers used by the first hardware instruction, the first set of operands being generated based on the set of initial operands and an operand offset.

23. 23. A data processing system as claimed in any one of claims 17 to 22, wherein the predicate mask includes an active bit for each non-zero element associated with the source operand.

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