Input / Output (I / O) Circuit with Dynamic Full-Gate Boosting of Pull-Up and Pull-Down Transistors - Patent application

Abstract

One aspect of the present disclosure relates to an apparatus comprising an output driver including a first p-channel metal oxide semiconductor field effect transistor (PMOS FET), a second PMOS FET coupled in series with the first PMOS FET between an upper voltage rail and an output, a first n-channel metal oxide semiconductor field effect transistor (NMOS FET), and a second NMOS FET coupled in series with the first NMOS FET between the output and a lower voltage rail, a first pre-driver coupled to gates of the first PMOS FET and the second PMOS FET and the first NMOS FET and the second NMOS FET, and a second pre-driver coupled to gates of the first PMOS FET and the second PMOS FET and the first NMOS FET and the second NMOS FET.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This patent application claims priority to pending U.S. non-provisional application Ser. No. 17 / 526,805, filed November 15, 2021, and assigned to the assignee of this patent application, which is expressly incorporated by reference herein as if fully set forth below and for all applicable purposes.

[0002] Aspects of the present disclosure relate generally to input / output (I / O) drivers, and more particularly to I / O circuits with dynamic full-gate boosting of pull-up and pull-down transistors. [Background technology]

[0003] An input / output (I / O) circuit is typically used to convert an input signal in a first voltage domain to generate an output signal in a second voltage domain. A voltage domain is defined by the voltage levels of high and low logic voltage levels or states of a signal. An input / output (I / O) circuit may receive an input signal from a circuit configured to process a signal in the first voltage domain. An input / output (I / O) circuit may provide an output signal to a circuit configured to process a signal in the second voltage domain. A voltage level shift may be upward if the second voltage domain has at least one logic voltage level higher than at least one corresponding logic voltage level of the first voltage domain. Summary of the Invention

[0004] SUMMARY OF THE DISCLOSURE The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an exhaustive overview of all contemplated implementations, and is not intended to identify key or critical elements of all implementations or to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the Detailed Description presented later.

[0005] An aspect of the present disclosure relates to an apparatus including an output driver including a first p-channel metal oxide semiconductor field effect transistor (PMOS FET), a second PMOS FET coupled in series with the first PMOS FET between a first voltage rail and an output, a first n-channel metal oxide semiconductor field effect transistor (NMOS FET), and a second NMOS FET coupled in series with the first NMOS FET between the output and a second voltage rail, a first pre-driver coupled to gates of the first PMOS FET, the second PMOS FET, the first NMOS FET, and the second NMOS FET, and a second pre-driver coupled to gates of the first PMOS FET, the second PMOS FET, and the first NMOS FET, and the second NMOS FET.

[0006] Another aspect of the disclosure relates to a method, comprising: applying a first control signal to a gate of a first p-channel metal oxide semiconductor field effect transistor (PMOS FET) and applying a second control signal to a gate of a second PMOS FET coupled in series with the first PMOS FET between a first voltage rail and an output, where the first control signal and the second control signal are at a high logic voltage when an output signal at the output is in a low logic state, the first control signal and the second control signal are at a low logic voltage when the output signal is in a high logic state, and the first control signal and the second control signal are at a first set of boost voltages when the output signal is transitioning from the low logic state to the high logic state; applying a third control signal to a gate of a first n-channel metal oxide semiconductor field effect transistor (NMOS FET) and applying a second control signal to a gate of a second NMOS FET coupled in series with the first NMOS FET between the output and a second voltage rail. applying a fourth control signal to the gate of the FET, wherein when the output signal is in a high logic state, the third control signal and the fourth control signal are at a low logic voltage, when the output signal is in a low logic state, the third control signal and the fourth control signal are at a high logic voltage, and when the output signal is transitioning from the high logic state to the low logic state, the third control signal and the fourth control signal are at a second set of boosted voltages.

[0007] Another aspect of the disclosure relates to an apparatus comprising: means for applying a first control signal to a gate of a first p-channel metal oxide semiconductor field effect transistor (PMOS FET) and a second control signal to a gate of a second PMOS FET coupled in series with the first PMOS FET between a first voltage rail and an output, the first control signal and the second control signal being at a high logic voltage when an output signal at the output is in a low logic state, the first control signal and the second control signal being at a low logic voltage when the output signal is in a high logic state, and the first control signal and the second control signal being at a first set of boost voltages when the output signal is transitioning from the low logic state to the high logic state, means for applying a third control signal to a gate of a first n-channel metal oxide semiconductor field effect transistor (NMOS FET) and a second NMOS FET coupled in series with the first NMOS FET between the output and a second voltage rail. and means for applying a fourth control signal to the gate of the FET, wherein when the output signal is in a high logic state, the third control signal and the fourth control signal are at a low logic voltage, when the output signal is in a low logic state, the third control signal and the fourth control signal are at a high logic voltage, and when the output signal is transitioning from the high logic state to the low logic state, the third control signal and the fourth control signal are at a second set of boosted voltages.

[0008] Another aspect of the present disclosure relates to a wireless communication device. A wireless communication device includes at least one antenna, a transceiver coupled to the at least one antenna, and an integrated circuit (IC) coupled to the transceiver, the IC including one or more input / output (I / O) circuits, at least one of the one or more I / O circuits including an output driver including a first p-channel metal oxide semiconductor field effect transistor (PMOS FET), a second PMOS FET coupled in series with the first PMOS FET between an upper voltage rail and an output, a first n-channel metal oxide semiconductor field effect transistor (NMOS FET), and a second NMOS FET coupled in series with the first NMOS FET between the output and a lower voltage rail, a first pre-driver coupled to gates of the first PMOS FET and the second PMOS FET and the first NMOS FET and the second NMOS FET, and a first pre-driver coupled to gates of the first PMOS FET and the second PMOS FET and the first NMOS FET and the second NMOS FET. a second pre-driver coupled to the gate of the FET.

[0009] To the accomplishment of the foregoing and related ends, the one or more implementations comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more implementations. These aspects are indicative, however, of but a few of the various ways in which the principles of the various implementations may be employed, and the described implementations are intended to include all such aspects and their equivalents. [Brief description of the drawings]

[0010] [Figure 1A] 1 illustrates a schematic diagram of an exemplary input / output (I / O) driver in accordance with one embodiment of the present disclosure. [Figure 1B] 1B illustrates a timing diagram of example signals associated with the operation of the I / O driver of FIG. 1A in accordance with another aspect of the present disclosure. [Figure 2A]1 shows a block / schematic diagram of an exemplary input / output (I / O) circuit according to another embodiment of the present disclosure. [Figure 2B] 2B shows a timing diagram of example signals associated with the operation of the I / O circuit of FIG. 2A in accordance with another embodiment of the present disclosure. [Figure 3A] 1 shows a schematic diagram of another exemplary input / output (I / O) circuit according to another embodiment of the present disclosure. [Figure 3B] 3B shows a timing diagram of example signals associated with the operation of the I / O circuit of FIG. 3A in accordance with another embodiment of the present disclosure. [Figure 4] 2 illustrates a block diagram of an exemplary pull-down gate boost control circuit in accordance with another aspect of the present disclosure. [Diagram 5] 5 illustrates a schematic diagram of an example multi-domain logic circuit of the pull-down gate boost control circuit of FIG. 4 in accordance with another embodiment of the present disclosure. [Figure 6] 2 illustrates a block diagram of an exemplary pull-up gate boost control circuit in accordance with another aspect of the present disclosure. [Figure 7] 7 illustrates a schematic diagram of an example multi-domain logic circuit of the pull-up gate boost control circuit of FIG. 6 in accordance with another embodiment of the present disclosure. [Figure 8] 1 shows a schematic diagram of an exemplary first pull-up pre-driver according to another aspect of the present disclosure. [Figure 9] 1 shows a schematic diagram of an exemplary second pull-up pre-driver according to another embodiment of the present disclosure. [Figure 10] 1 shows a schematic diagram of an exemplary first pull-down pre-driver according to another embodiment of the present disclosure. [Figure 11] 1 shows a schematic diagram of an exemplary second pull-down pre-driver according to another embodiment of the present disclosure. [Figure 12] 4 shows a flow diagram of an exemplary method for voltage level shifting an input signal to generate an output signal in accordance with another aspect of the present disclosure. [Figure 13] 1 illustrates a block diagram of an exemplary wireless communication device according to another aspect of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The detailed description of the present invention, described below in connection with the accompanying drawings, is intended as an illustration of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description of the present invention includes specific details intended to provide a thorough understanding of the various concepts. However, it will be apparent to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0012] FIG. 1A illustrates a schematic diagram of an example input / output (I / O) driver 100 according to one embodiment of the present disclosure. The I / O driver 100 receives an input signal V from, for example, a core circuit of an integrated circuit (IC) or a system-on-chip (SOC). IN The input signal V IN can vary between a high logic voltage (eg, 1.1V) and a low logic voltage (eg, 0.5V) according to a first voltage domain or a core voltage domain.

[0013] Input signal V IN In response to the high and low logic voltages of the PX voltage domain, the I / O driver 100 outputs an output signal V that swings between a high logic voltage (e.g., 1.8V) and a low logic voltage (e.g., 0V) according to a second voltage domain or the PX voltage domain, respectively. OUT at an output (e.g., an I / O pad represented as an X in a square). As described in more detail below, the high and low logic voltages of the PX voltage domain may vary substantially between a power supply voltage VDDPX (applied to a first voltage rail) and a power supply voltage VSSX (applied to a second voltage rail). I / O driver 100 provides an output signal V to a load coupled between the output and the second voltage rail VSSX. OUT The load has a capacitance C LOADAs used herein, a voltage rail and a supply voltage provided to a voltage rail may be referred to by the same label for ease of discussion. Similarly, a node and a voltage at a node may be referred to by the same label for ease of discussion.

[0014] In this example, the I / O driver 100 has a first voltage rail VDDPX and an output V OUT and a pull-up circuit connected between the first voltage rail VDDPX and the output V OUT to generate the output signal V OUT to and stabilizing at a high logic voltage, such as a supply voltage VDDPX at substantially a first rail voltage (e.g., 1.8V). The pull-up circuit also couples the first voltage rail VDDPX to the output V OUT Separate or disconnect the output signal V OUT The pull-up circuit is configured to allow the pull-up voltage VSS to transition to and stabilize at a low logic voltage, such as substantially VSS at a second rail voltage (e.g., 0V or ground). In this example, the ... 11 and M 12 , resistance R P Includes PMOS FET M 11 is the output V OUT to and from the first rail voltage VDDPX, respectively. 11 A control signal V for turning on / off PCTL_HV respond to.

[0015] PMOS FET M in the pull-up circuit 12 is a substantially constant gate voltage V, which may be set to VDDPX / 2 (e.g., 0.9V). PBIAS In this configuration, the PMOS FET M 12 is a PMOS FET M 11For example, the control signal V PCTL_HV When V is substantially a low logic voltage such as VDDPX / 2 (e.g., 0.9V), the PMOS FET M 11 is its gate-source voltage (V GS ) (for example, 1.8V-0.9V=0.9V) is the threshold voltage V T (For example, 0.4V) is larger than the voltage, so it turns on. PMOS FET M 11 By turning on, VDDPX is effectively connected to the PMOS FET M 12 Therefore, the PMOS FET M 12 That V GS (For example, 1.8V-0.9V=0.9V) is the threshold voltage V T (for example, 0.4V) so they turn on. 11 and M 12 When the power supply is turned on, VDDPX is P The output of the I / O driver 100 is V OUT , thereby providing an output signal V OUT The resistor R P is a PMOS FET M 11 and M 12 Limiting the current through these devices prevents undue stress or damage to these devices.

[0016] Similarly, the control signal V PCTL_HV When is substantially at a high logic voltage such as VDDPX (e.g., 1.8V), the PMOS FET M 11 That V GS (For example, 1.8V-1.8V=0V) is the threshold voltage V T (for example, 0.4V) so it is turned off. 11 When the power supply is turned off, VDDPX is applied to the PMOS FET M 12 The source of the PMOS FET M 12 Decreasing the voltage at the source of V PBIAS Voltage V below the threshold voltagePI Therefore, the PMOS FET M 12 That V GS is the threshold voltage V T does not exceed 100V, so it turns off. 11 and M 12 When both are turned off, the output V OUT is substantially isolated from VDDPX, and the pull-down circuit of the I / O driver 100 drives the output signal V OUT is allowed to pull down so that the output signal transitions to substantially VSSX (eg, 0V) and stabilizes.

[0017] Output signal V OUT When is essentially VSSX, the PMOS FET M 12 The total voltage difference between VDDPX and VSSX is the PMOS FET M 11 , thereby preventing a voltage difference between the device M 11 Instead, the voltage difference (VDDPX-VSSX) is 11 and M 12 Therefore, the PMOS FET M 12 is a PMOS FET M 11 It acts as a buffer device for

[0018] The I / O driver 100 outputs V OUT and a second voltage rail VSSX. The pull-down circuit OUT to a second voltage rail VSSX to provide the output signal V OUT The pull-down circuit is also configured to transition and stabilize the output V OUT from the second voltage rail VSSX to provide an output signal V OUTThe pull-down circuit is configured to transition to a high logic voltage, for example, substantially the first rail voltage VDDPX, and stabilize there. In this example, the pull-down circuit is configured to transition to a high logic voltage, for example, substantially the first rail voltage VDDPX, and stabilize there. 13 and M 14 and resistor R N Includes NMOS M 14 is the output V OUT to the second voltage rail VSSX and to isolate the second voltage rail VSSX from the second voltage rail VSSX. 14 A control signal V for turning on and off NCTL_LV respond to.

[0019] NMOS FET M in the pull-down circuit 13 is a substantially constant gate voltage V, which may be set to VDDPX / 2 (e.g., 0.9V). NBIAS In this configuration, the NMOS FET M 13 is an NMOS FET M 14 For example, the control signal V NCTL_LV When is at a high logic voltage, e.g., VDDPX / 2 (e.g., 0.9V), the NMOS FET M 14 That V GS (For example, 0.9V-0V=0.9V) is the threshold voltage V T (e.g., 0.4V) is greater than the threshold voltage, so it turns on. 14 When the NMOS FET M 13 In response, the NMOS FET M 13 That V GS (For example, 0.9V-0V=0.9V) is the threshold voltage V T (for example, 0.4V) so they turn on. 13 and M 14 When turned on, VSSX is connected to resistor R N Effectively output V OUT , resulting in an output signal V OUTThe resistor R N Device M 13 and M 14 Limiting the current through the resistors prevents excessive stress or damage to the device.

[0020] Similarly, the control signal V NCTL_LV When is at a low logic voltage, e.g., VSSX (e.g., 0V), the NMOS FET M 14 That V GS (For example, 0V-0V=0V) is the threshold voltage V T (for example, 0.4V) so it is turned off. 14 When the switch is turned off, VSSX is connected to the NMOS FET M 13 The source of the NMOS FET M 13 Reduce the source of V NBIAS Therefore, the NMOS FET M 13 That V GS is the threshold voltage V T does not exceed 100V, so it turns off. 13 and M 14 When both are turned off, the output V OUT is disconnected from the second voltage rail VSSX. This enables the pull-up circuit to OUT to transition to and stabilize at a high logic voltage, such as substantially the first rail voltage VDDPX (eg, 1.8V).

[0021] Output signal V OUT When VDDPX, NMOS FET M 13 The total voltage difference between VDDPX and VSSX is the NMOS FET M 14 , thereby preventing a voltage difference between the device M 14 Instead, the voltage difference (VDDPX-VSSX) is 13 and M 14Therefore, the NMOS FET M 13 is an NMOS FET M 14 It acts as a buffer device for

[0022] In addition, the output signal V OUT , control signal V PCTL_HV , and the control signal V NCTL_LV Each logic voltage is in a different voltage domain. For example, V OUT The high and low logic voltages associated with the voltage domains vary substantially between VDDPX (e.g., 1.8V) and VSSX (e.g., 0V) (sometimes referred to herein as the PX voltage domains). PCTL_HV The high and low logic voltages associated with the voltage domains vary substantially between VDDPX (e.g., 1.8V) and VSSIX (e.g., 0.9V) (sometimes referred to herein as HV voltage domains). NCTL_LV The high and low logic voltages associated with a voltage domain range substantially between VDDIX (eg, 0.9V) and VSSX (eg, 0V) (sometimes referred to herein as the LV voltage domain).

[0023] 1B illustrates a timing diagram of example signals associated with the operation of the example I / O driver 100 in accordance with another aspect of the disclosure. The horizontal axis of the timing diagram represents time and is divided into four states or periods: (1) the output signal V OUT is at a steady-state high logic voltage VDDPX; (2) when the output signal V OUT (3) When the output signal V, shown in the third column from the left, is transitioning from a high logic voltage VDDPX to a low logic voltage VSSX; OUT is at a steady-state low logic voltage VSSX, (4) the output signal V OUT is transitioning from a low logic voltage, VSSX, to a high logic voltage, VDDPX.

[0024] The vertical axis of the timing diagram represents various signals of the I / O driver 100. For example, from top to bottom, the signals are: (1) PMOS FET M 11 The control signal V PCTL_HV (2) PMOS FET M 12 Gate bias voltage V PBIAS (3) PMOS FET M 12 The voltage at the source, V PI (4) Output signal V of I / O driver 100 OUT (5)NMOS FET M 13 Gate bias voltage V NBIAS ;(6)NMOS FET M 13 The voltage at the source, V NI ; and (7) NMOS FET M 14 The control signal V NCTL_LV .

[0025] In operation, as shown in the leftmost column of the timing diagram, the output signal V OUT During the state or period when V is a steady-state high logic voltage VDDPX, the control signal V PCTL_HV is the low logic voltage VSSIX (e.g., 0.9V), and the gate bias voltage V PBIAS Both PMOS FETs M 11 and M 12 A constant VDDPX / 2 voltage (e.g., 0.9V) is required to turn on each PMOS FET M 11 and M 12 When both are turned on, VDDPX is connected to the output V OUT , thereby causing the output signal V OUT The PMOS FET M 12 The voltage at the source, V PI is substantially equal to VDDPX (e.g., 1.8V). Furthermore, during this state or period, the control signal V NCTL_LV is an NMOS FET M 14 The NMOS FET M is at a low logic voltage VSSX (e.g., 0V) to turn it off. 13 Gate bias voltage VNBIAS is a constant VDDPX / 2 voltage (e.g., 0.9V). NMOS FET M 14 When the NMOS FET M 13 The voltage at the source, V NI V NBIAS Below the threshold voltage, e.g., >V NBIAS -V T (e.g., >0.5V). Therefore, the NMOS FET M 13 and M 14 Both are turned off and the output V OUT Separate or detach from VSSX.

[0026] As shown in the second column from the left, the output signal V OUT During the state or period in which the PMOS FET M is in transition from the high logic voltage VDDPX to the low logic voltage VSSX, 11 Control signal for V PCTL_HV rises to the high logic voltage VDDPX (for example, 1.8V) and the PMOS FET M 11 Turn off the PMOS FET M 12 Gate bias voltage V PBIAS remains constant at VDDPX / 2 (e.g., 0.9V). Therefore, the PMOS FET M 12 The voltage at the source, V PI decreases, V PBIAS Less than a threshold voltage above, e.g. <V PBIAS +V T (e.g., <1.3V). Therefore, PMOS FET M 11 and M 12 Both are turned off and the output V OUT Also, during this state or period, the control signal V NCTL_LV is an NMOS FET M 14 The NMOS FET M is turned on by raising the voltage to a high logic voltage VDDIX (for example, 0.9V). 14 The on-state of the NMOS FET M 13 The voltage at the source, V NIThe NMOS FET M 13 Gate bias voltage V NBIAS remains at VDDPX / 2 (for example, 0.9V). Therefore, the NMOS FET M 13 The gate-source voltage V GS is its threshold voltage V T This results in the NMOS FET M 13 Both NMOS FETs M 13 and M 14 When the output signal V OUT transitions to VSSX (eg, 0V) and substantially stabilizes there.

[0027] When the voltage transition occurs, the output signal V OUT During the state or period when the control signal V is substantially equal to VSSX, the voltage remains substantially constant. PCTL_HV is the high logic voltage V DDPX and the bias voltage V PBIAS is VDDPX / 2, and device M 11 and M 12 Keeping the output V OUT to the first voltage rail (V DDPX ) to separate or disconnect from the PMOS FET M 12 The voltage at the source, V PI V PBIAS Above the threshold voltage V T The control signal V NCTL_LV is at the high logic voltage VDDIX and at the bias voltage V NBIAS is a constant VDDPX / 2, and the device M 14 and M 13 Keep both on to generate the output signal V OUT The low logic voltage VSSX is applied to both devices. 13 and M 14 When the NMOS FET M 13 The voltage at the source, V NI becomes VSSX (e.g., 0V).

[0028] As shown in the fourth column from the left, the output signal V OUT During the state or period in which the PMOS FET M is in transition from the low logic voltage VSSX to the high logic voltage VDDPX, 11 Control signal for V PCTL_HV is a PMOS FET M 11 The PMOS FET M is pulled to a low logic voltage VSSIX (e.g., 0.9V) to turn it on. 12 Gate bias voltage V PBIAS remains constant at VDDPX / 2 (e.g., 0.9V). Therefore, the PMOS FET M 11 and M 12 Therefore, both the PMOS FET M 12 The voltage at the source, V PI and output signal V OUT Also, during this state or period, the control signal V NCTL_LV is an NMOS FET M 14 The NMOS FET M is pulled to a low logic voltage VSSX (e.g., 0V) to turn it off. 13 Gate bias voltage V NBIAS remains constant at VDDPX / 2 (e.g., 0.9V). Therefore, the NMOS FET M 13 The voltage at the source, V NI V NBIAS , for example, to >0.5V. Therefore, the NMOS FET M 13 Gate-source voltage V GS is its threshold voltage V T Therefore, the NMOS FET M 13 Turn off the NMOS FET M 13 and M 14 Both are output signals V OUT Once the voltage transition occurs, the output signal V OUT is the high logic voltage V DDPXDuring this state or period, the voltage remains substantially constant.

[0029] There are some problems with the I / O driver 100. For example, 11 , M 12 , M 14 , and M 13 If the I / O devices in an IC or SOC are manufactured according to a certain technology node (e.g., to use the same technology node for all other non-I / O devices (e.g., core devices) in the IC or SOC), then any terminal (V GS , V GD , and V DS ) may be approximately 1.3 V. If devices are exposed to voltages that exceed the 1.3 V reliability limit for extended periods of time (e.g., more than a few picoseconds (ps)), recoverable or irrecoverable damage may occur to these devices. Such damage may result from negative bias temperature instability (NBTI) or hot carrier injection (HCI). As a result, the device may experience reduced performance and functionality, or may fail completely.

[0030] Referring again to FIG. 1B, as shown in the leftmost and rightmost columns of the timing diagram, the output signal V OUT When V is at high logic voltage VDDPX, the NMOS FET M 13 The voltage at the drain of the NMOS FET M 13 The voltage at the source of the NMOS FET M is 0.5V. 13 The voltage difference between the drain and source of the DS ) is 1.3V. As explained earlier, the NMOS FET M 13 This 1.3V voltage difference across nearly exceeds the 1.3V reliability limit when this device is manufactured according to the particular implementation.

[0031] Furthermore, as shown in the second column from the left, the output signal V OUT During the state or period when VDDPX is in transition to VSSX, 13The voltage at the source, V NI is generally the output V OUT The larger capacitive load C LOAD Due to this, the output signal V OUT The NMOS FET M 13 The voltage difference between the drain and source of DS is the output signal V from VDDPX to VSSX OUT During a transition, the supply voltage may increase to approximately 1.5V, again exceeding the reliability limit of 1.3V if the device is manufactured according to a particular implementation.

[0032] Similarly, as shown in the third column from the left, the output signal V OUT When V is a low logic voltage, the PMOS FET M 12 The voltage at the drain of the PMOS FET M is substantially VsSX (e.g., 0V). 12 The voltage at the source of the PMOS FET M is 1.3V. 12 The voltage difference between the drain and source of the DS ) is 1.3V. As mentioned before, PMOS FET M 12 This 1.3V voltage difference across nearly exceeds the 1.3V reliability limit for this device when manufactured according to the particular implementation.

[0033] Similarly, as shown in the fourth column from the left, the output signal V OUT During the state or period when the PMOS FET M 12 The voltage at the source, V PI is generally the output V OUT The larger capacitive load C LOAD Due to this, the output signal V OUT increases from 0V to 1.8V much faster than it increases from 1.3V to 1.8V. As a result, the PMOS FET M 12 The voltage difference between the drain and source of DSis the output signal V from VSSX to VDDPX OUT During the transition, the resistor R increases to approximately 1.5 V, again exceeding the reliability limit of 1.3 V if the device is manufactured according to the particular implementation. P and R N is a PMOS FET M 12 and NMOS FET M 13 V DS However, the resistor R P and R N may be undesirable because it takes up a significant IC footprint and generates unwanted electromagnetic (EM) energy.

[0034] FIG. 2A shows a schematic diagram of an input / output (I / O) circuit 200 according to another embodiment of the present disclosure. One difference between the I / O circuit 200 and the I / O driver 100 is that the I / O circuit 200 does not include a PMOS FET M 12 and NMOS FET M 13 The gate voltage applied to the output signal V OUT is changed or boosted during a transition from a high logic voltage to a low logic voltage and a transition from a low logic voltage to a high logic voltage, respectively. OUT During the transition of 12 and M 13 This is done to reduce the maximum voltage across each of the I / O circuits 200 below their respective reliability limits. 12 and M 13 A bias voltage is applied to the source of the output signal V OUT are at steady-state high and low logic voltages, respectively, to prevent overvoltage of such devices.

[0035] In summary, the I / O circuit 200 receives an input voltage V IN The input voltage V IN may vary between a high logic voltage and a low logic voltage according to a first (e.g., core) voltage domain. INIn response to the high and low voltages of V, I / O circuit 200 generates an output signal V that swings between a high logic voltage and a low logic voltage according to a second (e.g., PX) voltage domain, respectively. OUT The high and low logic voltages of the second voltage domain may be substantially equal to VDDPX and VSSX. The I / O circuit 200 generates a capacitance C LOAD A load with an output signal V OUT supplies.

[0036] More specifically, the I / O circuit 200 is connected to a first voltage rail VDDPX and an output V OUT A PMOS FET M 21 and M 22 Similarly, the output driver includes a pull-up circuit including an output V OUT and a second voltage rail VSSX. 23 and M 24 The pull-down circuit includes a pull-down circuit including:

[0037] The I / O circuit 200 receives an input signal V IN In response to the control signal V PCTL_HV As previously mentioned, the first PMOS pre-driver 210 is configured to generate V PCTL_HV The HV voltage domain of the I / O circuit 200 varies between a low logic voltage VSSIX (e.g., VDDPX / 2) and a high logic voltage VDDPX. IN In response to the control signal V LV The second PMOS pre-driver 211 is configured to generate a LV The LV voltage domain of varies between the low logic voltage VSSX and the high logic voltage VDDIX. Therefore, the input voltage V IN When is low, V PCTL_HV is in VDDPX, and V LV The input voltage V IN When is high, V PCTL_HV is in VSSIX, V LV is in VSSX.

[0038] Similarly, the I / O circuit 200 receives an input signal V IN In response to the control signal V NCTL_LV The first NMOS pre-driver 220 is configured to generate a V NCTL_LV The LV voltage domain of the I / O circuit 200 varies between a low logic voltage VSSX and a high logic voltage VDDIX. IN In response to the control signal V HV The second NMOS pre-driver 221 is configured to generate V HV The HV voltage domain of varies between the low logic voltage VSSIX and the high logic voltage VDDPX. Therefore, the input voltage V IN When is low, V NCTL_LV is in VDDIX, and V HV is at VDDPX. Input voltage V IN When is high, V NCTL_LV is in VSSX, V NCTL_HV is in VSSIX.

[0039] The control signal V generated by the first PMOS pre-driver 210 PCTL_HV is a PMOS FET M 21 Gate and V PI The control signal V generated by the second PMOS pre-driver 211 is applied to the voltage generator 214. LV V PCTL_LV The control signal V generated by the first NMOS pre-driver 220 is applied to the first NMOS pre-driver 212. NCTL_LV is an NMOS FET M 24 Gate and V NI The control signal V generated by the second NMOS pre-driver 221 is applied to the voltage generator 224. HV V NCTL_HV The voltage V V is applied to the pre-driver 222. PCTL_LV The pre-driver 212 is V LV and V OUT Based on the control signal V PCTL_LV The control signal V PCTL_LV is a PMOS FET M 22Similarly, V NCTL_HV The pre-driver 222 is V HV and V OUT Based on the control signal V NCTL_HV The control signal V NCTL_HV is an NMOS FET M 23 is applied to the gate of

[0040] V PI The voltage generator 214 is V PCTL_HV and V OUT Based on the voltage V PI It is configured to generate a voltage V PI is a PMOS FET M 22 The output signal V OUT is the steady-state low logic voltage VSSX, the voltage V PI is a PMOS FET M 22 For example, to protect the output signal V OUT When V is a steady-state low logic voltage (e.g., 0 V), the voltage V PI is substantially VDDIX (e.g., 0.9V). PI Due to this, the PMOS FET M 22 Drain-source voltage V DS is, for example, 0.9V, which is lower than the maximum reliability voltage of the device, for example, 1.3V.

[0041] Similarly, V NI The voltage generator 224 is V NCTL_LV and V OUT Based on the voltage V NI It is configured to generate a voltage V NI is an NMOS FET M 23 The voltage V NI is the output signal V OUT When is at the steady-state high logic voltage VDDPX, the NMOS FET M 23 For example, to protect the output signal V OUT When V is a steady-state high logic voltage VDDPX (for example, 1.8 V), the voltage V NIis essentially VDDIX (for example, 0.9V). NI Due to this, the NMOS FET M 23 Drain-source voltage V DS is, for example, 0.9V, which is lower than the maximum reliability voltage of the device, for example, 1.3V.

[0042] FIG. 2B illustrates a timing diagram associated with an exemplary operation of the I / O circuit 200 according to another embodiment of the present disclosure. For illustrative purposes, VDDPX is 1.8V, VDDIX / VSSIX is 0.9V, and VSSX is 0V. Also for illustrative purposes, the device M 21 , M 22 , M 22 , and M 21 V DS , V GS , and V DG The maximum reliable voltage of I / O circuit 200 is, as mentioned above, 1.3 V. It should be understood that such voltages and maximum reliable voltages may vary in various implementations based on the type of device and application used for I / O circuit 200.

[0043] Similar to the graph of FIG. 1B, the horizontal axis of the timing diagram represents time and is divided into four states or periods: (1) the output signal V OUT is a steady-state high logic voltage VDDPX; (2) when the output signal V OUT (3) When the output signal V, shown in the third column from the left, is transitioning from a high logic voltage VDDPX to a low logic voltage VSSX; OUT is at a steady-state low logic voltage VSSX, (4) the output signal V OUT is transitioning from a low logic voltage, VSSX, to a high logic voltage, VDDPX.

[0044] The vertical axis of the timing diagram represents various signals of the I / O circuit 200. For example, from top to bottom, the signals are: (1) PMOS FET M 21 The control signal V PCTL_HV (2) PMOS FET M22 Gate bias voltage V PCTL_LV ;(3) Output signal V OUT (4) NMOS FET M 23 Gate bias voltage V NCTL_HV ; and (5) NMOS FET M 24 The control signal V NCTL_LV .

[0045] As shown by the leftmost and rightmost columns, the output signal V OUT When V is at a high logic voltage VDDPX (e.g., 1.8V), the control signal V PCTL_HV is a PMOS FET M 21 A low logic voltage VSSIX (e.g., 0.9V) is required to turn on the PMOS FET M 22 The voltage at the source, V PI is VDDPX (for example, 1.8V), and the control signal V PCTL_LV is a non-boosted voltage (e.g., 0.9V) and the PMOS FET M 21 In response to the on-state of the PMOS FET M 22 Therefore, the output signal V OUT is the PMOS FET M 21 and M 22 Output V via OUT VDDPX (e.g., 1.8V) due to a first voltage rail VDDPX coupled to the output signal V OUT When V is at a high logic voltage VDDPX (e.g., 1.8V), the control signal V NCTL_LV is an NMOS FET M 24 A low logic voltage VSSX (e.g., 0V) is used to turn off the NI is an NMOS FET M 23 V DS below its reliability limit, and the control signal V NCTL_HV is the non-boosted voltage VSSIX (for example, 0.9V), and the NMOS FET M 23 Therefore, the output V OUT is the NMOS FET M 23 and M24 from the second voltage rail VSSX.

[0046] As shown in the second column from the left, the output signal V is converted from a high logic voltage VDDPX (1.8 V) to a low logic voltage VSSX (0 V). OUT In order to transition the control signal V NCTL_LV is changed from a low logic voltage VSSX (e.g., 0V) to a high logic voltage VDDIX (e.g., 0.9V), and the NMOS FET M 24 Turn on V NCTL_LV At the same time that the bias voltage V NCTL_HV is boosted from a non-boosted voltage (e.g., about VSSIX (e.g., 0.9V)) to a boosted voltage (e.g., VSSIX + about 0.5V = about 1.4V). OUT When first transitions from high to low, the boost voltage is 23 and M 24 , V OUT A voltage drop of 1.8V occurs between V and V. 23 and M. 24 Therefore, each device experiences a voltage drop of effectively 0.9V, which is less than the 1.3V reliability limit.

[0047] Output signal V OUT When V drops to a certain voltage level, the control signal V NCTL_HV is returned to the non-boosted voltage (for example, approximately VSSIX (0.9V)). NCTL_HV During the period when is the boost voltage (for example, about 1.4V), the NMOS FET M 23 For example, if the period is too short, the NMOS FET M 23 That V DS On the other hand, if the period is too long, the device M 23 is its gate-source voltage (V GS) and / or gate-drain voltage (V GD ) may be subject to overvoltage due to exceeding its reliability limit.

[0048] The period is the output signal V OUT Such speed depends on the rate at which V V decreases from V DPX to V SSX. LOAD It depends on the capacitance of the load, C LOAD When is relatively small, the output signal V OUT The period should be relatively short because the rate at which the capacitance of the load, C, decreases is relatively fast. LOAD When is relatively large, the output signal V OUT Since the rate at which V decreases is relatively slow, the period should be relatively long. NCTL_HV The pre-driver 222 outputs the output signal V OUT Based on how quickly the V transitions from high to low, the boosted V NCTL_HV Generate a voltage.

[0049] Furthermore, the output signal V is from a high logic voltage VDDPX (for example, 1.8V) to a low logic voltage VSSX (0V). OUT To facilitate the transition of the control signal V PCTL_HV is changed from a low logic voltage VSSIX (e.g., 0.9V) to a high logic voltage VDDPX (e.g., 1.8V), and the PMOS FET M 21 Turn off the output signal V OUT In response to a voltage decrease to a certain voltage level, V PI The voltage generator 214 generates a voltage V PI PMOS FET M 22 The control signal V applied to the gate of PCTL_LV is the high-to-low output signal V OUT Since VDDIX is kept constant (e.g., 0.9V) during the transition of 22 That V GS is essentially 0V, so the output signal V OUTDuring the high-to-low transition of 21 and M 22 This disconnects the output from the first voltage rail VDDPX.

[0050] As shown in the third column from the left, the output signal V OUT When the control signal V is at a steady-state low logic voltage VSSX (0V), NCTL_LV is the high logic voltage VDDIX (for example, 0.9V), and the NMOS FET M 24 keeps on, and the control signal V NCTL_HV is the non-boosted voltage VDDIX (for example, 0.9V), and the NMOS FET M 23 Therefore, the output signal V OUT is the NMOS FET M 23 and M 24 VSSX (0V) from the second voltage rail via . Therefore, the voltage V NI Also, the output signal V OUT When the control signal V is at a steady-state low logic voltage VSSX (0V), PCTL_HV is a PMOS FET M 21 is a high logic voltage VDDPX (e.g., 1.8V) to keep the PI As explained, PMOS FET M 22 VSSIX (e.g., 0.9V) to protect V from overvoltage, and the control signal V PCTL_HV is a PMOS FET M 22 The output of the I / O circuit 200 is the non-boosted voltage VDDIX (e.g., 0.9V) that keeps the turned-off PMOS FET M 21 and M 22 VDDPX from the first voltage rail VDDPX via

[0051] As shown in the fourth column from the left, the output signal V goes from a low logic voltage VSSX (e.g., 0V) to a high logic voltage VDDPX (e.g., 1.8V). OUT In order to transition the control signal V PCTL_HVis changed from a high logic voltage VDDPX (e.g., 1.8V) to a low logic voltage VSSIX (e.g., 0.9V), and the PMOS FET M 21 Turn on V PCTL_HV At the same time that the control signal V PCTL_LV changes from a non-boosted voltage (e.g., 0.9 V) to a boosted voltage (e.g., about 0.4 V). This means that the output signal V OUT When the first transitions from low to high, the PMOS FET M 21 and M 22 This is done to configure the turn-on resistance of each of the V and V to be more equal (e.g., substantially the same). In this example, this OUT The 1.8V voltage drop between the PMOS FET M 21 and M 22 Therefore, each device experiences a voltage drop of effectively 0.9V, which is less than the 1.3V reliability limit.

[0052] Output signal V OUT When the voltage rises to a certain level, the control signal V PCTL_LV is returned to a non-boosted voltage (e.g. VDDIX (e.g. 0.9V)). PCTL_LV During the period when is the boost voltage (for example, about 0.4V), the PMOS FET M 22 For example, if the period is too short, the PMOS FET M 22 That V DS On the other hand, if the period is too long, the device M 22 is the gate-source voltage (V GS ) and / or gate-drain voltage (V GD ) may be subject to overvoltage due to exceeding its reliability limit.

[0053] The period is the output signal V OUT Such speed depends on the rate at which VSS increases from VSSX to VDDPX. Such speed depends on the capacitive load C coupled to the output of the I / O circuit 200.LOAD It depends on the capacitance of the load, C LOAD When is relatively small, the output signal V OUT The period should be relatively short because the rate at which the capacitance of the load, C, increases is relatively fast. LOAD When is relatively large, the output signal V OUT Since the rate at which V increases is relatively slow, the period should be relatively long. Therefore, V PCTL_LV The pre-driver 212 outputs the output signal V OUT Based on how quickly the V transitions from low to high, the boosted V PCTL_LV Generate a voltage.

[0054] Furthermore, the output signal V V is a voltage from a low logic voltage VSSX (e.g., 0V) to a high logic voltage VDDPX (e.g., 1.8V). OUT To facilitate the transition of the control signal V NCTL_LV changes from a high logic voltage VDDIX (e.g., 0.9V) to a low logic voltage VSSX (e.g., 0V) and the NMOS FET M 24 Turn off the output signal V OUT In response to V rising to a certain voltage level, NI The voltage generator 224 generates a voltage V NI is generated substantially at VDDIX (for example, 0.9V). NMOS FET M 23 The control signal V applied to the gate of NCTL_HV is the low-to-high output signal V OUT During the transition of VSSIX, the voltage of the NMOS FET M 23 That V GS is essentially 0V, so the output signal V OUT During the low-to-high transition of 21 and M 22 This disconnects the output from the second voltage rail VSSX.

[0055] There are several problems with I / O circuit 200. First, the output signal V OUTThere is only one gate boost during each transition of the NMOS FET M 23 is the output signal V OUT It is the only device that is boosted during the high-to-low transition of the PMOS FET M 22 is the output signal V OUT This is the only device that is boosted during the low-to-high transition of the I / O driver. Boosting more than one FET during the transition creates a faster transition, allowing the I / O driver to operate faster.

[0056] Second, as shown in FIG. 2B, the gate boost in I / O circuit 200 is only about 30 percent (%) of the duration of the transition. Providing a higher percentage of the boost period during each transition would also hasten the transition, again allowing the I / O driver to operate faster. A further drawback of a relatively short boost duration (e.g., 30%) is that the output impedance changes during each transition. For example, during the boost period, the output impedance is significantly less than during the remainder of the transition or during the non-boosted period. The change in output impedance during each transition is a function of the output signal V OUT This can cause signal integrity (SI) problems in the

[0057] Third, the pull-up circuit (e.g., PMOS FET M 21 and M 22 ) and pull-down circuit (e.g., NMOS FET M 23 and M 24 ) are driven by different domain signals. For example, the PMOS FET M 21 and M 22 are the control signals V in the HV and LV voltage domains, respectively. PCTL_HV and V PCTL_LV Similarly, the pull-down circuit's NMOS FET M 23 and M 24 are the control signals V in the HV and LV voltage domains, respectively. NCTL_HV and V NCTL_LVBecause the HV and LV domain signals propagate through different transmission paths, there may be delay mismatch between these signals. This can be caused by the operation (e.g., the output signal V OUT This can have adverse effects on device performance (causing duty cycle distortion in the device) and reliability (e.g., subjecting the FET to overvoltage stress or damage). As an example, during a low-to-high transition, PCTL_HV The rising edge of V PCTL_LV If it arrives before the falling edge of 22 may be stressed or damaged by overvoltage, or V PCTL_HV The rising edge of V PCTL_LV If it arrives after the falling edge of 21 The same adverse effect can occur when the NMOS FET M 23 and M 24 also applies.

[0058] 3A illustrates a schematic diagram of another exemplary input / output (I / O) circuit 300 according to another aspect of the disclosure. In summary, the I / O circuit 300 uses one or more pre-drivers that boost both or all FETs in the pull-up and pull-down circuits of the I / O circuit 300 during rising and falling transitions, respectively. This allows for faster transitions and improves the speed of the I / O circuit 300.

[0059] Furthermore, the pre-driver(s) boost both or all of the FETs in the pull-up and pull-down circuits for a longer percentage (e.g., 80%) of the transition period. Again, this also enables faster transitions and faster speed performance of the I / O circuit 300. In addition, the longer boost period during the transition reduces the effect of output impedance changes. This reduces the output signal V OUT The signal integrity (SI) degradation of the

[0060] In addition, the control signal V PCTL_HV and V PCTL_LV, or the control signal V of the pull-down circuit NCTL_HV and V NCTL_LV The generation of is responsive to a single domain signal, which, as previously mentioned, is the output signal V OUT This prevents or reduces delay mismatch between signals that can cause duty cycle distortion in and overvoltage stress or damage to the output driver FETs. Additionally, the current load requirements for the intermediate voltage rails VDDIX or VSSIX are reduced by implementing a pre-driver involved in the transition that uses only the VDDPX voltage rail, which may already be configured to handle a higher current load.

[0061] In particular, the I / O circuit 300 includes a voltage level shifter 310, a gate boost control circuit 320, a steady state pre-driver 330, a transition pre-driver 340, an output driver 350, and a voltage domain splitter 360. The voltage level shifter 310 converts an input signal V IN and configured to receive an input signal V IN may be in an IC or SOC core voltage domain, sometimes referred to herein as the CX domain, where the voltage varies between a logic high (e.g., 1.1 V) at VDDCX and a logic low (e.g., 0.5 V) at VSSCX. The voltage level shifter 310 shifts the input signal V IN to voltage level shift the input signal V IN_HV and V IN_LV The input signal V IN_HV The input signal V may vary between a high logic voltage VDDPX (e.g., 1.8 V) and a low logic voltage VSSIX (e.g., 0.9 V). IN_LV can vary between a high logic voltage VDDIX (eg, 0.9V) and a low logic voltage VSSX (eg, 0V).

[0062] The gate boost control circuit 320 controls the PMOS FET M 21 and M 22 , and the pull-down circuit NMOS FET M 23 and M 24The gate boost enable signal V TR_LV and V TF_HV As shown, an output driver 350 may be configured for each output driver of the I / O circuit 200. The gate boost control circuit 320 generates an input signal V IN _ HV and V IN _ LV and the output signal V OUT The output voltage signal V generated by the voltage domain splitter 360 by splitting the PX voltage domain of OUT_HV and V OUT_LV Based on and, the gate boost enable signal V TR_LV and V TF_HV As indicated by the subscript, the output signal V OUT_HV is in the HV voltage domain, and the output signal V OUT_LV is in the LV voltage domain. As will be explained in more detail herein, the associated signal V IN_HV and V IN_LV Input signal V via IN initiates the start of the gate boost period and the associated signal V OUT_HV and V OUT_LV Output signal V via OUT ends the gate boost period.

[0063] The steady-state pre-driver 330 controls the PMOS FET M of the output driver 350 during the steady-state period. 21 and M 22 and NMOS FET M 23 and M 24 Control signal for V PCTL_HV , V PCTL_LV , V NCTL_HV , and V NCTL_LV The steady state period is configured to generate an output signal V OUT is not transitioning from one logic level or state to another. As described in more detail herein, the steady-state pre-driver 330 IN_HV and V IN_LVand gate boost enable signal V TR_LV and V TF_HV Based on this, the control signal V PCTL_HV , V PCTL_LV , V NCTL_HV , and V NCTL_LV Generate.

[0064] Referring to the timing diagram of FIG. 3B, the output signal V OUT When V is a steady-state high logic voltage VDDPX (e.g., 1.8V), the steady-state pre-driver 330 supplies the control signal V PCTL_HV , V PCTL_LV , V NCTL_HV , and V NCTL_LV , respectively at a low logic voltage VSSIX (e.g., 0.9V), a non-boosted voltage (e.g., 0.9V), a non-boosted voltage (e.g., 0.9V), and a low logic voltage VSSX (e.g., 0V). These voltage levels are generated by the PMOS FET M 21 and M 22 Turn on the NMOS FET M 23 and M 24 Turn off the output signal V OUT During the VDDPX steady state period, the gate boost control circuit 320 controls the gate boost enable signal V TR_LV and V TF_HV Note that these are in the LV and HV voltage domains and relate to rising and falling transitions, respectively, at their deasserted low VSSX (e.g., 0V) and high logic states VDDPX (e.g., 1.8V).

[0065] Output signal V OUT When V is a steady-state logic low voltage VSSX (e.g., 0V), the steady-state pre-driver 330 outputs the control signal V at a high logic voltage VDDPX (e.g., 1.8V), a non-boosted voltage (e.g., 0.9V), a non-boosted voltage (e.g., 0.9V), and a high logic voltage VDDIX (e.g., 0.9V). PCTL_HV , V PCTL_LV , V NCTL_HV , and V NCTL_LVThese voltage levels are generated by the PMOS FET M 21 and M 22 Turn off the NMOS FET M 23 and M 24 Turn on the output signal V OUT Similarly, during the VSSX steady state period, the gate boost control circuit 320 controls the gate boost enable signal V TR_LV and V TF_HV , respectively, in a deasserted low VSSX (eg, 0V) and high VDDPX (eg, 1.8V) logic state.

[0066] The transition pre-driver 340 drives the PMOS FET M of the output driver 350 during the transition period. 21 and M 22 and NMOS FET M 23 and M 24 Control signal for V PCTL_HV , V PCTL_LV , V NCTL_HV , and V NCTL_LV The transition period is configured to generate an output signal V OUT is transitioning from one logic level or state to another. As described in more detail herein, the transition pre-driver 340 controls the gate boost enable signal V TR_LV and V TF_HV Based on the control signal V PCTL_HV , V PCTL_LV , V NCTL_HV , and V NCTL_LV Generate.

[0067] Referring to the timing diagram of FIG. 3B, the input signal V IN_HV and V IN_LV The output signal V OUT When the gate boost enable signal V TF_HVat its asserted low logic state VSSIX (e.g., 0.9V) and the gate boost enable signal V TR_LV The deasserted gate boost enable signal V TR_LV In response, the steady-state pre-driver 330 drives the control signal V at a high logic voltage VDDPX (e.g., 1.8V) and a non-boosted voltage (e.g., 0.9V). PCTL_HV and V PCTL_LV These voltage levels are generated by the PMOS FET M 21 and M 22 Turn off.

[0068] Asserted Gate Boost Enable signal V TF_HV In response to this, the transition pre-driver 340 drives the control signal V NCTL_HV and V NCTL_LV These voltage level control signals are used to generate the NMOS FET M 23 and M 24 turn on the output signal V OUT During the steady-state low logic state VSSX of the NMOS FET M 23 and M 24 The turn-on resistance of the NMOS FET M must be less than that when driven by 0.9V. 23 and M 24 For gate boost of the output signal V OUT The output signal V OUT At approximately 80% of the high-to-low transitions of TF_HV (e.g., returning it to VDDPX (e.g., 1.8V)). In response, the transition pre-driver 340 deasserts V NCTL_HV Signal and V NCTL_LV Control of the signals is passed to steady-state pre-drivers 330, which change their state to the non-boosted voltage levels VDDIX and VSSIX, respectively (eg, both 0.9V).

[0069] The input signal V changes to a high logic voltage. IN_HV and V IN_LV As shown by the output signal V OUT When the gate boost enable signal V is transitioned from a low logic voltage VSSX (e.g., 0V) to a high logic voltage VDDPX (e.g., 1.8V), the gate boost control circuit 320 asserts the gate boost enable signal V in an asserted low logic state VDDIX (e.g., 0.9V). TR_LV and generates the gate boost enable signal V TF_HV Deasserted gate boost enable signal V TF_HV In response, the steady-state pre-driver 330 drives the control signal V at a non-boosted voltage (e.g., 0.9V) and a low logic voltage VSSX (e.g., 0V). NCTL_HV and V NCTL_LV These voltage level control signals are generated by the NMOS FET M 23 and M 24 Turn off.

[0070] Asserted Gate Boost Enable signal V TR_LV In response to this, the transition pre-driver 340 drives the control signal V PCTL_HV and V PCTL_LV These voltage levels are generated by the PMOS FET M 21 and M 22 turn on the output signal V OUT During the steady-state low logic state VSSX, the PMOS FET M 21 and M 22 is smaller than the turn-on resistance when driven by a non-boosted voltage, e.g., 0.9V. 21 and M 22 For gate boost of the output signal V OUT The output signal V OUTAt approximately 80% of the low-to-high transitions of TR_LV (e.g., returning it to VSSX (e.g., 0V)). In response, the transition pre-driver 340 deasserts V PCTL_HV Signal and V PCTL_LV Control of the signals is passed to the steady-state pre-drivers 330, which change their states to the non-boosted voltage levels VSSIX and VDDIX, respectively (eg, both 0.9V).

[0071] 4 illustrates a block diagram of an example of an exemplary pull-down gate boost control circuit 400 according to another aspect of the present disclosure. The pull-down gate boost control circuit 400 may be an exemplary detailed implementation of the pull-down side or portion of the gate boost control circuit 320 previously described. That is, the gate boost control circuit 400 is configured to receive an input signal V IN_HV and V IN_LV and the output signal V OUT_HV and V OUT_LV Based on and pull-down gate boost enable signal V TF_HV As described above, the pull-down gate boost control circuit 400 is configured to generate the gate boost enable signal V TF_HV The output signal V OUT During the falling transition period (e.g., 80% of the falling transition interval), an asserted low logic voltage VSSIX (e.g., 0.9V) is generated, and during the steady-state transition period and the rising transition period, a deasserted high logic voltage VDDPX (e.g., 1.8V) is generated.

[0072] In particular, the pull-down gate boost control circuit 400 includes a first inverter 405 and a second inverter 410, a hysteresis logic device 420, a first multi-domain logic circuit 430, a second multi-domain logic circuit 440, and a logic gate 450 (e.g., a NAND gate). A multi-domain logic circuit is a logic circuit that operates on signals in different voltage domains (e.g., HV and LV voltage domains). The first inverter 405 inverts an input signal V in the LV voltage domain. IN_LVReceives and inverts the complementary input signal, also in the LV voltage domain.

[0073]

number

[0074]

number

[0075] The first multi-domain logic circuit 430 receives an input signal V IN_HV and complementary input signal

[0076]

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[0077]

number

[0078] As mentioned before, the input signal V IN starts the pull-down gate boost period, and the output signal V OUT ends the pull-down gate boost period. Before the falling transition, the input signal V IN and the output signal V OUT is in a high logic steady state. The input signal V IN In response to input signal V being logic high, voltage level shifter 310 shifts input signal V IN_HV and V IN_LV Similarly, the output signal V OUT In response to this, the voltage domain splitter 460 generates a logic high output signal V OUT_HV and V OUT_LV The VDDPX (e.g., 1.8 V) and VDDIX (e.g., 0.9 V) are generated.

[0079] In this embodiment, the first multi-domain logic circuit 430 receives the signal V IN_HV Invert the pull-down gate boost start signal V TF1_HV Generates a signal V IN_HV is logic high, the pull-down gate boost start signal V TF1_HV is a logic low. Similarly, the second multi-domain logic circuit 440 outputs the signal

[0080]

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[0081]

number

[0082] Input signal V IN subsequently transitions to a low logic state, and the voltage level shifter 310 shifts the input signal VSSIX (e.g., 0.9V) to a logic low VSSIX (e.g., 0.9V) state and a logic high VDDIX (e.g., 0.9V) state. IN_HV and

[0083]

number

[0084] Output signal V OUT When transitions to a substantially low logic state, the voltage domain splitter 360 generates an output signal V OUT_HV and V OUT_LV at logic low states VSSIX (e.g., 0.9V) and VSSX (e.g., 0V), respectively. In response, the second multi-domain logic circuit 440 generates a high logic signal

[0085]

number

[0086] 5 illustrates another block diagram of an exemplary multi-domain logic circuit 500 according to another embodiment of the present disclosure. The multi-domain logic circuit 500 includes a first FET M 51 and the second FET M 52 The first FET M 51 may be implemented as a PMOS FET, and the second FET M 52 may be implemented as an NMOS FET. The multi-domain logic circuit 500 includes a third FET M 53 The inverter 510 and the PMOS FET M 53 is coupled in series between an upper voltage rail VDDPX and a lower voltage rail VSSIX (eg, associated with the HV voltage domain).

[0087] PMOS FET M 53 is the signal V2 LV With reference to the pull-down gate boost control circuit 400, the pull-down gate boost control circuit 400 includes a gate configured to receive a signal V2 LV When the multi-domain logic circuit 500 corresponds to the first multi-domain logic circuit 430, the complementary input signal

[0088]

number

[0089] PMOS FET M 51 and NMOS FET M 52 are coupled together to form the input of inverter 510, and complementary signals

[0090]

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[0091]

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[0092]

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[0093] PMOS FET M51 and NMOS FET M 52 510 include respective drains coupled together to form the output of the inverter 510, and the output signal V OUT_HV With reference to the pull-down gate boost control circuit 400, the output signal V OUT_HV When the multi-domain logic circuit 500 corresponds to the first multi-domain logic circuit 430, the pull-down gate boost start signal V TF1_HV and when the multi-domain logic circuit 500 corresponds to the second multi-domain logic circuit 440, the pull-down gate boost termination signal V TF2_HV The multi-domain logic circuit 500 may optionally include OUT_HV 5. The input may include a latch 520 (eg, a cross-coupled inverter) configured to latch the logic state of

[0094] 6 illustrates a block diagram of an example pull-up gate boost control circuit 600 according to another aspect of the present disclosure. The pull-up gate boost control circuit 600 may be an example detailed implementation of the pull-up side or portion of the gate boost control circuit 320 previously described. That is, the pull-up gate boost control circuit 600 receives an input signal V IN_HV , V IN_LV and the output signal V OUT_HV , V OUT_LV Based on and pull-up gate boost enable signal V TR_LV As described above, the pull-up gate boost control circuit 600 is configured to generate the gate boost enable signal V TR_LV , the output signal V OUT During the rising transition period (e.g., 80% of the rising transition period), an asserted high logic voltage VDDPX (e.g., 1.8V) is generated, and during the steady state and falling transition periods, a deasserted low logic voltage VSSIX (e.g., 0.9V) is generated.

[0095] In particular, the pull-up gate boost control circuit 600 includes a first inverter 605 and a second inverter 610, a hysteresis logic device 620, a first multi-domain logic circuit 630, a second multi-domain logic circuit 640, and a logic gate 650 (e.g., an AND gate). The first inverter 605 receives an input signal V IN_LV Receives and inverts the complementary input signal

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[0098] The first multi-domain logic circuit 630 receives an input signal V IN_HV and complementary input signal

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[0105] As mentioned before, the input signal V IN starts the pull-up gate boost period and the output signal V OUT ends the pull-up gate boost period. Before the rising transition, the input signal V IN and the output signal V OUT is in a low logic steady state. The input signal V IN In response to VSSIX being logic low, the voltage level shifter 310 shifts the input signal VSSIX (e.g., 0.9V) and VSSX (e.g., 0V) to logic low VSSIX (e.g., 0V). IN_HV and V IN_LVSimilarly, the output signal V OUT In response to VSSIX being logic low, the voltage domain splitter 460 outputs the output signal VSSIX at logic low VSSIX (e.g., 0.9V) and VSSSX (e.g., 0V). OUT_HV and V OUT_LV Generate.

[0106] The first multi-domain logic circuit 630 receives the signal

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[0109] Input signal V IN When V V subsequently transitions to a high logic state, the voltage level shifter 310 shifts the input signal V IN_HV and

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[0112] Output signal V OUT When Vddx substantially transitions to a high logic state, the voltage domain splitter 360 provides output signals Vddpx (e.g., 1.8V) and Vddix (e.g., 0.9V) at high logic states, respectively. OUT_HV and V OUT_LV In response, the second multi-domain logic circuit 640 generates a high logic signal V OUT_LV is inverted to generate the pull-up gate boost termination signal V TR2_LV Here, an AND gate 650 generates logic high and low input signals V TR1_LV and V TR2_LV , the AND gate 650 asserts the pull-up gate boost enable signal V in its deasserted low logic state VSSX (e.g., 0V) to terminate the pull-up gate boost period. TR_LV As mentioned above, the pull-up gate boost period is OUTtransitioning to a high logic state.

[0113] 7 illustrates a block diagram of an exemplary multi-domain logic circuit 700 according to another embodiment of the present disclosure. The multi-domain logic circuit 700 includes a first FET M, which may be implemented as an NMOS FET. 71 The multi-domain logic circuit 700 includes a second FET M 72 and the third FET M 73 The second FET M 72 may be implemented as a PMOS FET, and the third FET M 73 may be implemented as an NMOS FET. 71 and inverter 710 is coupled in series between an upper voltage rail VDDIX and a lower voltage rail VSSX (eg, associated with the LV voltage domain).

[0114] NMOS FET M 71 is the signal V1 HV With reference to the pull-up gate boost control circuit 600, the pull-up gate boost control circuit 600 includes a gate configured to receive a signal V1 HV When the multi-domain logic circuit 700 corresponds to the first multi-domain logic circuit 630, the input signal V IN_HV or, if the multi-domain logic circuit 700 corresponds to the second multi-domain logic circuit 640, the output signal

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[0116] PMOS FET M 72 and NMOS FET M 73 are coupled together to form the input of inverter 710, and complementary signals

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[0120] PMOS FET M 72 and NMOS FET M 73 710 include respective drains coupled together to form the output of the inverter 710, and the output signal V OUT_LV With reference to the pull-up gate boost control circuit 600, the output signal V OUT_LV When the multi-domain logic circuit 700 corresponds to the first multi-domain logic circuit 630, the pull-up gate boost start signal V TR1_LV and when the multi-domain logic circuit 700 corresponds to the second multi-domain logic circuit 640, the pull-up gate boost termination signal V TR2_LV The multi-domain logic circuit 700 may optionally include OUT_LV , may include a latch 720 (e.g., a cross-coupled inverter) configured to latch the logic state of

[0121] 8 shows a schematic diagram of an exemplary first pull-up pre-driver 800 according to another embodiment of the present disclosure. The first pull-up pre-driver 800 includes a PMOS FET M 21 Control signal for V PCTL_HVThe first pullup pre-driver 800 may be part of the steady-state pre-driver 330 and the transition pre-driver 340 that generate the first pullup pre-driver 810 and the first pullup transition pre-driver 830.

[0122] The first steady-state pull-up pre-driver 810 is connected between the upper voltage rail VDDPX and the lower voltage rail VSSIX associated with the HV voltage domain. 83 The inverter 820 then includes a PMOS FET M 81 and NMOS FET M 82 Includes PMOS FET M 81 and NMOS FET M 82 The inputs of the inverter 820 include gates coupled together to form the input of an inverter 820. The input of the inverter 820 is connected to an input signal V IN_HV The PMOS FET M 81 and NMOS FET M 82 also serves as the output of the first pull-up pre-driver 800, and is connected to a PMOS FET M 21 The drains of the inverter 820 are coupled together to form the output of the inverter 820, which is coupled to the gate of the output signal V OUT During the steady-state high and low and falling transitions of 21 Control signal for V PCTL_HV The PMOS FET M 83 is the pull-up gate boost enable signal V TR_LV The signal processing device includes a gate configured to receive the

[0123] The first pullup transition pre-driver 830 includes an NMOS FET M1 coupled between the upper voltage rail VDDPX and the output of the first pullup pre-driver 800. 84The first pullup transition pre-driver 830 includes a diode-connected NMOS FET M coupled in series between the output of the first pullup pre-driver 800 and the lower voltage rail VSSX. 85 and NMOS FET M 86 and another NMOS FET M 87 The NMOS FET M 84 includes a gate configured to receive a bias voltage VSSIX (e.g., 0.9V). 85 is diode-connected because its drain and gate are tied together. 86 includes a gate configured to receive a bias voltage VDDIX (e.g., 0.9V). 87 is the pull-up gate boost enable signal V TR_LV The signal processing device includes a gate configured to receive the

[0124] 3B, the operation of the first pull-up pre-driver 800 is as follows. OUT When V is in a steady-state high logic state V (e.g., 1.8 V), the control signal V PCTL_HV is in a low logic state VSSIX (e.g., 0.9V). OUT When the input signal V is in a steady-state high logic state V IN_HV is in a high logic state VDDPX (e.g., 1.8V) and the pull-up gate boost enable signal V TR_LV is in a deasserted low logic state VSSX (e.g., 0V). Therefore, the PMOS FET M 83 is turned on to enable the inverter 820, which in turn converts the input signal V IN_HV The high logic state VDDPX (e.g., 1.8 V) of the control signal V PCTL_HV During this steady state, the first pullup transition pre-driver 830 generates the pullup gate boost enable signal V TR_LVThe low logic state VSSX (e.g., 0V) of the NMOS FET M 87 is disabled because it keeps it off.

[0125] Control signal V PCTL_HV is the output signal V OUT is in a steady-state low logic state VSSX (e.g., 0 V), and is in a high logic state VDDPX (e.g., 1.8 V). OUT When the input signal V is in a steady-state low logic state VSSX (e.g., 0V), IN_HV is in a low logic state VSSX (e.g., 0V), and the pull-up gate boost enable signal V TR_LV is deasserted low logic state VSSX (e.g., 0V). Therefore, the PMOS FET M 83 is turned on to enable the inverter 820, which in turn converts the input signal V IN_HV The low logic state VSSX (e.g., 0 V) ​​of the control signal V PCTL_HV Similarly, during this steady state, the first pullup transition pre-driver 830 generates the pullup gate boost enable signal V TR_LV The low logic state VSSX (e.g., 0V) of the NMOS FET M 87 is disabled because it keeps it off.

[0126] Output signal V OUT When the control signal V is transitioning from a high logic state VDDPX (e.g., 1.8 V) to a low logic state VSSX (e.g., 1.8 V), PCTL_HV is in the high logic state VDDPX (e.g., 0V). The output signal V OUT When the input signal V IN_HV is in the low logic state VSSX (e.g., 0.9V), and the pull-up gate boost enable signal V TR_LV is in a deasserted low logic state VSSX (e.g., 0V). Therefore, the PMOS FET M 83 is turned on to enable the inverter 820, which in turn converts the input signal V IN_HVThe low logic state VSSX (e.g., 0 V) ​​of the control signal V PCTL_HV During this high-to-low transition period, the first pullup transition pre-driver 830 generates the pullup gate boost enable signal V TR_LV The low logic state VSSX (e.g., 0V) of the NMOS FET M 87 is disabled because it keeps it off.

[0127] Output signal V OUT When the control signal V is transitioning from a low logic state VSSX (e.g., 0 V) ​​to a high logic state VDDPX (e.g., 1.8 V), PCTL_HV is in the boost state (for example, about 0.4 V). The output signal V OUT When the input signal V IN_HV is in the high logic state VDDPX (e.g., 1.8V), and the pull-up gate boost enable signal V TR_LV is in an asserted high logic state VDDIX (e.g., 0.9V). Therefore, the PMOS FET M 83 is turned off to disable the first steady-state pullup pre-driver 810. The pullup gate boost enable signal V TR_LV When VDDIX is in an enabled high logic state (e.g., 0.9V), the NMOS FET M 87 turns on and creates a current path between VDDPX and VSSX. NMOS FET M 87 The turning on of also turns on the NMOS FET M86. Therefore, the diode-connected NMOS FET M 85 is coupled between the output of the first pull-up predriver 800 and the lower voltage rail VSSX, thereby providing a boosted voltage level of approximately 0.4V to the control signal V PCTL_HV (For example, a diode-connected NMOS FET M 85 The voltage drop across the upper NMOS FET M 84 is configured to limit the current between VDDPX and VSSX.

[0128] 9 shows a schematic diagram of an exemplary second pull-up pre-driver 900 according to another embodiment of the present disclosure. The second pull-up pre-driver 900 is a PMOS FET M 22 Control signal for V PCTL_LV The second pullup pre-driver 900 may be part of the steady-state pre-driver 330 and the transition pre-driver 340 that generate the second steady-state pullup pre-driver 910 and the second pullup transition pre-driver 930.

[0129] The second steady-state pullup pre-driver 910 has a source configured to receive a bias voltage VDDIX (e.g., 0.9V) and a pullup gate boost enable signal V TR_LV and a PMOS FET M of the output driver 350. 22 Control signal for V PCTL_LV and a drain serving as the output of the second pull-up pre-driver 900 to generate a PMOS FET M 91 (The output of the second pull-up pre-driver 900 is connected to a PMOS FET M 22 (coupled to the gate of

[0130] The second pullup transition pre-driver 930 includes an NMOS FET M1 coupled between the upper voltage rail VDDPX and the output of the second pullup pre-driver 900. 92 The second pullup transition pre-driver 930 includes an NMOS FET M between the output of the second pullup pre-driver 900 and the lower voltage rail VSSX. 94 A diode-connected NMOS FET M 93 Further includes an NMOS FET M 92 includes a gate configured to receive a bias voltage VSSIX (e.g., 0.9V). 93 The NMOS FET M is diode-connected because its drain and gate are tied together. 94is the pull-up gate boost enable signal V TR_LV The signal processing device includes a gate configured to receive the

[0131] 3B, the operation of the second pull-up pre-driver 900 is as follows. OUT The control signal V PCTL_LV is in a non-boosted state (e.g., 0.9V). The output signal V OUT When is in the above mentioned state, the pull-up gate boost enable signal V TR_LV is in a deasserted low logic state VSSX (e.g., 0V). This causes the PMOS FET M 91 turns on and its source voltage VDDIX (for example, 0.9V) is set by the control signal V PCTL_LV During these states, the second pullup transition pre-driver 930 outputs the pullup gate boost enable signal V TR_LV The low logic state VSSX (e.g., 0V) of the NMOS FET M 94 is disabled because it keeps it off.

[0132] Output signal V OUT When the control signal V is transitioning from a low logic state VSSX (e.g., 0 V) ​​to a high logic state VDDPX (e.g., 1.8 V), PCTL_LV is in the boost state (for example, about 0.4 V). The output signal V OUT When the pull-up gate boost enable signal V TR_LV is in an asserted high logic state VDDIX (e.g., 0.9V). Therefore, the PMOS FET M 91 is turned off to disable the second steady-state pullup pre-driver 910. The pullup gate boost enable signal V TR_LV When VDDIX is in an asserted high logic state (e.g., 0.9V), the NMOS FET M 94turns on and creates a current path between VDDPX and VSSX. Therefore, the diode-connected NMOS FET M 93 is coupled between the output of the second pull-up pre-driver 900 and the lower voltage rail VSSX, thereby providing a boosted voltage level of approximately 0.4V (e.g., a diode-connected NMOS FET M 93 The voltage drop across the control signal V PCTL_LV The upper NMOS FET M 92 is configured to limit the current between VDDPX and VSSX.

[0133] 10 shows a schematic diagram of an exemplary first pull-down pre-driver 1000 according to another embodiment of the present disclosure. The first pull-down pre-driver 1000 includes an NMOS FET M 24 The control signal V NCTL_LV The first pulldown predriver 1000 may be part of the steady-state predriver 330 and the transition predriver 340 that generate the first pulldown predriver 1010 and the first pulldown transition predriver 1030.

[0134] The first steady-state pull-down pre-driver 1010 includes an NMOS FET M1 coupled in series with an inverter 1020 between an upper voltage rail VDDIX and a lower voltage rail VSSX associated with the LV voltage domain. 101 Includes NMOS FET M 101 is the pull-down gate boost enable signal V TF_HV The inverter 1020 then includes a gate configured to receive a PMOS FET M 102 and NMOS FET M 103 Includes PMOS FET M 102 and NMOS FET M 103 The inputs of the inverter 1020 include gates coupled together to form the input of an inverter 1020. The input of the inverter 1020 is connected to an input signal V IN_LV The PMOS FET M 102and NMOS FET M 103 also serves as the output of the first pull-down pre-driver 1000, and is connected to an NMOS FET M 24 The drains of the inverter 1020 are coupled together to form the output of the inverter 1020, which is coupled to the gate of the OUT During the rising transition of 24 Control signal for V NCTL_LV is configured to generate

[0135] The first pull-down transition pre-driver 1030 includes a first PMOS FET M1 coupled in series between the upper voltage rail VDDPX and the output of the first pull-down pre-driver 1000. 104 and the second PMOS FET M 105 and a diode-connected PMOS FET M 106 The first pull-down transition pre-driver 1030 includes a third PMOS FET M coupled between the output of the first pull-down pre-driver 1000 and the lower voltage rail VSSX. 107 Further includes a PMOS FET M 104 is the pull-down gate boost enable signal V TF_HV The PMOS FET M 105 includes a gate configured to receive a bias voltage VSSIX (e.g., 0.9V). 106 The PMOS FET M is diode-connected because its drain and gate are tied together. 107 includes a gate configured to receive a bias voltage VDDIX (eg, 0.9V).

[0136] 3B, the operation of the first pull-down pre-driver 1000 is as follows. OUT When the control signal V is in a steady-state low logic state VSSX (e.g., 0V), NCTL_LV is in a high logic state VDDIX (e.g., 0.9V). The output signal VOUT When the input signal V is in a steady-state low logic state VSSX (e.g., 0V), IN_LV is a low logic state VSSX (e.g., 0V), and the pull-down gate boost enable signal V TF_HV is in a deasserted high logic state VDDPX (e.g., 1.8V). Therefore, the NMOS FET M 101 is turned on to enable the inverter 1020, which in turn drives the input signal V IN_LV The low logic state VSSX (e.g., 0 V) ​​of the control signal V NCTL_LV During this steady state, the pull-down gate boost enable signal V TF_HV The deasserted high logic state of VDDPX (for example, 1.8V) of the PMOS FET M 104 Therefore, the first pull-down transition pre-driver 1030 is disabled.

[0137] Output signal V OUT When V is in a steady-state high logic state V (e.g., 1.8 V), the control signal V NCTL_LV is in a low logic state VSSX (e.g., 0V). The output signal V OUT When the input signal V is in a steady-state high logic state V IN_LV is in a high logic state VDDIX (e.g., 0.9V) and the pull-down gate boost enable signal V TF_HV is in a deasserted high logic state VDDPX (e.g., 1.8V). Therefore, the NMOS FET M 101 is turned on to enable the inverter 1020, which in turn drives the input signal V IN_LV The high logic state VDDIX (e.g., 0.9V) of the control signal V NCTL_LV Similarly, during this steady state, the pull-down gate boost enable signal V TF_HV The deasserted high logic state of VDDPX (for example, 1.8V) of the PMOS FET M 104Therefore, the first pull-down transition pre-driver 1030 is disabled.

[0138] Output signal V OUT When the control signal V is transitioning from a low logic state VSSX (e.g., 0 V) ​​to a high logic state VDDPX (e.g., 0 V), NCTL_LV is in a low logic state VSSX (e.g., 1.8V). The output signal V OUT When the input signal V IN_LV is in a high logic state VDDIX (e.g., 0.9V) and the pull-down gate boost enable signal V TF_HV is in a deasserted high logic state VDDPX (e.g., 1.8V). Therefore, the NMOS FET M 101 is turned on to enable the inverter 1020, which in turn drives the input signal V IN_LV The high logic state VDDIX (e.g., 0.9V) of the control signal V NCTL_LV During this low-to-high transition, the pull-down gate boost enable signal V TF_HV The deasserted high logic state of VDDPX (for example, 1.8V) of the NMOS FET M 104 Therefore, the first pull-down transition pre-driver 1030 is disabled.

[0139] Output signal V OUT When the control signal V is transitioning from a high logic state VDDPX (e.g., 1.8 V) to a low logic state VSSX (e.g., 0 V), NCTL_LV is in the boost state (for example, about 1.4 V). The output signal V OUT When the input signal V IN_LV is in a low logic state VSSX (e.g., 0V), and the pull-down gate boost enable signal V TF_HV is in an asserted low logic state VSSIX (e.g., 0.9V). Therefore, the NMOS FET M 101is turned off to disable the first steady-state pulldown pre-driver 1010. The pulldown gate boost enable signal V TF_HV When VSSIX is in an asserted low logic state (e.g., 0.9V), the PMOS FET M 104 turns on and creates a current path between VDDPX and VSSX. 104 The on-state of the PMOS FET M 105 Therefore, the diode-connected PMOS FET M 106 is coupled between the upper voltage rail VDDPX and the output of the first pull-down pre-driver 1000. This causes the control signal V NCTL_LV (e.g., a diode drop below VDDPX (e.g., 1.8V). The lower PMOS FET M 107 is configured to limit the current between VDDPX and VSSX.

[0140] 11 shows a schematic diagram of an example second pull-down pre-driver 1100 according to another embodiment of the present disclosure. The second pull-down pre-driver 1100 is a NMOS FET M 23 The control signal V NCTL_HV The second pulldown predriver 1100 may be part of a steady-state predriver 330 and a transition predriver 340 that generate a second steady-state pulldown predriver 1110 and a second pulldown transition predriver 1130.

[0141] A second steady-state pulldown pre-driver 1110 has a drain configured to receive a bias voltage VSSIX (e.g., 0.9V) and a pulldown gate boost enable signal V TF_HV and a gate configured to receive the NMOS FET M of the output driver 350 serving as the output of the second pull-down pre-driver 1100. 23 Control signal for V NCTL_HV and an NMOS FET M 121(The output of the second pull-down pre-driver 1100 is an NMOS FET M 23 (coupled to the gate of

[0142] The second pull-down transition pre-driver 1130 has a diode-connected PMOS FET M connected between the upper voltage rail VDDPX and the output of the second pull-down pre-driver 1100. 123 A PMOS FET M 122 The second pulldown transition pre-driver 1130 includes a PMOS FET M coupled between the output of the second pulldown pre-driver 1100 and the lower voltage rail VSSX. 124 Further includes a PMOS FET M 122 is the pull-down gate boost enable signal V TF_HV The PMOS FET M 123 The PMOS FET M is diode-connected because its drain and gate are tied together. 124 includes a gate configured to receive a high logic voltage VDDIX (eg, 0.9V) of the LV voltage domain.

[0143] 3B, the operation of the second pull-down pre-driver 1100 is as follows. OUT When the control signal V is in a high steady state VDDPX (e.g., 1.8 V) and a low steady state VSSX (e.g., 0 V), or is transitioning from low to high, NCTL_HV is in a non-boosted state (e.g., 0.9V). The output signal V OUT When is in the above mentioned state, the pull-down gate boost enable signal V TF_HV is in a deasserted high logic state VDDPX (e.g., 1.8V). This allows the NMOS FET M 121 is turned on, and its drain voltage VSSIX (for example, 0.9 V) is set by the control signal V NCTL_HV During these conditions, the pull-down gate boost enable signal V TF_HVThe deasserted high logic state of VDDPX (for example, 1.8V) of the PMOS FET M 122 is kept off, so the second pull-down transition pre-driver 1130 is disabled.

[0144] Output signal V OUT When the control signal V is transitioning from a high logic state VDDPX (e.g., 1.8 V) to a low logic state VSSX (e.g., 0 V), NCTL_HV is in the boost state (for example, about 1.4V). The output signal V OUT When V is transitioning to a low logic state V (e.g., 0V), the pull-down gate boost enable signal V TF_HV is in an asserted low logic state VSSIX (e.g., 0.9V). Therefore, the NMOS FET M 121 is turned off to disable the second steady-state pulldown pre-driver 1110. The pulldown gate boost enable signal V TF_HV When VSSIX is in an asserted low logic state (e.g., 0.9V), the PMOS FET M 122 turns on and creates a current path between VDDPX and VSSX. Therefore, the diode-connected PMOS FET M 123 is coupled between the upper voltage rail VDDPX and the output of the second pull-down pre-driver 1100. This causes the control signal V NCTL_HV (for example, a diode drop below VDDPX). The lower PMOS FET M 124 is configured to limit the current between VDDPX and VSSX.

[0145] 12 illustrates a flow diagram of an exemplary method 1200 for voltage level shifting an input signal to generate an output signal according to another aspect of the disclosure. The method includes applying a first control signal to a gate of a first p-channel metal oxide semiconductor field effect transistor (PMOS FET) (block 1210). Examples of means for applying the first control signal to the gate of the first p-channel metal oxide semiconductor field effect transistor (PMOS FET) include any of the pull-up steady state pre-drivers or transition pre-drivers described herein.

[0146] The method 1200 further includes applying a second control signal to a gate of a second PMOS FET coupled in series with the first PMOS FET between the first voltage rail and the output, where the first control signal and the second control signal are at a high logic voltage when the output signal at the output is in a low logic state, the first control signal and the second control signal are at a low logic voltage when the output signal is in a low logic state, and the first control signal and the second control signal are at a first set of boost voltages, respectively, when the output signal is transitioning from a low logic state to a high logic state (block 1220). Examples of means for applying the second control signal to the gate of the second PMOS FET include any of the pull-up steady state pre-drivers or transition pre-drivers described herein.

[0147] The method 1200 further includes applying a third control signal to a gate of the first n-channel metal oxide semiconductor field effect transistor (NMOS FET) (block 1230). Examples of means for applying the third control signal to the gate of the first n-channel metal oxide semiconductor field effect transistor (NMOS FET) include any of the pull-down steady state pre-drivers or transition pre-drivers described herein.

[0148] The method 1200 further includes applying a fourth control signal to a gate of a second NMOS FET coupled in series with the first NMOS FET between the output and a second voltage rail, where the third control signal and the fourth control signal are at a low logic voltage when the output signal is in a high logic state, the third control signal and the fourth control signal are at a high logic voltage when the output signal is in a low logic state, and the third control signal and the fourth control signal are at a second set of boost voltages when the output signal is transitioning from a high logic state to a low logic state (block 1240). Examples of means for applying the fourth control signal to the gate of the second NMOS FET include any of the pull-down steady state pre-drivers or transition pre-drivers described herein.

[0149] 13 illustrates a block diagram of an exemplary wireless communication device 1300 according to another aspect of the disclosure. The wireless communication device 1300 includes at least one antenna 1360 (e.g., at least one antenna array), a transceiver 1350 coupled to the at least one antenna 1360, and an integrated circuit (IC) or system on chip (SOC) 1310 coupled to the transceiver. The IC or SOC 1310 includes one or more signal processing cores 1320 and one or more input / output (I / O) circuits 1330. The one or more I / O circuits 1330 may be implemented as any of the I / O circuits described herein.

[0150] According to a signal transmission application, one or more signal processing cores 1320 may be configured to process a transmit baseband (BB) signal in a first voltage domain (e.g., a CX voltage domain). One or more I / O circuits 1330 may be configured to voltage level shift the transmit (BB) baseband signal upward to a second voltage domain (e.g., a PX voltage domain). The transmit baseband (BB) signal in the second voltage domain is provided to a transceiver 1350 configured to generate a transmit radio frequency (RF) signal based on the transmit baseband (BB) signal. The transmit RF signal is provided to at least one antenna 1360 for wireless transmission to one or more remote wireless devices.

[0151] It should be understood that the inverters and logic gates (e.g., AND, NAND, etc.) described herein may be implemented with different configurations of transistors and / or combinations of logic gates. For example, an inverter may be implemented using a NAND gate.

[0152] The following provides a summary of aspects of the disclosure. Aspect 1: An output driver including a first p-channel metal-oxide-semiconductor field effect transistor (PMOS FET), a second PMOS FET coupled in series with the first PMOS FET between a first voltage rail and an output, a first n-channel metal-oxide-semiconductor field effect transistor (NMOS FET), and a second NMOS FET coupled in series with the first NMOS FET between the output and a second voltage rail; a first pre-driver coupled to gates of the first PMOS FET and the second PMOS FET and the first NMOS FET and the second NMOS FET; and a second pre-driver coupled to gates of the first PMOS FET and the second PMOS FET and the first NMOS FET and the second NMOS FET.

[0153] Example 2: The apparatus of example 1, wherein the first pre-driver includes a pull-up pre-driver coupled to a gate of the first PMOS FET.

[0154] Aspect 3: The apparatus of aspect 2, wherein the pullup pre-driver includes an inverter including an input configured to receive an input signal and an output coupled to a gate of the first PMOS FET, and a third PMOS FET coupled in series with the inverter between the first voltage rail and a third voltage rail, the third PMOS FET configured to receive a pullup gate boost enable signal.

[0155] Example 4: The apparatus of any one of Examples 1-3, wherein the second pre-driver includes a pull-up pre-driver coupled to a gate of the first PMOS FET.

[0156] Aspect 5: The apparatus of aspect 4, wherein the pull-up pre-driver includes: a third NMOS FET coupled between the first voltage rail and a gate of the first PMOS FET, the third NMOS FET including a gate configured to receive a first bias voltage; a diode-connected NMOS FET; a fourth NMOS FET including a gate configured to receive a second bias voltage; and a fifth NMOS FET coupled in series with the diode-connected NMOS FET and the fourth NMOS FET between the gate of the first PMOS FET and the second voltage rail, the fifth NMOS FET including a gate configured to receive a pull-up gate boost enable signal.

[0157] Example 6: The apparatus of any one of Examples 1-5, wherein the first pre-driver includes a pull-up pre-driver coupled to a gate of the second PMOS FET.

[0158] Aspect 7: The apparatus of aspect 6, wherein the pullup pre-driver includes a third PMOS FET including a source configured to receive a bias voltage, a gate configured to receive a pullup gate boost enable signal, and a drain coupled to the gate of the second PMOS FET.

[0159] Example 8: The apparatus of any one of Examples 1-7, wherein the second pre-driver includes a pull-up pre-driver coupled to a gate of the second PMOS FET.

[0160] Aspect 9: The apparatus of aspect 8, wherein the pull-up pre-driver comprises: a third NMOS FET coupled between the first voltage rail and a gate of the second PMOS FET, the third NMOS FET including a gate configured to receive a bias voltage; a diode-connected NMOS FET; and a fourth NMOS FET coupled in series with the diode-connected NMOS FET between the gate of the second PMOS FET and the second voltage rail, the fourth NMOS FET including a gate configured to receive a pull-up gate boost enable signal.

[0161] Example 10: The apparatus of any one of Examples 1-9, wherein the first pre-driver includes a pull-down pre-driver coupled to a gate of the second NMOS FET.

[0162] Aspect 11: The apparatus of aspect 10, wherein the pulldown pre-driver includes: a third NMOS FET including a gate configured to receive a pulldown gate boost enable signal; and an inverter coupled in series with the third NMOS FET between the third voltage rail and the second voltage rail, the inverter including an input configured to receive an input signal and an output coupled to the gate of the second NMOS FET.

[0163] Example 12: The apparatus of any one of Examples 1-11, wherein the second pre-driver includes a pull-down pre-driver coupled to a gate of the second NMOS FET.

[0164] Aspect 13: The apparatus of aspect 12, wherein the pulldown pre-driver includes a third PMOS FET including a gate configured to receive a pulldown gate boost enable signal, a fourth PMOS FET including a gate configured to receive a first bias voltage, a diode-connected PMOS FET coupled in series between the first voltage rail and a gate of the second NMOS FET, and the fourth PMOS FET including a gate configured to receive a second bias voltage.

[0165] Example 14: The apparatus of any one of Examples 1-13, wherein the first pre-driver includes a pull-down pre-driver coupled to a gate of the first NMOS FET.

[0166] Aspect 15: The apparatus of aspect 14, wherein the pulldown pre-driver includes a third NMOS FET including a drain configured to receive a bias voltage, a gate configured to receive a pulldown gate boost enable signal, and a drain coupled to the gate of the first NMOS FET.

[0167] Example 16: The apparatus of any one of Examples 1-15, wherein the second pre-driver includes a pull-down pre-driver coupled to a gate of the first NMOS FET.

[0168] Aspect 17: The apparatus of aspect 16, wherein the pulldown pre-driver includes: a third PMOS FET including a gate configured to receive a pulldown gate boost enable signal; a diode-connected PMOS FET coupled in series with the third PMOS FET between the first voltage rail and a gate of the first NMOS FET; and a fourth PMOS FET coupled between the gate of the first NMOS FET and the second voltage rail, the fourth PMOS FET including a gate configured to receive a bias voltage.

[0169] Example 18: The apparatus of any one of Examples 1 to 17, further comprising a gate boost control circuit coupled to the first pre-driver and the second pre-driver.

[0170] Example 19: The apparatus of example 18, wherein the gate boost control circuit includes a pull-up gate boost control circuit.

[0171] Aspect 20: The apparatus of aspect 19, wherein the pull-up gate boost control circuit includes: a first multi-domain logic circuit including a first input and a second input configured to receive an input signal in the first voltage domain and a complementary input signal in the second voltage domain, respectively, and a first output configured to generate a pull-up gate boost start signal in the second voltage domain; a second multi-domain logic circuit including a third input and a fourth input configured to receive a complementary output signal in the first voltage domain and an output signal in the second voltage domain, respectively, and a second output configured to generate a pull-up gate boost end signal in the second voltage domain; and a logic gate including a fifth input and a sixth input configured to receive the pull-up gate boost start signal and the pull-up gate end signal, respectively, and a third output configured to generate a pull-up gate boost enable signal in the second voltage domain, wherein the third output is coupled to the first pre-driver and the second pre-driver.

[0172] Aspect 21: The apparatus of aspect 20, wherein the first multi-domain logic circuit includes: a third NMOS FET including a gate configured to receive an input signal; and an inverter coupled in series with the third NMOS FET between the third voltage rail and the second voltage rail, the inverter including an input configured to receive a complementary input signal and an output configured to generate a pull-up gate boost start signal.

[0173] Aspect 22: The apparatus of aspect 20 or 21, wherein the second multi-domain logic circuit includes: a third NMOS FET including a gate configured to receive the complementary output signal; and an inverter coupled in series with the third NMOS FET between the third voltage rail and the second voltage rail, the inverter including an input configured to receive the input signal and an output configured to generate the pull-up gate boost termination signal.

[0174] Example 23: The apparatus of any one of Examples 18 to 22, wherein the gate boost control circuit includes a pull-down gate boost control circuit.

[0175] Aspect 24: The apparatus of aspect 23, wherein the pull-down gate boost control circuit includes: a first multi-domain logic circuit including a first input and a second input configured to receive an input signal in the first voltage domain and a complementary input signal in the second voltage domain, respectively, and a first output configured to generate a pull-down gate boost start signal in the first voltage domain; a second multi-domain logic circuit including a third input and a fourth input configured to receive a complementary output signal in the first voltage domain and an output signal in the second voltage domain, respectively, and a second output configured to generate a pull-down gate boost end signal in the first voltage domain; and a logic gate including a fifth input and a sixth input configured to receive the pull-down gate boost start signal and the pull-down gate end signal, respectively, and a third output configured to generate a pull-down gate boost enable signal in the first voltage domain, wherein the third output is coupled to the first pre-driver and the second pre-driver.

[0176] Aspect 25: The apparatus of aspect 24, wherein the first multi-domain logic circuit includes an inverter including an input configured to receive an input signal and an output configured to generate a pull-down gate boost start signal, and a third PMOS FET coupled in series with the inverter between the first voltage rail and a third voltage rail, the third PMOS FET including a gate configured to receive a complementary input signal.

[0177] Aspect 26: The apparatus of aspect 24 or 25, wherein the second multi-domain logic circuit includes an inverter including an input configured to receive a complementary output signal and an output configured to generate a pull-down gate boost termination signal, and a third PMOS FET coupled in series with the inverter between the first voltage rail and the third voltage rail, the third PMOS FET including a gate configured to receive the output signal.

[0178] Aspect 27: applying a first control signal to a gate of a first p-channel metal oxide semiconductor field effect transistor (PMOS FET); applying a second control signal to a gate of a second PMOS FET coupled in series with the first PMOS FET between a first voltage rail and an output, wherein the first control signal and the second control signal are at a high logic voltage when an output signal at the output is in a low logic state, the first control signal and the second control signal are at a low logic voltage when the output signal is in a high logic state, and the first control signal and the second control signal are at a first set of boost voltages when the output signal is transitioning from the low logic state to the high logic state; applying a third control signal to a gate of a first n-channel metal oxide semiconductor field effect transistor (NMOS FET); applying a second control signal to a gate of a second NMOS FET coupled in series with the first NMOS FET between the output and a second voltage rail. applying a fourth control signal to a gate of the FET, wherein when the output signal is in a high logic state, the third control signal and the fourth control signal are at a low logic voltage, when the output signal is in a low logic state, the third control signal and the fourth control signal are at a high logic voltage, and when the output signal is transitioning from the high logic state to the low logic state, the third control signal and the fourth control signal are each at a second set of boosted voltages.

[0179] Aspect 28: The method of aspect 27, further comprising initiating the first set of boost voltages and the second set of boost voltages based on an input signal, and terminating the first set of boost voltages and the second set of boost voltages based on an output signal.

[0180] Aspect 29: A method for supplying a first control signal to a gate of a first p-channel metal oxide semiconductor field effect transistor (PMOS FET), and a second control signal to a gate of a second PMOS FET coupled in series with the first PMOS FET between a first voltage rail and an output, wherein the first control signal and the second control signal are at a high logic voltage when an output signal at the output is in a low logic state, the first control signal and the second control signal are at a low logic voltage when the output signal is in a high logic state, and the first control signal and the second control signal are at a first set of boost voltages when the output signal is transitioning from the low logic state to the high logic state; and a third control signal to a gate of a first n-channel metal oxide semiconductor field effect transistor (NMOS FET), and a second NMOS FET coupled in series with the first NMOS FET between the output and a second voltage rail. and means for applying a fourth control signal to a gate of the FET, wherein when the output signal is in a high logic state, the third control signal and the fourth control signal are at a low logic voltage, when the output signal is in a low logic state, the third control signal and the fourth control signal are at a high logic voltage, and when the output signal is transitioning from the high logic state to the low logic state, the third control signal and the fourth control signal are at a second set of boosted voltages.

[0181] Aspect 30: A wireless communication device including at least one antenna, a transceiver coupled to the at least one antenna, and an integrated circuit (IC) including one or more input / output (I / O) circuits, wherein at least one of the one or more I / O circuits includes an output driver including a first p-channel metal-oxide-semiconductor field effect transistor (PMOS FET), a second PMOS FET coupled in series with the first PMOS FET between an upper voltage rail and an output, a first n-channel metal-oxide-semiconductor field effect transistor (NMOS FET), and a second NMOS FET coupled in series with the first NMOS FET between the output and a lower voltage rail, a first pre-driver coupled to gates of the first PMOS FET and the second PMOS FET and the first NMOS FET and the second NMOS FET, and a first pre-driver coupled to gates of the first PMOS FET and the second PMOS FET and the first NMOS FET and the second NMOS FET. a second pre-driver coupled to the gate of the FET.

[0182] The above description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising:

1. An output driver comprising: a first p-channel metal-oxide-semiconductor field effect transistor (PMOS FET); a second PMOS FET coupled in series with the first PMOS FET between a first voltage rail and an output; a first n-channel metal-oxide-semiconductor field effect transistor (NMOS FET); a second NMOS FET coupled in series with the first NMOS FET between the output and a second voltage rail; an output driver comprising: a first pre-driver coupled to the gates of the first and second PMOS FETs and to the gates of the first and second NMOS FETs; a second pre-driver coupled to the gates of the first and second PMOS FETs and to the gates of the first and second NMOS FETs; An apparatus comprising:

2. 2. The apparatus of claim 1, wherein the first pre-driver comprises a pull-up pre-driver coupled to the gate of the first PMOS FET.

3. The pull-up pre-driver an inverter including an input configured to receive an input signal and an output coupled to the gate of the first PMOS FET; a third PMOS FET coupled in series with the inverter between the first voltage rail and a third voltage rail, the third PMOS FET configured to receive a pull-up gate boost enable signal; The apparatus of claim 2 , comprising:

4. 2. The apparatus of claim 1, wherein the second pre-driver comprises a pull-up pre-driver coupled to the gate of the first PMOS FET.

5. The pull-up pre-driver a third NMOS FET coupled between the first voltage rail and the gate of the first PMOS FET, the third NMOS FET including a gate configured to receive a first bias voltage; a diode-connected NMOS FET; a fourth NMOS FET including a gate configured to receive the second bias voltage; a fifth NMOS FET coupled in series with the diode-connected NMOS FET and the fourth NMOS FET between the gate of the first PMOS FET and the second voltage rail, the fifth NMOS FET including a gate configured to receive a pull-up gate boost enable signal; The apparatus of claim 4 , comprising:

6. 2. The apparatus of claim 1, wherein the first pre-driver comprises a pull-up pre-driver coupled to the gate of the second PMOS FET.

7. 7. The apparatus of claim 6, wherein the pullup pre-driver comprises a third PMOS FET having a source configured to receive a bias voltage, a gate configured to receive a pullup gate boost enable signal, and a drain coupled to the gate of the second PMOS FET.

8. 2. The apparatus of claim 1, wherein the second pre-driver comprises a pull-up pre-driver coupled to the gate of the second PMOS FET.

9. The pull-up pre-driver a third NMOS FET coupled between the first voltage rail and the gate of the second PMOS FET, the third NMOS FET including a gate configured to receive a bias voltage; a diode-connected NMOS FET; a fourth NMOS FET coupled in series with the diode-connected NMOS FET between the gate of the second PMOS FET and the second voltage rail, the fourth NMOS FET including a gate configured to receive a pull-up gate boost enable signal; The apparatus of claim 8 , comprising:

10. 2. The apparatus of claim 1, wherein the first pre-driver comprises a pull-down pre-driver coupled to the gate of the second NMOS FET.

11. The pull-down pre-driver is a third NMOS FET including a gate configured to receive a pull-down gate boost enable signal; an inverter coupled in series with the third NMOS FET between a third voltage rail and the second voltage rail, the inverter including an input configured to receive an input signal and an output coupled to the gate of the second NMOS FET; The apparatus of claim 10 , comprising:

12. 2. The apparatus of claim 1, wherein the second pre-driver comprises a pull-down pre-driver coupled to the gate of the second NMOS FET.

13. The pull-down pre-driver is a third PMOS FET including a gate configured to receive a pull-down gate boost enable signal; a fourth PMOS FET including a gate configured to receive the first bias voltage; a diode-connected PMOS FET coupled in series between the first voltage rail and the gate of the second NMOS FET; a fourth PMOS FET including a gate configured to receive the second bias voltage; The apparatus of claim 12 , comprising:

14. 2. The apparatus of claim 1, wherein the first pre-driver comprises a pull-down pre-driver coupled to the gate of the first NMOS FET.

15. 15. The apparatus of claim 14, wherein the pulldown pre-driver comprises a third NMOS FET having a drain configured to receive a bias voltage, a gate configured to receive a pulldown gate boost enable signal, and a drain coupled to the gate of the first NMOS FET.

16. 2. The apparatus of claim 1, wherein the second pre-driver comprises a pull-down pre-driver coupled to the gate of the first NMOS FET.

17. The pull-down pre-driver is a third PMOS FET including a gate configured to receive a pull-down gate boost enable signal; a diode-connected PMOS FET coupled in series with the third PMOS FET between the first voltage rail and the gate of the first NMOS FET; a fourth PMOS FET coupled between the gate of the first NMOS FET and the second voltage rail, the fourth PMOS FET including a gate configured to receive a bias voltage; 17. The apparatus of claim 16, comprising:

18. 2. The apparatus of claim 1, further comprising a gate boost control circuit coupled to the first pre-driver and the second pre-driver.

19. 20. The apparatus of claim 18, wherein the gate boost control circuit comprises a pull-up gate boost control circuit.

20. The pull-up gate boost control circuit comprises: a first multi-domain logic circuit including a first input and a second input configured to receive an input signal in a first voltage domain and a complementary input signal in a second voltage domain, respectively, and a first output configured to generate a pull-up gate boost initiation signal in the second voltage domain; a second multi-domain logic circuit including a third input and a fourth input configured to receive a complementary output signal in the first voltage domain and an output signal in the second voltage domain, respectively, and a second output configured to generate a pull-up gate boost termination signal in the second voltage domain; a logic gate including a fifth input and a sixth input configured to receive the pull-up gate boost start signal and the pull-up gate end signal, respectively, and a third output configured to generate a pull-up gate boost enable signal in the second voltage domain, the third output coupled to the first pre-driver and the second pre-driver; 20. The apparatus of claim 19, comprising:

21. the first multi-domain logic circuit comprising: a third NMOS FET including a gate configured to receive the input signal; an inverter coupled in series with the third NMOS FET between a third voltage rail and the second voltage rail, the inverter including an input configured to receive the complementary input signal and an output configured to generate the pull-up gate boost start signal; 21. The apparatus of claim 20, comprising:

22. the second multi-domain logic circuit comprising: a third NMOS FET having a gate configured to receive the complementary output signal; an inverter coupled in series with the third NMOS FET between a third voltage rail and the second voltage rail, the inverter including an input configured to receive the input signal and an output configured to generate the pull-up gate boost termination signal; 21. The apparatus of claim 20, comprising:

23. 20. The apparatus of claim 18, wherein the gate boost control circuit comprises a pull-down gate boost control circuit.

24. The pull-down gate boost control circuit comprises: a first multi-domain logic circuit including a first input and a second input configured to receive an input signal in a first voltage domain and a complementary input signal in a second voltage domain, respectively, and a first output configured to generate a pull-down gate boost initiation signal in the first voltage domain; a second multi-domain logic circuit including a third input and a fourth input configured to receive a complementary output signal in the first voltage domain and an output signal in the second voltage domain, respectively, and a second output configured to generate a pull-down gate boost termination signal in the first voltage domain; a logic gate including a fifth input and a sixth input configured to receive the pull-down gate boost start signal and the pull-down gate end signal, respectively, and a third output configured to generate a pull-down gate boost enable signal in the first voltage domain, the third output coupled to the first pre-driver and the second pre-driver; 24. The apparatus of claim 23, comprising:

25. the first multi-domain logic circuit comprising: an inverter including an input configured to receive the input signal and an output configured to generate the pull-down gate boost start signal; a third PMOS FET coupled in series with the inverter between the first and third voltage rails, the third PMOS FET including a gate configured to receive the complementary input signal; 25. The apparatus of claim 24, comprising:

26. the second multi-domain logic circuit comprising: an inverter including an input configured to receive the complementary output signal and an output configured to generate the pull-down gate boost termination signal; a third PMOS FET coupled in series with the inverter between the first voltage rail and a third voltage rail, the third PMOS FET including a gate configured to receive the output signal; 25. The apparatus of claim 24, comprising:

27. applying a first control signal to a gate of a first p-channel metal-oxide-semiconductor field effect transistor (PMOS FET); applying a second control signal to a gate of a second PMOS FET coupled in series with the first PMOS FET between a first voltage rail and an output, wherein the first control signal and the second control signal are at a high logic voltage when an output signal at the output is in a low logic state, the first control signal and the second control signal are at a low logic voltage when the output signal is in a high logic state, and the first control signal and the second control signal are at a first set of boosted voltages when the output signal is transitioning from the low logic state to the high logic state; applying a third control signal to a gate of a first n-channel metal-oxide-semiconductor field effect transistor (NMOS FET); applying a fourth control signal to a gate of a second NMOS FET coupled in series with the first NMOS FET between the output and a second voltage rail, wherein the third control signal and the fourth control signal are at a low logic voltage when the output signal is in the high logic state, the third control signal and the fourth control signal are at a high logic voltage when the output signal is in the low logic state, and the third control signal and the fourth control signal are at a second set of boosted voltages when the output signal is transitioning from the high logic state to the low logic state; A method comprising:

28. initiating the first set of boost voltages and the second set of boost voltages based on an input signal; terminating the first set of boost voltages and the second set of boost voltages based on the output signal; 30. The method of claim 27, further comprising:

29. means for applying a first control signal to a gate of a first p-channel metal-oxide-semiconductor field effect transistor (PMOS FET); means for applying a second control signal to a gate of a second PMOS FET coupled in series with the first PMOS FET between a first voltage rail and an output, wherein when an output signal at the output is in a low logic state, the first control signal and the second control signal are at a high logic voltage, when the output signal is in a high logic state, the first control signal and the second control signal are at a low logic voltage, and when the output signal is transitioning from the low logic state to the high logic state, the first control signal and the second control signal are at a first set of boosted voltages; means for applying a third control signal to a gate of the first n-channel metal-oxide-semiconductor field effect transistor (NMOS FET); means for applying a fourth control signal to a gate of a second NMOS FET coupled in series with the first NMOS FET between the output and a second voltage rail, wherein the third control signal and the fourth control signal are at a low logic voltage when the output signal is in the high logic state, the third control signal and the fourth control signal are at a high logic voltage when the output signal is in the low logic state, and the third control signal and the fourth control signal are at a second set of boosted voltages when the output signal is transitioning from the high logic state to the low logic state; An apparatus comprising:

30. 1. A wireless communication device, comprising: At least one antenna; a transceiver coupled to the at least one antenna; an integrated circuit (IC) coupled to the transceiver, the IC including one or more input / output (I / O) circuits; The I / O circuit comprises:

1. An output driver comprising: a first p-channel metal-oxide-semiconductor field effect transistor (PMOS FET); a second PMOS FET coupled in series with the first PMOS FET between an upper voltage rail and an output; a first n-channel metal-oxide-semiconductor field effect transistor (NMOS FET); a second NMOS FET coupled in series with the first NMOS FET between the output and a lower voltage rail; an output driver including: a first pre-driver coupled to the gates of the first and second PMOS FETs and to the gates of the first and second NMOS FETs; a second pre-driver coupled to the gates of the first and second PMOS FETs and to the gates of the first and second NMOS FETs; Equipped with Wireless communication devices.

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