Electronic circuits, power conversion devices

Abstract

To provide an electronic circuit capable of cancelling a leakage current in a simple configuration.SOLUTION: The present invention relates to an electronic circuit comprising: a first capacitor connected to a power source side node of a switching element provided between a first line at a power source side and a second line at a ground side; a first diode of which the cathode is connected to the first capacitor; a second capacitor connected to the node; a second diode of which the cathode is connected to the second capacitor; a first current mirror circuit which discharges a grounded third capacitor on the basis of a current of the first capacitor in a case where the switching element is turned off; and a second current mirror circuit which charges the third capacitor on the basis of a current of the second capacitor in a case where the switching element is turned on.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to an electronic circuit and a power conversion device. [Background technology]

[0002] In a power conversion circuit, when a leakage current flows through a parasitic capacitance of a switching element, a noise terminal voltage may be generated at an input terminal (for example, see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2009-77533 A Summary of the Invention [Problem to be solved by the invention]

[0004] Incidentally, in Patent Document 1, a coil is used to generate an auxiliary current in order to cancel out the leakage current, which generally increases the manufacturing costs of the power conversion circuit.

[0005] The present invention has been made in consideration of the above-mentioned problems in the conventional technology, and an object of the present invention is to provide an electronic circuit capable of canceling leakage current with an inexpensive configuration. [Means for solving the problem]

[0006] The electronic circuit of the present invention, which solves the above-mentioned problems, comprises a first capacitor connected to a power supply side node of a switching element provided between a first line on the power supply side and a second line on the ground side, a first diode having a cathode connected to the first capacitor, a second capacitor connected to the node, a second diode having a cathode connected to the second capacitor, a first current mirror circuit that discharges a grounded third capacitor based on the current of the first capacitor when the switching element is turned off, and a second current mirror circuit that charges the third capacitor based on the current of the second capacitor when the switching element is turned on. Effect of the Invention

[0007] It is possible to provide an electronic circuit capable of canceling leakage current with an inexpensive configuration. [Brief description of the drawings]

[0008] [Figure 1] 1 is a diagram illustrating an example of a power conversion circuit 10. FIG. [Diagram 2] 1 is a diagram illustrating an example of a configuration of a power conversion circuit 10. FIG. [Diagram 3] 2 is a diagram showing an example of a path of a current flowing in a power conversion circuit 10. FIG. [Figure 4] 2 is a diagram showing an example of a path of a current flowing in a power conversion circuit 10. FIG. [Diagram 5] 2 is a diagram showing main waveforms of the power conversion circuit 10. FIG. [Figure 6] 1 is a diagram illustrating an example of the structure of a power conversion device 200. FIG. [Figure 7] FIG. 2 is a diagram illustrating an example of a power conversion circuit 15. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] At least the following points will become apparent from the description of this specification and the accompanying drawings.

[0010] =====This embodiment===== <<<Outline of Power Conversion Circuit 10>>> 1 is a diagram showing the configuration of a power conversion circuit 10 according to an embodiment of the present invention. The power conversion circuit 10 is a circuit that generates, for example, a U-phase AC voltage out of three-phase (U, V, W) AC voltages from an input voltage Vin. The power conversion circuit 10 includes lines L1, L2, capacitors Cd, Ce, Cc, NMOS transistors 30, 31, and a charge / discharge circuit 32.

[0011] Capacitor Cd provided between line L1 on the power supply side (P terminal side) and line L2 on the ground side (N terminal side) is an element for smoothing the voltage rectified by a rectifier circuit (not shown). In this embodiment, the voltage applied to capacitor Cd is defined as input voltage Vin. Capacitor Ce is an element for grounding the power conversion circuit 10. Line L1 corresponds to the "first line" and line L2 corresponds to the "second line."

[0012] The NMOS transistor 30 is a high-side switching element, and the NMOS transistor 31 is a low-side switching element. In this embodiment, the NMOS transistors 30, 31 provided between the line L1 and the line L2 are complementarily turned on and off by a drive circuit (not shown), thereby generating a U-phase AC voltage. In this embodiment, a node to which the source electrode of the NMOS transistor 30, the drain electrode of the NMOS transistor 31, and a U terminal (described later) are connected is defined as a node N0. Also, the node N0 corresponds to a "power supply side node."

[0013] The NMOS transistors 30 and 31 are power transistors used for power conversion. Therefore, for example, a parasitic capacitance Cs occurs between the drain electrode of the NMOS transistor 31 and the ground. When the NMOS transistors 30 and 31 are switched and the voltage of the node N0 changes, a leakage current IL flows through the capacitor Ce via the parasitic capacitance Cs.

[0014] Specifically, when the NMOS transistor 30 is turned on and the NMOS transistor 31 is turned off, the voltage of the node N0 rises to the level of the input voltage Vin (e.g., several hundred V, hereinafter referred to as H level). As a result, a leakage current IL indicated by a dashed line flows from the parasitic capacitance Cs to the capacitor Ce. On the other hand, when the NMOS transistor 30 is turned off and the NMOS transistor 31 is turned on, the voltage of the node N0 drops to the ground level (e.g., 0 V, hereinafter referred to as L level). As a result, a leakage current IL indicated by a dotted line flows from the capacitor Ce to the parasitic capacitance Cs. Therefore, when the NMOS transistors 30 and 31 are turned on and off, a noise terminal voltage corresponding to the leakage current IL is generated in the capacitor Ce.

[0015] The noise terminal voltage generated in the capacitor Ce may adversely affect other circuits or electronic devices connected via, for example, the ground line L2. Therefore, it is preferable to suppress the noise terminal voltage generated in the capacitor Ce. In this embodiment, in order to suppress such a noise terminal voltage, a capacitor Cc and a charge / discharge circuit 32 are provided to generate a compensation current for canceling the leakage current IL. In the power conversion circuit 10, the leakage current IL is actually canceled, but in FIG. 1, the leakage current IL is depicted for the sake of convenience in order to facilitate understanding.

[0016] <<Details of the capacitor Cc and the charge / discharge circuit 32>> Here, the capacitor Cc and the charge / discharge circuit 32 will be described in detail with reference to Fig. 2. The capacitor Cc is an element for passing a compensation current, and one end is grounded. The charge / discharge circuit 32 is a circuit for passing a compensation current, which flows in the opposite direction to the leakage current IL, through the capacitor Cc. The charge / discharge circuit 32 includes a power supply circuit 40, a discharge circuit 41, and a charge circuit 42. In this embodiment, the charge / discharge circuit 32 including the capacitor Cc corresponds to an "electronic circuit."

[0017] <<Power circuit 40>> The power supply circuit 40 is a circuit that generates a power supply voltage Vdd for operating the charging circuit 42 based on the voltage from the node N0. The power supply circuit 40 includes capacitors 50 and 52, diodes 51 and 53, and a Zener diode 54. The capacitor 50, the diode 51, and the capacitor 52 are connected in series between the node N0 and the ground line L2. The anode of the diode 51 is connected to the capacitor 50, and the cathode is connected to the capacitor 52. Although details will be described later, the capacitor 52 in this embodiment has a capacity that can sufficiently suppress voltage fluctuations with respect to the charging and discharging charges of the charging circuit 42 so that the charging circuit 42 can be operated.

[0018] Therefore, when node N0 changes from L level to H level, capacitor 52 is charged via capacitor 50 and diode 51. In addition, diode 53 is connected between capacitor 50 and line L2. Specifically, the cathode of diode 53 is connected to capacitor 50, and the anode is connected to line L2. Therefore, when node N0 changes from H level to L level, capacitor 50 is discharged to node N0 via diode 53.

[0019] Here, as described above, the diode 51, the cathode of which is connected, is connected to the capacitor 52. Therefore, even if the node N0 changes from the H level to the L level, the charge stored in the capacitor 52 is not discharged. In other words, since the capacitor 52 is charged from the node N0 every switching period, the power supply voltage Vdd that can stably operate the charging circuit 42 is generated in the capacitor 52.

[0020] Between the capacitor 52 and the ground line L2, a Zener diode 54 is connected, the cathode of which is connected to the capacitor 52 and the anode of which is connected to the line L2. Therefore, the Zener diode 54 operates as an element that clamps the power supply voltage Vdd so that the power supply voltage Vdd does not become higher than a predetermined voltage. In this embodiment, the "predetermined voltage" is the Zener voltage (e.g., 10 V) of the Zener diode 54. Therefore, the power supply circuit 40 supplies the power supply voltage Vdd of, for example, 10 V to the charging circuit 42.

[0021] In this embodiment, the wiring to which the power supply voltage Vdd is applied is referred to as "line L3", and line L3 corresponds to the "third line". Furthermore, capacitor 52 corresponds to the "fourth capacitor", and capacitor 50 corresponds to the "fifth capacitor". Furthermore, diode 51 corresponds to the "third diode", diode 53 corresponds to the "fourth diode", and Zener diode 54 corresponds to the "clamp element".

[0022] <<Discharge circuit 41>> The discharge circuit 41 is a circuit that discharges the capacitor Cc so that a leakage current IL does not flow to the capacitor Ce when the parasitic capacitance Cs is charged. The discharge circuit 41 includes a capacitor 60, a diode 61, and NPN transistors 62 and 63.

[0023] The capacitor 60, like the parasitic capacitance Cs, is an element that passes a current according to a change in the voltage level of the node N0. One end of the capacitor 60 is connected to the node N0, and the other end is connected to a diode 61 and a diode-connected NPN transistor 62. Therefore, when the node N0 becomes an H level, a current similar to that of the parasitic capacitance Cs passes through the diode-connected NPN transistor 62 via the capacitor 60.

[0024] Fig. 3 is a diagram for explaining an example of a path of a current flowing through the power conversion circuit 10 when the node N0 changes to an H level. Fig. 4 is a diagram showing an example of a main waveform of the power conversion circuit 10. First, at time t1 in Fig. 4, the NMOS transistor 30 turns on and the NMOS transistor 31 turns off, and the node N0 becomes an H level. As a result, as shown in Fig. 3, a current indicated by a dashed line flows from the parasitic capacitance Cs to the ground, and a current indicated by a dashed line flows through the capacitor 60 to the NPN transistor 62.

[0025] Here, the NPN transistor 62 and the NPN transistor 63 form a current mirror circuit. Therefore, the NPN transistor 63 discharges the capacitor Cc based on the current flowing through the NPN transistor 62. Specifically, the NPN transistor 63 generates a compensation current Ic (solid line) according to the current flowing through the NPN transistor 62, and absorbs the charge from the capacitor Cc. As a result, the leakage current IL (dashed line) flowing from the parasitic capacitance Cs to the ground is absorbed by the NPN transistor 63 via the capacitor Cc as the compensation current Ic (here, a discharge current).

[0026] Then, the current from the NPN transistors 62 and 63 circulates through the ground side line L2, the capacitor Cd, the power supply side line L1, and the NMOS transistor 30 to the node N0, for example.

[0027] In this embodiment, the capacitances of the capacitors 60 and Cc are determined so that the time changes in the magnitude (absolute value) of the leakage current IL (solid line) and the compensation current Ic (dashed dotted line) are equal, as shown in the enlarged view of the waveform at time t1 in Fig. 4. Note that, here, the direction of the current flowing from the power conversion circuit 10 to the ground is defined as the "positive direction", and the direction of the current flowing from the ground to the power conversion circuit 10 is defined as the "negative direction".

[0028] Therefore, in the power conversion circuit 10, when the node N0 becomes H level, the leakage current IL flows as the compensation current Ic to the NPN transistor 63 via the capacitor Cc. This prevents the leakage current IL from flowing to the capacitor Ce, thereby suppressing the change in the voltage Vce of the capacitor Ce. Note that FIG. 4 illustrates the waveform of the voltage Vce in the absence of the charge / discharge circuit 32 and the capacitor Cc as a reference waveform. In this manner, in this embodiment, when the node N0 becomes H level, the generation of noise terminal voltage in the capacitor Ce can be accurately suppressed.

[0029] When node N0 goes to the L level, diode 61 turns on, and the charge in capacitor 60 is discharged by a current passing through diode 61, capacitor 60, and node N0. Therefore, a current with a waveform similar to that of the current through parasitic capacitance Cs flows through capacitor 60 every time node N0 goes to the H level.

[0030] In this embodiment, the capacitor 60 corresponds to the “first capacitor”, the diode 61 corresponds to the “first diode”, the capacitor Cc corresponds to the “third capacitor”, and the current mirror circuit formed by the NPN transistors 62 and 63 corresponds to the “first current mirror circuit”.

[0031] <<Charging circuit 42>> The charging circuit 42 is a circuit that charges the capacitor Cc so that a leakage current IL does not flow to the capacitor Ce when the parasitic capacitance Cs is discharged. The charging circuit 42 includes a capacitor 70, a diode 71, and PNP transistors 72 and 73.

[0032] The capacitor 70 is an element that passes a current according to a change in the voltage level of the node N0, similar to the parasitic capacitance Cs. One end of the capacitor 70 is connected to the node N0, and the other end is connected to a diode 71 and a diode-connected PNP transistor 72. Therefore, when the node N0 becomes an L level, a current similar to that of the parasitic capacitance Cs passes through the diode-connected PNP transistor 72 via the capacitor 70.

[0033] 5 is a diagram for explaining an example of a path of a current flowing through the power conversion circuit 10 when the NMOS transistor 30 turns off and the NMOS transistor 31 turns on, causing the node N0 to change to the L level. For example, at time t2 in FIG. 4, when the NMOS transistor 30 turns off and the NMOS transistor 31 turns on, the node N0 becomes the L level. As a result, as shown in FIG. 5, a current indicated by a dashed line flows from the parasitic capacitance Cs to the node N0 (or the drain electrode of the NMOS transistor 31). At this time, a current indicated by a dashed line flows from the PNP transistor 72 to the node N0 via the capacitor 70.

[0034] Here, the PNP transistor 72 and the PNP transistor 73 form a current mirror circuit. Therefore, the PNP transistor 73 charges the capacitor Cc based on the current flowing through the PNP transistor 72. Specifically, the PNP transistor 73 generates a compensation current Ic (solid line) according to the current flowing through the PNP transistor 72, and supplies it to the capacitor Cc. As a result, the compensation current Ic (here, a charging current) flowing from the PNP transistor 73 to the ground via the capacitor Cc is supplied as a leakage current IL flowing through the parasitic capacitance Cs.

[0035] Then, the current to the node N0 circulates to the line L3 of the power supply circuit 40 via, for example, the NMOS transistor 31, the ground side line L2, and the capacitor 52. As described above, the capacitor 52 has a capacity that can sufficiently suppress voltage fluctuations due to the charging and discharging of the charging circuit 42. Therefore, even if a current is supplied from the capacitor 52 to the current mirror circuit of the charging circuit 42, the power supply circuit 40 can generate a stable voltage Vdd.

[0036] Here, in this embodiment, as shown in the enlarged view of the waveform at time t2 in FIG. 4, the capacitance values ​​of the capacitors 70 and Cc are determined so that the time change in magnitude (absolute value) of the leakage current IL (solid line) and the compensation current Ic (dash-dotted line) is equal. Therefore, in the power conversion circuit 10, when the node N0 becomes L level, the compensation current Ic flows as the leakage current IL through the capacitor Cs. Therefore, since the leakage current IL can be prevented from flowing to the capacitor Ce, the change in the voltage Vce of the capacitor Ce can be suppressed. In this way, in this embodiment, when the node N0 becomes L level, the generation of noise terminal voltage in the capacitor Ce can be accurately suppressed.

[0037] In this embodiment, the capacitor 70 corresponds to a “second capacitor,” and the diode 71 corresponds to a “second diode.” Moreover, the current mirror circuit formed by the PNP transistors 72 and 73 corresponds to a “second current mirror circuit.”

[0038] <<<An example of a power conversion device>>> 6 is an example of a plan view of a power conversion device 200 including the power conversion circuit 10. Note that the power conversion circuit 10 and the power conversion device 200 have the same configurations denoted by the same reference numerals. The power conversion device 200 includes a housing 210, a heat sink 220, a semiconductor module 230, and a circuit board 240.

[0039] Housing 210 is a substantially rectangular box-shaped member formed, for example, from resin, with an opening on its front surface, and houses heat sink 220, semiconductor module 230, and circuit board 240. Metal heat sink 220 made, for example, from copper is attached to the bottom surface of the housing, and semiconductor module 230 is attached to the front surface of heat sink 220.

[0040] The semiconductor module 230 is an electronic component that includes NMOS transistors 30 and 31 therein, and has terminals P, N, and U on its front surface. The terminal P is, for example, a terminal connected to the drain electrode of the NMOS transistor 30 and a line L1 on the power supply side, and the terminal N is a terminal connected to the source electrode of the NMOS transistor 31 and a line L2 on the ground side. The terminal U is a terminal connected to a node N0 to which the NMOS transistors 30 and 31 are connected.

[0041] The circuit board 240 is a rectangular printed circuit board on which the charge / discharge circuit 32 and the capacitor Cc of the power conversion circuit 10 are mounted, and is fixed to the semiconductor module 230 via a metal plate 250 connected to the terminal U and a metal plate 251 connected to the terminal N. The circuit board 240 is formed with conductive patterns (not shown) connected to the terminal U and the terminal N, respectively.

[0042] Furthermore, on the front surface of circuit board 240, capacitor 60 of discharge circuit 41, capacitor 70 of charging circuit 42, and capacitor Cc are mounted in an area on the side of terminal U. Then, near the center of circuit board 240, the components constituting discharge circuit 41 excluding capacitor 60 and the components constituting charging circuit 42 excluding capacitor 70 are mounted. Furthermore, the components constituting power supply circuit 40 are mounted in an area on the side of circuit board 240 farther from terminal U. One end of capacitor Cc is attached to heat sink 220, which functions as ground, via metal wire 252 and terminal 253.

[0043] In this way, since the capacitors 60, 70 are arranged in an area closer to the terminal U than the current mirror circuits of the discharge circuit 41 and the charge circuit 42, it is possible to reduce the impedance between the terminal U and the capacitors 60, 70. Therefore, the voltage applied to the capacitors 60, 70 and the voltage applied to the parasitic capacitance Cs of the NMOS transistor 30 become approximately equal. Therefore, in the power conversion device 200, it is possible to precisely match the waveform of the compensation current Ic with the waveform of the leakage current IL.

[0044] In the power conversion device 200, the terminal U corresponds to a "first terminal", the terminal N corresponds to a "second terminal", and the terminal 253 corresponds to a "ground terminal".

[0045] <<<An example of the power conversion circuit 15>>> FIG. 7 is a diagram showing an example of the power conversion circuit 15. The power conversion circuit 15 is a circuit used when generating a voltage of the U phase of a three-level inverter, for example. The power conversion circuit 15 includes lines L1, L2, capacitors Cdp, Cdn, Ce, and Cc, NMOS transistors 35 to 38, diodes D1 and D2, and a charge / discharge circuit 39. Note that the circuits and elements with the same reference numerals are the same in the power conversion circuit 10 shown in FIG. 2 and the power conversion circuit 15. For this reason, the following description will focus on circuits and elements that are different from the power conversion circuit 10.

[0046] Capacitors Cdp and Cdn connected in series are provided between the line L1 on the power supply side (P terminal side) and the line L2 on the ground side (N terminal side). The node to which the capacitors Cdp and Cdn are connected is a node connected to the M terminal (not shown), and for example, half the voltage (Vin / 2) of the input voltage Vin is applied as the voltage Vm.

[0047] Furthermore, four NMOS transistors 35 to 38 are connected in series between the line L1 and the line L2. In this embodiment, a terminal Up (not shown) of a semiconductor module including the NMOS transistors 35 to 38 is connected to a node N1 to which the source electrode of the NMOS transistor 35 and the drain electrode of the NMOS transistor 36 are connected.

[0048] A terminal U (not shown) of the semiconductor module is connected to a node N2 where the source electrode of the NMOS transistor 36 and the drain electrode of the NMOS transistor 37 are connected. Furthermore, a terminal Un (not shown) of the semiconductor module is connected to a node N3 where the source electrode of the NMOS transistor 37 and the drain electrode of the NMOS transistor 38 are connected.

[0049] The diodes D1 and D2 connected in series are connected between the node N1 and the node N3, and a voltage Vm is applied to the connection node of the diodes D1 and D2. The NMOS transistors 35 to 38 are turned on and off at a predetermined timing by a drive circuit (not shown), so that U-phase voltages corresponding to three levels (0, Vin / 2, Vin) are output from the nodes N1 to N3.

[0050] The NMOS transistors 35 to 38 are power transistors used for power conversion. Therefore, for example, a parasitic capacitance Cs1 occurs between the drain electrode of the NMOS transistor 36 and the ground. Then, for example, when the NMOS transistors 35 and 36 are switched complementarily and the voltage of the node N1 changes, a leakage current IL flows through the capacitor Ce via the parasitic capacitance Cs1.

[0051] In this embodiment, a parasitic capacitance Cs2 occurs between the drain electrode of the NMOS transistor 37 and the ground, and a parasitic capacitance Cs3 occurs between the drain electrode of the NMOS transistor 38 and the ground. Therefore, the above-mentioned leakage current IL occurs when the voltages of the nodes N2 and N3 change. Therefore, the power conversion circuit 15 is provided with a capacitor Cc and a charge / discharge circuit 39 for canceling (or suppressing) the leakage current IL, similar to the power conversion circuit 10.

[0052] <<Details of capacitor Cc and charge / discharge circuit 39>> The capacitor Cc is an element for passing a compensation current, and one end of the capacitor Cc is grounded. The charge / discharge circuit 39 is a circuit for passing a compensation current, which flows in the opposite direction to the leakage current IL, through the capacitor Cc. The charge / discharge circuit 39 includes a power supply circuit 40, a discharge circuit 45, and a charge circuit 46. Note that the power supply circuit (PS) 40 is the same as the circuit in Fig. 2 described above, and therefore a detailed description thereof will be omitted here.

[0053] <<Discharge circuit 45>> The discharge circuit 45 is a circuit that discharges the capacitor Cc so that leakage current IL does not flow to the capacitor Ce when each of the parasitic capacitances Cs1 to Cs3 is charged. The discharge circuit 45 includes a diode 61, NPN transistors 62 and 63, and capacitors 64 to 66. Note that the diode 61 and the NPN transistors 62 and 63 are the same as the elements in FIG. 2 described above, and therefore detailed description thereof will be omitted here.

[0054] The capacitor 64, like the parasitic capacitance Cs1, is an element that passes a current according to a change in the voltage level of the node N1. One end of the capacitor 64 is connected to the node N1, and the other end is connected to the diode 61 and the diode-connected NPN transistor 62. Therefore, when the level of the node N1 increases, a current similar to that of the parasitic capacitance Cs1 passes through the diode-connected NPN transistor 62 via the capacitor 64.

[0055] The capacitor 65 is an element that passes a current according to a change in the voltage level of the node N2, similar to the parasitic capacitance Cs2. One end of the capacitor 65 is connected to the node N2, and the other end is connected to the diode 61 and the diode-connected NPN transistor 62. Therefore, when the level of the node N2 increases, a current similar to that of the parasitic capacitance Cs2 passes through the diode-connected NPN transistor 62 via the capacitor 65.

[0056] The capacitor 66, like the parasitic capacitance Cs3, is an element that passes a current according to a change in the voltage level of the node N3. One end of the capacitor 66 is connected to the node N3, and the other end is connected to the diode 61 and the diode-connected NPN transistor 62. Therefore, when the level of the node N3 increases, a current similar to that of the parasitic capacitance Cs3 passes through the diode-connected NPN transistor 62 via the capacitor 66.

[0057] In this manner, in this embodiment, the capacitors 64-66 capable of generating a current similar to the leakage current IL flowing through the parasitic capacitances Cs1-Cs3 of the NMOS transistors 36-38 are connected to the nodes N1-N3. Then, a compensation current Ic in the opposite direction to the leakage current IL is generated in the capacitor Cc based on the current generated in these capacitors 64-66. Therefore, in this embodiment, when the voltage levels of the nodes N1-N3 become high, it is possible to accurately suppress the generation of noise terminal voltage in the capacitor Ce.

[0058] <<Charging circuit 46>> The charging circuit 46 is a circuit that charges the capacitor Cc so that leakage current IL does not flow to the capacitor Ce when each of the parasitic capacitances Cs1 to Cs3 is discharged. The charging circuit 46 includes a diode 71, PNP transistors 72 and 73, and capacitors 74 to 76. Note that the diode 71 and the PNP transistors 72 and 73 are the same as the elements in FIG. 2 described above, and therefore detailed description thereof will be omitted here.

[0059] The capacitor 74 is an element that passes a current corresponding to a change in the voltage level of the node N1, similar to the parasitic capacitance Cs1. One end of the capacitor 74 is connected to the node N1, and the other end is connected to the diode 71 and the diode-connected PNP transistor 72. Therefore, when the level of the node N1 becomes low, a current similar to that of the parasitic capacitance Cs1 passes through the diode-connected PNP transistor 72 via the capacitor 74.

[0060] The capacitor 75 is an element that passes a current corresponding to a change in the voltage level of the node N2, similar to the parasitic capacitance Cs2. One end of the capacitor 75 is connected to the node N2, and the other end is connected to the diode 71 and the diode-connected PNP transistor 72. Therefore, when the level of the node N2 becomes low, a current similar to that of the parasitic capacitance Cs2 passes through the diode-connected PNP transistor 72 via the capacitor 75.

[0061] The capacitor 76 is an element that passes a current corresponding to a change in the voltage level of the node N3, similar to the parasitic capacitance Cs3. One end of the capacitor 76 is connected to the node N3, and the other end is connected to the diode 71 and the diode-connected PNP transistor 72. Therefore, when the level of the node N3 becomes low, a current similar to that of the parasitic capacitance Cs3 passes through the diode-connected PNP transistor 72 via the capacitor 76.

[0062] In this manner, in this embodiment, the capacitors 74-76 capable of generating a current similar to the leakage current IL flowing through the parasitic capacitances Cs1-Cs3 of the NMOS transistors 36-38 are connected to the nodes N1-N3. Then, a compensation current Ic in the opposite direction to the leakage current IL is generated in the capacitor Cc based on the current generated in these capacitors 74-76. Therefore, in this embodiment, when the voltage levels of the nodes N1-N3 become low, the generation of noise terminal voltage in the capacitor Ce can be accurately suppressed.

[0063] ====Summary==== The power conversion circuits 10 and 15 of the present embodiment have been described above. For example, in the power conversion circuit 10, the capacitors 60 and 70 are connected to a node N0 at which a parasitic capacitance Cs between the NMOS transistor 31 and ground occurs. Then, the charge / discharge circuit 32 generates a compensation current Ic in the capacitor Cc based on the current flowing through the capacitors 60 and 70, which cancels the leakage current IL. Therefore, the power conversion circuit 10 does not need to use electronic components such as an auxiliary coil, and can suppress the leakage current IL with an inexpensive configuration.

[0064] Furthermore, since the anodes of the diodes 61 and 71 are connected to the line L2, the diodes 61 and 71 can appropriately discharge the capacitors 60 and 70. For example, the anodes of the diodes 61 and 71 may be grounded. However, for example, when the diodes 61 and 71 are grounded in the power conversion device 200, it is necessary to connect the anodes to the heat sink 220 via wires (not shown). In this embodiment, the anodes of the diodes 61 and 71 can be connected to a conductive pattern (not shown) connected to the line L2 (i.e., the terminal N) of the circuit board 240, so that the number of components such as wires can be reduced.

[0065] 5, the compensation current Ic output from the charging circuit 42 flows through the capacitor Cc, the NMOS transistor 31, the line L2, the capacitor 52, and the line L3 to the current mirror circuit of the PNP transistors 72 and 73. By causing the current to flow through such a path, it is possible to prevent the leakage current IL from flowing into the capacitor Ce.

[0066] Also, for example, the power supply voltage Vdd for operating the charging circuit 42 may be generated using a voltage dividing circuit that divides the voltage of the lines L1 and L2. However, using such a voltage dividing circuit increases the power consumed by the voltage dividing circuit. The power supply circuit 40 of this embodiment generates the power supply voltage Vdd based on the voltage of the node N0 that changes between the H level and the L level, so that the power consumption can be reduced.

[0067] Power supply circuit 40 also includes capacitors 50 and 52 that divide the voltage of node N0, and diode 51 that prevents capacitor 52 from discharging. Furthermore, it includes diode 53 that discharges capacitor 50 when node N0 becomes L level, so that capacitor 52 is charged every switching period. By using power supply circuit 40 configured in this way, it is possible to generate a stable power supply voltage Vdd based on the voltage of node N0.

[0068] Furthermore, the anode of the diode 53 that discharges the capacitor 50 is not grounded but is connected to the line L2 on the ground side. Therefore, for example, in the power conversion device 200, the number of parts such as wires can be reduced.

[0069] The power supply circuit 40 is provided with a Zener diode 54 that clamps the power supply voltage Vdd so that the power supply voltage Vdd does not exceed a Zener voltage (for example, 10 V). Therefore, in this embodiment, it is possible to prevent a high voltage from being applied to the PNP transistors 72 and 73.

[0070] Generally, when a device including a switching element is operated, leakage current may occur, resulting in a large noise terminal voltage. In such a case, for example, as shown in the power conversion device 200 of Fig. 6, a circuit board 240 on which the capacitor Cc and the charge / discharge circuit 32 are mounted may be attached to the semiconductor module 230. By attaching such a circuit board 240 to the semiconductor module 230, the leakage current is reliably cancelled, thereby suppressing the generation of the noise terminal voltage.

[0071] Moreover, the capacitors 60, 70, which have a function similar to that of the parasitic capacitance Cs, are preferably mounted on the circuit board 240 near the terminal U. By arranging the capacitors 60, 70 in such positions, the compensation current Ic and the leakage current IL can be matched with higher accuracy.

[0072] In this embodiment, a MOS transistor is used as a switching element for power conversion provided between the line L1 and the line L2, but it may be, for example, a bipolar transistor or an IGBT (Insulated Gate Bipolar Transistor). Each of the NMOS transistors 30 and 31 has, for example, a parasitic capacitance between the drain and source and between the gate and source, but this is omitted in this embodiment.

[0073] Moreover, although bipolar transistors are used in the current mirror circuit of the charge / discharge circuit 32, for example, MOS transistors may also be used.

[0074] The above-mentioned embodiment is for the purpose of facilitating understanding of the present invention, and is not intended to limit the present invention. Furthermore, the present invention can be modified or improved without departing from the spirit of the present invention, and it goes without saying that the present invention includes equivalents thereof. [Explanation of symbols]

[0075] 10,15 Power conversion circuits 30, 31, 35 to 38 NMOS transistors 32,39 Charge / discharge circuit 40 Power circuit 41 Discharge circuit 42 Charging circuit 50, 52, 60, 65, 66, 70, 75, 76, Cd, Cdp, Cdn, Ce, Cc, Cs, Cs1 to Cs3 capacitors 51, 53, 61, 71, D1, D2 Diodes 54 Zener Diode 62,63 NPN transistor 72,73 PNP transistors 200 Power conversion device 210 Cabinet 220 Heat sink 230 Semiconductor Module 240 Circuit Board 250,251 metal plate 252 Wire 253,U,N,P terminal L1~L3 lines N0~N3 nodes

Claims

1. a first capacitor connected to a node on the output side of the first switching element on the power supply side and the second switching element on the ground side, the first switching element being provided between a first line on a power supply side and a second line on a ground side; a first diode having a cathode connected to the first capacitor; a second capacitor connected to the node; a second diode having a cathode connected to the second capacitor; a first current mirror circuit that discharges a grounded third capacitor based on a current through the first capacitor when the first switching element is turned on and the second switching element is turned off; a second current mirror circuit that charges the third capacitor based on a current of the second capacitor when the first switching element is turned off and the second switching element is turned on; Equipped with the first current mirror circuit is operated by being supplied with a current flowing through the first capacitor, and discharges the third capacitor; the second current mirror circuit operates by outputting a current flowing through the second capacitor, and charges the third capacitor; electronic circuit.

2. 2. The electronic circuit of claim 1, The anode of the first diode is connected to the second line; The anode of the second diode is connected to the second line. electronic circuit.

3. 3. An electronic circuit according to claim 1 or 2, a fourth capacitor having one end connected to a third line to which a power supply voltage of the second current mirror circuit is applied and the other end connected to the second line; electronic circuit.

4. 4. An electronic circuit according to claim 3, a power supply circuit that generates the power supply voltage based on a voltage of the node; electronic circuit.

5. 5. An electronic circuit according to claim 4, The power supply circuit includes: The fourth capacitor; a fifth capacitor connected to the node; a third diode having an anode connected to the fifth capacitor and a cathode connected to the fourth capacitor; a fourth diode having a cathode connected to the fifth capacitor; An electronic circuit comprising:

6. 6. An electronic circuit according to claim 5, The anode of the fourth diode is connected to the second line. electronic circuit.

7. 7. An electronic circuit according to claim 5 or 6, The power supply circuit includes: further comprising a clamp element that clamps the power supply voltage so that the power supply voltage does not exceed a predetermined voltage; electronic circuit.

8. An electronic circuit according to any one of claims 1 to 7; a semiconductor module including the first and second switching elements; A ground terminal to be grounded; A power conversion device comprising:

9. The power conversion device according to claim 8, a circuit board on which the electronic circuit is mounted, the semiconductor module has a first terminal connected to the node and a second terminal connected to the second line; In the circuit board, the first and second capacitors are provided closer to the first terminal than elements constituting the first and second current mirror circuits. Power conversion equipment.

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