Vector calculation device, vector calculation method and program

Abstract

To provide a vector operation technique for enabling vector processing of a calculation using random values.SOLUTION: A vector operation apparatus 204 includes: a vector instruction receiving unit 2040 which receives a vector instruction; a random value generation unit 2044 which generates random values and supplies the random values; and a vector operation control unit 2041 which controls the random values to be supplied to operation means which executes the vector instruction when the received vector instruction is a vector random value instruction which uses random values.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to vector operation techniques. [Background technology]

[0002] Ising model processing for simulating the behavior of general magnetic materials involves a process of randomly changing values ​​with a probability that depends on the value obtained during the calculation.

[0003] Patent Document 1 describes an example of parallel processing using random numbers in a neural network. In the technology of Patent Document 1, the operands are directly modified and the same data is sent to multiple operation paths to perform parallel processing. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2019-079524 A Summary of the Invention [Problem to be solved by the invention]

[0005] In a vector computing device, when a process is performed in which a value is randomly changed with a probability that depends on a value obtained during a calculation, the dependency on the value of each element hinders the conversion of the process to vector processing. Therefore, even if such a process is performed in a vector computing device, the performance improvement that comes from vector processing cannot be obtained.

[0006] The process described in Patent Document 1 is not intended to be executed by a vector computing device, and therefore cannot resolve the obstacle to vector processing of a process that randomly changes a value with a probability that depends on a value obtained during a calculation. Vector processing of a process that randomly changes a value with a probability that depends on a value obtained during a calculation is made possible, for example, by vector processing a calculation that uses random numbers.

[0007] One of the objectives of the present disclosure is to provide a vector operation technique that enables vector processing of operations using random numbers. [Means for solving the problem]

[0008] A vector calculation device according to one aspect of the present disclosure includes a vector instruction receiving means for receiving a vector instruction, a random number generating means for generating a random number and supplying the generated random number, and a vector calculation control means for controlling the random number to be supplied to a calculation means for executing the vector instruction when the received vector instruction is a vector random number instruction that uses a random number.

[0009] A vector calculation method according to one aspect of the present disclosure accepts a vector instruction, generates a random number, and, if the accepted vector instruction is a vector random number instruction that uses a random number, controls so that the generated random number is supplied to a calculation means that executes the vector instruction.

[0010] A program according to an aspect of the present disclosure causes a computer to execute a vector instruction reception process for receiving a vector instruction, a random number generation process for generating a random number and supplying the generated random number, and, if the received vector instruction is a vector random number instruction that uses a random number, a vector operation control process for controlling the random number to be supplied to an operation means that executes the vector instruction. Another aspect of the present disclosure is also realized by a storage medium that stores the above-mentioned program. Effect of the Invention

[0011] The present disclosure has the effect of enabling vector processing of operations using random numbers. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a block diagram illustrating an example of the configuration of a vector calculation device according to a first embodiment of the present disclosure. [Diagram 2]FIG. 2 is a flowchart illustrating an example of the operation of the vector calculation device according to the first embodiment of the present disclosure. [Diagram 3] FIG. 3 is a diagram illustrating an example of a source code of an algorithm for the Ising model processing. [Figure 4] FIG. 4 is a block diagram illustrating an example of a configuration of a processor according to the second embodiment of the present disclosure. [Diagram 5] FIG. 5 is a block diagram illustrating an example of the configuration of a vector instruction processing unit according to the second embodiment of the present disclosure. [Figure 6] FIG. 6 is a flowchart illustrating an example of the operation of the vector instruction processing unit 104 of the processor according to the second embodiment of the present disclosure. [Figure 7] FIG. 7 is a flowchart illustrating an example of the operation of a vector operation instruction execution process of the vector instruction processing unit 104 of the processor according to the second embodiment of the present disclosure. [Figure 8] FIG. 8 is a diagram showing an example of an assembly language description for a vector computer. [Figure 9] FIG. 9 is a diagram illustrating an example of a hardware configuration of a computer capable of realizing a calculation device according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Before describing the embodiments of the present disclosure, an algorithm for the above-mentioned Ising model processing will be described when the Metropolis method or the like is applied to a case in which two types of spin states are represented by +1 and -1.

[0014] FIG. 3 is a diagram showing a schematic example of a source code of an algorithm for processing an Ising model. In this algorithm, a two-dimensional H expressed by the formula H=-Aj*Σ{neighborhood spin}-B*{own spin} is used as a Hamiltonian. In this formula, Aj represents the interaction, and B represents the magnetic field. This algorithm aims to minimize or maximize the energy associated with the reversal of the own spin in each element, and manipulates each spin state while changing it randomly to a certain extent to obtain a final solution. The calculation performed at that time basically has an access pattern that is compatible with vectorization, but involves a process of changing the spin state randomly with a probability that depends on the intermediate calculation result. In the example shown in FIG. 3, the process of block A corresponds to the above process. In block A0, the generated random number is compared with the magnitude of the intermediate calculation result, and the presence or absence of spin reversal in the next loop is determined based on the result of the comparison. In the algorithm shown in FIG. 3, such value dependency of each element hinders vectorization. Therefore, such an algorithm could not enjoy the performance improvement by vector processing.

[0015] <First embodiment> First, a first embodiment of the present disclosure will be described in detail with reference to the drawings.

[0016] <Configuration> 1 is a block diagram illustrating an example of the configuration of a vector calculation unit 204 according to the first embodiment of the present disclosure. The vector calculation unit 204 of this embodiment corresponds to the vector instruction processing unit 104 of the embodiment described below. In the example illustrated in FIG. 1, the vector calculation unit 204 of this embodiment includes a vector instruction receiving unit 2040, a random number generating unit 2044, and a vector calculation control unit 2041.

[0017] The vector instruction receiving unit 2040 receives a vector instruction. The random number generating unit 2044 generates random numbers and supplies a random number vector including the generated random numbers as elements.

[0018] When the accepted vector instruction is a vector random number instruction using random numbers, the vector operation control unit 2041 controls so that a random number vector is supplied to an operation unit that executes the vector instruction. This operation unit corresponds to the multiplier / adder 1046 in the embodiment described below. In the description of the embodiment of the present disclosure, a vector random number instruction using random numbers is specifically an instruction for vector processing that targets at least random numbers (i.e., a vector instruction). More specifically, a vector random number instruction refers to a vector instruction that is an instruction for vector processing that targets at least a random number vector that is a vector of random numbers. The values ​​of the elements of a random number vector are not necessarily the same value. The random numbers included as elements in a random number vector may be, for example, independently generated random numbers. The random numbers of the present disclosure may be so-called pseudo-random numbers.

[0019] The vector instruction receiving unit 2040 corresponds to the vector instruction receiving unit 2040 in the embodiment described later. The vector operation control unit 2041 corresponds to the vector operation control unit 1041 in the embodiment described later. The random number generating unit 2044 corresponds to the random number generator 1044 in the embodiment described later. The random number generating unit 2044 may further correspond to the selection circuit 1045 in the embodiment described later.

[0020] <Operation> FIG. 2 is a flowchart showing an example of the operation of the vector calculation device 204 according to the first embodiment of the present disclosure. In the example shown in FIG. 2, the vector instruction reception unit 2040 receives a vector instruction (step S101). Next, the vector calculation control unit 2041 determines the type of the received vector instruction (step S102). If the vector instruction is a vector random number instruction that is a vector instruction using random numbers (YES in step S103), the random number generation unit 2044 generates a random number to generate a random vector (step S104). The vector calculation control unit 1041 controls so that the random number vector is supplied to the calculation unit that executes the processing of the received vector instruction (step S105). If the received vector instruction is not a vector random number instruction (NO in step S103), the vector calculation device 204 ends the operation shown in FIG. 2.

[0021] 2, the vector calculation unit 204 may perform operations that a general vector calculator performs when it receives a vector instruction. Specifically, the vector calculation unit 204 may receive a vector instruction from the vector instruction reception unit 1040 and pass the received vector instruction to the calculation unit. In addition, the vector calculation unit 204 may control so that data used by the received vector instruction, which is stored in a vector register included in the vector calculation unit 204, is supplied to the calculation unit.

[0022] <Effects> This embodiment has the effect of enabling vector processing of operations using random numbers, because when the vector instruction received is a vector random number instruction using random numbers, the vector operation control unit 2041 controls so that a random number vector is supplied to the operation unit that executes the vector instruction.

[0023] <Second embodiment> Next, a second embodiment of the present disclosure will be described in detail with reference to the drawings.

[0024] <Configuration> 4 is a block diagram showing an example of the configuration of the processor 10 according to the second embodiment of the present disclosure. In the scope shown in FIG. 4, the processor 10 of this embodiment has a configuration of a general vector processor. The processor 10 is also connected to a memory 20. Note that the configuration of the processor 10 of this embodiment is not limited to the example shown in FIG. 4. For example, an additional cache hierarchy or a memory network may exist between the processor 10 and the memory 20.

[0025] Processor 10 includes a fetch / decode unit 102, a scheduler 103, a vector instruction processing unit 104, a memory access instruction processing unit 105, a scalar operation instruction processing unit 106, a branch instruction processing unit 107, and a scalar register 110. Processor 10 includes, as an L1 (Level 1) cache, an L1 instruction cache 101 and an L1 data cache 108. Processor 10 further includes an L2 cache 109.

[0026] The L1 instruction cache 101 caches instruction codes. The fetch / decode unit 102 fetches instruction codes from the instruction cache 101, decodes the fetched instruction codes and performs register renaming, and sends the instructions obtained by the decoding and register renaming to the scheduler 103. The scheduler 103 performs general reorder buffer and reservation station operations on the received instructions. The scheduler 103 sends executable instructions to one or more of the vector instruction processing unit 104, memory access instruction processing unit 105, scalar operation instruction processing unit 106, and branch instruction processing unit 107 according to the type of the instruction.

[0027] The memory access instruction processing unit 105 processes instructions such as scalar load and scalar store. The memory access instruction processing unit 105 is equivalent to a memory access instruction processing unit that processes load instructions and store instructions in a general scalar processor. The memory access instruction processing unit 105 executes load and store accesses to the L1 data cache 108.

[0028] The L1 data cache 108 caches data for scalar processing. The L1 data cache 108 requests data from the L2 cache 109 when the status of data stored in the L1 data cache 108 satisfies a predetermined condition. The data request from the L1 data cache 108 to the L2 cache 109 is a request to read data stored in the L2 cache 109 and transmit the read data to the L1 data cache 108. The L1 data cache 108 writes data to the L2 cache 109 when the status of data stored in the L1 data cache 108 satisfies another predetermined condition. Writing data to the L2 cache 109 is to read data stored in the L1 data cache 108 and write the read data to the L2 cache 109. The conditions under which the L1 data cache 108 requests data from the L2 cache 109 and the conditions under which the L1 data cache 108 writes data to the L2 cache 109 may each be appropriately determined in advance.

[0029] The L2 cache 109 can store both scalar data and vector data. The L2 cache 109 reads and writes data in accordance with a request from the L1 data cache 108. Specifically, the L2 cache 109 reads stored data in accordance with a request to read data from the L1 data cache 108, and sends the read data to the L1 data cache 108. The L2 cache 109 receives data from the L1 data cache 108 in accordance with a request to write data from the L1 data cache 108, and stores the received data. The L2 cache 109 reads and writes data in accordance with a request from the vector instruction processing unit 104. Specifically, the L2 cache 109 reads stored data in accordance with a request to read data from the vector instruction processing unit 104, and sends the read data to the vector instruction processing unit 104. The L2 cache 109 receives data from the vector instruction processing unit 104 in accordance with a request to write data from the vector instruction processing unit 104, and stores the received data.

[0030] The L2 cache 109 requests the memory 20 to read or write data depending on the status of the stored data. Specifically, if the status of the stored data satisfies a predetermined condition, the L2 cache 109 writes the stored data to the memory 20. If the status of the stored data satisfies another predetermined condition, the L2 cache 109 reads data stored in the memory 20. These predetermined conditions may be determined as appropriate in advance. The predetermined condition for the L2 cache 109 may be different from the predetermined condition for the L1 data cache.

[0031] The scalar operation instruction processing unit 106 receives instructions such as scalar addition, scalar subtraction, logical operation, and special processing from the scheduler 103, and executes the received instructions such as scalar addition, scalar subtraction, logical operation, and special processing.

[0032] The branch instruction processing unit 107 receives a branch instruction from the scheduler 103 and executes the received branch instruction.

[0033] The scalar register 110 is equivalent to a register in a general scalar processor. The scalar register 110 is used in the same manner as a register in a general scalar processor. In an example described later, the scalar register 110 includes 128 64-bit registers. In the following example, these registers are represented as SR0 to SR127, respectively. Note that the configuration of the scalar register 110 is not limited to this example.

[0034] The vector instruction processing unit 104 receives a vector memory access instruction, a vector operation instruction, etc. from the scheduler 103 via a bus 10400, and executes the received vector memory access instruction, vector operation instruction, etc. The bus 10400 is a bus that connects the scheduler 103 and the vector instruction processing unit 104. When the received instruction is a vector memory load instruction or a vector store instruction, the vector instruction processing unit 104 performs memory access processing on the L2 cache 109 or the memory 20 via a bus 10401. The bus 10401 is a bus that connects the vector instruction processing unit 104 and the L2 cache 109. The vector operation instruction is, for example, a vector addition instruction and a vector subtraction instruction.

[0035] The vector instruction processing unit 104 of this embodiment will be described in detail below.

[0036] Fig. 5 is a block diagram illustrating an example of a configuration of the vector instruction processing unit 104 according to the second embodiment of the present disclosure. In the example illustrated in Fig. 5, the vector instruction processing unit 104 includes a vector instruction receiving unit 1040, a vector operation control unit 1041, a vector register 1042, a vector memory access control unit 1043, a random number generator 1044, a selection circuit 1045, and a multiplier / adder 1046.

[0037] The vector instruction receiving unit 1040 receives a vector instruction from the scheduler 103 via the bus 10400. The vector instruction receiving unit 1040 determines the destination of the received vector instruction from the vector memory access control unit 1043 and the vector operation control unit 1041 according to the type of the received vector instruction. The vector instruction receiving unit 1040 sends the received vector instruction to the determined destination.

[0038] Specifically, when the type of the received vector instruction is, for example, vector memory access, the vector instruction receiving unit 1040 sends the received vector instruction to the vector memory access control unit 1043. In the description of this embodiment, the vector memory access is a type of instruction for exchanging data between the vector register 1042 and the L2 cache 109 or the memory 20. Specifically, an instruction whose type is vector memory access includes, for example, an instruction for writing data in the vector register 1042 to the L2 cache 109 or the memory 20, and an instruction for reading data in the L2 cache 109 or the memory 20 to the vector register 1042. Hereinafter, an instruction whose type is vector memory access is also referred to as a vector memory access instruction.

[0039] Furthermore, if the type of the accepted vector instruction is, for example, a vector operation, the vector instruction accepting unit 1040 sends the accepted vector instruction to the vector operation control unit 1041. In the description of this embodiment, the vector operation is a type of instruction for vector operation, including, for example, vector addition and vector subtraction. Hereinafter, an instruction whose type is a vector operation is also referred to as a vector operation instruction.

[0040] When the vector memory access control unit 1043 receives a vector memory access instruction from the vector instruction receiving unit 1040, it executes data transfer between the vector register 1042 and the L2 cache 109 or the memory 20 in accordance with the received instruction.

[0041] The vector register 1042 is equivalent to a vector register implemented in a general vector computer. In the example described below, the vector register 1042 includes 64 sets of vectors. One set of vectors stores 256 elements of 64-bit data. In the example below, the 64 sets of vectors are represented as VR0 to VR63, respectively. Note that the configuration of the vector register 1042 is not limited to the above example.

[0042] The vector operation control unit 1041 receives a vector instruction whose type is vector operation from the vector instruction receiving unit 1040. The vector operation control unit 1041 controls the execution of vector processing such as vector addition and vector subtraction according to the received vector instruction. The control of the execution of vector processing by the vector operation control unit 1041 will be described in detail later.

[0043] The multiplier-adder 1046 executes vector processing. The multiplier-adder 1046 may be, for example, a general FMA (Fused Multiply-Add) arithmetic unit. The multiplier-adder 1046 sends the result of the operation to the vector register 1042. The result of the operation sent to the vector register 1042 is used to update the register value of the vector register 1042. Note that, in the example of this embodiment, for simplicity, a configuration in which the vector instruction processing unit 104 includes a single multiplier-adder 1046 will be described. However, the vector instruction processing unit 104 may include multiple multiplier-adders 1046. The vector instruction processing unit 104 may include one or both of hardware for other logical operations and hardware for special operations.

[0044] The random number generator 1044 generates random numbers. The random number generator 1044 generates random numbers within a specified range. The random number generator 1044 sends the generated random numbers to the selection circuit 1045. Specifically, the random number generator 1044 may generate vector data whose element values ​​are random numbers, and send the generated vector data to the selection circuit 1045. Hereinafter, vector data whose element values ​​are random numbers will also be referred to as a random vector. The elements of the random vector may be, for example, random numbers generated so that they are not necessarily identical to each other.

[0045] The selection circuit 1045 receives the random number generated by the random number generator 1044 (specifically, for example, a random number vector) and the value read from the vector register 1042 (in other words, vector data). The selection circuit 1045 selects a value to be input to the multiplication and addition unit 1046 from the random number generated by the random number generator 1044 and the value read from the vector register 1042 in accordance with the control of the vector operation control unit 1041. The selection circuit 1045 inputs the selected value to the multiplication and addition unit 1046.

[0046] In the example shown in FIG. 5, the random number generated by the random number generator 1044 is input to the selection circuit 1045 via the bus 10405 from the random number generator 1044. The selection circuit 1045 receives the random number generated by the random number generator 1044 from the random number generator 1044 via the bus 10405. The value read from the vector register 1042 is input to the selection circuit 1045 via the bus 10404. The selection circuit 1045 receives the value read from the vector register 1042 via the bus 10404. The selection circuit 1045 selects a value to be input to the multiplier / adder 1046 under the control of the vector operation control unit 1041 via the bus 10406. The control by the vector operation control unit 1041 will be described in detail below.

[0047] When the vector instruction received from the vector instruction receiving unit 1040 is a vector instruction using a random number, the vector operation control unit 1041 controls the selection circuit 1045 so that the random number generated by the random number generator 1044 is input to the multiplier / adder 1046. A vector instruction using a random number is specifically, for example, a vector instruction that targets the above-mentioned random number vector, in other words, a vector instruction in which the above-mentioned random number vector is an argument (i.e., an instruction described as a vector random number instruction in the description of the embodiment of the present disclosure).

[0048] For example, when the received vector instruction is a vector random number instruction, the vector operation control unit 1041 sends a signal representing an instruction to input the random number generated by the random number generator 1044 to the multiplier / adder 1046 to the selection circuit 1045 via the bus 10406. The signal representing an instruction to input the random number generated by the random number generator 1044 to the multiplier / adder 1046 is hereinafter referred to as a random number selection signal. When the selection circuit 1045 receives the random number selection signal via the bus 10406, the selection circuit 1045 inputs the random number generated by the random number generator 1044 to the multiplier / adder 1046. When the selection circuit 1045 receives the random number selection signal via the bus 10406, the selection circuit 1045 may transmit an instruction to generate a random number to the random number generator 1044. In this case, when the random number generator 1044 receives an instruction to generate a random number from the selection circuit 1045, the random number generator 1044 generates a random number and sends the generated random number to the selection circuit 1045 via the bus 10405.

[0049] When the received vector instruction is not a vector random number instruction, the vector operation control unit 1041 may send a signal representing an instruction to input the value read from the vector register 1042 to the multiplier / adder 1046 to the selection circuit 1045 via the bus 10406. In the following description, the signal representing an instruction to input the value read from the vector register 1042 to the multiplier / adder 1046 is referred to as a register data selection signal. In this case, when the selection circuit 1045 receives the register data selection signal via the bus 10406, it inputs the value read from the vector register 1042 to the multiplier / adder 1046.

[0050] If the received vector instruction is not a vector random number instruction, the vector operation control unit 1041 does not need to send a register data selection signal to the selection circuit 1045. In this case, if the selection circuit 1045 receives a random number selection signal via the bus 10406, it inputs the random number generated by the random number generator 1044 to the multiplier / adder 1046. If the selection circuit 1045 receives a random number selection signal via the bus 10405, it inputs the value read from the vector register 1042 to the multiplier / adder 1046.

[0051] The control by the vector calculation control unit 1041 is not limited to the above example.

[0052] The vector operation control unit 1041 may send the received vector instruction to the multiplier / adder 1046 via the bus 10404. The vector operation control unit 1041 may control the vector register 1042 so that the data of the vector used by the received vector instruction is read from the vector register 1042 and input to the multiplier / adder 1046 via the bus 10403.

[0053] 5 is depicted as the vector memory access control unit 1043 storing data loaded from the L2 cache 109 or the memory 20 in the vector register 1042. The vector memory access control unit 1043 may be configured to input the data loaded from the L2 cache 109 or the memory 20 to the multiplier / adder 1046. If the vector instruction processing unit 104 includes another arithmetic unit, the output of the other arithmetic unit may be input to the multiplier / adder 1046.

[0054] The vector memory access control unit 1043 may be configured to input data that the vector memory access control unit 1043 has loaded from the L2 cache 109 or the memory 20 to the selection circuit 1045. In this case, the selection circuit 1045 accepts not only the output from the vector register 1042 and the random number generator 1044 but also the data that the vector memory access control unit 1043 has loaded from the L2 cache 109 or the memory 20 as input. The vector memory access control unit 1043 may be configured to input the output of another arithmetic unit to the selection circuit 1045. In this case, the selection circuit 1045 further accepts the output of another arithmetic unit as input. In these cases, the selection circuit 1045 selects data to be input to the multiplication and addition unit 1046 from the data accepted as input under the control of the vector operation control unit 1041, and inputs the selected data to the multiplication and addition unit 1046. The vector operation control unit 1041 controls the selection circuit 1045 by a signal sent to the selection circuit 1045 via a bus 10406 ​​so that the data used by the accepted vector instruction is selected by the selection circuit 1045 and input to the multiplier / adder 1046.

[0055] <Operation> 6 is a flowchart showing an example of an operation of the vector instruction processing unit 104 of the processor 10 according to the second embodiment of the present disclosure. The operation shown in FIG. 6 is an example of an operation of processing a vector instruction when the vector instruction processing unit 104 accepts the vector instruction.

[0056] 6, first, the vector instruction receiving unit 1040 receives a vector instruction (step S201). The vector instruction receiving unit 1040 determines the type (in other words, the type) of the received vector instruction (step S202). If the type of the determined vector instruction is vector memory access (YES in step S203), the vector memory access control unit 1043 executes the vector instruction of the vector memory access (step S204). In other words, the vector memory access control unit 1043 reads data from the L2 cache 109 or the memory 20, which is represented by the vector instruction whose type is vector memory access.

[0057] If the type of the determined vector instruction is not vector memory access (NO in step S203), in this embodiment, the type of the received vector instruction is vector operation. In this case, the vector instruction processing unit 104 executes a vector operation instruction execution process (step S205). The vector operation instruction execution process will be described in detail below.

[0058] FIG. 7 is a flowchart illustrating an example of the operation of the vector operation instruction execution process of the vector instruction processing unit 104 of the processor 10 according to the second embodiment of the present disclosure.

[0059] If the vector instruction is a vector random number instruction (YES in step S211), the random number generator 1044 generates a random number to generate a random vector (step S212). The vector operation control unit 1041 controls so that the random vector is supplied to the multiplication and addition unit 1046 (step S213). The vector operation control unit 1041 further controls so that data required for the multiplication and addition unit 1046 to execute the vector instruction is input to the multiplication and addition unit 1046. Then, the multiplication and addition unit 1046 executes the vector instruction (step S214).

[0060] If the vector instruction is not a vector random number instruction (NO in step S211), the vector operation control unit 1041 controls the multiplication and addition unit 1046 to input data necessary for the multiplication and addition unit 1046 to execute the vector instruction. Then, the multiplication and addition unit 1046 executes the vector instruction (step S214). Then, the vector instruction processing unit 104 ends the operation shown in FIG. 7.

[0061] <Effects> This embodiment has the same effects as those of the first embodiment. The reason why the effects of this embodiment are obtained is the same as the reason why the effects of the first embodiment are obtained.

[0062] <Example> In the following, an example of the operation of the processor 10 of the present disclosure will be described using an example of an assembly language description in which processing according to the algorithms of parts A and A0 of the example shown in FIG. 3 is described in the assembly language of a vector computer.

[0063] Fig. 8 is a diagram showing an example of an assembly language description for a vector computer. In the example shown in Fig. 8, the number given to the instruction of the line is added to the left end of the line. The process represented by the assembly language description shown in Fig. 8, which is executed by the processor 10 shown in Fig. 4, will be described below.

[0064] An instruction 901 is a floating-point scalar division instruction that sets -1.0 / Temperature to the scalar register SR 100. This Temperature is a floating-point value that is an argument of the function igingmodel() in the example shown in FIG.

[0065] The instruction 902 is an instruction to read the contents of spin[i][0] to spin[i]

[0255] into the vector register VR0. The instruction 903 is an instruction to read the contents of spin[i][2] to spin[i]

[0257] into the vector register VR1. The instruction 904 is an instruction to read the contents of spin[i-1][1] to spin[i-1]

[0256] into the vector register VR2. The instruction 905 is an instruction to read the contents of spin[i+1][1] to spin[i+1]

[0256] into the vector register VR3. The instruction 906 is an instruction to read the contents of spin[i][1] to spin[i]

[0256] into the vector register VR4.

[0066] Instruction 907 is a vector add instruction (VFADD instruction) that adds the contents of vector register VR0 and the contents of vector register VR1 and stores the result in vector register VR5. Instruction 908 is a vector add instruction (VFADD instruction) that adds the contents of vector register VR2 and the contents of vector register VR3 and stores the result in vector register VR6. Instruction 909 is a vector add instruction (VFADD instruction) that adds the contents of vector register VR5 and the contents of vector register VR6 and stores the result in vector register VR7. Instructions 907, 908, and 909 store the sum of the contents of vector registers VR0, VR1, VR2, and VR3 into vector register VR7.

[0067] Instruction 910 is a floating-point scalar multiplication instruction that calculates the value of -1.0*Aj and stores the result in scalar register SR0. Note that the operator "*" represents multiplication. The value Aj is a value representing an interaction, as described above. Instruction 911 is a scalar multiplication instruction that calculates the value of -1.0*B and stores the result in scalar register SR1. The value B represents the value of the magnetic field.

[0068] Instruction 912 is a vector floating-point multiplication and addition instruction that calculates a Hamiltonian and stores the result in vector register VR8. Instruction 913 is a vector floating-point multiplication instruction that calculates the energy when the spin at coordinates [i] [j] is in the current state and stores the energy in vector register VR9. Instruction 914 is an instruction for calculating the energy when the spin is reversed, and is a vector floating-point multiplication instruction that calculates a value obtained by multiplying the value of the energy stored in vector register VR9 by a value of -1.0 and stores the result in vector register VF10. Instruction 915 is an instruction for calculating the difference between the energy when the spin is not reversed and the energy when the spin is reversed. Specifically, instruction 915 is a vector floating-point subtraction instruction that calculates a value obtained by subtracting the value stored in vector register VR9 from the value stored in vector register VR10 and stores the result in vector register VR11.

[0069] The VRANCP instruction of instruction 916 is an example of the vector random number instruction described above. The VRANCP instruction of instruction 916 will be described in detail below. Specifically, the operation of the components of the processor 10 when the instruction executed by the processor 10 is the VRANCPZ instruction of instruction 916 will be described. In the example shown in FIG. 8, the input operands of the VRANCP instruction of instruction 916 are the vector register VR11 and the scalar register SR100. The vector register VR11 stores the vector data of the energy calculated by the instruction 915. The scalar register SR100 stores the value of -1.0 / Temperature calculated by the instruction 901.

[0070] The instruction 916 VRANCP is executed by the processor 10 in the same manner as other vector instructions. First, an instruction code is fetched from the L1 instruction cache 101 by the fetch and decode unit 102. The fetched instruction code is decoded by the fetch and decode unit 102 and registered in the scheduler 103. When the VRANCP instruction is issued, the scheduler 103 reads the value stored in the scalar register SR100 and sends the decoded instruction and the read value to the vector instruction processing unit 104 via the bus 10400.

[0071] The vector instruction reception unit 1040 of the vector instruction processing unit 104 receives a vector instruction and determines the type of the received vector instruction. If it is determined that the received vector instruction is a VRANCP instruction, the vector instruction reception unit 1040 sends the VRANCP instruction and the value stored in the received SR100 to the vector operation control unit 1041.

[0072] The vector operation control unit 1041 receives the VRANCP command and the value of SR100 from the vector command reception unit 1040, and sends the received VRANCP command and the value of SR100 to the multiplication and addition unit 1046 via the bus 10404. The vector operation control unit 1041 also reads data stored in the vector register VR11 from the vector register 1042, and controls the data to be input to the multiplication and addition unit 1046 via the bus 10403. The vector operation control unit 1041 controls the selection circuit 1045 via the bus 10406 ​​so as to select the output from the random number generator 1044 and input the selected output from the random number generator 1044 to the multiplication and addition unit 1046.

[0073] The random number generator 1044 generates a random value and sends the generated value to the selection circuit 1045. The method by which the random number generator 1044 generates a random value may be any of the existing methods for generating a random value in an electronic circuit including a general processor. The random number generator 1044 may have a function for specifying the range of distribution of the values ​​of the random numbers to be generated, or a function for changing the distribution of the random numbers to be generated.

[0074] The multiplier / adder 1046 receives the VRANCP instruction, the value read from the scalar register SR100, and the random number generated by the random number generator 1044. As a process of the received VRANCP instruction, the multiplier / adder 1046 calculates a value obtained by subtracting the product of the value stored in the vector register VR11 and the value stored in the scalar register SR100 from the random value generated by the random number generator 1044 by floating-point multiplication and addition, and returns the result of the calculation to the vector register 1042. For example, the vector calculation control unit 1041 controls so that the data returned to the vector register 1042 is stored in the vector register VR12 of the vector register 1042. By executing the instruction 916, the calculation result of the formula rand() - (-1.0*energy / Temperature) shown in FIG. 3 is stored in the vector register VR12. The result of this calculation is used to determine the comparison portion in the block A0 shown in FIG. 3.

[0075] This completes the processing of instruction 916.

[0076] The next instruction 917 is a vector AND operation instruction (i.e., a VAND instruction) that extracts only the most significant bit of each element of the data stored in the vector register VR12 and stores the extracted bit information in the vector register VR12. In the IEEE (Institute of Electrical and Electronics Engineers) floating-point format, the most significant bit is a sign bit that represents the sign. If the sign of an element of the value obtained as a result of instruction 917 is negative, then the condition "rand() < -1.0?energyD / Temperature" is satisfied for that element.

[0077] Instruction 918 is a vector XOR instruction that calculates an element-by-element XOR of the sign bit stored in vector register VR12 and vector register VR4 in which the original value of spin[i][j] is stored, and stores the result of the operation in vector register VR4. Vector register VR12 stores the sign bit extracted as a result of the processing by instruction 917. The processing of instruction 918 inverts the signs of elements whose signs are negative in the value obtained as a result of instruction 917.

[0078] <Other embodiments> The processor including the above-mentioned vector instruction processing unit 104 and the vector processing unit 204 can each be realized by dedicated hardware. The vector instruction processing unit 104 and the vector processing unit 204 can also each be realized by a computer including a memory into which a program read from a storage medium is loaded and a processor that executes the program. The vector instruction processing unit 104 and the vector processing unit 204 can also each be realized by a combination of the above-mentioned computer and dedicated hardware.

[0079] FIG. 9 is a diagram showing an example of a hardware configuration of a computer 10000 capable of realizing the above-mentioned vector instruction processing unit 104 and vector operation unit 204. In the example shown in FIG. 9, the computer 10000 includes a processor 10001, a memory 10002, a storage device 10003, and an I / O (Input / Output) interface 10004. The computer 10000 can also access a storage medium 10005. The memory 10002 and the storage device 10003 are, for example, storage devices such as a RAM (Random Access Memory) and a hard disk. The storage medium 10005 is, for example, a storage device such as a RAM or a hard disk, a ROM (Read Only Memory), or a portable storage medium. The storage device 10003 may be the storage medium 10005. The processor 10001 can read and write data and programs from and to the memory 10002 and the storage device 10003. The processor 10001 can access, for example, other devices via the I / O interface 10004. The processor 10001 can access a storage medium 10005. The storage medium 10005 stores a program that causes the computer 10000 to operate as the above-mentioned vector calculation device.

[0080] The processor 10001 loads a program, which is stored in the storage medium 10005 and causes the computer 10000 to operate as the above-mentioned vector calculation device, into the memory 10002. Then, the processor 10001 executes the program loaded into the memory 10002, causing the computer 10000 to operate as the above-mentioned vector calculation device.

[0081] The vector instruction reception unit 1040, the vector operation control unit 1041, the vector memory access control unit 1043, and the random number generator 1044 can be realized, for example, by the processor 10001 that executes a program loaded in the memory 10002. The vector instruction reception unit 2040, the vector operation control unit 2041, and the random number generation unit 2044 can be realized, for example, by the processor 10001 that executes a program loaded in the memory 10002. The vector register 1042 can be realized, for example, by the memory 10002 included in the computer 10000. Part or all of the vector instruction reception unit 1040, the vector operation control unit 1041, the vector memory access control unit 1043, the random number generator 1044, the selection circuit 1045, and the multiplication and addition unit 1046 can be realized by dedicated circuits. Part or all of the vector instruction reception unit 2040, the vector operation control unit 2041, and the random number generation unit 2044 can be realized by dedicated circuits.

[0082] Furthermore, some or all of the above-described embodiments can be described as, but are not limited to, the following supplementary notes.

[0083] (Appendix 1) vector instruction receiving means for receiving a vector instruction; A random number generating means for generating random numbers and supplying the generated random numbers; a vector operation control means for controlling, when the accepted vector instruction is a vector random number instruction using a random number, the random number to be supplied to an operation means for executing the vector instruction; A vector calculation unit comprising:

[0084] (Appendix 2) a selection means for selecting one state from a first state in which the vector stored in the vector register is supplied to the calculation means via a first bus and a second state in which the random number is supplied to the calculation means via the first bus. Equipped with The vector operation control means controls the selection means to select the second state when the accepted vector instruction is the vector random number instruction, thereby controlling the random number to be supplied to the operation means. 2. The vector calculation device according to claim 1.

[0085] (Appendix 3) When the vector instruction is the vector random number instruction that uses a vector in addition to the random number, the vector operation control means supplies the vector from the vector register to the operation means together with the random number. 3. The vector calculation device according to claim 2.

[0086] (Appendix 4) The vector register; the computing means being connected to the vector register by the first bus and to the selecting means by a second bus; Equipped with When the vector instruction is the vector random number instruction that uses the vector in addition to the random number, the vector operation control means supplies the vector instruction to the operation means, supplies the vector from the vector register to the operation means via the first bus, and supplies the random number from the random number generation means to the operation means via the second bus. 4. The vector calculation device according to claim 3.

[0087] (Appendix 5) The random number generating means generates a random number vector that is a vector including the random numbers as elements; the vector operation control means controls the random number vector to be supplied as the random number to the operation means when the accepted vector instruction is the vector random number instruction; 5. The vector calculation device according to claim 1 .

[0088] (Appendix 6) The vector instruction is an instruction for comparing the random number vector with a scalar value multiple of the vector, element by element. 6. The vector calculation device according to claim 5.

[0089] (Appendix 7) Accepts vector instructions, Generate random numbers, When the accepted vector instruction is a vector random number instruction that uses a random number, the generated random number is supplied to a calculation means that executes the vector instruction. Vector operation method.

[0090] (Appendix 8) selecting, by a selection means, one state from a first state in which the vector stored in the vector register is supplied to the calculation means via a first bus and a second state in which the random number is supplied to the calculation means via the first bus; When the received vector instruction is the vector random number instruction, the random number is supplied to the calculation means by controlling to select the second state. 8. The vector calculation method according to claim 7.

[0091] (Appendix 9) if the vector instruction is a vector random number instruction that uses a vector in addition to the random number, supplying the vector from the vector register to the arithmetic means together with the random number. 9. A vector calculation method according to claim 8.

[0092] (Appendix 10) the computing means is connected to the vector register by the first bus and to the selecting means by a second bus; if the vector instruction is the vector random number instruction that uses the vector in addition to the random number, supply the vector instruction to the computing means, supply the vector from the vector register to the computing means via the first bus, and supply the random number to the computing means via the second bus. 10. The vector calculation method according to claim 9.

[0093] (Appendix 11) Generate a random number vector that is a vector containing the random numbers as elements; When the accepted vector instruction is the vector random number instruction, control is performed so that the random number vector is supplied to the calculation means as the random number. 11. A vector calculation method according to any one of claims 7 to 10.

[0094] (Appendix 12) The vector instruction is an instruction for comparing the random number vector with a scalar value multiple of the vector, element by element. 12. The vector calculation method according to claim 11.

[0095] (Appendix 13) A vector instruction receiving process that receives a vector instruction; A random number generation process that generates random numbers and supplies the generated random numbers; a vector operation control process for controlling, when the accepted vector instruction is a vector random number instruction using a random number, the random number to be supplied to an operation means for executing the vector instruction; A program that causes a computer to execute the following.

[0096] (Appendix 14) a process of selecting, by a selection means, one state from a first state in which the vector stored in the vector register is supplied to the calculation means via a first bus and a second state in which the random number is supplied to the calculation means via the first bus; and causing the computer to further execute the The vector operation control process controls the selection means to select the second state when the accepted vector instruction is the vector random number instruction, thereby controlling the random number to be supplied to the operation means. 14. The program according to claim 13.

[0097] (Appendix 15) When the vector instruction is the vector random number instruction that uses a vector in addition to the random number, the vector operation control process supplies the vector from the vector register to the operation means together with the random number. 15. The program according to claim 14.

[0098] (Appendix 16) the computing means is connected to the vector register by the first bus and to the selecting means by a second bus; When the vector instruction is the vector random number instruction that uses the vector in addition to the random number, the vector operation control process supplies the vector instruction to the operation means, supplies the vector from the vector register to the operation means via the first bus, and supplies the vector to the operation means via the second bus. 16. The program according to claim 15.

[0099] (Appendix 17) The random number generation process generates a random number vector that is a vector including the random numbers as elements; the vector operation control process controls, when the accepted vector instruction is the vector random number instruction, to supply the random number vector to the operation means as the random number; 17. A program according to any one of appendix 13 to 16.

[0100] (Appendix 18) The vector instruction is an instruction for comparing the random number vector with a scalar value multiple of the vector, element by element. 18. The program according to claim 17.

[0101] Although the present invention has been described above with reference to the embodiment, the present invention is not limited to the above embodiment. Various modifications that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention. [Explanation of symbols]

[0102] 10 Processors 20 Memory 101 Instruction Cache 102 Fetch and Decode Section 103 Scheduler 104 Vector instruction processing unit 105 Memory access instruction processing unit 106 Scalar operation instruction processing unit 107 Branch instruction processing unit 108 Data Cache 109 Cache 110 Scalar Register 204 Vector Calculation Unit 901 command 902 Instructions 903 Instructions 904 Command 905 Command 906 Instructions 907 command 908 command 909 command 910 command 911 command 912 command 913 command 914 command 915 command 916 command 917 command 918 command 1040 Vector instruction reception unit 1041 Vector operation control unit 1042 Vector Registers 1043 Vector memory access control unit 1044 Random Number Generator 1045 Selection Circuit 1046 Multiplier and Adder 2040 Vector instruction reception unit 2041 Vector operation control unit 2044 Random Number Generator 10000 Computers 10001 Processor 10002 Memory 10003 Storage device 10004 I / O Interface 10005 Storage medium 10400 Bus 10401 Bus 10403 Bus 10404 Bus 10405 Bus 10406 ​​Bus

Claims

1. vector instruction receiving means for receiving a vector instruction; A random number generating means for generating random numbers and supplying the generated random numbers; a vector operation control means for controlling, when the accepted vector instruction is a vector random number instruction using a random number, the random number to be supplied to an operation means for executing the vector instruction; a selection means for selecting one state from a first state in which the vector stored in the vector register is supplied to the calculation means via a first bus and a second state in which the random number is supplied to the calculation means via the first bus; Equipped with The vector operation control means if the received vector instruction is the vector random number instruction, controlling the selection means to select the second state, thereby controlling the random number to be supplied to the calculation means; if the vector instruction is a vector random number instruction that uses a vector in addition to the random number, supplying the vector from the vector register to the arithmetic means together with the random number. Vector processing unit.

2. The vector register; the computing means being connected to the vector register by a second bus and to the selection means by the first bus; Equipped with When the vector instruction is the vector random number instruction that uses the vector in addition to the random number, the vector operation control means supplies the vector instruction to the operation means, supplies the vector from the vector register to the operation means via the second bus, and supplies the random number from the random number generating means to the operation means via the first bus.

2. The vector calculation unit according to claim 1.

3. The random number generating means generates a random number vector that is a vector including the random numbers as elements; the vector operation control means controls the random number vector to be supplied as the random number to the operation means when the accepted vector instruction is the vector random number instruction; 3. The vector calculation device according to claim 1 or 2.

4. The vector instruction is an instruction for comparing the random number vector with a scalar value multiple of the vector, element by element.

4. The vector calculation unit according to claim 3.

5. Accepts vector instructions, Generate random numbers, when the accepted vector instruction is a vector random number instruction using a random number, a selection means for selecting one state from a first state in which a vector stored in a vector register is supplied to a calculation means that executes the vector instruction via a first bus and a second state in which the random number is supplied to the calculation means via the first bus is controlled to select the second state, thereby controlling so that the generated random number is supplied to the calculation means; if the vector instruction is a vector random number instruction that uses a vector in addition to the random number, supplying the vector from the vector register to the arithmetic means together with the random number. Vector operation method.

6. A vector instruction receiving process that receives a vector instruction; A random number generation process that generates random numbers and supplies the generated random numbers; a vector operation control process for controlling, when the accepted vector instruction is a vector random number instruction using a random number, the random number to be supplied to an operation means for executing the vector instruction; a selection process for selecting one state from a first state in which the vector stored in the vector register is supplied to the calculation means via a first bus and a second state in which the random number is supplied to the calculation means via the first bus; on the computer, The vector operation control process includes: if the received vector instruction is the vector random number instruction, controlling the selection process to select the second state, thereby controlling the random number to be supplied to the calculation means; if the vector instruction is a vector random number instruction that uses a vector in addition to the random number, supplying the vector from the vector register to the arithmetic means together with the random number. program.

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