Silicon carbide semiconductor device and silicon carbide semiconductor substrate

Abstract

According to the present invention, first and second buffer regions (11, 12) and an n- type drift region (2) are sequentially epitaxially grown on an n+ type starting substrate (21). The impurity concentration of the first buffer region (11) is higher than the impurity concentration of the n- type drift region (2), but lower than the impurity concentration of the n+ type starting substrate (21). The impurity concentration of the second buffer region (12) is higher than the impurity concentration of the first buffer region (11), and continuously increases from the gradient change point (41a) on the n- type drift region (2) side toward the gradient change point (41b) on the first buffer region (11) side at a first impurity concentration gradient (41), while continuously decreasing from the gradient change point (41a) toward a first interface (27) at a second impurity concentration gradient (42) and continuously decreasing from the gradient change point (41b) toward a second interface (26) at a third impurity concentration gradient (43). The second impurity concentration gradient (42) is smaller than the third impurity concentration gradient (43). Consequently, reliability is improved.

Description

[Technical field]

[0001] The present invention relates to a silicon carbide semiconductor device and a silicon carbide semiconductor substrate. [Background technology]

[0002] Conventionally, in SiC-MOSFETs (Metal Oxide Semiconductor Field Effect Transistors: MOS-type field effect transistors with an insulated gate made of a three-layer structure of metal-oxide-semiconductor), which use silicon carbide (SiC) as a semiconductor material, n + On the starting substrate of type n - A semiconductor chip is used in which the epitaxial layers that will become the p-type drift region and p-type base region are epitaxially grown in sequence. Basal plane dislocations (BPDs) occur inside the epitaxial layers of the semiconductor chip due to propagation from the starting substrate or process damage during epitaxial growth.

[0003] The p-type base region and n-type - When the parasitic diode (body diode) formed by the pn junction with the drift region becomes conductive, stacking faults grow (expand) in the epitaxial layer, creating a high resistance layer, making it difficult for current to flow, and the on-voltage of the MOSFET increases. The cause of stacking faults is the bipolar action of the body diode, which - It is speculated that the minority carriers (holes) injected into the n-type drift region recombine with electrons near the BPDs, which are the starting points of stacking faults. - By placing an n-type buffer region (epitaxial layer) between the pn junction and the BPD, the number of holes reaching the BPD from the pn junction is reduced, thereby suppressing the growth of stacking faults.

[0004] As a conventional SiC-MOSFET, a device has been proposed in which the buffer region has a two-layer structure with different impurity concentrations and thicknesses (see, for example, Patent Documents 1 to 3 below). In Patent Documents 1 to 3 below, - n + By using a two-layer structure with low impurity concentration and thin thickness on the starting substrate side, - n-type drift region side + The impurity concentration of the second buffer region is n + The impurity concentration of the first buffer region is approximately the same as that of the starting substrate, thereby enhancing the effect of suppressing the growth of stacking faults. + The thickness of the second buffer region can be measured by Fourier transform using infrared light reflected at the interface with the n-type buffer region (first buffer region) on the starting substrate.

[0005] In addition, in the following Patent Documents 1 to 3, n + The impurity concentration of the starting substrate is 1×10 18 / cm 3 More than 2×10 19 / cm 3 The impurity concentration of the first buffer region is n + The impurity concentration of the starting substrate or the second buffer region is 1 / 3 or less, and preferably 1×10 17 / cm 3 More than 1×10 18 / cm 3 the thickness of the first buffer region is 0.1 μm or more and 5 μm or less, preferably 1 μm or more, the impurity concentration of the second buffer region is three times or more the impurity concentration of the first buffer region, and n + The impurity concentration of the second buffer region is approximately the same as that of the starting substrate, and the thickness of the second buffer region is 3 μm or more. - It is disclosed that the impurity concentration of the type drift region is lower than the impurity concentrations of the first and second buffer regions.

[0006] Also, as another conventional silicon carbide semiconductor device, a device has been proposed in which the buffer region has a stacked structure of two or more layers with different impurity concentrations (see, for example, Patent Documents 4 and 5 below). + The impurity concentration of the first buffer region on the starting substrate side is n + By lowering the impurity concentration to less than that of the starting substrate, + The probability that BPDs propagating from the starting substrate are converted to threading edge dislocations (TEDs) in the first buffer region is relatively high. + A starting substrate, a first buffer region and an n - By increasing the impurity concentration in the n-type drift region, - This prevents the generation of new crystal defects in the mold drift region.

[0007] In the following Patent Document 4, + The impurity concentration of the starting substrate is 5×10 17 / cm 3 More than 1×10 19 / cm 3 The impurity concentration of the first buffer region is n + The impurity concentration of the starting substrate is 5×10 16 / cm 3 More than 1×10 19 / cm 3 The thickness of the first buffer region is 500 nm, and the impurity concentration of the second buffer region is n + The impurity concentration of the starting substrate is 5×10 18 / cm 3 More than 2×10 19 / cm 3 the thickness of the second buffer region is 1 μm or less, and n - The impurity concentration of the drift region is 1×10 lower than that of the first buffer region. 14 / cm 3 5×10 or more 16 / cm 3 is less than or equal to n - The thickness of the mold drift region is disclosed to be 10 μm.

[0008] In addition, in the following Patent Document 4, n + Between the starting substrate and the first buffer region, between the first buffer region and the second buffer region, and between the second buffer region and n - The second buffer region and the n-type drift region are each provided with a buffer region in which the impurity concentration changes continuously in the depth direction, so that the impurity concentration at each interface does not change sharply, thereby further suppressing the occurrence of crystal defects. - Between the n-type drift region and the second buffer region, - The impurity concentration is increased to 2×10 per 1 μm of thickness toward the interface with the mold drift region. 18 / cm 3 By arranging a buffer region of about 10 μm in thickness, which is reduced by about 10 μm, the buffer region and n - It is disclosed that the impurity concentration does not become steep at the interface with the type drift region.

[0009] In the following Patent Document 5, n + The impurity concentration of the first buffer region on the starting substrate side is n + By lowering the impurity concentration to less than that of the starting substrate, + The probability that BPDs propagating from the starting substrate are converted to TEDs in the first buffer region is relatively high. By making the impurity concentration in the second buffer region higher than that in the first buffer region, the p-type base region and the n-type - The depletion layer extending from the pn junction with the n-type drift region is stopped by the second buffer region. + Between the starting substrate and the first buffer region, + A buffer region in which the impurity concentration continuously increases from the interface with the mold starting substrate toward the interface with the first buffer region is disposed, so that BPDs are easily converted to TEDs at the interface between the buffer region and the first buffer region.

[0010] In the following Patent Document 5, + The impurity concentration of the starting substrate is 1×10 18 / cm 3 Larger, 1×10 19 / cm 3The impurity concentration of the first buffer region is 1×10 16 / cm 3 Larger, 1×10 17 / cm 3 The thickness of the first buffer region is several hundreds of nanometers, and the impurity concentration of the second buffer region is 1×10 17 / cm 3 More than 1×10 19 / cm 3 The thickness of the second buffer region is less than 0.5 μm to 8 μm, and n - The impurity concentration in the drift region is 1×10 14 / cm 3 5×10 or more 16 / cm 3 is less than n - The thickness of the drift region is 3 μm to 80 μm, and the impurity concentration of the first buffer region is always n + The impurity concentration of the first buffer region is lower than that of the first substrate and the second buffer region, and - It is disclosed that the impurity concentration of the doped region is higher than that of the doped region. [Prior art documents] [Patent documents]

[0011] [Patent Document 1] International Publication No. 2017 / 104751 [Patent Document 2] Patent No. 6627938 [Patent Document 3] Patent No. 6729757 [Patent Document 4] Patent No. 6351874 [Patent Document 5] Patent No. 6791274 Summary of the Invention [Problem to be solved by the invention]

[0012] However, in the conventional silicon carbide semiconductor substrate, the second buffer region (n -By relatively increasing the impurity concentration of the n-type drift region side buffer region, - Since the difference in impurity concentration between the second buffer region and the n-type drift region becomes large, - As a result, lattice defects are more likely to occur near the interface with the type drift region, and the reliability of the silicon carbide semiconductor substrate is reduced. Also, as the impurity concentration of the second buffer region becomes higher, the controllability of the impurity concentration in the epitaxial growth of the second buffer region becomes worse, and the impurity concentration of the second buffer region varies in the depth direction more significantly, causing the on-voltage of the silicon carbide semiconductor substrate to fluctuate and reducing the reliability.

[0013] In order to solve the above-mentioned problems associated with the conventional techniques, an object of the present invention is to provide a silicon carbide semiconductor device and a silicon carbide semiconductor substrate capable of improving reliability. [Means for solving the problem]

[0014] In order to solve the above-mentioned problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention is a silicon carbide semiconductor device in which a current flows in a direction perpendicular to a main surface of a semiconductor substrate formed by epitaxially growing an epitaxial layer on a starting substrate made of silicon carbide, and has the following features: A first semiconductor region of a first conductivity type is provided inside the epitaxial layer. A second semiconductor region of a first conductivity type is provided inside the epitaxial layer, between the first semiconductor region and the starting substrate, and in contact with the starting substrate. The second semiconductor region has a higher impurity concentration than the first semiconductor region and a lower impurity concentration than the starting substrate. A third semiconductor region of a first conductivity type is provided inside the epitaxial layer, between the first semiconductor region and the second semiconductor region, and in contact with the first semiconductor region and the second semiconductor region.

[0015] The third semiconductor region has a higher impurity concentration than the second semiconductor region. The impurity concentration of the third semiconductor region increases continuously with a first impurity concentration gradient from a predetermined first depth position relatively close to a first interface between the third semiconductor region and the first semiconductor region to a predetermined second depth position relatively close to a second interface between the second semiconductor region and the third semiconductor region, and reaches a maximum impurity concentration at the second depth position. The impurity concentration of the third semiconductor region decreases continuously with a second impurity concentration gradient from the first depth position to the first interface. The impurity concentration of the third semiconductor region decreases continuously with a third impurity concentration gradient from the second depth position to the second interface. The second impurity concentration gradient is smaller than the third impurity concentration gradient.

[0016] In addition, in the silicon carbide semiconductor device according to the present invention, an absolute value of the first impurity concentration gradient is smaller than an absolute value of the second impurity concentration gradient and an absolute value of the third impurity concentration gradient.

[0017] In addition, in the silicon carbide semiconductor device according to the present invention, an impurity concentration of the third semiconductor region is equal to or less than half of the impurity concentration of the starting substrate.

[0018] In the silicon carbide semiconductor device according to the present invention, the impurity concentration of the third semiconductor region is 1.0×10 18 / cm 3 Above 5.0×10 18 / cm 3 It is characterized by being within the following range.

[0019] In the silicon carbide semiconductor device according to the present invention, the impurity concentration of the third semiconductor region is 3.0×10 18 / cm 3 It is characterized in that it is within the above range.

[0020] In the silicon carbide semiconductor device according to the present invention, the impurity concentration of the starting substrate is 1.0×10 18 / cm 3 Above 1.0×10 19 / cm 3 It is characterized by being within the following range.

[0021] In the silicon carbide semiconductor device according to the present invention, the impurity concentration of the second semiconductor region is 0.5×10 18 / cm 3 More than 1.5 x 10 18 / cm 3 It is characterized by being within the following range.

[0022] In addition, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, a thickness of the third semiconductor region is in the range of more than 1 μm and less than 7 μm.

[0023] In addition, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, a thickness of the second semiconductor region is in the range of more than 1 μm and not more than 4 μm.

[0024] In addition, in the silicon carbide semiconductor device according to the present invention, the second semiconductor region has a thickness of 1 μm or less.

[0025] In addition, in the silicon carbide semiconductor device according to the present invention described above, the third semiconductor region has a thickness of 1 μm or less.

[0026] In addition, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, a total thickness of the second semiconductor region and the third semiconductor region is in the range of 2 μm to 8 μm.

[0027] The silicon carbide semiconductor device according to the present invention includes a fourth semiconductor region of a second conductivity type, a fifth semiconductor region of a first conductivity type, a gate insulating film, a gate electrode, a first electrode, and a second electrode. The fourth semiconductor region is provided between a first main surface of the semiconductor substrate and the first semiconductor region within the epitaxial layer. The fifth semiconductor region is selectively provided between the first main surface of the semiconductor substrate and the fourth semiconductor region within the epitaxial layer. The gate insulating film is provided in contact with a region of the fourth semiconductor region between the first semiconductor region and the fifth semiconductor region. The gate electrode is provided on the opposite side of the fourth semiconductor region with the gate insulating film interposed therebetween. The first electrode is provided on a first main surface of the semiconductor substrate formed by the epitaxial layer, and is electrically connected to the fourth semiconductor region and the fifth semiconductor region. The second electrode is provided on a second main surface of the semiconductor substrate formed by the starting substrate, and is electrically connected to the starting substrate.

[0028] In order to solve the above-mentioned problems and achieve the object of the present invention, a silicon carbide semiconductor substrate according to the present invention is a silicon carbide semiconductor substrate obtained by epitaxially growing an epitaxial layer on a starting substrate made of silicon carbide, and has the following features: A first semiconductor region of a first conductivity type is provided inside the epitaxial layer. A second semiconductor region of a first conductivity type is provided inside the epitaxial layer, between the first semiconductor region and the starting substrate, and in contact with the starting substrate. The second semiconductor region has a higher impurity concentration than the first semiconductor region and a lower impurity concentration than the starting substrate. A third semiconductor region of a first conductivity type is provided inside the epitaxial layer, between the first semiconductor region and the second semiconductor region, and in contact with the first semiconductor region and the second semiconductor region.

[0029] The third semiconductor region has a higher impurity concentration than the second semiconductor region. The impurity concentration of the third semiconductor region increases continuously with a first impurity concentration gradient from a predetermined first depth position relatively close to a first interface between the third semiconductor region and the first semiconductor region to a predetermined second depth position relatively close to a second interface between the second semiconductor region and the third semiconductor region, and reaches a maximum impurity concentration at the second depth position. The impurity concentration of the third semiconductor region decreases continuously with a second impurity concentration gradient from the first depth position to the first interface. The impurity concentration of the third semiconductor region decreases continuously with a third impurity concentration gradient from the second depth position to the second interface. The second impurity concentration gradient is smaller than the third impurity concentration gradient.

[0030] According to the above-mentioned invention, by providing the third semiconductor region, it is possible to suppress the occurrence of stacking faults over time. By forming the first to third impurity concentration gradients in the impurity concentration distribution of the third semiconductor region, the decrease rate of the impurity concentration (second impurity concentration gradient) on the first semiconductor region side of the third semiconductor region becomes gentle, and the stress generated in the semiconductor substrate due to the impurity concentration difference between the third semiconductor region and the first semiconductor region can be reduced. Therefore, it is possible to suppress the occurrence of lattice defects near the first interface between the third semiconductor region and the first semiconductor region. Effect of the Invention

[0031] Advantageous Effects of Invention The silicon carbide semiconductor device and silicon carbide semiconductor substrate according to the present invention have the advantage of being able to improve reliability. [Brief description of the drawings]

[0032] [Figure 1] FIG. 1 is a cross-sectional view showing a structure of a silicon carbide semiconductor substrate according to a first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view showing a structure of the silicon carbide semiconductor device according to the first embodiment. [Diagram 3] FIG. 3 is a characteristic diagram showing the impurity concentration distribution of the first and second buffer regions of FIG. [Figure 4] FIG. 4 is a chart showing the relationship between the impurity concentration and thickness of the first and second buffer regions and the on-voltage Von in the experimental example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] Preferred embodiments of the silicon carbide semiconductor device and silicon carbide semiconductor substrate according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in a layer or region prefixed with n or p, electrons or holes, respectively, are majority carriers. In addition, + and - appended to n or p respectively mean that the impurity concentration is higher and lower than that of a layer or region not prefixed with that. In the following description of the embodiments and the accompanying drawings, the same reference numerals are assigned to similar configurations, and duplicated explanations will be omitted.

[0034] (Embodiment) The structure of a silicon carbide semiconductor device according to an embodiment will be described. FIGS. 1 and 2 are cross-sectional views showing the structures of a silicon carbide semiconductor substrate and a silicon carbide semiconductor device according to an embodiment, respectively. FIG. 3 is a characteristic diagram showing the impurity concentration distributions of the first and second buffer regions of FIG. 1. FIG. 3 shows a case where the target thickness t1 of the first buffer region 11 is 1 μm and the target thickness t2 of the second buffer region 12 is 7 μm. Also, FIG. 3 does not show the impurity concentration distributions near both main surfaces of the silicon carbide semiconductor substrate 20, and n + Starting substrate 21 and n - Only a portion of each of the mold drift regions 2 (near the interfaces 25 and 27 with the first and second buffer regions 11 and 12) is shown in the figure.

[0035] The silicon carbide semiconductor substrate 20 according to the embodiment shown in FIG. +The epitaxial substrate is formed by stacking a plurality of n-type epitaxial layers 22-24 doped with an n-type impurity such as nitrogen (N) in this order on the front surface of a starting substrate 21, and is suitable for fabricating (manufacturing) vertical silicon carbide semiconductor devices in which current flows in a direction perpendicular to the main surface of the semiconductor substrate (semiconductor chip), such as SiC-MOSFETs (FIG. 2) and pin (p-intrinsic-n) diodes (not shown). When fabricating a SiC-MOSFET using silicon carbide semiconductor substrate 20, n + The starting substrate 21 is n + This forms an n-type drain region 1. When a pin diode is fabricated using a silicon carbide semiconductor substrate 20, + The starting substrate 21 is n + This becomes the cathode region.

[0036] n + The impurity concentration of the starting mold substrate 21 is, for example, 1.0×10 18 / cm 3 Above 1.0×10 19 / cm 3 The epitaxial layers 22 to 24 are respectively a first buffer region (n-type buffer region: second semiconductor region) 11 and a second buffer region (n + type buffer region: third semiconductor region) 12 and n - The n-type drift region (first semiconductor region) 2. The impurity concentration of the n-type epitaxial layer 22 (first buffer region 11) is n + Starting substrate 21 and n + The impurity concentration of the n-type epitaxial layer 23 (second buffer region 12) is lower than that of the n-type epitaxial layer 24 (second buffer region 12). - Type epitaxial layer 24(n - The impurity concentration of the first buffer region 11 is, for example, 0.5×10 18 / cm 3 More than 1.5 x 10 18 / cm 3 It is within the range of the following.

[0037] The thickness t1 of the first buffer region 11 is preferably in the range of, for example, more than 1 μm and not more than about 4 μm. When the thickness t2 of the second buffer region 12 exceeds 1 μm, the thickness t1 of the first buffer region 11 may be set to be not more than about 1 μm. The first buffer region 11 is formed by epitaxially growing the epitaxial layers 22 to 24 and the epitaxial layers 31 and 32 (see FIG. 2) described later. + It has a function of converting BPD propagated from the starting mold substrate 21 into TED. In addition, it is possible to measure the thickness of the second buffer region 12 by Fourier transform using the infrared light reflected on the surface (interfaces 25, 26) of the first buffer region 11 (see Patent Documents 1 to 3 mentioned above).

[0038] The second buffer region 12 is a pn junction that serves as a main junction (for example, a p-type base region 4 and a p + The n-type regions 13 and 14 and the n-type current diffusion regions 3 and - When a current flows in the forward direction through the pn junction 33 (FIG. 2) with the first buffer region 12, minority carriers (holes) generated at the interface of the pn junction are captured and annihilated by recombination with majority carriers (electrons), resulting in a larger n-channel density than that of the second buffer region 12. + It has the function of reducing the number of holes that reach the BPD present on the starting substrate 21 side. - Type drift region 2 and n + By providing the second buffer region 12 between the mold starting substrate 21 and the SiC-MOSFET, the growth of stacking faults over time due to use of the SiC-MOSFET can be suppressed.

[0039] The impurity concentration of the second buffer region 12 is n + The impurity concentration of the starting substrate 21 is lower than that of the n + The impurity concentration of the second buffer region 12 is about half or less of the impurity concentration of the starting mold substrate 21. Specifically, the impurity concentration of the second buffer region 12 is, for example, 1.0×10 18 / cm 3 Above 5.0×10 18 / cm 3 Within the range of about 3.0×10 18 / cm 3It is preferable that the impurity concentration of the second buffer region 12 is within the above range. By setting the impurity concentration of the second buffer region 12 within the above range, the impurity concentration of the second buffer region 12 can be controlled to about ±10% of the target impurity concentration. Therefore, the controllability of the impurity concentration in the epitaxial growth of the second buffer region 12 is improved compared to the conventional structure in which the impurity concentration of the second buffer region exceeds the upper limit of the above range.

[0040] The impurity concentration of the second buffer region 12 is n - The second portion 23b and the n + The first portion 23a in the predetermined depth range where the impurity concentration is relatively high in the approximate center of the second buffer region 12 is higher than the third portion 23c in the mold starting substrate 21 side (the first buffer region 11 side). - This is a depth range from a predetermined depth position (hereinafter referred to as the gradient change point: first depth position) 41a that is relatively close to the interface (first interface) 27 with the mold drift region 2 to a predetermined depth position (gradient change point: second depth position) 41b that is relatively close to the interface (second interface) 26 between the first buffer region 11 and the second buffer region 12 (FIG. 3).

[0041] The impurity concentration distribution in the depth direction of the second buffer region 12 has a peak at a first portion 23a (a portion between gradient change points 41a and 41b) in a predetermined depth range in the approximate center where the impurity concentration is relatively high, and the n - Drift region 2 side and n + The impurity concentration in the second buffer region 12 in the depth direction is gradually decreased toward the starting substrate 21 side. - Gradient change points 41a to n on the side of the mold drift region 2 + A first portion 23a up to the gradient change point 41b on the starting substrate 21 side, and n - From the gradient change point 41a on the side of the drift region 2 to the second buffer region 12 and - A second portion 23b extending to an interface 27 with the n-type drift region 2; +In a third portion 23c from a gradient change point 41b on the mold starting substrate 21 side to an interface 26 between the first buffer region 11 and the second buffer region 12, first to third impurity concentration gradients 41 to 43 different from each other are formed.

[0042] Specifically, by setting the impurity concentration of the second buffer region 12 within the above range, the impurity concentration of the second buffer region 12 is n - Gradient change points 41a to n on the side of the mold drift region 2 + The impurity concentration in the second buffer region 12 increases continuously toward the gradient change point 41b on the mold starting substrate 21 side, and reaches a maximum at the gradient change point 41b. - Gradient change points 41a to n on the side of the mold drift region 2 + The absolute value of a first impurity concentration gradient 41 (increase rate: the slope of an approximate straight line is shown by the thinnest broken line in FIG. 3) in which the impurity concentration increases continuously as it approaches a gradient change point 41b on the mold starting substrate 21 side is - The absolute value of the second impurity concentration gradient 42 (rate of decrease) in which the impurity concentration decreases continuously toward the type drift region 2, and the absolute value of the third impurity concentration gradient 43 (rate of decrease) in which the impurity concentration decreases continuously from the gradient change point 41b toward the first buffer region 11 are very small compared to the absolute value of the second impurity concentration gradient 42 (rate of decrease) in which the impurity concentration decreases continuously toward the type drift region 2, and the absolute value of the third impurity concentration gradient 43 (rate of decrease) in which the impurity concentration decreases continuously from the gradient change point 41b toward the first buffer region 11.

[0043] Suppose the impurity concentration of the second buffer region 12 is n - When the impurity concentration of the second buffer region 12 is lowered to a level equal to or lower than the impurity concentration of the type drift region 2, the impurity concentration of the second buffer region 12 becomes uniform in the depth direction. When the impurity concentration of the second buffer region 12 is increased beyond the upper limit of the above range, the impurity concentration of the second buffer region 12 becomes n - From the drift region 2 side, n + The inventors have confirmed that the impurity concentration in the second buffer region 12 decreases continuously at a predetermined gradient toward the starting mold substrate 21. When the impurity concentration in the second buffer region 12 exceeds the upper limit of the above range, the second buffer region 12 and the n -The inventors have confirmed that an increase in the difference in impurity concentration between the type drift region 2 and the semiconductor substrate 30 generates stress and the like in the semiconductor substrate 30, resulting in crystal defects (lattice defects and the like) other than stacking faults.

[0044] In the embodiment, by setting the impurity concentration of the second buffer region 12 within the above range, the impurity concentration distribution in the depth direction of the second buffer region 12 is - Gradient change points 41a to n on the side of the mold drift region 2 + A first impurity concentration gradient 41 is formed in which the impurity concentration continuously increases toward a gradient change point 41b on the mold starting substrate 21 side. The first impurity concentration gradient 41 is formed in the impurity concentration distribution in the depth direction of the second buffer region 12, so that the impurity concentration distribution in the depth direction of the second buffer region 12 has a gradient of n - The second impurity concentration gradient 42 on the n-type drift region 2 side is + The second impurity concentration gradient 43 on the side of the starting substrate 21 is smaller than that on the side of the starting substrate 21. - The stress caused by the difference in impurity concentration between the second buffer region 12 and the n-type drift region 2 is reduced, and - Since crystal lattices are more likely to bond with each other at the interface 27 with the mold drift region 2, lattice defects are less likely to occur.

[0045] In addition, in the impurity concentration distribution in the depth direction of the second buffer region 12, n - The second impurity concentration gradient 42 on the n-type drift region 2 side is - The impurity concentration decreases in the shape of a parabola that is convex (upward convex) toward the high impurity concentration side near the gradient change point 41a on the side of the type drift region 2. + The third impurity concentration gradient 43 on the side of the starting substrate 21 is the n + The impurity concentration decreases in a parabolic manner convex toward the high impurity concentration side near the gradient change point 41b on the mold starting substrate 21 side. - The parabolic impurity concentration distribution near the gradient change point 41a of the second impurity concentration gradient 42 on the side of the type drift region 2 is n +Compared to the parabolic impurity concentration distribution near gradient change point 41b of third impurity concentration gradient 43 on the mold starting substrate 21 side, the curvature is smaller and the decrease in impurity concentration is more gradual.

[0046] One starting point of the second impurity concentration gradient 42 of the impurity concentration distribution in the second buffer region 12 is n - The gradient change point 41a on the side of the drift region 2, and the other starting point is n - This is a predetermined depth position (gradient change point) 42a in the drift region 2. - The impurity concentration distribution of the n-type drift region 2 has the same impurity concentration gradient as the second impurity concentration gradient 42 of the impurity concentration distribution of the second buffer region 12, and is different from the second buffer region 12 in the n-type drift region 2. - From the interface 27 with the type drift region 2 - The gradient gradually decreases toward the gradient change point 42a in the drift region 2, and at the gradient change point 42a, - This is the minimum impurity concentration in the n-type drift region 2. - The impurity concentration of the drift region 2 is uniformly n in the depth direction in the portion away from the second buffer region 12 (the portion to the left of the gradient change point 42a). - This is the minimum impurity concentration in the type drift region 2.

[0047] One starting point of the third impurity concentration gradient 43 of the impurity concentration distribution in the second buffer region 12 is n + The starting point on the other side of the mold starting substrate 21 is a gradient change point 41b, and the starting point on the other side is a predetermined depth position (gradient change point) 43a in the first buffer region 11. Therefore, the impurity concentration distribution in the first buffer region 11 has the same impurity concentration gradient as the third impurity concentration gradient 43 of the impurity concentration distribution in the second buffer region 12, and decreases continuously from the interface 26 between the first buffer region 11 and the second buffer region 12 toward the gradient change point 43a in the first buffer region 11, and the first buffer region 11 has a minimum impurity concentration at the gradient change point 43a, and the starting point on the other side of the impurity concentration gradient decreases continuously from the interface 26 between the first buffer region 11 and the second buffer region 12 toward the gradient change point 43a in the first buffer region 11, and the first buffer region 11 has a minimum impurity concentration at the gradient change point 43a. + The impurity concentration increases continuously toward the mold starting substrate 21 at a fourth predetermined impurity concentration gradient 44 .

[0048] One starting point of the fourth impurity concentration gradient 44 of the impurity concentration distribution in the first buffer region 11 is the gradient change point 43a in the first buffer region 11, and the other starting point is n + This is a predetermined depth position (gradient change point) 44a in the starting mold substrate 21. + The impurity concentration distribution of the starting substrate 21 has the same impurity concentration gradient as the fourth impurity concentration gradient 44 of the impurity concentration distribution of the first buffer region 11, and is n + The gradient increases continuously from the interface 25 between the starting mold substrate 21 and the first buffer region 11 toward the gradient change point 44a, and at the gradient change point 44a, + This is the maximum impurity concentration of the starting substrate 21. + The impurity concentration of the starting mold substrate 21 is uniform in the depth direction in the portion away from the first buffer region 11 (the portion to the right of the gradient change point 44a). + This is the maximum impurity concentration of the starting substrate 21.

[0049] The second buffer region 12 and - The interface 27 with the n-type drift region 2 is - The gradient change points 41a and n on the side of the drift region 2 - The interface 26 between the first buffer region 11 and the second buffer region 12 is located at a depth intermediate the gradient change point 42a in the second buffer region 12 (the middle of the second impurity concentration gradient 42). + This is the depth position midway between the gradient change point 41b on the mold starting substrate 21 side and the gradient change point 43a in the first buffer region 11 (the midway of the third impurity concentration gradient 43). + An interface 25 between the mold starting substrate 21 and the first buffer region 11 is located at a depth position that is linearly symmetrical to an interface 26 between the first buffer region 11 and the second buffer region 12 with respect to a gradient change point 43a in the first buffer region 11.

[0050] The thickness t2 of the second buffer region 12 is preferably in the range of, for example, more than 1 μm and less than 7 μm. When the thickness t1 of the first buffer region 11 exceeds 1 μm, the thickness t2 of the second buffer region 12 may be set to about 1 μm or less. The total thickness t10 (= t1 + t2) of the first buffer region 11 and the second buffer region 12 is, for example, in the range of about 2 μm to 8 μm, and is preferably as thin as possible. The thinner the total thickness t10 of the first buffer region 11 and the second buffer region 12 (especially the thinner the thickness t2 of the second buffer region 12, which has a relatively high impurity concentration), the more the material cost can be reduced and the more the warpage of the silicon carbide semiconductor substrate 20 (semiconductor substrate 30, which will be described further below) can be reduced. If the total thickness t10 of the first buffer region 11 and the second buffer region 12 exceeds the upper limit of the above range, the surface roughness (unevenness) of the silicon carbide semiconductor substrate 20 increases, deteriorating the coverage of the insulating film or increasing the leakage current between the gate and source of, for example, a SiC-MOSFET, which is not preferable.

[0051] n - The impurity concentration of the drift region 2 is, for example, 1.0×10 15 / cm 3 Above 2.0×10 16 / cm 3 It is within the range of about n - The thickness t3 of the drift region 2 is, for example, in the range of about 5 μm to 35 μm. - The n-type drift region 2 (the n-type drift region 2 - A p-type epitaxial layer which becomes the p-type base region 4 (see FIG. 2) or the p-type anode region is epitaxially grown on the n-type epitaxial layer 24), or a p-type epitaxial layer is epitaxially grown via an n-type epitaxial layer, thereby forming a p-n junction (e.g., corresponding to p-n junction 33 in the SiC MOSFET in FIG. 2) which becomes the main junction of a SiC MOSFET (FIG. 2) or a pin diode (not shown).

[0052] A SiC-MOSFET fabricated using a silicon carbide semiconductor substrate 20 will be described with reference to Fig. 2. The silicon carbide semiconductor device 10 according to the embodiment shown in Fig. 2 is a vertical SiC-MOSFET having a trench gate structure on the front surface side of a semiconductor substrate (semiconductor chip) 30 using SiC as a semiconductor material. The semiconductor substrate 30 is an n-type SiC-MOSFET of the silicon carbide semiconductor substrate 20 shown in Fig. 1 described above. - The epitaxial substrate is formed by stacking epitaxial layers 31 and 32 in this order on the p-type epitaxial layer 24. The semiconductor substrate 30 has a main surface on the p-type epitaxial layer 32 side as a front surface (first main surface) and an n-type epitaxial layer 33 as a second main surface. + The main surface on the starting mold substrate 21 side is referred to as the back surface. + The starting substrate 21 is n + This becomes the first type drain region.

[0053] As described above, the epitaxial layers 22 to 24 are the first and second buffer regions 11 and 12, respectively, and the n - The first and second buffer regions 11 and 12 are n - Type drift region 2 and n + The first buffer region 11 is provided between the starting substrate 21 and the n + The second buffer region 12 is adjacent to the starting substrate 21. - adjacent to the drift region 2. - The epitaxial layer 31 has an n-type current diffusion region 3 and a p-type + The n-type regions 13 and 14 are selectively formed (FIG. 2), or - The p-type epitaxial layer 32 becomes the p-type drift region 2 (not shown). The p-type epitaxial layer 32 becomes the p-type base region 4. The p-type base region 4 is connected to the front surface of the semiconductor substrate 30 and - It is provided between the mold drift region 2.

[0054] The trench gate structure includes a p-type base region (fourth semiconductor region) 4, a n + p-type source region (fifth semiconductor region) 5, ++ The p-type contact region 6, the trench 7, the gate insulating film 8 and the gate electrode 9 are formed. -Between the n-type drift region 2 and the bottom surface of the trench 7, + A n-type current diffusion region 3 and a p-type drain region 1 are formed at a deep position on the side of the n-type drain region 1. + The n-type current diffusion region 3 and the p-type current diffusion region 4 are selectively provided. + The n-type regions 13 and 14 are formed by ion implantation. - The n-type epitaxial layer 31 is a diffusion region formed inside the n-type epitaxial layer 31. - The n-type epitaxial layer 31 includes an n-type current diffusion region 3 and a p-type + The portion excluding the mold regions 13 and 14 is n - The n-type epitaxial layer 24 - This becomes type drift region 2.

[0055] The n-type current diffusion region 3 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. The n-type current diffusion region 3 is disposed between the p-type base region 4 and the n-type base region 5 in the depth direction between the adjacent trenches 7. - The n-type current diffusion region 3 is in contact with the n-type drift region 2, and extends in a direction parallel to the front surface of the semiconductor substrate 30 up to the trench 7, and contacts the gate insulating film 8. The n-type current diffusion region 3 does not necessarily have to be provided. When the n-type current diffusion region 3 is not provided, the n-type current diffusion region 3 is replaced by - Type drift region 2 is n + The insulating film 8 extends from the p-type drain region 1 side to the p-type base region 4 and also extends in a direction parallel to the front surface of the semiconductor substrate 30 to the trench 7 and contacts the gate insulating film 8 .

[0056] p + The n-type regions 13 and 14 are fixed to the potential of a source electrode (first electrode) 16 described later, and have the function of depleting the n-type current diffusion region 3 (or depleting the n-type current diffusion region 3, or both) when the SiC-MOSFET (silicon carbide semiconductor device 10) is turned off, thereby reducing the electric field applied to the gate insulating film 8 at the bottom of the trench 7. + The p-type region 13 is provided apart from the p-type base region 4 and faces the bottom surface of the trench 7 in the depth direction. + The mold region 13 is p +The p-type region 14 is electrically connected to the source electrode 16 by being partially connected to the p-type region 14 or to another p-type region. + The mold region 13 may be in contact with the gate insulating film 8 at the bottom surface of the trench 7, or may be spaced apart from the bottom surface of the trench 7.

[0057] p + The type region 14 is provided between the adjacent trenches 7 and + It is provided apart from the mold area 13. + The n-type region 14 + The surface on the side of the n-type source region 5 contacts the p-type base region 4 and is electrically connected to the source electrode 16 via the p-type base region 4. The trench 7 penetrates the p-type epitaxial layer 32 from the front surface of the semiconductor substrate 30 in the depth direction to the n-type current diffusion region 3 (or the n-type current diffusion region 3 if no n-type current diffusion region 3 is provided). - Between the adjacent trenches 7, an n-type drift region 2 is formed between the front surface of the semiconductor substrate 30 and the p-type base region 4. + Type source region 5 and p ++ Mold contact regions 6 are selectively provided.

[0058] n + Type source region 5 and p ++ The n-type contact region 6 is a diffusion region formed in the p-type epitaxial layer 32 by ion implantation. + Type source region 5 and p ++ The portion excluding the p-type contact region 6 is the p-type base region 4. + Type source region 5 and p ++ The contact region 6 reaches the front surface of the semiconductor substrate 30. + The source region 5 is p ++ The gate insulating film 8 is provided on the trench 7 side of the contact region 6 and is in contact with the gate insulating film 8 on the side wall of the trench 7. ++ The contact region 6 may not be provided. ++ When the type contact region 6 is not provided, ++Instead of the p-type contact region 6 , the p-type base region 4 reaches the front surface of the semiconductor substrate 30 .

[0059] A gate electrode 9 is provided on the gate insulating film 8 inside the trench 7 so as to fill the trench 7. The gate insulating film 8 is a n-type insulating film formed on the inner wall of the trench 7. + A p-type source region 5, a p-type base region 4, and an n-type current diffusion region 3 (or an n-type current diffusion region 3 if the n-type current diffusion region 3 is not provided) are - The trench 7 is in contact with the gate electrode 9 (type drift region 2). A gate electrode 9 is provided inside the trench 7 with a gate insulating film 8 interposed therebetween. Although only one unit cell (a constituent unit of an element) of the MOSFET is shown in FIG. 2, a plurality of unit cells having the same trench gate structure are arranged adjacent to each other on the semiconductor substrate 30. An interlayer insulating film 15 is provided on the front surface of the semiconductor substrate 30 and covers the gate electrode 9.

[0060] The contact holes in the interlayer insulating film 15 are + Type source region 5 and p ++ Type contact region 6(p ++ If no p-type contact region 6 is provided, the p-type base region 4 is exposed. The source electrode 16 is in ohmic contact with the front surface of the semiconductor substrate 30 through a contact hole in the interlayer insulating film 15, and + Type source region 5, p ++ The back surface (n + A drain electrode (second electrode) 17 is provided on the entire surface of the back surface of the starting substrate 21. The drain electrode 17 is + Type drain region 1(n + In contact with the starting substrate 21), + The gate electrode 1 is electrically connected to the drain region 1 .

[0061] The operation of the silicon carbide semiconductor device 10 according to the embodiment will now be described. When a voltage equal to or greater than the gate threshold voltage is applied to the gate electrode 9 while a positive voltage (forward voltage) with respect to the source electrode 16 is applied to the drain electrode 17, a channel (n-type inversion layer) is formed in the portion of the p-type base region 4 along the sidewall of the trench 7. + From the drain region 1 through the channel + A current flows toward the type source region 5, and the SiC-MOSFET (silicon carbide semiconductor device 10) turns on.

[0062] On the other hand, when a forward voltage is applied between the source and drain, and a voltage less than the gate threshold voltage is applied to the gate electrode 9, p + The p-type regions 13 and 14 and the p-type base region 4, and the n-type current diffusion region 3 and - When the pn junction (main junction) 33 between the type drift region 2 and the SiC-MOSFET is reverse-biased, no current flows and the SiC-MOSFET maintains the off state. + As the depletion layer spreads to the type regions 13 and 14, the electric field applied to the gate insulating film 8 on the bottom surface of the trench 7 is alleviated.

[0063] When the SiC-MOSFET is turned off, a negative voltage with respect to the source electrode 16 is applied to the drain electrode 17, so that the p-type base region 4 and the p + The n-type regions 13 and 14, the n-type current diffusion region 3 and the n - A forward current can be passed through a parasitic diode (body diode) formed by the pn junction 33 of the SiC-MOSFET and the type drift region 2. For example, the parasitic diode built into the inside of this semiconductor substrate 30 can be used as a free wheel diode for protecting the SiC-MOSFET itself.

[0064] The bipolar action of the body diode - The minority carriers (holes) injected into the n-type drift region 2 - Type drift region 2 and n +The electrons are recombined with electrons and disappear in the second buffer region 12 disposed between the starting substrate 21 and the n-type substrate 21. + This can reduce the number of holes that reach the BPDs present on the mold starting substrate 21 side, and suppress the growth of stacking faults in the epitaxial layers 22 to 24, 31, and 32. This can suppress an increase in the on-voltage Von of the SiC-MOSFET.

[0065] Next, a method for manufacturing the silicon carbide semiconductor device 10 according to the embodiment will be described. + A mold starting substrate (starting wafer) 21 is prepared. Next, + The front surface of the starting mold substrate 21 is provided with first and second buffer regions 11 and 12 and n - The epitaxial layers 22 to 24 and 31 that will become the n-type drift region 2 are epitaxially grown in this order. + The silicon carbide semiconductor substrate (semiconductor wafer) 20 shown in FIG. 1 is fabricated from the starting substrate 21 and the epitaxial layers 22 to 24. The first and second buffer regions 11, 12 and n - The conditions of the n-type drift region 2 (impurity concentration and thicknesses t1 to t3) are as described above. - The impurity concentration of the n-type epitaxial layer 31 is, for example, - The impurity concentration in the second drift region is the same as that in the first drift region.

[0066] n + 500 particles / cm in the starting mold substrate 21 2 ~1000 pieces / cm 2 Although there is a BPD of about n during epitaxial growth, + The BPD propagating from the starting substrate 21 to the epitaxial layers 22 to 24 and 31 is n + In the first buffer region 11 (n-type epitaxial layer 22) that is first epitaxially grown on the n-type starting substrate 21, the n-type epitaxial layer 22 is easily converted to TED. +It is possible to reduce the number of BPDs that extend from the n-type starting substrate 21 through the n-type epitaxial layer 22 to the epitaxial layers 23, 24, and 31. Therefore, when the body diode of the SiC-MOSFET (silicon carbide semiconductor device 10) is conductive, - It is possible to suppress the growth of stacking faults in the epitaxial layers 22 to 24, 31, and 32 starting from BPDs due to recombination of minority carriers (holes) injected into the type drift region 2.

[0067] Next, photolithography and ion implantation of p-type impurities are used to create n - The p epitaxial layer 31 is provided with p + Type region 13 and p + The lower part of the mold region 14 (n + The n-type drain region 1 side portion is selectively formed. Also, by photolithography and ion implantation of n-type impurities, - In the surface region of the epitaxial layer 31, adjacent p + Type region 13 and p + Between the n-type region 14 and the n-type current diffusion region 3, a lower portion of the n-type current diffusion region 3 is formed. - The p-type epitaxial layer 31 + The n-type regions 13 and 14 and the n-type current diffusion region 3 + The part on the mold starting substrate 21 side is n - This becomes type drift region 2.

[0068] Next, further epitaxial growth is performed to obtain n - The n-type epitaxial layer 31 is then grown to a predetermined thickness. Next, the n-type epitaxial layer 31 is formed by photolithography and ion implantation of p-type impurities. - In the thickened portion of the epitaxial layer 31, + The upper part of the mold region 14 (n + The n-type source region 5 side portion is selectively formed. Also, by photolithography and ion implantation of n-type impurities, - The upper part of the n-type current spreading region 3 is formed in the thickened portion of the p-type epitaxial layer 31. +The upper portion of the n-type region 14 and the upper portion of the n-type current diffusion region 3 are p + The p-type region 14 and the n-type current diffusion region 3 are formed in positions facing each other. + The n-type region 14 is connected to the bottom of the n-type current spreading region 3 .

[0069] Next, n - A p-type epitaxial layer 32 that will become the p-type base region 4 is epitaxially grown (deposited) on the p-type epitaxial layer 31. + A semiconductor substrate (semiconductor wafer) 30 is fabricated by sequentially stacking epitaxial layers 22 to 24, 31, and 32 on the front surface of a starting p-type substrate 21. Next, photolithography and ion implantation are repeatedly performed under different conditions to form n-type ions in the surface region of the p-type epitaxial layer 32. + Type source region 5 and p ++ The p-type contact region 6 is selectively formed on the p-type epitaxial layer 32. + Type source region 5 and p ++ n-type contact region 6 - The portion on the p-type epitaxial layer 31 side becomes the p-type base region 4 .

[0070] Next, all the diffusion regions (p + type regions 13, 14, n-type current diffusion region 3, + Type source region 5 and p ++ A heat treatment is performed on the n-type contact region 6) to activate the impurities. This heat treatment may be performed each time a diffusion region is formed by ion implantation. Next, a n-type contact region 7 is formed by photolithography and etching. + A trench 7 is formed so as to penetrate the p-type source region 5 and the p-type base region 4 and reach the n-type current diffusion region 3. Next, a gate insulating film 8, a gate electrode 9, an interlayer insulating film 15, a source electrode 16, and a drain electrode 17 are formed by a general method. Thereafter, the semiconductor wafer (semiconductor substrate 30) is diced (cut) into individual chips, thereby completing the silicon carbide semiconductor device 10 of FIG.

[0071] As described above, according to the embodiment, the silicon carbide semiconductor substrate has n + The first and second buffer regions and n-type starting substrate - The epitaxial layers that form the n-type drift region are epitaxially grown in this order. The impurity concentration of the first buffer region is - The impurity concentration in the n-type drift region is higher than that in the n-type drift region. + The impurity concentration of the second buffer region is lower than that of the starting substrate. The impurity concentration of the second buffer region is higher than that of the first buffer region. + By first epitaxially growing an n-type epitaxial layer that will become the first buffer region on the starting n-type substrate, + Since the ratio of BPDs propagating from the starting substrate to the epitaxial layer that are converted to TEDs can be increased, the growth of stacking faults originating from BPDs can be suppressed.

[0072] The impurity concentration of the second buffer region is n - The impurity concentration of the second buffer region increases continuously at a first impurity concentration gradient from a first depth position relatively close to a first interface with the first-type drift region to a second depth position relatively close to a second interface between the first buffer region and the second buffer region, has a maximum impurity concentration at the second depth position, decreases continuously at a second impurity concentration gradient from the first depth position to the first interface, and decreases continuously at a third impurity concentration gradient from the second depth position to the second interface. - The rate of decrease in the impurity concentration on the drift region side (second impurity concentration gradient) is + The decrease rate of the impurity concentration on the starting substrate side (third impurity concentration gradient) is smaller than that on the starting substrate side (third impurity concentration gradient).

[0073] n - Type drift region and n + By providing the second buffer region between the starting substrate and the silicon carbide semiconductor device, it is possible to suppress the occurrence of stacking faults over time due to use of the silicon carbide semiconductor device. - Type drift region and n +Even if the n-type impurity concentration becomes relatively high between the first and second starting substrates, the first to third impurity concentration gradients described above are formed in the impurity concentration distribution of the second buffer region, so that the n-type impurity concentration of the second buffer region can be reduced. - The rate of decrease in the impurity concentration on the n-type drift region side (second impurity concentration gradient) becomes gentler, and the second buffer region and - The stress generated in the semiconductor substrate due to the difference in impurity concentration between the second buffer region and the n-type drift region can be reduced. - This makes it possible to suppress the occurrence of lattice defects in the vicinity of the first interface with the type drift region.

[0074] The first to third impurity concentration gradients of the impurity concentration distribution of the second buffer region are set so that the impurity concentration of the second buffer region is 1.0×10 18 / cm 3 Above 5.0×10 18 / cm 3 The second buffer region is formed by lowering the impurity concentration within the range below. Furthermore, by lowering the impurity concentration within the range, the controllability of the impurity concentration in the epitaxial growth of the second buffer region is improved, and the variation in the impurity concentration in the depth direction of the second buffer region is suppressed, so that the fluctuation in the on-voltage can be suppressed. Therefore, by providing the second buffer region, the occurrence of stacking faults over time can be suppressed, and by setting the impurity concentration of the second buffer region within the above range, the occurrence of lattice defects and Von fluctuations due to the provision of a second buffer region with a relatively high impurity concentration can be suppressed, so that the reliability can be improved.

[0075] (Experimental Example) The relationship between the impurity concentration and thicknesses t1 and t2 of the first and second buffer regions 11 and 12 and the on-voltage Von was examined. FIG. 4 is a table showing the relationship between the impurity concentration and thickness of the first and second buffer regions 11 and 12 and the on-voltage Von in an experimental example. In accordance with the silicon carbide semiconductor device 10 according to the above-described embodiment, a predetermined number of samples (SiC-MOSFETs) were fabricated (hereinafter referred to as experimental examples) in which the impurity concentration and thicknesses t1 and t2 of the first and second buffer regions 11 and 12 were set under different design conditions (16 conditions: hereinafter referred to as samples No. 1 to No. 16). The body diodes of all these samples were set under the same condition (1000 A / cm 2 After passing a forward current through the SiC-MOSFET, the on-voltage Von of the SiC-MOSFET was measured.

[0076] Figure 4 shows the results of verifying the rate of variation (hereafter referred to as Von variation) from the design value of on-voltage Von (on-voltage Von expected under the design conditions of each sample) for each sample under these multiple conditions. In Figure 4, when the Von variation rate is less than 1% for all samples under the same conditions, the effect of suppressing fluctuations in on-voltage Von (hereafter referred to as Von variation suppression effect) is high (marked with a circle). When the Von variation rate is less than 5% for all samples under the same conditions, the effect of suppressing on-voltage variation is deemed to be good (marked with a triangle). Design conditions in which there is even one sample with a Von variation rate of 5% or more are deemed to have a low Von variation suppression effect (marked with an x). Under the design conditions of samples where the Von variation suppression effect is marked with a circle or triangle, it is possible to suppress Von variation within a practically usable range.

[0077] 4, it was confirmed that the Von fluctuation suppression effect was low (marked with x) in sample No. 1 (second buffer region 12 thickness t2 = 0 μm) which does not have the second buffer region 12, and samples No. 6, No. 10, No. 13, and No. 16 which do not satisfy the ranges of impurity concentration and thicknesses t1, t2 of the first and second buffer regions 11, 12 of the embodiment described above. On the other hand, it was confirmed that samples No. 2 to No. 5, No. 7 to No. 9, No. 11, No. 12, No. 14, and No. 15 which satisfy the ranges of impurity concentration and thicknesses t1, t2 of the first and second buffer regions 11, 12 of the embodiment described above can suppress Von fluctuation within a practically usable range (marked with circles and triangles).

[0078] In this way, it has been confirmed that Von fluctuations can be suppressed by satisfying the ranges of the impurity concentrations and thicknesses t1, t2 of the first and second buffer regions 11, 12 in the above-mentioned embodiment. In particular, satisfying the range of the impurity concentration of the second buffer region 12 in the above-mentioned embodiment improves the impurity concentration controllability of the epitaxial growth of the second buffer region 12 and reduces the variation in the impurity concentration of the second buffer region 12 in the depth direction, thereby enhancing the effect of suppressing Von fluctuations. Therefore, satisfying the range of the impurity concentration of the second buffer region 12 in the above-mentioned embodiment can reduce the n - By making the rate of decrease in the impurity concentration on the side of the type drift region 2 (second impurity concentration gradient 42: see FIG. 3) gentle, the occurrence of lattice defects can be suppressed, and the Von fluctuation can also be suppressed.

[0079] The present invention is not limited to the above-mentioned embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, the present invention may be applied to a Schottky barrier diode (SBD) or an IGBT (Insulated Gate Bipolar Transistor). When the present invention is applied to an SBD, the n-type silicon carbide semiconductor substrate in FIG. - When the present invention is applied to an IGBT, an electrode that makes Schottky contact with the n-type epitaxial layer is formed.+ Instead of the starting substrate, p + A starting substrate having a first conductivity type may be used. Also, instead of the trench gate structure, a planar gate structure may be used. Also, in the present invention, the first conductivity type is n-type and the second conductivity type is p-type, but the conductivity types are not limited to this, and the present invention is similarly valid even if the conductivity types (n-type, p-type) are reversed. [Industrial Applicability]

[0080] INDUSTRIAL APPLICABILITY As described above, the silicon carbide semiconductor device and silicon carbide semiconductor substrate according to the present invention are useful for power semiconductor devices used in power conversion devices and power supply devices for various industrial machines, and are particularly suitable for SiC-MOSFETs and pin diodes. [Explanation of symbols]

[0081] 1n + Type drain region 2n - Type Drift Region 3 n-type current diffusion region 4 p-type base region 5n + Type Source Area 6 p ++ Mold Contact Area 7. Trench 8 Gate insulating film 9 Gate electrode 10 Silicon carbide semiconductor device 11 First buffer region (n-type buffer region) 12 Second buffer area (n + type buffer area) 13,14 p + type area 15 Interlayer insulating film 16 Source electrode 17 Drain electrode 20 Silicon carbide semiconductor substrate 21 n + Starting substrate 22~24,31,32 Epitaxial layer 25 n + Interface between starting substrate and first buffer region 26 Interface between first and second buffer regions 27 Second buffer area and n - Interface with the mold drift region 30 Semiconductor Substrate 33 pn junction 41-44 Impurity concentration gradient 41a, 41b, 42a, 43a, 44a: Impurity concentration distribution gradient change points t1 Thickness of the first buffer region t2 Thickness of the second buffer region t3 n - Mold drift region thickness t10 Total thickness of the first and second buffer regions

Claims

1. A silicon carbide semiconductor device in which a current flows in a direction perpendicular to a main surface of a semiconductor substrate formed by epitaxially growing an epitaxial layer on a starting substrate made of silicon carbide, a first semiconductor region of a first conductivity type provided within the epitaxial layer; a second semiconductor region of a first conductivity type provided in the epitaxial layer between the first semiconductor region and the starting substrate and in contact with the starting substrate, the second semiconductor region having a higher impurity concentration than the first semiconductor region and a lower impurity concentration than the starting substrate; a third semiconductor region of a first conductivity type having an impurity concentration higher than that of the second semiconductor region, the third semiconductor region being provided in contact with the first semiconductor region and the second semiconductor region and between the first semiconductor region and the second semiconductor region within the epitaxial layer; Equipped with The impurity concentration of the third semiconductor region is the impurity concentration continuously increases at a first impurity concentration gradient from a predetermined first depth position relatively close to a first interface between the third semiconductor region and the first semiconductor region toward a predetermined second depth position relatively close to a second interface between the second semiconductor region and the third semiconductor region, and reaches a maximum impurity concentration at the second depth position; the impurity concentration continuously decreases at a second impurity concentration gradient from the first depth position toward the first interface, the third impurity concentration gradient decreases continuously from the second depth position toward the second interface; and the impurity concentration is lower than that of the starting substrate; The silicon carbide semiconductor device, wherein the second impurity concentration gradient is smaller than the third impurity concentration gradient.

2. 2 . The silicon carbide semiconductor device according to claim 1 , wherein an absolute value of the first impurity concentration gradient is smaller than an absolute value of the second impurity concentration gradient and an absolute value of the third impurity concentration gradient.

3. 2 . The silicon carbide semiconductor device according to claim 1 , wherein an impurity concentration of said third semiconductor region is equal to or less than half of an impurity concentration of said starting substrate.

4. The impurity concentration of the third semiconductor region is 1.0×10 １８ / cm ３ Above 5.0 x 10 １８ / cm ３ 2. The silicon carbide semiconductor device according to claim 1, wherein the semiconductor device has a capacitance within the range below.

5. The impurity concentration of the third semiconductor region is 3.0×10 １８ / cm ３ 5. The silicon carbide semiconductor device according to claim 4, wherein the capacitance is within the above range.

6. The impurity concentration of the starting substrate is 1.0×10 １８ / cm ３ Above 1.0 x 10 １９ / cm ３ 2. The silicon carbide semiconductor device according to claim 1, wherein the semiconductor device has a capacitance within the range below.

7. The impurity concentration of the second semiconductor region is 0.5×10 １８ / cm ３ Above 1.5 x 10 １８ / cm ３ 2. The silicon carbide semiconductor device according to claim 1, wherein the semiconductor device has a capacitance within the range below.

8. 2 . The silicon carbide semiconductor device according to claim 1 , wherein the third semiconductor region has a thickness in the range of more than 1 μm and less than 7 μm.

9. 9. The silicon carbide semiconductor device according to claim 8, wherein the second semiconductor region has a thickness in the range of more than 1 μm and not more than 4 μm.

10. The silicon carbide semiconductor device according to claim 8 , wherein the second semiconductor region has a thickness of 1 μm or less.

11. 2 . The silicon carbide semiconductor device according to claim 1 , wherein the second semiconductor region has a thickness in the range of more than 1 μm and not more than 4 μm.

12. The silicon carbide semiconductor device according to claim 11 , wherein the third semiconductor region has a thickness of 1 μm or less.

13. 2 . The silicon carbide semiconductor device according to claim 1 , wherein a total thickness of said second semiconductor region and said third semiconductor region is within a range of not less than 2 μm and not more than 8 μm.

14. a fourth semiconductor region of a second conductivity type provided within the epitaxial layer between the first main surface of the semiconductor substrate and the first semiconductor region; a fifth semiconductor region of a first conductivity type selectively provided within the epitaxial layer between the first main surface of the semiconductor substrate and the fourth semiconductor region; a gate insulating film provided in contact with a region of the fourth semiconductor region between the first semiconductor region and the fifth semiconductor region; a gate electrode provided on the opposite side of the fourth semiconductor region with the gate insulating film interposed therebetween; a first electrode provided on a first main surface formed of the epitaxial layer of the semiconductor substrate and electrically connected to the fourth semiconductor region and the fifth semiconductor region; a second electrode provided on a second main surface of the semiconductor substrate formed of the starting substrate and electrically connected to the starting substrate; The silicon carbide semiconductor device according to any one of claims 1 to 13, comprising:

15. A silicon carbide semiconductor substrate in which an epitaxial layer is epitaxially grown on a starting substrate made of silicon carbide, a first semiconductor region of a first conductivity type provided within the epitaxial layer; a second semiconductor region of a first conductivity type provided in the epitaxial layer between the first semiconductor region and the starting substrate and in contact with the starting substrate, the second semiconductor region having a higher impurity concentration than the first semiconductor region and a lower impurity concentration than the starting substrate; a third semiconductor region of a first conductivity type having an impurity concentration higher than that of the second semiconductor region, the third semiconductor region being provided in contact with the first semiconductor region and the second semiconductor region and between the first semiconductor region and the second semiconductor region within the epitaxial layer; Equipped with The impurity concentration of the third semiconductor region is the impurity concentration continuously increases at a first impurity concentration gradient from a predetermined first depth position relatively close to a first interface between the third semiconductor region and the first semiconductor region toward a predetermined second depth position relatively close to a second interface between the second semiconductor region and the third semiconductor region, and reaches a maximum impurity concentration at the second depth position; the impurity concentration continuously decreases at a second impurity concentration gradient from the first depth position toward the first interface, the third impurity concentration gradient decreases continuously from the second depth position toward the second interface; and the impurity concentration is lower than that of the starting substrate; The silicon carbide semiconductor substrate, wherein the second impurity concentration gradient is smaller than the third impurity concentration gradient.

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