MEMORY DEVICES, INTEGRATED CIRCUIT BOARDS, MEMORY CHIPS, ELECTRONIC DEVICES, AND METHOD FOR MANUFACTURING MEMORY DEVICES - Patent application

Abstract

To provide a fabrication method for protecting a memory bit material during an etching process.SOLUTION: A memory cell structure includes at least one memory bit layer 112 stacked between top and bottom electrodes. The memory bit layer provides a storage element for a corresponding memory cell. A plurality of conductive layers 110, 114 are included between the memory bit layer and either or both of the top and bottom electrodes to provide a better ohmic contact. In any case, a dielectric liner structure 109 is provided on sidewalls of the memory bit layer. The dielectric liner structure includes a first dielectric layer 116, and may also include a second dielectric layer 118 on the first dielectric layer. Either or both of the first dielectric layer and the second dielectric layer include a high dielectric constant material. As will be appreciated, the dielectric liner structure effectively protects the memory bit layer from lateral erosion and contamination during the etching of subsequent layers beneath the memory bit layer.SELECTED DRAWING: Figure 1A

Description

[Background technology]

[0001] As electronic devices become smaller and more complex, the need to store and access more data similarly quickly grows. New memory architectures have been developed that use arrays of memory cells with specialized materials that have variable bulk resistance, the resistance of which determines whether a given memory cell stores a logic "0" or a logic "1". Many challenges exist when manufacturing such memory architectures. [Brief description of the drawings]

[0002] Features and advantages of embodiments of the claimed subject matter will become apparent as the following detailed description proceeds and when reference is made to the drawings.

[0003] [Figure 1A] 1 is a partial cross-sectional view of a stacked array of memory cells according to some embodiments of the present disclosure.

[0004] [Figure 1B] 2A-2C are orthogonal cross-sectional views of a stacked array of memory cells in accordance with some embodiments of the present disclosure. [Figure 1C] 2A-2C are orthogonal cross-sectional views of a stacked array of memory cells in accordance with some embodiments of the present disclosure.

[0005] [Diagram 2] 1 is a cross-sectional view of a chip package including one or more memory dies according to some embodiments of the present disclosure.

[0006] [Diagram 3] 1A-1D are partial cross-sectional views of a memory device during a manufacturing procedure of the memory device according to some embodiments of the present disclosure.

[0007] [Figure 4A] 1A-1D are orthogonal cross-sectional views of states of a memory device during manufacturing according to some embodiments of the present disclosure. [Figure 4B] 1A-1D are orthogonal cross-sectional views of states of a memory device during manufacturing according to some embodiments of the present disclosure.

[0008] [Figure 5A] 1A-1C are orthogonal cross-sectional views of another state of a memory device during manufacturing according to some embodiments of the present disclosure. [Figure 5B] 1A-1C are orthogonal cross-sectional views of another state of a memory device during manufacturing according to some embodiments of the present disclosure.

[0009] [Figure 6A] 1A-1C are orthogonal cross-sectional views of another state of a memory device during manufacturing according to some embodiments of the present disclosure. [Figure 6B] 1A-1C are orthogonal cross-sectional views of another state of a memory device during manufacturing according to some embodiments of the present disclosure.

[0010] [Figure 7A] 1A-1C are orthogonal cross-sectional views of another state of a memory device during manufacturing according to some embodiments of the present disclosure. [Figure 7B] 1A-1C are orthogonal cross-sectional views of another state of a memory device during manufacturing according to some embodiments of the present disclosure.

[0011] [Figure 8A] 1A-1C are orthogonal cross-sectional views of another state of a memory device during manufacturing according to some embodiments of the present disclosure. [Figure 8B] 1A-1C are orthogonal cross-sectional views of another state of a memory device during manufacturing according to some embodiments of the present disclosure.

[0012] [Figure 9A] 1A-1C are orthogonal cross-sectional views of another state of a memory device during manufacturing according to some embodiments of the present disclosure. [Figure 9B] 1A-1C are orthogonal cross-sectional views of another state of a memory device during manufacturing according to some embodiments of the present disclosure.

[0013] [Figure 10A] 1A-1C are orthogonal cross-sectional views of another state of a memory device during manufacturing according to some embodiments of the present disclosure. [Figure 10B] 1A-1C are orthogonal cross-sectional views of another state of a memory device during manufacturing according to some embodiments of the present disclosure.

[0014] [Figure 11A] 1A-1C are orthogonal cross-sectional views of another state of a memory device during manufacturing according to some embodiments of the present disclosure. [Figure 11B] 1A-1C are orthogonal cross-sectional views of another state of a memory device during manufacturing according to some embodiments of the present disclosure.

[0015] [Figure 12A] 1A-1C are orthogonal cross-sectional views of another state of a memory device during manufacturing according to some embodiments of the present disclosure. [Figure 12B] 1A-1C are orthogonal cross-sectional views of another state of a memory device during manufacturing according to some embodiments of the present disclosure.

[0016] [Figure 13A] 1A-1C are orthogonal cross-sectional views of another state of a memory device during manufacturing according to some embodiments of the present disclosure. [Figure 13B] 1A-1C are orthogonal cross-sectional views of another state of a memory device during manufacturing according to some embodiments of the present disclosure.

[0017] [Figure 14A] 1A-1C are orthogonal cross-sectional views of another state of a memory device during manufacturing according to some embodiments of the present disclosure. [Figure 14B] 1A-1C are orthogonal cross-sectional views of another state of a memory device during manufacturing according to some embodiments of the present disclosure.

[0018] [Figure 15] 1 is a flow chart of a process for manufacturing a memory device according to an embodiment of the present disclosure.

[0019] [Figure 16] 1 is an exemplary electronic device that may include one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] The following detailed description proceeds with reference to exemplary embodiments, many alternatives, modifications, and variations of which will become apparent in light of this disclosure. It is further understood that the drawings are not necessarily drawn to scale or intended to limit the disclosure to the particular configurations shown. For example, while some drawings generally show perfect straight lines, right angles, and smooth surfaces, given any real-world limitations of the processing equipment and technology used, actual implementations of integrated circuit structures may not meet perfect straight lines, right angles, and some features may have surface topologies or otherwise non-smooth surfaces.

[0021] A memory cell design is disclosed. The design is particularly suitable for a three-dimensional cross-point (3D X-point) memory configuration, although it will become apparent that other memory applications may benefit. In one embodiment, the memory cell structure includes at least one memory bit layer stacked between a top electrode and a bottom electrode. The memory bit layer provides the storage element for the corresponding memory cell. One or more additional conductive layers may be included between the memory bit layer and either the top electrode or the bottom electrode or both to provide better ohmic contact. In either case, a dielectric liner structure is provided on the sidewalls of the memory bit layer. In one embodiment, the liner structure includes a dielectric layer, while in another embodiment, the liner structure includes a second dielectric layer on the first dielectric layer. Either the first dielectric layer and / or the second dielectric layer or both include a high-k material. As will be appreciated in view of this disclosure, the dielectric liner structure effectively protects the memory bit layer from lateral erosion and contamination during etching of subsequent layers below the memory bit layer. Numerous configurations and embodiments will become apparent in view of this disclosure. General Overview

[0022] As mentioned above, there are some non-trivial problems associated with fabricating memory arrays based on memory bit material bulk resistance changes. For example, the memory bit material may be included as a layer in a multi-layer stack that further includes an electrode material layer. This multi-layer stack is then etched into an array of smaller individual stacks. Each of the individual stacks may be used as one memory cell of the overall array. One problem that occurs during this etching process is that as the etching continues on the stacks, the etching process exposes various layers of material, and some materials may contaminate other materials if they are exposed together in the same etching chamber. For example, etching a metal material while exposing the memory bit material may cause sidewall damage to the memory bit material. For example, in some cases, etching tungsten while leaving portions of the memory bit material exposed may cause undesired lateral etching of the memory bit material, resulting in a tapered shape. This tapered shape causes degradation of electrical properties and reduces the performance of the memory cell.

[0023] Therefore, techniques and designs are provided herein to help eliminate or otherwise reduce such problems. In an exemplary embodiment, a manufacturing method is provided for using a dielectric liner layer or structure to protect a memory bit layer before further etching is performed on the metal layer. The method includes depositing a first conductive layer on a substrate and depositing a first stack on the first conductive layer. The first stack includes a first memory bit layer. The method includes etching only a portion of the total thickness of the first stack such that the entire thickness of the first memory bit layer is etched but the next metal layer is not (or is otherwise minimally etched), and then depositing one or more dielectric layers on at least one or more sidewalls of the memory bit layer. The method further includes etching the remaining portion of the first stack and etching the thickness of the conductive layer after the dielectric liner is in place on the memory bit layer.

[0024] The various operations should not be described sequentially as multiple separate operations or processes in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations are necessarily order dependent. In particular, these operations need not be performed in the order presented. The operations described may be performed in a different order than in the described embodiment. Various additional operations may be performed and / or described operations may be omitted in additional embodiments.

[0025] The description uses the phrases "in one embodiment" or "in an embodiment," each of which may refer to one or more of the same or different embodiments. Furthermore, terms such as "comprising," "including," and "having" used with respect to embodiments of the present disclosure are synonymous. When used to describe a range of dimensions, the phrase "between X and Y" represents a range that includes X and Y. For convenience, the phrase "FIG. 1" may be used to refer to the set of drawings in FIG. 1A and FIG. 1B, the phrase "FIG. 4" may be used to refer to the set of drawings in FIG. 4A and FIG. 4B, and so forth.

[0026] It should be readily understood that the meaning of "above" and "over" in this disclosure should be interpreted in the broadest manner to include not only the meaning of "directly", "above" and "over" something, but also the meaning of something with intermediate features or layers between them. In addition, the meaning of "on" in this disclosure should be interpreted as meaning "directly" with respect to something (i.e., without intermediate features or layers between them).

[0027] Additionally, terms such as "beneath," "below," "lower," "above," "upper," and similar such spatially relative terms may be used herein to describe the relationship of one element or feature to another element or feature as illustrated, and to simplify the description. Spatially relative terms are intended to include different orientations of the device during use or operation in addition to the orientation shown in the figures. The device may be in other orientations (rotated 90 degrees or otherwise) and therefore the spatially relative descriptors used herein may be interpreted similarly.

[0028] As used herein, the term "substrate" refers to a material to which subsequent layers of material are added. The substrate itself may be patterned. Materials added on top of the substrate may be patterned or left unpatterned. Additionally, substrates may include a wide array of semiconductor materials, such as, for example, silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, substrates may be fabricated from non-conductive materials, such as, for example, glass, plastic, or sapphire wafers.

[0029] As used herein, the term layer refers to a portion of a material that includes a region having a thickness. A monolayer is a layer consisting of a single layer of atoms of any material. A layer can extend throughout an underlying or overlying structure or can have an extent that is less than the extent of an underlying or overlying structure. Additionally, a layer can be a homogeneous or heterogeneous region of a continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be disposed between the top and bottom surfaces of a continuous structure or between any pair of horizontal surfaces at its top and bottom surfaces. A layer can extend horizontally, vertically, and / or along a tapered surface. A layer can be conformal to any surface (whether flat or curved) that has a relatively uniform thickness throughout the layer. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers on, above, and / or below it. Memory Array Architecture

[0030] FIG. 1A illustrates a cross-sectional view of a portion 100 of a memory cell array according to an embodiment. According to an embodiment, the portion 100 includes adjacent memory cells 102, each including a stack of material layers 108 sandwiched between a particular word line 104 and a bit line 106. To read from or program the memory cell 102 at the intersection (between) of the selected word line 104 and the selected bit line 106, a potential is applied across the particular word line 104 and the particular bit line 106. In such a manner, the word line 104 and the bit line 106 provide a top electrode and a bottom electrode for the memory cell 102. As described in this example, the word line 104 is orthogonal to the bit line 106. The word line 104 and the bit line 106 may be fabricated from any conductive material, such as a metal, a metal alloy, or polysilicon. In some examples, the word line 104 and the bit line 106 are fabricated from tungsten, silver, aluminum, gold, carbon, or copper, or a multi-layer structure comprising such materials (e.g., a tungsten layer and a carbon layer).

[0031] According to an embodiment, each memory cell 102 includes a stack 108 having at least one memory bit layer 112. As used herein, the term "memory bit layer" refers to the standard meaning of that term in the context of a memory device, and in some cases refers to one or more layers including a metalloid alloy. Metalloids include, for example, boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te), selenium (Se), and polonium (Po). In some embodiments, the memory bit layer 112 includes a chalcogenide, which comprises an alloy of germanium, arsenic, antimony, and tellurium, such as GeTe, GeSbTe, GeBiTe (GeTe alloyed with bismuth), GeAsSe, GeSiAsSe, or GeInSbTe (GeSbTe alloyed with indium), to name a few non-limiting examples. Additionally, it should be noted that the stoichiometry of such chalcogenide compounds may vary from one embodiment to another, and that such compounds expressed without a stoichiometric coefficient or value are intended to represent all forms of that compound.

[0032] The memory bit layer 112 includes a material that changes its threshold voltage based on the polarity of the electrical potential applied to it to represent either a logic "0" or a logic "1" for a given memory cell 102. In an exemplary embodiment, a chalcogenide is used as the memory bit material and can change its threshold voltage based on the polarity of the electrical potential applied to the chalcogenide.

[0033] The stack 108 may include one or more other conductive layers. For example, the stack 108 may include a first conductive layer 110 and a second conductive layer 114 to provide an enhanced ohmic contact to the memory bit layer 112. In one embodiment, the conductive layers 110 and 114 include tungsten and / or carbon.

[0034] As described above, at least the sidewalls of the memory bit layer 112 are protected by a dielectric liner structure 109, which in an exemplary embodiment includes a dielectric liner 116. According to an embodiment, the dielectric liner 116 includes a high-k material. As shown, the dielectric liner 116 can be present in contact with one or more sidewalls of only a portion of the total thickness of the stack 108 (e.g., rather than the entire thickness of the stack 108). For example, in the exemplary embodiment shown, the dielectric liner 116 is not present in contact with the sidewalls of the first conductive layer 110. The dielectric liner 116 effectively protects the memory bit layer 112 from lateral erosion and contamination during etching of lower material layers (e.g., layer 110, etc.). Further examples of the dielectric liner 116 and details of its manufacturing process are described with respect to FIGS. 5-14.

[0035] It is further noted that the dielectric liner structure 109 may include additional layers. For example, in the exemplary embodiment shown, an additional dielectric layer 118 is provided on each sidewall of the memory cell 102 to act as a barrier between the various material layers of the memory cell 102 and the oxide fill 120. In some embodiments, the oxide fill 120 fills the remaining area between adjacent memory cells 102. It is noted that the additional dielectric layer 118 may cover a larger portion of the memory cell sidewall. For example, in the exemplary embodiment shown, the dielectric liner 118 is present in contact with the sidewall of the first conductive layer 110 in addition to the dielectric liner 116. In yet other embodiments, an initial dielectric layer, such as a nitride layer, is deposited prior to the dielectric liner 116 to improve adhesion between the liner 116 and the memory cell material.

[0036] 1B and 1C are cross-sectional views of a memory array 122 according to an embodiment. These cross-sectional views are perpendicular to each other in the memory array 122. The memory array 122 includes a number of memory cells 102 arranged in arrays A, B, and C stacked in the Z direction to form a three-dimensional memory structure. The array includes an ordered arrangement of rows and columns of memory cells 102 in the XY plane as shown in FIG. 1B and FIG. 1C. Similarly, other ordered arrangements are possible. In general, each memory cell 102 includes a stack 108 including one or more bit layers. In addition, the sidewalls of portions of the stack 108 are protected by a dielectric liner structure 109 such that at least one or more bit layers of the stack 108 are protected.

[0037] The memory array 122 further includes a number of word lines 104 and bit lines 106 that are used to address particular memory cells 102. As described in this example, the word lines 104 are orthogonal to the bit lines 106, and the memory array 100 alternates between the word lines 104 and the bit lines 106 in the Z direction. With reference to Figures 1B and 1C, the word lines 104 extend along the Y direction (into and out of the page in Figure 1B) and the bit lines 106 extend along the X direction (into and out of the page in Figure 1C).

[0038] The number of memory cells 102 shown is used purely as an example, and it is understood that any number of memory cells 102 can be used in each stage, and any number of stages in the Z direction can be used as well. According to an embodiment, the height in the Z direction of a given memory cell 102 is between about 30 nm and about 50 nm. According to an embodiment, the width in either the X or Y direction of a given memory cell 102 is between about 10 nm and about 20 nm. The width may be the same in both the X and Y directions. In some embodiments, the width of a given memory cell differs between the X and Y directions. Any number of memory cell geometries may be used, as will be understood.

[0039] FIG. 2 illustrates an exemplary embodiment of a chip package 200. As shown, the chip package 200 includes one or more dies 202. The chip package 200 may be a memory device if the die 202 includes one or more memory dies, whether dedicated memory dies or some other die with memory portions juxtaposed to other functional circuits of the die (e.g., a processor with on-board memory, etc.). In some configurations, the die 202 may include any number of memory arrays 122, as well as any other circuitry used to interface with the memory arrays. In still other embodiments, the memory arrays 122 may be present on one die 202 and other circuitry used to interface with the die 202 (e.g., cell selection circuitry, read circuitry, and programming circuitry) on other dies in the chip package 200.

[0040] As will be further appreciated, the chip package 200 includes a housing 204 coupled to a package substrate 206. The housing 204 may be any standard or proprietary housing, for example, providing electromagnetic shielding and environmental protection for the components of the chip package 200. The one or more dies 202 may be conductively coupled to the package substrate 206 using connections 208 that may be implemented with any number of standard or proprietary connection mechanisms, such as, for example, solder bumps, ball grid arrays (BGAs), pins, or wire bonds, to name a few. The package substrate 206 may be any standard or proprietary package substrate, but in some cases includes a dielectric material having conductive paths (e.g., including conductive vias and conductive lines) that extend across the dielectric material between faces of the package substrate 206 or between different locations on each face. In some embodiments, the package substrate 206 may have a thickness less than 1 millimeter (e.g., between 0.1 millimeters and 0.5 millimeters), although any number of package geometries may be used. Additional conductive contacts 212 may be disposed on the opposite side of the package substrate 206, for example, to conductively contact a printed circuit board or the like. One or more vias 210 extend across the thickness of the package substrate 206 to provide a conductive path between one or more connections 208 and one or more contacts 212. The vias 210 are illustrated as single straight posts through the package substrate 206 for ease of illustration, although other configurations may be used (e.g., damascene, dual damascene, through silicon vias). In still other embodiments, the vias 210 are fabricated by multiple smaller stacked vias, or zigzag at different locations across the package substrate 206. In the illustrated embodiment, the contacts 212 are solder balls (e.g., bump-based connections, or ball grid array arrangement), although any suitable package bonding mechanism may be used (e.g., pins in a pin grid array arrangement, or areas in a land grid array arrangement). In some embodiments, solder resist is disposed between the contacts 212 to inhibit shorting.

[0041] In some embodiments, the molding material 214 may be disposed around one or more dies 202 contained within the housing 204 (e.g., between the die 202 and the package substrate 206 as an underfill material, as well as between the die 202 and the housing 204 as an overfill material). The dimensions and quality of the molding material 214 may vary from one embodiment to another, but in some embodiments, the molding material 214 is less than 1 millimeter thick. Exemplary materials that can be used for the molding material 214 include suitable epoxy molding materials. In some cases, the molding material 214 is thermally conductive in addition to being electrically insulating. Manufacturing Procedure

[0042] FIG. 3 is a cross-sectional view showing an early stage of the manufacturing process for a portion of the memory array 100 according to an embodiment. Subsequent FIGS. 4-14 show further stages of the manufacturing process, with each figure showing a cross-section along the X axis (A) and along the Y axis (B). For example, FIG. 4A shows a cross-sectional view of a portion of the memory array 122 along the X axis at the break line AA shown in FIG. 4B, and FIG. 4B shows a cross-sectional view of a portion of the memory array 122 along the Y axis at the break line BB shown in FIG. 4A. For all figures, the Z axis is the vertical axis on the page (i.e., along the respective thicknesses of the deposited layers). The various layers and structures shown in FIGS. 3-14 are not intended to be drawn to scale, but are shown in a particular shape for visual clarity. It is further noted that some intermediate processes may be performed (e.g., polishing and removal processes, or other standard processes, etc.) that are not explicitly shown as will be understood. In other embodiments, not all layers shown may be used and / or additional layers may be included.

[0043] 3, a first conductive layer 304 is deposited on a substrate 301, followed by deposition of a stack 308. The substrate 301 may be any suitable substrate material for forming additional layers of material thereon. In some embodiments, the substrate 301 comprises a bulk semiconductor material such as silicon, germanium, silicon germanium (SiGe), gallium arsenide, or indium phosphide. The substrate 301 may include one or more insulating layers on its top surface, such as silicon oxide or silicon nitride, or may be buried beneath an upper semiconductor layer, such as in a semiconductor-on-insulator substrate configuration.

[0044] The first conductive layer 304 may be a metal, such as, for example, tungsten, silver, aluminum, titanium, cobalt, or an alloy. In some embodiments, the first conductive layer 304 has a sufficient thickness (e.g., a thickness between 1 nm and 50 nm) to propagate a signal after the first conductive layer 304 is patterned into a word line or bit line.

[0045] According to an embodiment, the stack 308 may include one or more conductive layers 310 and 314 having a memory bit layer 312 sandwiched therebetween. Each of the conductive layers 310 and 314 may include any conductive material that enhances ohmic contact to the memory bit layer 312. In one example, the conductive layers 310 and 314 include carbon. The first stack 308 may include any number of deposited layers having at least one memory bit layer 312. In some embodiments, the stack 308 includes two or more layers having memory bit materials. The various layers may be deposited using standard deposition techniques, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD) techniques.

[0046] According to one embodiment, first conductive layer 304 has a thickness of about 30 to 50 nm, each of conductive layers 310 and 314 has a thickness of about 10 to 15 nm, and memory bit layer 312 has a thickness of about 15 to 25 nm. All layers can be deposited using any standard deposition technique, such as metal sputtering or evaporation for first conductive layer 304, and plasma enhanced chemical vapor deposition (PECVD) for conductive layers 310, 314 and memory bit layer 312.

[0047] According to an embodiment, FIGS. 4A and 4B show a first etching process that etches a portion of the total thickness t of the stack 308 (generally indicated by the arrows). According to an embodiment, the etch forms a strip of the material layer including the memory bit layer 312 extending along the Y direction. The etch process etches the thickness of the memory bit layer 312, thus exposing the sidewalls of the memory bit layer 312. However, according to an embodiment, the etch does not extend into any portion of the first conductive layer 304. In one example, the etch stops at the conductive layer 310. In some other examples, the etch extends into a portion of the thickness of the conductive layer 310. Lateral etching of the material layers is minimized due to the anisotropy of the etch process. According to an embodiment, this anisotropic etch is performed using standard dry etching techniques by placing the substrate 301 in a vacuum chamber and introducing different gas chemistries and bias potentials to etch the various material layers. In addition, standard lithography techniques are performed to form a hard mask layer (not shown) to mask portions of the layers from etching. Exemplary hardmask layers include silicon oxide or silicon nitride.

[0048] 5A and 5B show deposition of a first dielectric layer 502 on at least the sidewalls of the memory bit layer 312. Although not explicitly shown for clarity, the deposition of the first dielectric layer 502 covers all areas of the device, and an etching process is performed to remove the planar portion of the first dielectric layer 502, thus leaving the sidewall portion of the deposited film. In the illustrated example, the dielectric layer 502 is deposited on the sidewalls of the memory bit layer 312, on the sidewalls of the conductive layer 314, and on the top surface of the conductive layer 310.

[0049] The first dielectric layer 502 may comprise, for example, silicon nitride, due to its favorable adhesive properties to most other materials. In some other examples, the first dielectric layer 502 comprises a high-k material that may be used with or without a nitride layer on its own. Examples of high-k materials include materials containing one or more of the following elements: lithium (Li), boron (B), magnesium (Mg), aluminum (Al), silicon (Si), calcium (Ca), scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), zinc (Zn), gallium (Ga), germanium (Ge), strontium (Sr), yttrium (Y), zirconium (Zr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), or a combination thereof. The first dielectric layer 502 may comprise oxides of ruthenium (Ru), rhodium (Rh), indium (In), tin (Sn), antimony (Sb), barium (Ba), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), dysporosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), hafnium (Hf), tantalum (Ta), iridium (Ir), platinum (Pt), lead (Pb), and bismuth (Bi). In certain exemplary embodiments, the first dielectric layer 502 comprises hafnium oxide (Hfo), zirconium oxide (ZrO), or aluminum oxide (AlO). Other examples of high dielectrics include hafnium silicon oxide, lanthanum aluminum oxide, barium strontium titanium oxide, zirconium silicon oxide, barium titanium oxide, strontium titanium oxide, lead scandium tantalum oxide, and lead zinc niobate. In a more general sense, a high dielectric is a dielectric material having a dielectric constant greater than that of silicon dioxide. According to an embodiment, the first dielectric layer 502 may be deposited, for example, using a low temperature (e.g., less than 350° C.) atomic layer deposition (ALD) process. According to an embodiment, the first dielectric layer 502 may be deposited at a thickness of about 20 Å to about 50 Å.

[0050] According to an embodiment, Figures 6A and 6B show a second etching process (generally indicated by arrows) that etches the remaining portion of the thickness of the stack 308 and the thickness of the first conductive layer 304. The second etching process may be similar to the etching process shown in Figure 4 to provide the desired angle of directionality, such as an anisotropic dry etch. Less directional etches (wet and / or dry can be used as well, but lateral etching may occur, which may or may not be acceptable in any application). During the second etching process, the exposed sidewalls of the memory bit layer 312 are protected by the first dielectric layer 502. According to an embodiment, specifically, during the time that the first conductive layer 304 is etched, a portion of the memory bit layer 312 is not exposed. The etching process patterns strips of the first conductive layer 304 extending in the Y direction, thus forming multiple of either word lines or bit lines.

[0051] According to an embodiment, Figures 7A and 7B show the deposition of an additional layer of material between adjacent layer stacks. According to some such embodiments, a second dielectric layer 702 is deposited on the first dielectric layer 502. According to an embodiment, the second dielectric layer 702 is further deposited on the sidewalls of each layer stack and on the sidewalls of the etched first conductive layer 304. In some embodiments, the second dielectric layer 702 may include any of the materials described above for the first dielectric layer 502, but may be different in other embodiments. For example, in some embodiments, the first layer 502 is a nitride and the second layer 702 is a high-k dielectric, while in other embodiments, the first layer 502 is a high-k dielectric and the second layer 702 is a regular dielectric (e.g., an oxide, nitride, or oxynitride). The second dielectric layer 702 may be deposited, for example, to a thickness of about 20 Å to about 50 Å using standard deposition techniques, such as the same low-temperature ALD process used to deposit the first dielectric layer 502.

[0052] A filler material 704 is deposited between adjacent layer stacks to fill the remaining areas. In some embodiments, the filler material 704 is silicon oxide and is deposited using a PECVD process. After deposition of the filler material 704, the top surface of the structure may be planarized using a chemical mechanical polishing (CMP) process.

[0053] According to an embodiment, Figures 8A and 8B show the deposition of a second conductive layer 806 and another stack 804 including at least one memory bit layer 802. The stack 804 may have substantially the same structure as the stack 308, but in other embodiments, may be modified in one or more respects, as will be appreciated. Similarly, the second conductive layer 806 may be the same material as the first conductive layer 304, but need not be. In some embodiments, the second conductive layer 806 has a greater thickness than the first conductive layer 304.

[0054] According to an embodiment, FIGS. 9A and 9B show another etching process that etches a portion of the total thickness t of the stack 804 (generally indicated by the arrows). According to an embodiment, the etch forms strips of several material layers of the stack 804, including the memory bit layer 802, extending along the X direction. In this example, as shown, the etch process etches the thickness of the memory bit layer 802, thus exposing the sidewalls of the memory bit layer 802. However, according to an embodiment, the etch does not extend into any portion of the second conductive layer 806. Lateral etching of the material layers is minimized due to the anisotropy of the etch process. According to an embodiment, this anisotropic etch is performed using standard dry etching techniques by placing the substrate 301 in a vacuum chamber and introducing different gas chemistries and bias potentials to etch the various material layers. In addition, standard lithography techniques are performed to form a hard mask layer (not shown) to mask portions of the layers from etching. Exemplary hard mask layers include silicon oxide or silicon nitride.

[0055] According to an embodiment, Figures 10A and 10B show deposition of a third dielectric layer 1002 on at least the sidewalls of the memory bit layer 802. Although not explicitly shown for clarity, the deposition of the third dielectric layer 1002 covers all areas of the device, and an etching process is performed to remove the flat portion of the third dielectric layer 1002, thus leaving the sidewall portion of the deposited film. The third dielectric layer 1002 may include any of the same materials described above for the first dielectric layer 502. The third dielectric layer 1002 may be deposited using a low temperature (e.g., less than 350°C) ALD process. The third dielectric layer 1002 may be deposited to a thickness of about 20 Å to about 50 Å.

[0056] According to an embodiment, Figures 11A and 11B show another etching process (generally indicated by arrows) that etches the remaining portion of the thickness of the stack 804 and the thickness of the second conductive layer 806. According to an embodiment, the etching process may be similar to the etching process shown in Figure 6. During the etching process, the memory bit layer 802 is protected by the third dielectric layer 1002. According to an embodiment, specifically, during the time that the second conductive layer 806 is etched, some of the exposed sidewalls of the memory bit layer 802 are not exposed. The etching process patterns strips of the second conductive layer 806 extending in the X-direction, thus forming multiple of either the word lines or the bit lines.

[0057] In some embodiments, the etching process continues further past the second conductive layer 806, etching through a portion of the thickness of the stack 308. Thus, the etching process of Figure 11 begins to form individual memory cells out of the stack 308. The etching process etches through the thickness of the memory bit layer 312, thus exposing the sidewalls of the memory bit layer 312. According to an embodiment, however, the etching does not extend into any portion of the first conductive layer 304.

[0058] 12A and 12B illustrate the deposition of a fourth dielectric layer 1216 over the third dielectric layer 1002 and also over at least the exposed sidewalls of the memory bit layer 312. The fourth dielectric layer 1216 may include, for example, any of the exemplary materials described above for the first dielectric layer 502. The fourth dielectric layer may be deposited to a thickness of about 20 Å to about 50 Å using standard deposition techniques, such as the same low temperature ALD process used to deposit the first dielectric layer 502.

[0059] According to an embodiment, Figures 13A and 13B show another etching process (generally indicated by the arrows) that etches into the remaining portion of the thickness of the stack 308, but does not (or only minimally) etch into the first conductive layer 304. According to an embodiment, the etching process may be similar to the etching process shown in Figure 6. The memory bit layer 312 is protected by the fourth dielectric layer 1216 if any portion of the first conductive layer 304 is exposed during the etching process.

[0060] According to certain embodiments, Figures 14A and 14B show the deposition of additional layers of material between adjacent layer stacks. According to some such embodiments, a fifth dielectric layer 1418 is deposited on the fourth dielectric layer 1216, and a filler material 1420 is deposited to fill the remaining areas between adjacent layer stacks. As described above with respect to Figure 7, the fifth dielectric layer 1418 and the filler material 1420 may be substantially similar to the second dielectric layer 702 and the filler material 704, respectively.

[0061] According to one embodiment, a first stage of memory cells 102 is formed using the fabrication steps illustrated in Figures 3-14. The fabrication steps may be repeated multiple times to form additional stages of memory cells 102 and the threshold voltages thereon. During the etching process for the metal layers (such as conductive layers 304 and 806), one or more dielectric layers are present on the sidewalls of the one or more memory bit layers to protect the one or more memory bit layers during the etching process.

[0062] In some embodiments, the fourth dielectric layer 1216 is not deposited and the etching performed in FIG. 13 is not performed. In these examples, the bottom portion of the layer stack 308 (eg, conductive layer 310) remains deposited across a number of memory cells extending in the Y direction.

[0063] FIG. 15 is a flow chart of a method 1500 of fabricating a memory device including an array of memory cells having memory bit materials according to an embodiment. Various operations of method 1500 may be illustrated in FIGS. 3-14. However, association of various operations of method 1500 with specific components illustrated in FIGS. 3-14 is not intended to imply architectural and / or use limitations. Rather, FIGS. 3-14 provide one exemplary embodiment of method 1500. Other operations may be performed during or after any operation of method 1500.

[0064] The method 1500 begins at step 1502 where a conductive layer is deposited on a substrate. The conductive layer may be, for example, a layer of tungsten, and may be subsequently patterned into a number of word lines or bit lines. Other suitable conductive materials may be used as well, as will be appreciated.

[0065] The method 1500 continues at step 1504 where a layer stack is deposited on the conductive layer. The layer stack can include any number of layers including multiple conductive layers and at least one memory bit layer. The memory bit layer can be sandwiched by conductive layers within the layer stack. The conductive layers within the layer stack can be or otherwise include carbon. The memory bit layer can include, for example, a chalcogenide or can otherwise include other exemplary materials as provided in various ways herein.

[0066] The method 1500 continues with step 1506, where an etching process is performed only through a portion of the thickness of the layer stack. According to one embodiment, at least the thickness of the memory bit layer is etched such that the sidewalls of the memory bit layer are exposed. By etching only a portion of the layer stack, the etch does not expose the underlying conductive layer.

[0067] The method 1500 continues with step 1508 where a dielectric layer is deposited on the exposed sidewalls of the memory bit layer. The dielectric layer may include silicon nitride due to its favorable adhesion properties to most other materials. In some other examples, the dielectric layer includes a high-k material. Examples of high-k materials include oxides of one or more of the following elements: Li, B, Mg, Al, Si, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Sr, Y, Zr, Nb, Mo, Ru, Rh, Sn, Sb, Ba, La, Ce, Pr, Nd, Sm, Eu, Gd, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, Ir, Pt, Pb, and Bi. The dielectric layer may be deposited using a low-temperature ALD process. The dielectric layer may be deposited at a thickness of about 20 Å to about 50 Å. In some embodiments, multiple dielectric layers are deposited on the exposed sidewalls of the memory bit layer. The multiple dielectric layers may have different thicknesses and material compositions.

[0068] The method 1500 continues with operation 1510 where a second etch is performed on the remaining portion of the layer stack and also on the thickness of the conductive layer. The second etch process may be similar to the first etch process of operation 1506. During the second etch process, the memory bit layer is protected by a dielectric layer deposited on its sidewalls. In particular, according to an embodiment, during the time that the conductive layer is etched, no part of the memory bit layer is exposed. The etch process patterns strips of the conductive layer, thus forming multiple of either word lines or bit lines.

[0069] According to one embodiment, the operations of method 1500 are generally repeated to form each stage of memory cells in a three-dimensional memory device.

[0070] 16 illustrates an exemplary electronic device 1600 that may include one or more memory devices such as the embodiments disclosed herein. In some embodiments, the electronic device 1600 may host or otherwise be incorporated into a personal computer, a workstation, a server system, a laptop computer, an ultra laptop computer, a tablet, a touchpad, a portable computer, a handheld computer, a palmtop computer, a personal digital assistant (PDA), a mobile phone, a combination of a mobile phone and a PDA, a smart device (e.g., a smart phone or a smart tablet), a mobile internet appliance (MID), a messaging device, a data communication device, an imaging device, a wearable device, an embedded system, etc. In some embodiments, any combination of different devices may be used.

[0071] In some embodiments, the electronic device 1600 may include any combination of a processor 1602, a memory 1604, a network interface 1606, an input / output (I / O) system 1608, a user interface 1610, and a storage system 1612. As will be further understood, a bus and / or interconnect is further provided to enable communication between the various components listed above and / or other components not shown. The electronic device 1600 may be coupled to a network 1616 via the network interface 1606 to enable communication with other computing devices, platforms, or resources. Other components and functions not reflected in the block diagram of FIG. 16 will be apparent in view of this disclosure, and it will be understood that other embodiments are not limited to any particular hardware configuration.

[0072] The processor 1602 may be any suitable processor and may include one or more co-processors or controllers to assist in control and processing operations associated with the electronic device 1600. In some embodiments, the processor 1602 may be implemented as any number of processor cores. The processor (or processor core) may be any type of processor, such as, for example, a microprocessor, an embedded processor, a digital signal processor (DSP), a graphics processor (GPU), a network processor, a field programmable gate array, or other device configured to execute code. The processors may be multi-threaded cores in that they may include more than one hardware thread context (or "logical processor") per core.

[0073] The memory 1604 may be implemented using any suitable type of digital storage including, for example, flash memory and / or random access memory (RAM). In some embodiments, the memory 1604 may include various layers of a memory hierarchy and / or a memory cache. The memory 1604 may be implemented as a volatile memory device, such as, for example, but not limited to, a RAM, a dynamic RAM (DRAM), or a static RAM (SRAM) device. The storage system 1612 may be implemented as a non-volatile storage device, such as, for example, but not limited to, one or more hard disk drives (HDDs), solid state drives (SSDs), universal serial bus (USB) drives, optical disk drives, tape drives, internal storage devices, tape drives, attached storage devices, flash memory, battery-backed synchronous DRAM (SDRAM), and / or network-accessible storage devices. In some embodiments, the storage system 1612 may include techniques to improve enhanced storage performance protection for high value digital media when multiple hard drives are included. According to some embodiments of the present disclosure, either or both of the memory 1604 and the storage system 1612 include one or more memory arrays 122 having memory cells 102 fabricated using the processes described herein. According to some embodiments of the present disclosure, either or both of the memory 1604 and the storage system 1612 may be incorporated into a chip package 200 and coupled to a printed circuit board (PCB) along with one or more other devices.

[0074] The processor 1602 may be configured to execute an operating system (OS) 1614, which may include any suitable operating system, such as, for example, Google Android® (Google Inc., Mountain View, Calif.), Microsoft Windows® (Microsoft Corp., Redmond, Wash.), Apple OSX (Apple Inc., Cupertino, Calif.), Linux®, or a real-time operating system (RTOS).

[0075] The network interface 1606 may be any suitable network chip or chipset that enables wired and / or wireless connections between the electronic device 1600 and / or other components of the network 1616, thereby enabling the electronic device 1600 to communicate with other local and / or remote computing systems, servers, cloud-based servers, and / or other resources. The wired communications may conform to existing (or future developed) standards, such as, for example, Ethernet. The wireless communications may conform to existing (or future developed) standards, such as, for example, cellular communications including Long Term Evolution (LTE), Wireless Fidelity (WiFi), Bluetooth, and / or Near Field Communication (NFC). Exemplary wireless networks include, but are not limited to, wireless local area networks, wireless personal area networks, wireless metropolitan area networks, cellular networks, and satellite networks.

[0076] The I / O system 1608 may be configured to interface between various I / O devices and other components of the electronic device 1600. The I / O devices may include, but are not limited to, a user interface 1610. The user interface 1610 may include devices such as, for example, a display element, a touchpad, a keyboard, a mouse, and speakers (not shown). The I / O system 1608 may include a graphics subsystem configured to perform image processing for rendering on the display element. The graphics subsystem may be, for example, a graphics processing unit or a visual processing unit (VPU). An analog or digital interface may be used to communicatively connect to the graphics subsystem and the display element. For example, the interface may be any High Definition Multimedia Interface (HDMI), DisplayPort, Wireless HDMI, and / or any other suitable interface using wireless high definition compliant technology. In some embodiments, the graphics subsystem may be incorporated into the processor 1602 or any chipset of the electronic device 1600.

[0077] It will be appreciated that in some embodiments, the various components of electronic device 1600 may be combined or integrated into a system-on-chip (SoC) architecture. In some embodiments, the components may be hardware components, firmware components, software components, or any suitable combination of hardware, firmware, or software.

[0078] In various embodiments, the electronic device 1600 may be implemented as a wireless system, a wired system, or a combination of both. When implemented as a wireless system, the electronic device 1600 may include a number of components and interfaces suitable for communication over a wireless shared medium, such as, for example, one or more antennas, transmitters, receivers, transceivers, amplifiers, filters, control logic, etc. Examples of wireless shared media may include a portion of a wireless spectrum, such as, for example, a radio frequency spectrum. When implemented as a wired system, the electronic device 1600 may include a number of components and interfaces suitable for communication over a wired communication medium, such as, for example, an I / O adapter, a physical connector that connects to an I / O adapter corresponding to the wired communication medium, a network interface card (NIC), a disk controller, a video controller, an audio controller, etc. Examples of wired communication media may include wires, cable metal leads, printed circuit boards (PCBs), backplanes, switch fabrics, semiconductor materials, twisted pair wires, coaxial cables, optical fibers, etc.

[0079] Unless otherwise indicated, terms such as, for example, "processing," "computing," "calculating," "determining," etc. may be understood to refer to the actions and / or processing of a computer or computing system or similar electronic computing device to manipulate and / or transform data represented as physical quantities (e.g., electrons) in registers and / or memory units of the computer system to other data similarly represented as physical quantities in registers, memory units, or other such information storage transmission or display of the computer system. Embodiments are not limited in this context.

[0080] Numerous specific details are described herein to provide a thorough understanding of the embodiments. However, it will be understood that in view of this disclosure, the embodiments may be practiced without these specific details. In other instances, well-known processes, components, and circuits have not been described in detail so as not to obscure the embodiments. It will be understood that specific structural and functional details disclosed herein are representative and do not necessarily limit the scope of the embodiments. In addition, although the subject matter has been described in explicit language regarding structural features and / or methodological acts, it will be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described herein. Rather, the specific features and acts described herein are disclosed as exemplary forms of implementing the claims. Further Exemplary Embodiments

[0081] The following examples relate to further embodiments, from which numerous variations and configurations will become apparent.

[0082] Example 1 is a memory device comprising a plurality of conductive bitlines, a plurality of conductive wordlines, and a set of memory cells included in a memory cell array, each of the memory cells being disposed between a corresponding bitline of the plurality of conductive bitlines and a corresponding wordline of the plurality of conductive wordlines, each of the memory cells including a stack having a memory bit layer and a dielectric layer on one or more sidewalls of only a portion of a total thickness of the stack such that the dielectric layer is on one or more sidewalls of the memory bit layer.

[0083] Example 2 includes the subject matter of Example 1, where the memory cell array is organized in three dimensions with memory cells arranged in rows and columns along multiple XY planes stacked in the Z direction.

[0084] Example 3 includes the subject matter of example 2, wherein the one or more memory cells have a dimension along the X direction that is greater than a dimension along the Y direction.

[0085] Example 4 includes the subject matter of any one of Examples 1-3, and includes a stack consisting of only a first conductive layer, a memory bit layer on the first conductive layer, and a second conductive layer on the memory bit layer, and only the stack is present between a corresponding bit line of the plurality of conductive bit lines and a corresponding word line of the plurality of conductive word lines.

[0086] Example 5 includes the subject matter of example 4, wherein a dielectric layer is on the second conductive layer on one or more sidewalls, and a dielectric layer is on a top surface of the first dielectric layer.

[0087] Example 6 includes the subject matter of any one of examples 1-5, wherein the plurality of conductive bitlines are orthogonal to the plurality of conductive wordlines.

[0088] Example 7 includes the subject matter of any one of examples 1-6, wherein the one or more memory cells have a height between about 60 nm and about 80 nm.

[0089] Example 8 includes the subject matter of any one of Examples 1-7, wherein the dielectric layer comprises a high dielectric constant material.

[0090] Example 9 includes the subject matter of any one of Examples 1-8, wherein the dielectric layer is a first dielectric layer, and the device further comprises a second dielectric layer on the first dielectric layer, the second dielectric layer on one or more sidewalls of the total thickness of the stack such that the first dielectric layer is not present between the second dielectric layer and the stack in at least one location.

[0091] Example 10 includes the subject matter of any one of examples 1-9, wherein the memory bit layer comprises a chalcogenide.

[0092] Example 11 includes the subject matter of any one of examples 1-10, wherein the plurality of conductive bitlines and the plurality of conductive wordlines comprise one or both of tungsten and carbon.

[0093] Example 12 is an integrated circuit comprising the memory device according to any one of Examples 1 to 11.

[0094] Example 13 is a printed circuit board comprising the integrated circuit of Example 12.

[0095] Example 14 is a memory chip including the memory device according to any one of Examples 1 to 11.

[0096] Example 15 is an electronic device, the electronic device comprising a chip package including one or more dies, the one or more dies including a stack between word lines and bit lines, a stack including a memory bit layer, and a dielectric layer on one or more sidewalls of only a portion of a total thickness of the stack, such that the dielectric layer is on one or more sidewalls of the memory bit layer.

[0097] Example 16 includes the subject matter of example 15, where the bitlines run perpendicular to the wordlines.

[0098] Example 17 includes the subject matter of example 15 or example 16, wherein the dielectric layer includes a high dielectric constant material.

[0099] Example 18 includes the subject matter of any one of Examples 15-17, wherein the dielectric layer is a first dielectric layer, and the device further comprises a second dielectric layer on the first dielectric layer, the second dielectric layer being on one or more sidewalls of the total thickness of the stack such that the first dielectric layer is not present between the second dielectric layer and the stack in at least one location.

[0100] Example 19 includes the subject matter of any one of examples 15-18, wherein the memory bit layer includes a chalcogenide.

[0101] Example 20 includes the subject matter described in any one of Examples 15 to 19, and includes a stack consisting of only a first conductive layer, a memory bit layer on the first conductive layer, and a second conductive layer on the memory bit layer, and only the stack is present between the word line and the bit line.

[0102] Example 21 is a method of manufacturing a memory device, the method including depositing a conductive layer on a substrate, depositing a stack on the conductive layer, the stack including a memory bit layer, etching only a portion of the stack's total thickness such that the entire thickness of the memory bit layer is etched, depositing a dielectric layer on at least one or more sidewalls of the memory bit layer, and etching the remainder of the stack and the thickness of the conductive layer.

[0103] Example 22 includes the subject matter of example 21, wherein the dielectric layer includes a high dielectric constant material.

[0104] Example 23 includes the subject matter of examples 21 or 22, wherein depositing the dielectric layer includes depositing the first dielectric layer to a thickness of from 20 Å to 50 Å.

[0105] Example 24 includes the subject matter of any one of Examples 21-23, further comprising depositing a second dielectric layer over the first dielectric layer.

[0106] Example 25 includes the subject matter of example 24, wherein depositing the second dielectric layer includes depositing silicon nitride.

[0107] Example 26 includes the subject matter of any one of Examples 21-25, including depositing the first dielectric layer including depositing the first dielectric layer using atomic layer deposition (ALD).

[0108] Example 27 includes the subject matter of any one of Examples 21-26, wherein the stack is a first stack, the conductive layer is a first conductive layer, and the memory bit layer is a first memory bit layer, and the method further includes depositing a second conductive layer over the first stack and depositing a second stack over the second conductive layer, the second stack comprising a second memory bit layer.

[0109] Example 28 includes the subject matter of Example 27, and further includes etching only a portion of the total thickness of the second stack such that the entire thickness of the second memory bit layer is etched; depositing a second dielectric layer on at least one or more sidewalls of the second memory bit layer; and etching the remaining portion of the second stack, the thickness of the conductive layer, and the thickness of the first stack.

[0110] Example 29 includes the subject matter of example 28, further comprising depositing a third dielectric layer on one or more sidewalls of at least the second memory bit layer.

[0111] Example 30 includes the subject matter of any one of examples 21-29, wherein the memory bit layer includes a chalcogenide.

[0112] Example 31 includes the subject matter of any one of Examples 21-30, including depositing a conductive layer including depositing one or both of tungsten and carbon. [Other possible items] [Item 1] a plurality of conductive bitlines; a plurality of conductive wordlines; a set of memory cells included in a memory cell array, each of the memory cells being disposed between a corresponding bit line of the plurality of conductive bit lines and a corresponding word line of the plurality of conductive word lines; Each of the memory cells is a stack having a memory bit layer; and a dielectric layer on one or more sidewalls of only a portion of the total thickness of the stack, such that the dielectric layer is on one or more sidewalls of the memory bit layer. [Item 2] 2. The memory device of item 1, wherein the memory cell array is configured three-dimensionally with memory cells arranged in rows and columns along multiple XY planes stacked in the Z direction. [Item 3] 3. The memory device of claim 2, wherein one or more of the memory cells have a dimension along the X direction that is greater than a dimension along the Y direction. [Item 4] the laminate only comprises a first conductive layer, the memory bit layer on the first conductive layer, and a second conductive layer on the memory bit layer; 2. The memory device of claim 1, wherein only the stack exists between the corresponding bit line of the plurality of conductive bit lines and the corresponding word line of the plurality of conductive word lines. [Item 5] 5. The memory device of claim 4, wherein the dielectric layer is on one or more sidewalls of the second conductive layer and the dielectric layer is on a top surface of the first dielectric layer. [Item 6] Item 2. The memory device of item 1, wherein the plurality of conductive bitlines are orthogonal to the plurality of conductive wordlines. [Item 7] 2. The memory device of claim 1, wherein the one or more memory cells have a height between about 60 nm and about 80 nm. [Item 8] Item 2. The memory device of item 1, wherein the dielectric layer comprises a high dielectric constant material. [Item 9] 2. The memory device of claim 1, wherein the dielectric layer is a first dielectric layer, the device further comprising a second dielectric layer on the first dielectric layer, the second dielectric layer on one or more sidewalls of the total thickness of the stack such that the first dielectric layer is not present between the second dielectric layer and the stack in at least one location. [Item 10] Item 13. The memory device of item 1, wherein the memory bit layer comprises a chalcogenide. [Item 11] Item 2. The memory device of item 1, wherein the plurality of conductive bitlines and the plurality of conductive wordlines comprise one or both of tungsten and carbon. [Item 12] Item 2. An integrated circuit comprising the memory device described in item 1. [Item 13] Item 13. A printed circuit board comprising the integrated circuit according to item 12. [Item 14] A memory chip comprising the memory device described in item 1. [Item 15] A chip package having one or more dies, At least one of the one or more dies is a stack between a word line and a bit line, the stack comprising a memory bit layer; and a dielectric layer on one or more sidewalls of only a portion of a total thickness of the stack, such that a dielectric layer is on one or more sidewalls of the memory bit layer. [Item 16] Item 16. The electronic device of item 15, wherein the dielectric layer comprises a high dielectric constant material. [Item 17] Item 16. The electronic device of item 15, wherein the dielectric layer is a first dielectric layer, and the electronic device further comprises a second dielectric layer on the first dielectric layer, the second dielectric layer being on one or more sidewalls of the total thickness of the stack such that the first dielectric layer is not between the second dielectric layer and the stack in at least one location. [Item 18] Item 16. The electronic device of item 15, wherein the memory bit layer comprises a chalcogenide. [Item 19] the laminate only comprises a first conductive layer, the memory bit layer on the first conductive layer, and a second conductive layer on the memory bit layer; Item 16. The electronic device of item 15, wherein only the stack is between the word line and the bit line. [Item 20] 1. A method for manufacturing a memory device, comprising: depositing a conductive layer on a substrate; depositing a stack on the conductive layer, the stack including a memory bit layer; etching only a portion of the total thickness of the stack such that the entire thickness of the memory bit layer is etched; depositing a dielectric layer on at least one or more sidewalls of the memory bit layer; and etching the remaining portion of the stack and the thickness of the conductive layer. A method for manufacturing a memory device.

Claims

1. a plurality of conductive bitlines; a plurality of conductive wordlines; a set of memory cells in a memory cell array, each of the memory cells being disposed between a corresponding bit line of the plurality of conductive bit lines and a corresponding word line of the plurality of conductive word lines; Each of the memory cells comprises: a stack having a memory bit layer; a first dielectric layer on one or more sidewalls corresponding to only a portion of the total thickness of the stack, such that the first dielectric layer is on one or more sidewalls of the memory bit layer; a second dielectric layer covering the first dielectric layer at the one or more sidewalls; Equipped with the plurality of conductive bitlines and the plurality of conductive wordlines comprise a multi-layer structure including both a tungsten layer and a carbon layer; the second dielectric layer covers the first dielectric layer and is on the one or more sidewalls corresponding to the total thickness of the stack such that the first dielectric layer is not between the second dielectric layer and the stack in at least one location; the first dielectric layer comprises a high dielectric constant material, the high dielectric constant material comprising at least one of an oxide of Li, B, Mg, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Sr, Y, Zr, Nb, Mo, Ru, Rh, In, Sn, Sb, Ba, La, Ce, Pr, Nd, Sm, Eu, Gd, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, Ir, Pt, Pb, and Bi; Memory device.

2. The memory device of claim 1 , wherein the memory cell array is configured three-dimensionally with memory cells arranged in rows and columns along multiple XY planes stacked in a Z direction.

3. 3. The memory device of claim 2, wherein one or more of the memory cells have a dimension along an X direction and a dimension along a Y direction, the dimension along the X direction being greater than the dimension along the Y direction.

4. the laminate only comprises a first conductive layer, the memory bit layer on the first conductive layer, and a second conductive layer on the memory bit layer; 4. The memory device of claim 1, wherein only the stack exists between the corresponding bit line of the plurality of conductive bit lines and the corresponding word line of the plurality of conductive word lines.

5. 5. The memory device of claim 4, wherein the first dielectric layer is on one or more sidewalls of the second conductive layer and the first dielectric layer is on a top surface of the first conductive layer.

6. The memory device of claim 1 , wherein the conductive bitlines are orthogonal to the conductive wordlines.

7. The memory device of claim 1 , wherein one or more of the memory cells have a height of between about 60 nm and about 80 nm.

8. The memory device of claim 1 , wherein the second dielectric layer comprises the high-k material.

9. 6. The memory device of claim 4, wherein the first and second conductive layers comprise tungsten and / or carbon to enhance ohmic contact to the memory bit layer.

10. The memory device of claim 1 , wherein the memory bit layer comprises a chalcogenide.

11. The memory device of claim 1 , further comprising a cell selection circuit for selecting the memory cells.

12. An integrated circuit comprising the memory device according to any one of claims 1 to 11.

13. A printed circuit board comprising the integrated circuit of claim 12.

14. A memory chip comprising the memory device according to any one of claims 1 to 11.

15. A chip package having one or more dies, At least one of the one or more dies A memory device according to any one of claims 1 to 11, Electronic devices.

16. 1. A method for manufacturing a memory device, comprising: depositing a conductive layer for a bit line or word line on a substrate, the conductive layer comprising a multi-layer structure including both a tungsten layer and a carbon layer; depositing a stack on the conductive layer, the stack including a memory bit layer; etching only a portion of the total thickness of the stack such that the entire thickness of the memory bit layer is etched; depositing a first dielectric layer on at least one or more sidewalls of the etched memory bit layer; etching the remaining portion of the stack and the thickness of the conductive layer for the bit line or word line; depositing a second dielectric layer over the first dielectric layer on the one or more sidewalls, the second dielectric layer overlying the first dielectric layer and on the one or more sidewalls corresponding to the total thickness of the stack such that the first dielectric layer is not between the second dielectric layer and the stack in at least one location; Including, the first dielectric layer comprises a high dielectric constant material, the high dielectric constant material comprising at least one of an oxide of Li, B, Mg, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Sr, Y, Zr, Nb, Mo, Ru, Rh, In, Sn, Sb, Ba, La, Ce, Pr, Nd, Sm, Eu, Gd, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, Ir, Pt, Pb, and Bi; A method for manufacturing a memory device.

17. The method of claim 16 further comprising depositing a filler material between adjacent second dielectric layers.

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