Semiconductor substrates, solar cells and photovoltaic power generation modules

Abstract

To provide an invention in a field of solar batteries and more specifically a semiconductor substrate, a solar battery, and a photovoltaic power generation module.SOLUTION: A back surface of a semiconductor substrate has an N-type conductive region and a P-type conductive region. The N-type conductive region is provided with a first non-pyramid textured structure and the P-type conductive region is provided with a second non-pyramid textured structure. A surface of a top part of the first non-pyramid textured structure and a surface of a top part of the second non-pyramid textured structure are both a polygon plane. The non-pyramid shape is a tower base, a square board, or a stair formed by breaking an end of a tower of a pyramid-like small structure. The first non-pyramid textured structure includes at least two sub-structures laminated at least partially and at least two second sub-structures arranged not to be laminated on each other next to each other.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to the technical field of photovoltaic cells, in particular to semiconductor substrates, solar cells and photovoltaic modules. [Background technology]

[0002] Traditional crystalline silicon cells adopt double-sided contact metallization design. The front or back of the cell needs to have a textured light trapping structure to increase the transmission path of incident light in the cell so that the solar spectrum can be utilized more effectively. However, traditional textured surfaces affect the subsequent film layer passivation and slurry contact interface to a certain extent, which further affects the cell performance. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention provides a semiconductor substrate, a solar cell and a photovoltaic module that solve the problem that the surface texture structure of a conventional solar cell affects the subsequent film layer passivation and the slurry contact interface, and further affects the cell performance. [Means for solving the problem]

[0004] In a first aspect, the present invention provides a semiconductor substrate, the rear surface of the semiconductor substrate having an N-type conductivity region and a P-type conductivity region, the N-type conductivity region being provided with a first non-pyramidal textured structure and the P-type conductivity region being provided with a second non-pyramidal textured structure; a top surface of the first non-pyramidal texture structure and a top surface of the second non-pyramidal texture structure are both polygonal planes, and a one-dimensional size of the top surface of the first non-pyramidal texture structure is smaller than a one-dimensional size of the top surface of the second non-pyramidal texture structure; The first non-pyramidal textured structure has a top surface having a one-dimensional size of 5 μm or more and 12 μm or less, and the second non-pyramidal textured structure has a top surface having a one-dimensional size of 10 μm or more and 40 μm or less.

[0005] In one possible design, the first non-pyramidal textured structure has a top surface with a one-dimensional size of 7 μm or more and 10 μm or less.

[0006] In one possible design, the top surface of the second non-pyramidal textured structure has a one-dimensional size of 15 μm or more and 35 μm or less.

[0007] In one possible design, the first non-pyramidal textured structure includes two or more first substructures that are at least partially stacked and two or more second substructures that are arranged in an adjacent non-stacked manner; a one-dimensional size of a top surface of an outermost first substructure of the at least partially stacked first substructures in a direction away from and perpendicular to the rear surface is 5 μm or more and 12 μm or less; The top surface of the second substructure spaced from the rear surface has a size in one dimension that is greater than or equal to 5 μm and less than or equal to 12 μm.

[0008] In one possible design, the second non-pyramidal textured structure includes two or more third substructures in at least a partially stacked arrangement and two or more fourth substructures in an adjacent non-stacked arrangement; a one-dimensional size of a top surface of an outermost third substructure of the at least partially stacked two or more third substructures in a direction spaced from and perpendicular to the rear surface is 10 μm or more and 40 μm or less; The top surface of the fourth substructure spaced from the rear surface has a size in one dimension not less than 10 μm and not more than 40 μm.

[0009] In one possible design, there is a boundary between the N-type conductivity region and the P-type conductivity region, and a void is provided in the N-type conductivity region and / or the P-type conductivity region proximate the boundary.

[0010] In one possible design, a void is provided in the N-type conductivity region and / or the P-type conductivity region at a position 5 μm to 15 μm away from the boundary line.

[0011] In one possible design, a void is provided in the N-type conductivity region and / or the P-type conductivity region at a position 5 μm to 10 μm away from the boundary line.

[0012] In one possible design, the voids have a diameter of 1 μm to 10 μm.

[0013] In one possible design, the voids have a diameter of 1 μm to 5 μm.

[0014] In one possible design, the voids have a depth of 0.5 μm to 2 μm.

[0015] In one possible design, the spacing between two adjacent N-type conductive regions or the spacing between two adjacent P-type conductive regions is 0.8 mm to 1.2 mm, the distribution ratio of the N-type conductive regions on the rear surface of the semiconductor substrate is 50% to 85%, and the distribution ratio of the P-type conductive regions on the rear surface of the semiconductor substrate is 15% to 50%.

[0016] In one possible design, the shape of the polygonal plane includes at least one of a rhombus, a rectangle, a trapezoid, an approximate rhombus, an approximate rectangle, and an approximate trapezoid.

[0017] In one possible design, the semiconductor substrate is a P-type crystalline silicon substrate.

[0018] In a second aspect of the present invention, the present invention further provides a solar cell comprising: The semiconductor substrate; a tunnel oxide layer disposed in an N-type conductive region on a rear surface of the semiconductor substrate; a local back surface field provided in a P-type conductive region on a rear surface of the semiconductor substrate; a polycrystalline silicon thin film layer provided on a side of the tunnel oxide layer away from the semiconductor substrate; a eutectic layer provided on the local back surface field; a backside passivation layer disposed on the side of the polysilicon thin film layer away from the tunnel oxide layer and on the P-type conductive region; a first electrode passing through the back surface passivation layer to form an ohmic contact with the local back surface field; a second electrode passing through the rear passivation layer and the polysilicon thin film layer to form an ohmic contact therewith.

[0019] In one possible design, the semiconductor device further comprises a front passivation layer and an anti-reflection layer disposed on a front surface of the semiconductor substrate and stacked in sequence in a direction away from the semiconductor substrate.

[0020] In a third aspect of the present invention, the present invention further provides a photovoltaic power generation module, the photovoltaic power generation module including the above-mentioned solar cell, the solar cell being electrically connected in the form of a whole sheet or in the form of a plurality of divided sheets to form a solar cell string. Effect of the Invention

[0021] The present invention has the following advantageous effects. The present invention provides a semiconductor substrate having an N-type conductive region and a P-type conductive region, the N-type conductive region is provided with a first non-pyramidal texture structure, the P-type conductive region is provided with a second non-pyramidal texture structure, the top surface of the first non-pyramidal texture structure and the top surface of the second non-pyramidal texture structure are both polygonal planes, the one-dimensional size of the top surface of the first non-pyramidal texture structure is smaller than the one-dimensional size of the top surface of the second non-pyramidal texture structure, and the one-dimensional size range of the top surface of the first non-pyramidal texture structure and the one-dimensional size range of the top surface of the second non-pyramidal texture structure are further limited. In the present invention, the non-pyramidal texture structures of different sizes are correspondingly designed for the doping characteristics of N-type conductive type doping and P-type conductive type doping, so that the passivation quality of the corresponding region is more correspondingly improved, the contact characteristics with the slurry are improved, and the fabricated solar cell can obtain a higher cell conversion efficiency.

[0022] It is to be understood that the foregoing general description and the following detailed description are merely illustrative and are not restrictive of the present invention. [Brief description of the drawings]

[0023] [Figure 1] 1 is a scanning electron microscope photograph at 1k magnification of a semiconductor substrate according to a first embodiment of the present invention. [Diagram 2] 1 is a micrograph of a first non-pyramidal texture structure on an N-type conductivity region on a semiconductor substrate according to a first embodiment of the present invention, taken at a first angle. [Diagram 3] 4 is a scanning electron microscope photograph of a first non-pyramidal texture structure on an N-type conductive region on a semiconductor substrate according to a first embodiment of the present invention, taken at a second angle. [Figure 4] 4 is a micrograph taken at a first angle of a second non-pyramidal texture structure on a P-type conductivity region on a semiconductor substrate according to a first embodiment of the present invention. [Diagram 5]4 is a scanning electron microscope photograph of a second non-pyramidal texture structure on a P-type conductive region on a semiconductor substrate according to the first embodiment of the present invention, taken at a second angle. [Figure 6] 1 is a scanning electron microscope photograph at 2k magnification of a semiconductor substrate according to a first embodiment of the present invention. [Figure 7] 1 is a scanning electron microscope photograph at 5k magnification of a semiconductor substrate according to a first embodiment of the present invention. [Figure 8] 1 is a scanning electron microscope photograph at 10k magnification of a semiconductor substrate according to a first embodiment of the present invention. [Figure 9] FIG. 2 is a structural schematic diagram of a solar cell according to a second embodiment of the present invention.

[0024] The drawings herein are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present invention, and together with the specification serve to explain the principles of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] In order to better understand the solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the drawings.

[0026] Obviously, the described embodiments are only some of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments that a person skilled in the art can obtain without requiring inventive efforts fall within the scope of protection of the present invention.

[0027] The terms used in the embodiments of the present invention are only for the purpose of describing particular embodiments, and are not intended to limit the present invention. The singular forms "a," "the," and "the" used in the embodiments of the present invention and the appended claims are also intended to include the plural forms unless the context clearly dictates otherwise.

[0028] It should be understood that the term "and / or" used in this specification is only a relational relationship to describe related objects, and indicates that three kinds of relations may exist. For example, A and / or B can indicate three kinds of situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the symbol " / " in this specification generally indicates that the related objects before and after are in an "or" relationship.

[0029] It should be noted that directional terms such as "upper", "lower", "left", and "right" described in the embodiments of the present invention are described in terms of angles shown in the drawings and should not be understood as limiting the embodiments of the present invention. It should be further understood that in the context, when referring to an element being connected "upper" or "lower" to another element, it may not only be directly connected to the "upper" or "lower" of the other element, but also indirectly connected to the "upper" or "lower" of the other element through an intermediate element.

[0030] An IBC (Interdigitated Back Contact) cell is a back-contact solar cell in which all electrodes are provided on the back surface of a semiconductor substrate, and since there is no shielding of electrodes on the front surface of the semiconductor substrate, the entire area of ​​the front surface can receive sunlight. This allows the IBC cell to have a high photoelectric conversion efficiency. The back surface of the semiconductor substrate of an IBC cell is generally formed with a certain texture structure by polishing or partial texturing. The conventional texture structure affects the subsequent film layer passivation and slurry contact interface to a certain extent, which further affects the photoelectric conversion efficiency of the IBC cell.

[0031] In view of this, in a first aspect, the present invention provides a semiconductor substrate 1, as shown in Figure 1. A rear surface of the semiconductor substrate 1 has an N-type conductivity region 11 and a P-type conductivity region 12, the N-type conductivity region 11 is provided with a first non-pyramidal textured structure 111, as shown in Figures 2 and 3, and the P-type conductivity region 12 is provided with a second non-pyramidal textured structure 121, as shown in Figures 4 and 5; a top surface of the first non-pyramidal texture structure 111 and a top surface of the second non-pyramidal texture structure 121 are both polygonal planes, and a one-dimensional size L1 of the top surface of the first non-pyramidal texture structure 111 is smaller than a one-dimensional size L2 of the top surface of the second non-pyramidal texture structure 121; The one-dimensional size L1 of the top surface of the first non-pyramidal texture structure 111 is greater than or equal to 5 μm and less than or equal to 12 μm, and the one-dimensional size L2 of the top surface of the second non-pyramidal texture structure 121 is greater than or equal to 10 μm and less than or equal to 40 μm.

[0032] It should be explained that the semiconductor substrate 1 generally has a front surface and a rear surface, and the front surface of the semiconductor substrate 1 may refer to the light-receiving surface, i.e., the surface (light-receiving surface) that is irradiated with sunlight, and the rear surface of the semiconductor substrate 1 is the surface facing away from the front surface. The non-pyramidal shape can be understood as a tower base / square pedestal or step-like shape formed by breaking the tower end of a pyramidal microstructure. The non-pyramidal texture structure may be formed by carrying out a process such as chemical etching, laser etching, mechanical method or plasma etching on the semiconductor substrate 1. The one-dimensional size of the top surface of the non-pyramidal texture structure may specifically be the length, width, diagonal length, circular diameter, etc. of the surface, and is not limited thereto. In some examples, when measuring the one-dimensional size representing the top surface of the non-pyramidal texture structure, the orientation of the film layer surface may be directly measured through a test instrument (optical microscope, atomic force microscope, scanning electron microscope, transmission electron microscope, etc.).

[0033] Preferably, the semiconductor substrate 1 may be one of a single crystal silicon substrate, a polycrystalline silicon substrate, a microcrystalline silicon substrate, or a silicon carbide substrate. In some embodiments, the semiconductor substrate is a P-type crystalline silicon substrate, and the one-dimensional size of the top surface of the first non-pyramidal texture structure 111 may be 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, or 12 μm, etc., and of course may be other values ​​within the above range, and is not limited here. The shape of the polygonal plane includes at least one of a rhombus, a square, a trapezoid, an approximately rhombus, an approximately square, and an approximately trapezoid. The one-dimensional size of the top surface of the second non-pyramidal texture structure 121 may be 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, or 40 μm, and of course may be other values ​​within the above range, and is not limited here.

[0034] As can be seen, the semiconductor substrate of the present invention has an N-type conductive region 11 and a P-type conductive region 12 on the rear surface, and the N-type conductive region 11 and the P-type conductive region 12 are respectively used for N-type conductive type doping and P-type conductive type doping during the fabrication of a solar cell. In the present invention, the N-type conductive region 11 is provided with a first non-pyramidal textured structure 111, and the P-type conductive region 12 is provided with a second non-pyramidal textured structure 121. Compared with the pyramidal textured structure, during the fabrication of a solar cell, the non-pyramidal textured structure is more favorable for the formation of a later film layer on the semiconductor substrate 1, and can obtain higher passivation quality, and the non-pyramidal textured structure has better contact characteristics with the slurry, and can be better filled when the screen printing metal slurry forms an electrode, resulting in better electrode contact, and resulting in higher open circuit voltage and fill factor, and resulting in higher cell conversion efficiency.

[0035] In the present invention, it is limited that the top surface of the first non-pyramidal textured structure 111 and the top surface of the second non-pyramidal textured structure 121 are both polygonal planes, and the one-dimensional size of the top surface of the first non-pyramidal textured structure 111 is smaller than the one-dimensional size of the top surface of the second non-pyramidal textured structure 121, and further limited the one-dimensional size range of the top surface of the first non-pyramidal textured structure 111 and the one-dimensional size range of the top surface of the second non-pyramidal textured structure 121. In the present invention, for the doping characteristics of N-type conductive type doping and P-type conductive type doping, non-pyramidal textured structures of different sizes are correspondingly designed, so that the passivation quality of the corresponding areas can be more correspondingly improved, and the contact characteristics with the slurry can be improved, so that the fabricated solar cell can obtain higher cell conversion efficiency.

[0036] Preferably, the one-dimensional size of the top surface of the first non-pyramidal texture structure 111 is not less than 7 μm and not more than 10 μm.

[0037] As can be seen, by further limiting the one-dimensional size of the top surface of the first non-pyramidal textured structure 111, during the process of fabricating the solar cell, the N-type conductive region 11 can obtain higher passivation quality and better contact characteristics with the slurry, resulting in higher open circuit voltage and fill factor, and thus higher cell conversion efficiency.

[0038] Preferably, the one-dimensional size of the top surface of the second non-pyramidal texture structure 121 is not less than 15 μm and not more than 35 μm.

[0039] As can be seen, by further limiting the one-dimensional size of the top surface of the second non-pyramidal texture structure 121, during the process of fabricating the solar cell, the P-type conductive region 12 can obtain higher passivation quality and better contact characteristics with the slurry, resulting in higher open circuit voltage and fill factor, and higher cell conversion efficiency.

[0040] In some embodiments, as shown in FIG. 2, the first non-pyramidal textured structure 111 includes two or more first substructures 1111 that are at least partially stacked and two or more second substructures 1112 that are arranged adjacently and non-stacked; Among the at least partially stacked two or more first sub-structures 1111, a one-dimensional size L11 of a top surface of the outermost first sub-structure 1111 in a direction away from the rear surface and perpendicular to the rear surface is 5 μm or more and 12 μm or less; The first dimension L12 of the top surface of the second substructure 1112 remote from the rear surface is not less than 5 μm and not more than 12 μm.

[0041] It should be explained that the direction away from and perpendicular to said rear face may be understood as the loading direction.

[0042] As can be seen, since the first non-pyramidal textured structure 111 of the present invention includes two or more first sub-structures 1111 at least partially stacked and two or more adjacent non-stacked arranged second sub-structures 1112, the roughness of the first non-pyramidal textured structure 111 can be controlled within a desired range, which is beneficial for the screen printing stage of the solar cell, and can enhance the slurry contact at the N-type conductive region 11, increase the slurry pulling force, improve the cell quality and yield, and also increase the open circuit voltage of the solar cell, and improve the fill factor and photoelectric conversion efficiency.

[0043] In some embodiments, as shown in FIG. 4, the second non-pyramidal textured structure 121 includes two or more third substructures 1211 that are at least partially stacked and two or more fourth substructures 1212 that are adjacently arranged in a non-stacked manner; Among the two or more third substructures 1211 at least partially stacked, a one-dimensional size of a top surface of the outermost third substructure 1211 in a direction away from the rear surface and perpendicular to the rear surface is 10 μm or more and 40 μm or less; The one-dimensional size of the top surface of the fourth substructure 1212 spaced from the rear surface is not less than 10 μm and not more than 40 μm.

[0044] As can be seen, since the second non-pyramidal textured structure 121 of the present invention includes two or more third sub-structures 1211 at least partially stacked and two or more adjacent non-stacked arranged fourth sub-structures 1212, the roughness of the second non-pyramidal textured structure 121 can be controlled within a desired range, which is beneficial for the screen printing stage of the solar cell, and can enhance the slurry contact with the N-type conductive region 11, increase the slurry pulling force, improve the cell quality and yield, and also increase the open circuit voltage of the solar cell, and improve the fill factor and photoelectric conversion efficiency.

[0045] In some embodiments, as shown in FIG. 6, there is a boundary line 13 between the N-type conductivity region 11 and the P-type conductivity region 12, and as shown in FIGS. 6-8, a void 131 is provided in a position adjacent to the boundary line 13 in the N-type conductivity region 11 and / or the P-type conductivity region 12.

[0046] As can be seen, the void 131 provided in a position close to the boundary line 13 of the N-type conductive region 11 and / or the P-type conductive region 12 is advantageous for carrier transmission and also advantageous for improving battery performance, and can also improve the reflectance of the 900-1200 band by 1% to 10%.

[0047] In some embodiments, the void 131 is formed when, during the fabrication of a solar cell, laser light is used to remove excess film layers from the P-type conductive region 12, where the laser light thermally damages the nearby N-type conductive region 11, destroying its surface film layer, and the thermally damaged region is then etched during a subsequent alkaline polishing process.

[0048] In some embodiments, a void 131 is provided at a position 5 μm to 15 μm away from the boundary line 13 in the N-type conductive region and / or the P-type conductive region.

[0049] Preferably, the placement position of the void 131 may be 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm or 15 μm, etc., and of course may be other values ​​within the above range, and is not limited thereto.

[0050] Preferably, a void 131 is provided at a position 5 μm to 10 μm away from the boundary line 13 in the N-type conductive region 11 and / or the P-type conductive region 12 .

[0051] In some embodiments, the voids 131 have a diameter between 1 μm and 10 μm.

[0052] Preferably, the diameter of the voids 131 may be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm or 10 μm, etc., and of course may be other values ​​within the above ranges, and is not limited thereto.

[0053] Preferably, the diameter of the voids 131 is between 1 μm and 5 μm.

[0054] In some embodiments, the voids 131 have a depth of between 0.5 μm and 2 μm.

[0055] Preferably, the depth of the void 131 may be 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, 1.6 μm, 1.7 μm, 1.8 μm, 1.9 μm, or 2 μm, etc., and may of course be other values ​​within the above range, and is not limited thereto. Here, the depth value of the void 131 may be obtained by scanning with a 3D microscope. In some specific embodiments, the depth of the void 131 may be 1 / 2 to 1 / 3 of the alkaline polishing etching depth (based on the polishing surface etching).

[0056] In some embodiments, the distance between two adjacent N-type conductive regions 11 or the distance between two adjacent P-type conductive regions 12 is 0.8 mm to 1.2 mm, the distribution ratio of the N-type conductive regions 11 on the rear surface of the semiconductor substrate 1 is 50% to 85%, and the distribution ratio of the P-type conductive regions 12 on the rear surface of the semiconductor substrate 1 is 15% to 50%.

[0057] Preferably, the interval between two adjacent N-type conductive regions 11 or the interval between two adjacent P-type conductive regions 12 may be 0.8 mm, 0.85 mm, 0.9 mm, 0.95 mm, 1.0 mm, 1.05 mm, 1.1 mm, 1.15 mm, 1.2 mm, etc., and may of course be other values ​​within the above range, and is not limited here. The distribution ratio of the N-type conductive region 11 on the rear surface of the semiconductor substrate 1 may be 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, etc., and may of course be other values ​​within the above range, and is not limited here. Correspondingly, the distribution ratio of the P-type conductive region 12 on the rear surface of the semiconductor substrate 1 may be 50%, 45%, 40%, 35%, 30%, 25%, 20%, 15%, etc., and may of course be other values ​​within the above range, and is not limited here.

[0058] As can be understood, by limiting the distance between two adjacent N-type conductive regions 11 or the distance between two adjacent P-type conductive regions 12 on the semiconductor substrate 1, and limiting the distribution ratio of the N-type conductive regions 11 and the P-type conductive regions 12 on the rear surface of the semiconductor substrate 1, a PN junction with excellent conductivity can be formed in the semiconductor substrate 1 during the process of fabricating a solar cell, and the photoelectric performance of the fabricated solar cell can be improved.

[0059] In some specific embodiments, in the fabrication of the semiconductor substrate 1 of the present invention, first, a backside structure having the form of a small tower base is fabricated using alkaline polishing, and the corresponding film layer is deposited to form an N-type conductive region, and then, a P-type conductive region is identified using film cutting with laser light, and then, laser light damage is removed again using alkaline polishing to form a planar surface form of a large tower base. When removing the excess film layer of the P-type region with laser light, the laser light thermally damages the nearby N-type conductive region, destroying its surface film layer, and the thermally damaged region is etched in the subsequent alkaline polishing process to form a void. In the fabrication process, the laser light process may be adjusted to control the thermal damage within a certain range from the boundary.

[0060] It should be noted that the semiconductor substrate 1 of the present invention may be formed during the manufacturing process of the solar cell, or may be formed during the preparation of the original substrate (silicon slice) prior to the manufacturing process of the solar cell.

[0061] In a second aspect, the present invention further provides a solar cell, which includes the above-mentioned semiconductor substrate 1 of the present invention, a tunnel oxide layer 2, a local back surface field 3, a polycrystalline silicon thin film layer 4, a eutectic layer 5, a rear passivation layer 6, a first electrode 7 and a second electrode 8, as shown in FIG. The semiconductor substrate 1 may be one of a monocrystalline silicon substrate, a polycrystalline silicon substrate, a microcrystalline silicon substrate or a silicon carbide substrate. In some embodiments, the semiconductor substrate is a P-type crystalline silicon substrate.

[0062] A tunnel oxide layer 2 is provided on the N-type conductive region 11 on the rear surface of the semiconductor substrate 1. The tunnel oxide layer 2 may be a laminated structure of one or more of a silicon oxide layer, an aluminum oxide layer, a silicon oxynitride layer, a molybdenum oxide layer, and a hafnium oxide layer. In other embodiments, the tunnel oxide layer 2 may be an oxygen-containing silicon nitride layer, an oxygen-containing silicon carbide layer, etc. In some possible embodiments, the tunnel oxide layer 2 may be formed by etching and then treating the N-type conductive region 11 on the rear surface of the semiconductor substrate 1 using an ozone oxidation method, a high-temperature thermal oxidation method, a nitric acid oxidation method, a chemical vapor deposition method, or a low-pressure chemical vapor deposition method.

[0063] A local back surface field 3 is provided in the P-type conductive region 12 on the rear surface of the semiconductor substrate 1. The local back surface field 3 formed in the P-type conductive region 12 can increase the open circuit voltage of the fabricated solar cell, reduce the aluminum-silicon contact resistance Rs, and effectively improve the photoelectric conversion efficiency of the cell. In some specific embodiments, the local back surface field 3 is an aluminum back surface field.

[0064] A polycrystalline silicon thin film layer 4 is provided on the side of the tunnel oxide layer 2 that is away from the semiconductor substrate 1. The polycrystalline silicon thin film has the electrical properties of crystalline silicon, and has the advantages of being less expensive than amorphous silicon thin films, requiring simple equipment, and being able to be fabricated in a large area. The polycrystalline silicon thin film layer 4 may be formed by depositing the polycrystalline silicon thin film layer 4 on the surface of the tunnel oxide layer 2 using any one of physical vapor deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, and atomic layer deposition.

[0065] A eutectic layer 5 is provided on the local back surface field 3. In some specific embodiments, the eutectic layer 5 is a silicon aluminum eutectic layer.

[0066] A rear passivation layer 6 is provided on the side of the polysilicon thin film layer 4 away from the tunnel oxide layer 2 and on the P-type conductive region 12, and the rear passivation layer 6 provides a passivation function to the rear surface of the semiconductor substrate 1. The rear passivation layer 6 may be composed of one or more passivation layers. The rear passivation layer 6 may include passivation layers such as aluminum oxide, silicon nitride, silicon oxide, silicon oxynitride, and carbon-doped silicon oxynitride layers. In some specific embodiments, the rear passivation layer 6 includes a first rear passivation layer 61 and a second rear passivation layer 62, and the first rear passivation layer 61 and the second rear passivation layer 62 are sequentially provided along a direction away from the rear surface of the semiconductor substrate 1. In some specific embodiments, the first rear passivation layer 61 may be an aluminum oxide layer, and the second rear passivation layer 62 may be a silicon nitride layer.

[0067] A first electrode 7 passes through the rear passivation layer 6 and forms an ohmic contact with the local back surface field 3 .

[0068] The second electrode 8 passes through the rear passivation layer 6 and the polysilicon thin film layer 4 in sequence to form an ohmic contact. The first electrode 7 and the second electrode 8 may be formed by applying a metal conductive slurry to the surface of the rear passivation layer 6 and then firing it. In some embodiments, the material of the first electrode 7 and / or the second electrode 8 includes a metal material such as silver, aluminum, copper, nickel, etc. In one specific embodiment, the first electrode 7 includes an aluminum material, and the second electrode includes a silver material.

[0069] In some specific embodiments, as shown in FIG. 9, the solar cell comprises: The semiconductor substrate 1 further includes a front passivation layer 9 and an anti-reflection layer 10, which are disposed on the front surface of the semiconductor substrate 1 and are sequentially stacked in a direction away from the semiconductor substrate 1. The front passivation layer 9 performs a passivation function on the front surface of the semiconductor substrate 1, and the front passivation layer 9 may be composed of one or more passivation layers. The front passivation layer 9 may include passivation layers such as aluminum oxide, silicon nitride, silicon oxide, silicon oxynitride, and carbon-doped silicon oxynitride layers. In some specific embodiments, the front passivation layer 9 may be an aluminum oxide layer. The anti-reflection layer 10 can prevent or reduce light reflection, and can fully utilize the purpose of solar energy. The anti-reflection layer 10 may be formed on the front passivation layer 9 by methods such as chemical vapor deposition, physical vapor deposition, and high-temperature nitridation. In some specific embodiments, the anti-reflection layer 10 may be a silicon oxynitride layer.

[0070] In a third aspect, the present invention further provides a photovoltaic module. The photovoltaic module includes the solar cell described above, and can improve the cell conversion efficiency of the photovoltaic module. The photovoltaic module includes the solar cell described above, and the solar cell is electrically connected in the form of a whole sheet or a plurality of divided sheets (e.g., a plurality of divided sheets, such as 1 / 2 equal slices, 1 / 3 equal slices, 1 / 4 equal slices, etc.) to form a plurality of cell strings, and the plurality of cell strings are electrically connected in a series connection and / or parallel connection manner. In some embodiments, the photovoltaic module further includes a packaging material layer and a cover plate, the packaging material layer seals the plurality of solar cell strings, and the cover plate covers the packaging material layer. For example, the material of the packaging material layer may be an organic material such as EVA, POE, or PET, and the cover plate may be a cover plate having a light-transmitting function, such as a glass cover plate or a plastic cover plate.

[0071] In a fourth aspect, the present invention further provides a method for producing the solar cell described above, the method comprising the steps of:

[0072] In step S1, a semiconductor substrate 1 is provided, and a texturing process and an oxidation process are sequentially performed on the semiconductor substrate 1.

[0073] In step S2, a front passivation layer 9 and an anti-reflection layer 10 are sequentially laminated on the front surface of the semiconductor substrate 1 in a direction away from the semiconductor substrate 1.

[0074] In step S3, the rear surface of the semiconductor substrate 1 is pickled, and then polished with an alkaline solution to form a first non-pyramidal texture structure 111 on the rear surface of the semiconductor substrate 1.

[0075] In step S4, a tunnel oxide layer 2 is formed on the first non-pyramid texture structure 111 on the rear surface of the semiconductor substrate 1, and a polysilicon thin film layer 4 is deposited on the surface of the tunnel oxide layer 2. In some specific embodiments, the polysilicon thin film layer 4 may further be doped to form a doped conductive layer.

[0076] In step S5, the P-type conductive region 12 is identified and formed using film cutting with laser light, the region in which the first non-pyramidal texture structure 111 is formed is designated as the N-type conductive region 11, and the P-type conductive region 12 on the rear surface of the semiconductor substrate 1 is polished using an alkaline solution, so that a second non-pyramidal texture structure 121 is formed in the P-type conductive region 12 on the rear surface of the semiconductor substrate 1. The top surface of the first non-pyramidal texture structure 111 and the top surface of the second non-pyramidal texture structure 121 are both polygonal planes, and the one-dimensional size L1 of the top surface of the first non-pyramidal texture structure 111 is smaller than the one-dimensional size L2 of the top surface of the second non-pyramidal texture structure 121, the one-dimensional size L1 of the top surface of the first non-pyramidal texture structure 111 is 5 μm or more and 12 μm or less, and the one-dimensional size L2 of the top surface of the second non-pyramidal texture structure 121 is 10 μm or more and 40 μm or less. In some specific embodiments, the conditions for film cutting by laser light include selecting an ultraviolet laser with a wavelength of 355 nm or a green laser with a wavelength of 556 nm as the laser type, and a spot size of 30 μm to 100 μm. In some specific embodiments, when the laser light is used to remove the excess film layer of the P-type conductive region 12, the laser light thermally damages the nearby N-type conductive region 11, destroying its surface film layer, and the thermally damaged region is etched in the subsequent alkaline polishing process to form voids 131. During fabrication, the heat loss can be controlled within a certain range by adjusting the laser film-cutting parameters.

[0077] In step S6, patterning is performed on the P-type conductivity region 12 on the rear surface of the semiconductor substrate 1 to form a local back surface field 3 and a eutectic layer 5.

[0078] In step S7, a rear passivation layer 6 is deposited on the surface of the polysilicon thin film layer 4 and the P-type conductive region 12. In some specific embodiments, the rear passivation layer 6 includes a first rear passivation layer 61 and a second rear passivation layer 62, and during fabrication, the first rear passivation layer 61 is deposited on the surface of the polysilicon thin film layer 4 and the P-type conductive region 12, and then the second rear passivation layer 62 is deposited.

[0079] Comparative Example The comparative example provides a solar cell, which comprises a semiconductor substrate, a rear surface of the semiconductor substrate having an N-type conductivity region and a P-type conductivity region, the N-type conductivity region and the P-type conductivity region being provided with the same non-pyramidal texture structure.

[0080] Compared to the cell structure of the comparative example, a first non-pyramidal textured structure and a second non-pyramidal textured structure of different size specifications are provided in the N-type conductive region and the P-type conductive region of the rear surface of the solar cell of the present invention, while the other structures and manufacturing methods are the same, and the following was discovered through a comparison test.

[0081] [Table 1] Comparison of the performance of the solar cell of the present invention with that of the comparative example [Table 1]

[0082] However, the conversion efficiency of the solar cell = (open voltage * short circuit current * fill factor) / (cell area * light irradiation width) 10 * 100%. It can be seen that the open circuit voltage, short circuit current, and fill factor are proportional to the conversion efficiency. From the data in Table 1, it can be seen that the conversion efficiency of the solar cell in which the semiconductor substrate 1 has a non-pyramid texture structure of a different standard size is 0.17% higher than the conversion efficiency of the solar cell in which the semiconductor substrate 1 has a non-pyramid texture structure of the same standard.

[0083] The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included within the protection scope of the present invention. [Explanation of symbols]

[0084] 1-Semiconductor Substrate 11-N type conductive region 111-First non-pyramidal texture structure 1111-First substructure 1112-Second substructure 12-P type conductive region 121-Secondary non-pyramidal texture structure 1211-Third Substructure 1212-4th substructure 13-Border 131-Void 2-Tunnel oxide layer 3- Local back surface field 4-Polycrystalline silicon thin film layer 5-eutectic layer 6-Rear passivation layer 61-First rear passivation layer 62-Second rear passivation layer 7-1st electrode 8-Second electrode 9-Front passivation layer 10-Anti-reflection layer

Claims

1. A semiconductor substrate, the rear surface of the semiconductor substrate has an N-type conductivity region and a P-type conductivity region, the N-type conductivity region being provided with a first non-pyramidal texture structure and the P-type conductivity region being provided with a second non-pyramidal texture structure; a top surface of the first non-pyramidal texture structure and a top surface of the second non-pyramidal texture structure are both polygonal planes, and a one-dimensional size of the top surface of the first non-pyramidal texture structure is smaller than a one-dimensional size of the top surface of the second non-pyramidal texture structure; the first non-pyramidal texture structure has a top surface with a one-dimensional size of 5 μm or more and 12 μm or less, and the second non-pyramidal texture structure has a top surface with a one-dimensional size of 10 μm or more and 40 μm or less; The non-pyramidal shape refers to a tower base, a square trapezoid, or a stepped shape formed by breaking the tower end of a pyramidal microstructure, and the one-dimensional size is the diagonal length of the polygonal plane; The first non-pyramidal texture structure comprises: two or more first substructures at least partially stacked and two or more second substructures arranged in an adjacent non-stacked manner; a one-dimensional size of a top surface of an outermost first substructure of the at least partially stacked two or more first substructures in a direction spaced from the rear surface and perpendicular to the rear surface is 5 μm or more and 12 μm or less; a one-dimensional size of a top surface of the second substructure spaced from the rear surface is equal to or greater than 5 μm and equal to or less than 12 μm; A semiconductor substrate characterized in that there is a boundary line between the N-type conductive region and the P-type conductive region, and a void is provided in a position close to the boundary line of the P-type conductive region by alkaline polishing etching of a thermally damaged region close to the N-type conductive region, and the depth of the void is 1 / 2 to 1 / 3 of the alkaline polishing etching depth, and the depth of the void is 0.5 μm to 2 μm.

2. A semiconductor substrate, the rear surface of the semiconductor substrate has an N-type conductivity region and a P-type conductivity region, the N-type conductivity region being provided with a first non-pyramidal texture structure and the P-type conductivity region being provided with a second non-pyramidal texture structure; a top surface of the first non-pyramidal texture structure and a top surface of the second non-pyramidal texture structure are both polygonal planes, and a one-dimensional size of the top surface of the first non-pyramidal texture structure is smaller than a one-dimensional size of the top surface of the second non-pyramidal texture structure; the first non-pyramidal texture structure has a top surface with a one-dimensional size of 5 μm or more and 12 μm or less, and the second non-pyramidal texture structure has a top surface with a one-dimensional size of 10 μm or more and 40 μm or less; The non-pyramidal shape refers to a tower base, a square trapezoid, or a stepped shape formed by breaking the tower end of a pyramidal microstructure, and the one-dimensional size is the diagonal length of the polygonal plane; The second non-pyramidal texture structure comprises: two or more third substructures at least partially stacked and two or more fourth substructures arranged adjacently and non-stacked; a one-dimensional size of a top surface of an outermost third substructure, of the at least partially stacked two or more third substructures, in a direction spaced apart from the rear surface and perpendicular to the rear surface, is 10 μm or more and 40 μm or less; a one-dimensional size of a top surface of the fourth substructure spaced from the rear surface is equal to or larger than 10 μm and equal to or smaller than 40 μm; A semiconductor substrate characterized in that there is a boundary line between the N-type conductive region and the P-type conductive region, and a void is provided in a position close to the boundary line of the P-type conductive region by alkaline polishing etching of a thermally damaged region close to the N-type conductive region, and the depth of the void is 1 / 2 to 1 / 3 of the alkaline polishing etching depth, and the depth of the void is 0.5 μm to 2 μm.

3. 3. The semiconductor substrate according to claim 1, wherein a void is provided in the N-type conductive region at a position close to the boundary line.

4. 4. The semiconductor substrate according to claim 3, wherein the distance between the void and the boundary line in the N-type conductive region and / or the P-type conductive region is 5 μm to 15 μm.

5. 4. The semiconductor substrate according to claim 3, wherein the voids have a diameter of 1 μm to 10 μm.

6. The semiconductor substrate according to claim 1 or 2; a tunnel oxide layer disposed in an N-type conductivity region on a rear surface of the semiconductor substrate; a local back surface field established in a P-type conductivity region on a rear surface of the semiconductor substrate; a polycrystalline silicon thin film layer provided on the tunnel oxide layer on a side away from the semiconductor substrate; a eutectic layer provided in the local back surface field; a backside passivation layer disposed on the side of the polysilicon thin film layer away from the tunnel oxide layer and on the P-type conductive region; a first electrode passing through the back surface passivation layer to form an ohmic contact with the local back surface field; a second electrode passing through the rear passivation layer and forming an ohmic contact with the polycrystalline silicon thin film layer.

7. 7. The solar cell according to claim 6, further comprising a front passivation layer and an anti-reflection layer provided on the front surface of the semiconductor substrate and stacked in this order in a direction away from the semiconductor substrate.

8. A photovoltaic module, The photovoltaic power generation module comprises the solar cell according to claim 6, wherein the solar cell is electrically connected in the form of a single sheet or in the form of multiple divided sheets to form a solar cell string.

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