Power supply semiconductor integrated circuits

Abstract

To avoid a notification omission when an external resistor is detached from a terminal, in an IC for a power supply that includes a circuit for detecting a short-circuit anomaly and a thermal shutdown circuit.SOLUTION: A semiconductor integrated circuit for power supply includes: a first transistor composing an output transistor and a current mirror circuit; a short-circuit anomaly detection circuit that detects a short-circuit state of a voltage output terminal, based on a voltage of a resistor element connected in series with the first transistor; and a first output terminal that outputs a detection result by the short-circuit anomaly detection circuit to an external part. A current limit value applied by a current limit circuit is set within a current detection range applied by the short-circuit anomaly detection circuit, and the short-circuit anomaly detection circuit can detect the short-circuit state of the voltage output terminal even when the current limit circuit limits a current.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a technology that is effective when used in a power supply semiconductor integrated circuit (power supply IC) that constitutes a voltage regulator such as a series regulator that converts DC voltage or a power supply switch that supplies or cuts off the voltage of a power supply device directly to a load. [Background technology]

[0002] 2. Description of the Related Art A series regulator (hereinafter, abbreviated as regulator) is a power supply device that outputs a DC voltage of a desired potential by controlling a transistor provided between a DC voltage input terminal and an output terminal. In automotive regulators, in general, in-vehicle electronic devices such as car navigation systems are connected to the regulator via a connector. Therefore, vibrations of the vehicle body can cause the connector to come off, opening the output terminal of the power supply, or causing a short circuit inside the electronic device as a load. Therefore, in-vehicle regulators are required to have the function to detect such abnormal conditions.

[0003] Therefore, for example, as shown in FIG. 8, an invention has been proposed relating to a semiconductor integrated circuit for a regulator (IC for a regulator) configured to include an open circuit abnormality detection comparator CMP1 that detects the open state of the output terminal and a short circuit abnormality detection comparator CMP2 that detects the short circuit state, and to generate abnormality detection signals Err_op, Err_sc and output them from the output terminal (Patent Documents 1 and 2).

[0004] The inventions described in Patent Documents 1 and 2 disclose an embodiment in which, in a regulator IC (FIG. 8) provided with a thermal shutdown circuit that stops the operation of an error amplifier when the chip temperature rises above a predetermined temperature, an OR gate 18 takes the logical sum of the output of comparator CMP2 for detecting short-circuit anomalies and the output of the thermal shutdown circuit TSD, and turns transistor Q6 on and off to output an abnormality detection signal Err_sc. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2017-45096 A [Patent Document 2] JP 2018-55545 A Summary of the Invention [Problem to be solved by the invention]

[0006] The regulator IC shown in FIG. 8 is provided with terminals P1 and P2 for connecting an external resistor Rop for detecting open abnormalities and an external resistor Rsc for detecting short abnormalities. When the resistors Rop and Rsc are normally connected to the terminals P1 and P2, the regulator IC outputs abnormality detection signals Err_op, Err_sc as shown in Table 1 below according to the detection state. However, if the external resistor Rop for detecting open abnormalities is disconnected from terminal P1, the abnormality detection signals Err_op, Err_sc as shown in Table 2 are output, and if the external resistor Rsc for detecting short abnormalities is shorted, the abnormality detection signals Err_op, Err_sc as shown in Table 3 are output.

[0007] [Table 1] [Table 2] [Table 3]

[0008] Comparing Table 1 with Table 2 and Table 3, it was found that when the thermal shutdown circuit TSD operates with the external resistor Rop disconnected from terminal P1, it outputs "H, L" as the abnormality detection signals Err_op and Err_sc, as shown in Table 1, instead of "L, L" as they should be output as in Table 1. Also, when a short circuit occurs in the output terminal or the load device with the external resistor Rsc for detecting short abnormalities in a shorted state, it outputs "H, H" as the abnormality detection signals Err_op and Err_sc, as shown in Table 3, instead of "H, L" as they should be output as in Table 1, resulting in an issue where a false report is made that a normal state is reported despite the fact that an abnormality actually exists.

[0009] If the thermal shutdown circuit TSD cannot accurately report that it is operating, or that a short circuit has occurred at the output terminal, this could be fatal to the power supply, and it is desirable to avoid this. On the other hand, referring to Table 2, even if an open circuit abnormality occurs at the output terminal when the external resistor Rop is in an open state, it will output "H,H" instead of "L,H" as it should. However, an open circuit abnormality at the output terminal simply causes the load device to not operate, and is not fatal to the power supply, so it can be tolerated.

[0010] The present invention has been made in light of the above-mentioned problems, and has as its object to prevent a failure to notify the operation of the thermal shutdown circuit or a failure to notify the short circuit at the output terminal when an external resistor becomes detached from the terminal in a power supply IC such as a regulator IC or a power switch IC that is equipped with a circuit for detecting short-circuit abnormalities at the output terminal and a thermal shutdown circuit. Another object of the present invention is to enable the use of a current limit circuit having a fold-back characteristic in a power supply IC (a regulator IC, a power switch IC) further equipped with a current limit circuit. [Means for solving the problem]

[0011] In order to achieve the above object, the present invention provides A power supply semiconductor integrated circuit comprising: an output transistor connected between a voltage input terminal to which a DC voltage is input and a voltage output terminal; a control circuit for controlling the output transistor in response to an output feedback voltage; and a current limit circuit for limiting an output current caused by the output transistor to a value not greater than a predetermined value, a first transistor forming a current mirror circuit together with the output transistor; a short circuit abnormality detection circuit that detects a short circuit state of the voltage output terminal based on a voltage of a resistor element connected in series with the first transistor; a first output terminal for outputting a detection result by the short circuit abnormality detection circuit to an outside, the current limit circuit is configured to be capable of outputting a signal indicating that the current limit circuit is operating when the output current is limited; a current limit value by the current limit circuit is set within a current detection range by the short circuit abnormality detection circuit, and the short circuit abnormality detection circuit can detect a short circuit state of the voltage output terminal even when the current limit circuit is limiting the current, A signal obtained by taking the logical sum of the detection signal of the short circuit abnormality detection circuit and the output signal of the current limit circuit. Signals indicating anomalies based on is output from the first output terminal.

[0012] According to the power supply semiconductor integrated circuit having the above-mentioned configuration, even if the resistor element connected in series with the output transistor and the transistor constituting the current mirror circuit is shorted, the short state can be detected by the current limit circuit and the occurrence of the abnormality can be notified to the outside. Also, since the short abnormality detection circuit can detect the short state of the voltage output terminal even when the current limit circuit is limiting the current, a circuit having a fold-back characteristic can be used as the current limit circuit, thereby protecting the load device and setting the detection value or detection range of the short abnormality detection circuit to the larger current side, thereby expanding the actual use range of the output current. In addition, even if a short circuit abnormality occurs at the output terminal while the external resistor for detecting a short circuit is shorted, a correct abnormality detection signal can be output.

[0013] Preferably, the second transistor forms a current mirror circuit with the output transistor; an open circuit abnormality detection circuit that detects an open circuit state of the voltage output terminal based on a voltage of a resistor element that is connected in series with the second transistor; a second output terminal for outputting a detection result by the open circuit abnormality detection circuit to an outside; a thermal shutdown circuit that stops the operation of the control circuit when the detected temperature is equal to or higher than a predetermined temperature; before The output signal of the short circuit abnormality detection circuit and the output signal of the current limit circuit In addition, the output signal of the thermal shutdown circuit Based on the signal ORed with The above A signal indicating an abnormality is output from the first output terminal, A signal obtained by taking a logical OR of the output signal of the thermal shutdown circuit and the output signal of the open circuit abnormality detection circuit is output from the second output terminal. With the above-described configuration, even if the resistive element connected in series with the second transistor becomes open, the abnormal state output from the first output terminal and the second output terminal when the thermal shutdown circuit operates can be made to be the desired, accurate reporting state.

[0014] Also, preferably, the output of the short circuit abnormality detection circuit and the output of the current limit circuit A delay circuit is provided to delay the The output of the delay circuit 、 The output of the short circuit abnormality detection circuit before being delayed The signal obtained by ORing the output signal of the current limit circuit with the signal and 、 A signal indicating an abnormality is output from the first output terminal based on the signal obtained by taking the logical product of With this configuration, it is possible to prevent the short circuit detection circuit from erroneously detecting the rush current that flows to charge the output capacitor when the power supply semiconductor integrated circuit starts operating as a short circuit abnormality at the output terminal.

[0015] Also, preferably, the output of the short circuit abnormality detection circuit and the output of the current limit circuit and a delay circuit for delaying the output of the open circuit abnormality detection circuit, The output of the delay circuit 、 The output of the short circuit abnormality detection circuit before being delayed The signal obtained by ORing the output signal of the current limit circuit with the signal and 、 a signal indicating an abnormality is output from the first output terminal based on a signal obtained by taking a logical product of the above, A signal indicating an abnormality is output from the second output terminal based on a signal obtained by taking a logical product of the output of the delay circuit and the output of the open abnormality detection circuit before it is delayed. According to the above-mentioned configuration, the short circuit abnormality detection circuit and the open circuit abnormality detection circuit of the output terminal are Current Limit Circuit In a power supply semiconductor integrated circuit having the above-mentioned, it is possible to prevent the short circuit detection circuit from erroneously detecting a rush current as a short circuit abnormality at the output terminal.

[0016] Further, preferably, a first overvoltage protection circuit is provided which detects an abnormal state and stops the output, When the first overvoltage protection circuit is operating, the first output terminal and the second output terminal are changed to a state indicating an abnormality based on a signal indicating an operating state output from the first overvoltage protection circuit. According to this configuration, in a power supply semiconductor integrated circuit equipped with an overvoltage protection circuit, when the overvoltage protection circuit operates, the occurrence of an abnormality can be notified to the outside from the first output terminal and the second output terminal. Here, an example of the overvoltage protection circuit is an output overvoltage protection circuit that detects an overvoltage state of the output voltage output from the voltage output terminal and stops the output.

[0017] Also, preferably, an external terminal to which the feedback voltage is input; a second overvoltage protection circuit that detects an overvoltage state of the feedback voltage and stops the output; When the second overvoltage protection circuit is operating, the first output terminal and the second output terminal are changed to a state indicating an abnormality based on a signal indicating an operating state output from the second overvoltage protection circuit. According to this configuration, in a power supply semiconductor integrated circuit having an overvoltage protection circuit that detects an overvoltage state of the feedback voltage and stops the output, when the overvoltage protection circuit operates, the occurrence of an abnormality can be notified to the outside from the first output terminal and the second output terminal. Effect of the Invention

[0018] According to the present invention, in a power supply semiconductor integrated circuit having a circuit for detecting short circuit and open circuit abnormalities in an output terminal and a thermal shutdown circuit, it is possible to prevent failure to notify the operation of the thermal shutdown circuit and failure to notify the short circuit in the output terminal when an external resistor is disconnected from the terminal.Furthermore, in a power supply semiconductor integrated circuit further having a current limit circuit, there is an effect that a current limit circuit having a fold-back characteristic can be used. [Brief description of the drawings]

[0019] [Figure 1] 1 is a circuit configuration diagram showing an embodiment of a regulator IC to which the present invention is applied. [Diagram 2]1A is a characteristic diagram showing the characteristics of a current limit circuit in a conventional regulator IC, and FIG. 1B is a characteristic diagram showing the characteristics of a current limit circuit constituting the regulator IC of the embodiment. [Diagram 3] 1A is a diagram showing the relationship between the short abnormality detection range and the current limit value in a conventional regulator IC, and FIG. 1B is a diagram showing the relationship between the short abnormality detection range and the current limit value in the regulator IC of the embodiment. [Figure 4] 2 is a circuit diagram showing a specific example of a current limit circuit constituting a regulator IC of an embodiment. FIG. [Diagram 5] FIG. 2 is a circuit diagram showing a first modified example of a regulator IC according to an embodiment. [Figure 6] FIG. 11 is a circuit diagram showing a second modified example of the regulator IC of the embodiment. [Figure 7] FIG. 2A is a circuit diagram showing an example of the configuration of a power switch IC, and FIG. 2B is a circuit diagram showing an example of the configuration of an IC when the present invention is applied to a power switch IC having an open circuit abnormality detection circuit and a short circuit abnormality detection circuit. [Figure 8] FIG. 1 is a circuit diagram showing an example of the configuration of a conventional regulator IC. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. Fig. 1 shows an embodiment of a series regulator as a DC power supply device to which the present invention is applied. In Fig. 1, the part enclosed by the dashed line is formed as a semiconductor integrated circuit (regulator IC) 10 on a semiconductor chip such as single crystal silicon, and a capacitor Co is connected to the output terminal OUT of the regulator IC 10 to function as a DC power supply device that supplies a stable DC voltage.

[0021] In the regulator IC10 of this embodiment, as shown in FIG. 1, a voltage control transistor Q1 made of a P-channel MOS transistor is connected between a voltage input terminal IN to which a DC voltage VDD is applied and an output terminal OUT, and bleeder resistors R1 and R2 for dividing the output voltage Vout are connected in series between the output terminal OUT and a ground line to which a ground potential GND is applied.

[0022] The voltage VFB divided by the output voltage dividing resistors R1 and R2 is fed back to the non-inverting input terminal of an error amplifier 11, which serves as an error amplifier circuit that controls the gate terminal of the voltage control transistor Q1. The error amplifier 11 controls the voltage control transistor Q1 in accordance with the potential difference between the output feedback voltage VFB and a predetermined reference voltage Vref, so that the output voltage Vout becomes a desired potential.

[0023] The regulator IC10 of this embodiment is also provided with a reference voltage circuit 12 for generating a reference voltage Vref to be applied to the inverting input terminal of the error amplifier 11, a bias circuit 13 for passing an operating current to the error amplifier 11 and the reference voltage circuit 12, a current limit circuit 14 connected to the gate terminal of the voltage control transistor Q1 for limiting the output current, and a thermal shutdown circuit 15 for stopping the operation of the error amplifier 11 and turning off the transistor Q1 when the chip temperature rises above a predetermined temperature. CE is an external terminal to which a signal for turning the IC operation on / off is input.

[0024] The reference voltage circuit 12 can be composed of a resistor and a Zener diode in series, etc. The bias circuit 13 has a function of supplying or cutting off a bias current to the error amplifier 11 in response to a control signal input to an external terminal CE from an external microcomputer (CPU), etc. The current limit circuit 14 limits the output current Io by clamping so that the drain current does not increase beyond a predetermined value when the output current increases due to an abnormality in the load, etc., causing the output voltage to decrease and the error amplifier 11 attempts to lower the gate voltage so that more current flows through the transistor Q1.

[0025] Furthermore, in the regulator IC10 of this embodiment, transistors Q2 and Q3 are provided in parallel with the voltage control transistor Q1, which constitutes a current mirror circuit with Q1, and the same voltage as that applied to the gate terminal of the voltage control transistor Q1 is applied to the gate terminals of these transistors Q2 and Q3 as control terminals. As a result, a current proportional to the drain current of Q1 (current of 1 / N) flows through Q2 and Q3 according to the size ratio N of the elements. When the transistor Q1 is configured by connecting N transistors of the same size in parallel, and Q2 and Q3 are each configured by one transistor, they are set so that a current proportional to the number of elements flows.

[0026] In addition, the regulator IC10 of this embodiment is provided with an external terminal P1 for connecting a resistor Rop for current-to-voltage conversion outside the chip, and an external terminal P2 for connecting a resistor Rsc, and the drain terminal of the current mirror transistor Q2 is connected to the external terminal P1, and the drain terminal of the current mirror transistor Q3 is connected to the external terminal P2. Further, there are provided a comparator CMP1 for detecting an open circuit abnormality, the inverting input terminal of which is connected to the external terminal P1 and a reference voltage Vref1 is applied to a non-inverting input terminal, and a comparator CMP2 for detecting a short circuit abnormality, the non-inverting input terminal of which is connected to the external terminal P2 and a reference voltage Vref1 is applied to an inverting input terminal. Although not particularly limited, the open circuit abnormality detection comparator CMP1 and the short circuit abnormality detection comparator CMP2 are preferably ones having hysteresis characteristics.

[0027] The resistance value of the external resistor Rop is set so that the voltage across both terminals of the resistor becomes equal to the reference voltage Vref1 when a relatively small detection current for an open circuit anomaly flows through the voltage control transistor Q1, while the resistance value of the external resistor Rsc is set so that the voltage across both terminals of the resistor becomes equal to the reference voltage Vref1 when a relatively large detection current for a short circuit anomaly flows through the voltage control transistor Q1. In this manner, in this embodiment, the current values ​​for detecting open circuit and short circuit abnormalities are set using the external resistors Rop and Rsc, so that the detection current value (threshold value) can be set arbitrarily according to the system being used, and the same voltage value can be used as the reference voltage Vref1 used by the comparators CMP1 and CMP2, thereby simplifying the circuit for generating the reference voltage.

[0028] The regulator IC10 of this embodiment is also provided with an OR gate G1 which takes the logical sum of the output OP_OUT of the comparator CMP1 and the output TSD_OUT of the thermal shutdown circuit 15, and an OR gate G2 which takes the logical sum of the output SC_OUT of the comparator CMP2, the output CL_OUT of the current limit circuit 14, and the output TSD_OUT of the thermal shutdown circuit 15. Here, the output CL_OUT of the current limit circuit 14 is a signal indicating that the current limit circuit 14 is operating, and the output TSD_OUT of the thermal shutdown circuit 15 is a signal indicating that the thermal shutdown circuit 15 is operating.

[0029] Further, there are provided an N-channel MOS transistor Q5, the gate terminal of which receives the output of the OR gate G1, and an N-MOS transistor Q6, the gate terminal of which receives the output of the OR gate G2. The regulator IC is provided with external terminals P3 and P4 for outputting signals to an external CPU or the like in an open-drain format, with the drain terminal of the transistor Q5 connected to the external terminal P3 and the drain terminal of the transistor Q6 connected to the external terminal P4.

[0030] In the conventional IC in Figure 8, when the thermal shutdown circuit TSD operates, it should output "L, L" as the abnormality detection signals Err_op and Err_sc as shown in Table 1, but when the thermal shutdown circuit TSD operates while the external resistor Rop for open abnormality detection is disconnected from terminal P1, it outputs "H, L" as shown in Table 2. In contrast, the regulator IC10 of this embodiment is provided with the OR gate G1 that takes the logical sum of the output OP_OUT of the comparator CMP1 and the output TSD_OUT of the thermal shutdown circuit 15, as described above. Therefore, when the thermal shutdown circuit operates with the external resistor Rop disconnected from the terminal P1, it is possible to output "L, L" as the abnormality detection signals Err_op, Err_sc, as shown in Table 4.

[0031] In addition, in the conventional IC in Figure 8, when a short circuit occurs at the output terminal, the abnormality detection signals Err_op and Err_sc should be output as "H, L" as shown in Table 1. However, when a short circuit occurs while the external resistor Rsc for detecting short circuits is shorted, "H, H" is output as shown in Table 3. In contrast to this, in the regulator IC10 of this embodiment, as described above, the output CL_OUT of the current limit circuit 14 is input to the OR gate G2, so that the current limit circuit 14 operates when the output terminal OUT is in a short-circuit state, regardless of the output SC_OUT of the comparator CMP2, and thus it is possible to output "H, L" as the abnormality detection signals Err_op, Err_sc, as shown in Table 5.

[0032] [Table 4] [Table 5]

[0033] Furthermore, in the regulator IC10 of this embodiment, even if the current limit circuit 14 operates to throttle the output current Io according to the foldback characteristic as shown in Fig. 2(B), if the current limit circuit 14 operates when the output terminal OUT is shorted, the output CL_OUT can output a low-level abnormality detection signal Err_sc. This also makes it possible to expand the actual use range of the output current Io. The reason for this will be explained below.

[0034] In the conventional regulator IC shown in FIG. 8, if the current limit value is within the detection range of the short circuit abnormality detection circuit (comparator CMP2) having hysteresis characteristics, the current limit circuit will operate and will not be able to accurately detect and report a short circuit abnormality in the output terminal. Therefore, as shown in FIG. 3(A), it was necessary to set the current limit value to a large current value away from the short circuit detection range and to make the current limit circuit characteristic a drooping type characteristic as shown in 2(A).

[0035] In contrast, in the regulator IC10 of this embodiment, even if the current limit circuit 14 operates, it is possible to accurately detect and report a short circuit abnormality at the output terminal, so that the current limit value can be set within the short circuit abnormality detection range. Therefore, as shown in Fig. 3(B), it is possible to expand the actual use range of the output current Io. In addition, by using a current limit circuit 14 having a fold-back characteristic, it is possible to protect the load device from an overcurrent.

[0036] Fig. 4 shows a specific example of a current limit circuit 14 that has a foldback characteristic and outputs a signal CL_OUT that changes to a high level when the circuit is operating. The current limit circuit 14 in Fig. 4 includes a main circuit section 14A that operates as a normal current limit circuit, and a signal generating section 14B that generates and outputs a signal CL_OUT that notifies that the main circuit section 14A is operating. Note that the current mirror circuit shown in Fig. 4 is just one example, and is not limited to the above configuration.

[0037] 4, the main circuit section 14A of the current limit circuit 14 of this embodiment includes a MOS transistor Q11 and a resistor R11 connected in series between the power supply voltage terminal VDD and the ground point, a resistor R12 and a MOS transistor Q12 connected in series between the power supply voltage terminal VDD and the ground point, and a MOS transistor Q13 connected in series between the power supply voltage terminal VDD and the gate terminal of the MOS transistor Q11 and having a gate terminal connected to a connection node N2 between R12 and Q12. Of the above transistors, Q12 is an N-MOS, and Q11 and Q13 are P-MOS.

[0038] 1 to form a current mirror circuit, so that a current proportional to the current (Io) flowing through Q1 flows through MOS transistor Q11. The gate terminal of MOS transistor Q12 is connected to a connection node N1 between transistor Q11 and resistor R11, so that Q12 and resistor R12 operate as a source-grounded amplifier circuit. In the main circuit section 14A, as the output current Io increases, the current flowing through the resistor R11 increases, causing the voltage at the connection node N1 to increase, which is then amplified by the source-grounded amplifier circuit made up of Q12 and resistor R12. When the transistor Q13 turns on, the gate voltage of the voltage control transistor Q1 is raised to reduce the output current, thereby providing overcurrent protection.

[0039] The signal generating unit 14B includes a MOS transistor Q14 and a constant current source I1 connected in series between a power supply voltage terminal VDD and a ground point, and inverters INV1 and INV2 connected to a connection node N3 between the transistor Q14 and the constant current source I1. The gate terminals of the transistor Q14 are connected to the transistor Q13 of the main circuit unit 14A so as to form a current mirror circuit. When the main circuit unit 14A operates to limit the current, the transistor Q14 turns on, increasing the potential of the node N3, and the output CL_OUT of the inverter INV2 changes to a high level, which is a signal indicating that the current limit circuit 14 is operating.

[0040] (Modification) Next, a modification of the regulator IC of the above embodiment will be described with reference to FIGS. The configuration of a regulator IC of the first modified example is shown in Fig. 5. The modified example shown in Fig. 5 is provided with a delay circuit 16 that delays the abnormality detection signals OP_OUT, SC_OUT, an OR gate G3 that takes the logical sum of the output SC_OUT of the comparator CMP2 and the output CL_OUT of the current limit circuit 14, and a NOR gate G4 that takes the logical sum of the output of the OR gate G3 and the output OP_OUT of the comparator CMP1, and is configured so that a signal obtained by taking the logical AND of the signal delayed by the delay circuit 16 and the signal before the delay is input to the OR gates G1 and G2.

[0041] In this way, by providing the delay circuit 16, it is possible to prevent a false detection pulse from appearing at the output of the comparator CMP2 for detecting short circuit anomalies, which would otherwise occur if a relatively large rush current (inrush current) flows toward the capacitor Co of the output terminal when the IC is started up. The delay circuit 16 is composed of a constant current source I2, a switch transistor Qs connected in series with the constant current source I2, and a comparator CMP3 which receives the potential of a connection node N0 between the constant current source I2 and the transistor Qs and a predetermined reference voltage Vref2 as inputs, and the output voltage of the NOR gate G4 is input to the gate terminal of the transistor Qs.The delay circuit 16 is also equipped with an external terminal CD connected to the connection node N0, and is configured to increase the delay time without increasing the chip size by connecting an external capacitor Cd charged by the constant current source I1 to the terminal CD.

[0042] Furthermore, at the downstream of the delay circuit 16, there are provided an AND gate G5 which takes the logical product of the output of the delay circuit 16 and the output OP_OUT of the comparator CMP1 before delay, and an AND gate G6 which takes the logical product of the output of the delay circuit 16 and the output of the OR gate G3. In the delay circuit 16, in a normal operating state in which the outputs of the comparators CMP1, CMP2 and the output CL_OUT of the current limit circuit 14 are at a low level, the output of the OR gate G3 is at a low level and the output of the NOR gate G4 is at a high level, so that a high level is applied to the gate terminal of the transistor Qs by the NOR gate G4, turning the transistor Qs on and the capacitor Cd is in a discharged state.

[0043] When the comparator CMP1 detects an open state of the output terminal or the comparator CMP2 detects a short state of the output terminal and the output of either one of the comparators changes to a high level, the output of the NOR gate G4 changes to a low level and the transistor Qs is turned off. Also, when the current limit circuit 14 operates and its output CL_OUT changes to a high level, the output of the NOR gate G4 changes to a low level and the transistor Qs is turned off.

[0044] Then, the capacitor Cd is gradually charged, and the potential of the connection node N0 gradually rises. After a predetermined time has elapsed, when the potential of the connection node N0 becomes higher than the reference voltage Vref2 of the comparator CMP3, the output of the comparator CMP3 changes from low level to high level. When the comparator CMP1 detects an open circuit abnormality of the output terminal, the output of the AND gate G5 changes to high level, turning on the transistor Q5, and the open circuit abnormality detection signal Err_op output from the external terminal P3 changes from high level to low level.

[0045] Furthermore, when the comparator CMP2 detects a short circuit at the output terminal or the current limit circuit 14 is operating, the output of the AND gate G6 goes high, turning on the transistor Q6 and causing the short circuit detection signal Err_sc output from the external terminal P4 to go from high to low. The delay time of the delay circuit 16 is set to a time slightly longer than the period during which the rush current flows. By providing the delay circuit 16 and the AND gates G3 and G4 as described above, it is possible to prevent the short circuit detection comparator CMP2 from generating a false detection pulse due to the detection of a rush current.

[0046] FIG. 6 shows the configuration of a regulator IC according to a second modified example. There are three differences between the second modified example shown in FIG. 6 and the first modified example shown in FIG. 6, output voltage dividing resistors R1 and R2 that divide the output voltage Vout to generate the feedback voltage VFB are connected to the output terminal OUT as external elements, and the IC is provided with an external terminal FB for inputting the feedback voltage VFB. By using the resistors R1 and R2 as external elements, the voltage value of the output voltage Vout can be adjusted by changing the ratio of the resistors R1 and R2 outside the IC.

[0047] The second difference from the first variant is that the second variant in FIG. 6 is provided with an overvoltage protection circuit (OVP) 19A that detects an overvoltage state of the output voltage Vout and stops the output, and an overvoltage protection circuit (FB_OVP) 19B that detects an overvoltage state of the voltage VFB of the external terminal FB and stops the output. By providing these circuits, the IC can be protected from an overvoltage state of the external terminal FB. 6, an OR gate G7 is provided that receives as inputs a signal OVP_OUT indicating that overvoltage protection circuit 19A has operated, a signal FB_OVP_OUT indicating that overvoltage protection circuit 19B has operated, and the output TSD_OUT of thermal shutdown circuit 15, and the output of this OR gate G7 is input to OR gates G1 and G2. This makes it possible to notify the outside that overvoltage protection circuit 19A or 19B has operated.

[0048] Table 6 below shows the relationship between each state of the regulator IC of the second modified example and the abnormality detection signals Err_op and Err_sc. [Table 6]

[0049] In the above embodiment, the present invention is applied to a regulator IC, but the present invention can also be applied to a power switch IC 20 that supplies or cuts off the voltage of a power supply device (such as a battery) directly to a load as shown in Fig. 7(A). The power switch IC shown in Fig. 7(A) has a gate control circuit 21 instead of an error amplifier, and the gate control circuit 21 is designed to control the output transistor Q1 to a full-on state or a full-off state depending on whether the control terminal CE is at a high level or a low level. Fig. 7(B) shows an embodiment in which the present invention is applied to the power switch IC of Fig. 7(A). As in Fig. 7(B), it is also possible to apply the configuration of the regulator IC shown in Fig. 5 or 6 to the power switch IC of Fig. 7(A). With this power switch IC 20 as well, the same effects as those described in the above embodiment can be obtained.

[0050] Although the invention made by the present inventor has been specifically described based on the embodiment, the present invention is not limited to the above embodiment. For example, in the second modification of the embodiment, an overvoltage protection circuit (OVP) 19A for the output voltage Vout and an overvoltage protection circuit (FB_OVP) 19B for the voltage VFB of the external terminal P6 are provided, but the present invention can be applied to a power supply IC having either one of the overvoltage protection circuits. Also, in the embodiment, the comparator CMP1 for detecting an open circuit abnormality and the comparator CMP2 for detecting a short circuit abnormality have a hysteresis characteristic, but the comparators may not have a hysteresis characteristic.

[0051] Furthermore, in the above embodiment, MOS transistors are used as the transistors constituting the internal circuits of the regulator IC 10 and the power switch IC 20, but bipolar transistors may be used instead of MOS transistors. Also, the delay capacitor Cd may be formed on the IC chip instead of being an external element. In the above embodiment, the protection circuit for the IC is described as including the current limit circuit 14, the thermal shutdown circuit 15, the output voltage overvoltage protection circuit 19A, and the feedback voltage overvoltage protection circuit 19B. However, the present invention can also be applied to a regulator IC or a power switch IC that includes other protection circuits, such as a circuit that detects an overvoltage state of the input voltage and stops operation. [Explanation of symbols]

[0052] 10...regulator IC, 11...error amplifier, 12...reference voltage circuit, 13...bias circuit, 14...current limit circuit, 15...thermal shutdown circuit, 16...delay circuit, 19A, 19B...overvoltage protection circuit, CMP1...comparator for detecting open circuit abnormality, CMP2...comparator for detecting short circuit abnormality, Q1...transistor for voltage control (output transistor), Q2, Q3...current mirror transistor, Cd...delay capacitor

Claims

1. A power supply semiconductor integrated circuit comprising: an output transistor connected between a voltage input terminal to which a DC voltage is input and a voltage output terminal; a control circuit for controlling the output transistor in response to an output feedback voltage; and a current limit circuit for limiting an output current caused by the output transistor to a value not greater than a predetermined value, a first transistor forming a current mirror circuit together with the output transistor; a short circuit abnormality detection circuit that detects a short circuit state of the voltage output terminal based on a voltage of a resistor element connected in series with the first transistor; a first output terminal for outputting a detection result by the short circuit abnormality detection circuit to an outside, the current limit circuit is configured to be capable of outputting a signal indicating that the current limit circuit is operating when the output current is limited; a current limit value by the current limit circuit is set within a current detection range by the short circuit abnormality detection circuit, and the short circuit abnormality detection circuit can detect a short circuit state of the voltage output terminal even when the current limit circuit is limiting the current, a signal indicating an abnormality based on a signal obtained by taking the logical sum of a detection signal of the short circuit abnormality detection circuit and an output signal of the current limit circuit is output from the first output terminal.

2. a second transistor forming a current mirror circuit with the output transistor; an open circuit abnormality detection circuit that detects an open circuit state of the voltage output terminal based on a voltage of a resistor element that is connected in series with the second transistor; a second output terminal for outputting a detection result by the open circuit abnormality detection circuit to an outside; a thermal shutdown circuit that stops the operation of the control circuit when the detected temperature is equal to or higher than a predetermined temperature; a signal indicating the abnormality is output from the first output terminal based on a signal obtained by taking a logical OR of the output signal of the short abnormality detection circuit, the output signal of the current limit circuit, and the output signal of the thermal shutdown circuit; 2. The power supply semiconductor integrated circuit according to claim 1, wherein a signal obtained by taking a logical sum of an output signal of the thermal shutdown circuit and an output signal of the open circuit abnormality detection circuit is output from the second output terminal.

3. a delay circuit for delaying an output of the short circuit abnormality detection circuit and an output of the current limit circuit; 2. The power supply semiconductor integrated circuit according to claim 1, wherein a signal indicating an abnormality is output from the first output terminal based on a signal obtained by taking a logical product of an output of the delay circuit and a signal obtained by taking a logical sum of an output signal of the short circuit abnormality detection circuit before being delayed and an output signal of the current limit circuit.

4. a delay circuit for delaying an output of the short circuit abnormality detection circuit, an output of the current limit circuit, and an output of the open circuit abnormality detection circuit; a signal indicating an abnormality is output from the first output terminal based on a signal obtained by taking a logical AND of an output of the delay circuit, an output signal of the short circuit abnormality detection circuit before being delayed, and an output signal of the current limit circuit; 3. The power supply semiconductor integrated circuit according to claim 2, wherein a signal indicating an abnormality is output from the second output terminal based on a signal obtained by taking a logical product of an output of the delay circuit and an output of the open abnormality detection circuit before being delayed.

5. a first overvoltage protection circuit that detects an abnormal state and stops output; 5. The power supply semiconductor integrated circuit according to claim 2, wherein the first output terminal and the second output terminal are changed to a state indicating an abnormality based on a signal indicating an operating state output from the first overvoltage protection circuit when the first overvoltage protection circuit is operating.

6. 6. The power supply semiconductor integrated circuit according to claim 5, wherein the first overvoltage protection circuit is an output overvoltage protection circuit which detects an overvoltage state of the output voltage output from the voltage output terminal and stops the output.

7. an external terminal to which the feedback voltage is input; a second overvoltage protection circuit that detects an overvoltage state of the feedback voltage and stops the output; 7. The power supply semiconductor integrated circuit according to claim 2, wherein the first output terminal and the second output terminal are changed to a state indicating an abnormality based on a signal indicating an operating state output from the second overvoltage protection circuit when the second overvoltage protection circuit is operating.

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