Semiconductor Device

Abstract

To provide a semiconductor device in which the influence on on-resistance can be suppressed while the operation of a parasitic transistor is suppressed.SOLUTION: A semiconductor device includes: a semiconductor part including a terminal, a first region, and a second region between the first region and the terminal, and also including a first semiconductor layer with a first conductivity type, a second semiconductor layer with a second conductivity type, a third semiconductor layer with the first conductivity type, and a fourth semiconductor layer with the second conductivity type having higher second conductivity type impurity concentration than the second semiconductor layer; a gate electrode provided in the semiconductor part and having a side surface facing the second semiconductor layer; and an upper electrode provided on the semiconductor part in contact with the third semiconductor layer and the fourth semiconductor layer. The ratio of the area of the fourth semiconductor layer to the area of the third semiconductor layer in the second region is larger than the ratio of the area of the fourth semiconductor layer to the area of the third semiconductor layer in the first region.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] In vertical-structure semiconductor devices that control on / off operation using trench gates, there is a problem that the operation of parasitic transistors at turn-off tends to concentrate current, especially in areas close to the device end (including corners), resulting in low breakdown resistance. One effective means of suppressing the operation of parasitic transistors is to provide a layer that reduces carrier discharge resistance by providing a high-concentration contact layer with the same polarity as the base layer of the transistor (hereinafter defined as a carrier drain (layer)). However, if the ratio of the carrier drain region is made too high, it will cause an increase in on-resistance. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6604585 Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments provide a semiconductor device capable of suppressing an increase in on-resistance while suppressing the operation of a parasitic transistor. [Means for solving the problem]

[0005] According to an embodiment, a semiconductor device includes a semiconductor part having an end, a first region, and a second region located between the first region and the end, the semiconductor part having a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, a third semiconductor layer of the first conductivity type provided on the second semiconductor layer, and a fourth semiconductor layer of a second conductivity type provided on the second semiconductor layer and having a higher second conductivity type impurity concentration than the second semiconductor layer, a gate electrode provided in the semiconductor part and having a side surface facing the second semiconductor layer, an insulating film provided between the side surface of the gate electrode and the semiconductor part, and an upper electrode provided on the semiconductor part and in contact with the third semiconductor layer and the fourth semiconductor layer. A ratio of an area of ​​the fourth semiconductor layer to an area of ​​the third semiconductor layer in the second region is greater than a ratio of an area of ​​the fourth semiconductor layer to an area of ​​the third semiconductor layer in the first region. The fourth semiconductor layer has a first portion disposed in the first region, a second portion disposed in the second region, and a third portion disposed in the second region and connecting the first portion and the second portion. A width of the second portion and a width of the third portion are greater than a width of the first portion. A plurality of the gate electrodes and a plurality of the third portions are alternately arranged in a second direction intersecting with a first direction in which the gate electrodes extend. A length in the second direction of a region in which the plurality of the third portions are arranged in the second direction via the gate electrodes is longer in a region closer to a corner portion of the semiconductor section. [Brief description of the drawings]

[0006] [Figure 1] 1 is a schematic plan view showing a configuration example of a semiconductor device according to an embodiment; [Diagram 2] 1 is a schematic cross-sectional perspective view of a semiconductor device according to an embodiment; [Diagram 3] 1 is a schematic plan view showing a configuration example of a semiconductor device according to an embodiment; [Figure 4] 1 is a schematic plan view showing a configuration example in the vicinity of a corner portion of a semiconductor device according to an embodiment; [Diagram 5] 1 is a schematic plan view showing a configuration example in the vicinity of a corner portion of a semiconductor device according to an embodiment; [Figure 6] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment mounted on a wiring board; [Figure 7] 1 is a graph showing measurement results of on-resistance and second breakdown capability of a semiconductor device. [Figure 8] 2 is a schematic plan view showing an example of the arrangement of first and second regions in the semiconductor device of the embodiment; FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals.

[0008] FIG. 1 is a schematic plan view showing an example of a configuration of a semiconductor device 1. As shown in FIG. FIG. 2 is a schematic cross-sectional perspective view of the semiconductor device 1. As shown in FIG.

[0009] The semiconductor device 1 has a semiconductor portion 10, an upper electrode 62 provided on the upper surface of the semiconductor portion 10, and a common electrode (or lower electrode) 61 provided on the lower surface of the semiconductor portion 10.

[0010] Two directions perpendicular to each other in a plane parallel to the upper or lower surface of the semiconductor portion 10 are defined as an X direction and a Y direction, and a direction perpendicular to the X direction and the Y direction is defined as a Z direction.

[0011] The semiconductor device 1 is a vertical semiconductor device in which a current flows in a vertical direction (Z direction) connecting an upper electrode 62 and a common electrode 61 in the semiconductor portion 10. The semiconductor device 1 also has a gate electrode 20 with a trench gate structure for controlling the on / off operation of the current.

[0012] The semiconductor device 1 has a first transistor Q1 and a second transistor Q2 that share a common electrode 61. The first transistor Q1 and the second transistor Q2 are adjacent to each other in the X direction. The first transistor Q1 and the second transistor Q2 have the same structure, for example, a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). The configuration shown in FIG. 2 is a common configuration for the first transistor Q1 and the second transistor Q2.

[0013] As shown in FIG. 1, the semiconductor portion 10 has a termination 100, a first region 101, and a second region 102 located between the first region 101 and the termination 100. The termination 100 includes the outermost side surface and corner portions of the semiconductor portion 10. The boundary between the first region 101 and the second region 102 is typically indicated by a two-dot chain line. The second region 102 is formed along the termination 100. The second region 102 is also disposed between the first transistor region in which the first transistor Q1 is formed and the second transistor region in which the second transistor Q2 is formed. In one semiconductor device 1, the first region 101 is wider than the second region 102.

[0014] The material of the semiconductor portion 10 is, for example, silicon, or may be, for example, silicon carbide, gallium nitride, or the like.

[0015] In the following description, the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type.

[0016] As shown in FIG. 2, the semiconductor section 10 has an n-type drain layer (or semiconductor substrate) 11, an n-type drift layer (first semiconductor layer) 12 provided on the drain layer 11, a p-type base layer (second semiconductor layer) 13 provided on the drift layer 12, an n-type source layer (third semiconductor layer) 14 provided on the base layer 13, and a p-type carrier extraction layer (fourth semiconductor layer) 15 provided on the base layer 13.

[0017] The n-type impurity concentration of the drift layer 12 is lower than the n-type impurity concentration of the drain layer 11 and the n-type impurity concentration of the source layer 14. The p-type impurity concentration of the carrier extraction layer 15 is higher than the p-type impurity concentration of the base layer 13.

[0018] A plurality of gate electrodes 20 are provided in the semiconductor portion 10. The gate electrodes 20 extend in the X direction within the semiconductor portion 10. An insulating film 31 is provided between the gate electrodes 20 and the semiconductor portion 10. The insulating film 31 is provided between a side surface of the gate electrode 20 and the base layer 13. The side surface of the gate electrode 20 faces the base layer 13 via the insulating film 31.

[0019] The semiconductor portion 10 is divided in the Y direction by the gate electrode 20 and has a mesa portion 70 extending in the X direction. A base layer 13, a source layer 14, and a carrier extraction layer 15 are provided in the mesa portion 70. In other words, the base layer 13, the source layer 14, and the carrier extraction layer 15 are provided between the gate electrodes 20 adjacent to each other in the Y direction. The source layers 14 and the carrier extraction layers 15 are alternately arranged along the X direction.

[0020] An upper electrode (source electrode) 62 is provided on the upper surface of the semiconductor portion 10. The upper electrode 62 is in contact with the source layer 14 and the carrier extraction layer 15. An insulating film 32 is provided between the upper electrode 62 and the gate electrode 20. A common electrode (drain electrode) 61 is provided on the lower surface of the semiconductor portion 10.

[0021] The upper electrode 62 is separated into two on the semiconductor portion 10. As indicated by the dashed lines in Fig. 1, a first source electrode 62a is formed in the first transistor region in which the first transistor Q1 is formed, and a second source electrode 62b is formed in the second transistor region in which the second transistor Q2 is formed.

[0022] For example, two first source pads S1 are arranged on the first source electrode 62a. The first source pads S1 are electrically connected to the first source electrode 62a. For example, two second source pads S2 are arranged on the second source electrode 62b. The second source pads S2 are electrically connected to the second source electrode 62b.

[0023] The common electrode 61 is not separated within one semiconductor device 1, but is provided in common to the first transistor Q1 and the second transistor Q2.

[0024] For example, one first gate pad G1 is disposed on the semiconductor portion 10 of the first transistor region. For example, one second gate pad G2 is disposed on the semiconductor portion 10 of the second transistor region.

[0025] FIG. 3 is a schematic plan view showing the positional relationship between the gate electrode 20, gate wirings 21a and 21b, gate pads G1 and G2, source layer 14, and carrier extraction layer 15 in the semiconductor device 1. As shown in FIG.

[0026] The gate electrodes 20 of the first transistor Q1 extend in the X-direction. The gate electrodes 20 of the first transistor Q1 are electrically connected to a first gate wiring 21a that is formed so as to surround the region in which the gate electrodes 20 are arranged. The first gate wiring 21a is electrically connected to the first gate pad G1. The first gate wiring 21a is arranged in the second region 102 on the terminal end 100 side.

[0027] The gate electrodes 20 of the second transistor Q2 extend in the X-direction. The gate electrodes 20 of the second transistor Q2 are electrically connected to a second gate wiring 21b that is formed so as to surround the region in which the gate electrodes 20 are arranged. The second gate wiring 21b is electrically connected to the second gate pad G2. The second gate wiring 21b is arranged in the second region 102 on the terminal end 100 side.

[0028] When a voltage equal to or greater than the threshold voltage is applied to the gate electrode 20, a channel is formed in a region of the base layer 13 facing the gate electrode 20. The gate electrode 20 of the first transistor Q1 and the gate electrode 20 of the second transistor Q2 can be controlled electrically independently of each other.

[0029] FIG. 6 is a schematic cross-sectional view of the semiconductor device 1 mounted on the wiring board 200. As shown in FIG.

[0030] The semiconductor device 1 is mounted on the wiring board 200 with the common electrode 61 facing upward. The first source pad S1, the second source pad S2, the first gate pad G1, and the second gate pad G2 of the semiconductor device 1 are joined to a conductor portion 201 of the wiring board 200 via a joining member (e.g., solder) 90.

[0031] The semiconductor device 1 of the embodiment can be incorporated in, for example, a charge / discharge circuit and used as a switch that controls bidirectional current conduction for charging and discharging. The first transistor Q1 and the second transistor Q2 share a drain portion (the drain layer 11 and the common electrode 61), and the first source electrode 62a of the first transistor Q1 and the second source electrode 62b of the second transistor Q2 are connected to terminals that are electrically independent (to which different potentials are applied). A current flows between the first transistor Q1 and the second transistor Q2 via the common electrode 61.

[0032] 2 may operate at the time of turn-off when the application of a voltage equal to or higher than the threshold voltage to the gate electrode 20 is stopped. The parasitic transistor Tr is an npn-type transistor in which the drift layer 12 serves as the collector, the source layer 14 serves as the emitter, and the base layer 13 serves as the base.

[0033] At the time of turn-off, a steep voltage change (dv / dt) occurs between the drain and source, causing a base current IB of the parasitic transistor Tr to flow through the capacitance between the base layer 13 and the drift layer 12, generating a base-emitter potential VBE, and turning on the parasitic transistor Tr. When the parasitic transistor Tr turns on, a current path different from the original current path of the MOSFET controlled by the gate electrode 20 is formed, which may cause destruction.

[0034] If the holes accumulated in the base layer 13 through the carrier extraction layer 15 at the time of turn-off are not easily extracted to the upper electrode (source electrode) 62, even a small base current IB generates a base-emitter potential VBE sufficient to turn on the parasitic transistor Tr.

[0035] One of the countermeasures for suppressing the generation of the base-emitter potential VBE that turns on the parasitic transistor Tr is to increase the area of ​​the carrier extraction layer 15. However, when the area of ​​the carrier extraction layer 15 is increased, the area of ​​the source layer 14 is relatively reduced, resulting in a trade-off relationship in which the on-resistance increases.

[0036] A large electric field is applied to the area of ​​the semiconductor portion 10 close to the termination 100, including the corner portion, and current tends to concentrate therein, making the area close to the termination 100 particularly prone to breakdown.

[0037] Therefore, in this embodiment, the ratio M of the area of ​​the carrier extraction layer 15 to the area of ​​the source layer 14 in the second region 102 close to the termination 100 is set to be larger than the ratio N of the area of ​​the carrier extraction layer 15 to the area of ​​the source layer 14 in the first region 101 located more inward than the second region 102. The ratio M per unit area in the second region 102 is larger than the ratio N per unit area in the first region 101.

[0038] For example, as shown in Fig. 3, the carrier extraction layer 15 has a first portion 51 disposed in a first region 101 and a second portion 52 disposed in a second region 102. The second portion 52 is formed along the gate wirings 21a, 21b in the vicinity of the gate wirings 21a, 21b. The gate wirings 21a, 21b are disposed between the second portion 52 and the terminal end 100. The first portion 51 is indicated by a thick solid line in the Y direction in Fig. 3. That is, the width of the first portion 51 in the X direction is the width of the thick solid line.

[0039] In the first region 101, the first portions 51 extend (are lined up) in the Y direction like broken lines separated by the gate electrode 20. The second portions 52 also extend (are lined up) in the Y direction like broken lines separated by the gate electrode 20. In the second portions 52, the width in the X direction of the portion extending in the Y direction is larger than the width in the X direction of the first portions 51. In the second portions 52, the portion extending in the X direction, which is the direction in which the gate electrode 20 extends, is continuous and not separated. The width in the Y direction of the portion of the second portions 52 that extends continuously in the X direction is larger than the width in the X direction of the first portions 51.

[0040] By making the width of the second portion 52 arranged in the second region 102 larger than the width of the first portion 51 arranged in the first region 101, holes in the base layer 13 in the second region 102 are more likely to escape to the upper electrode 62 through the carrier extraction layer 15. This makes it possible to suppress the operation of the parasitic transistor Tr, which is likely to occur in a region close to the termination 100 at the time of turn-off, and improve the breakdown resistance. By making the width of the first portion 51 arranged in the first region 101, which is wider than the second region 102 and occupies most of the region in which the channel is formed in the semiconductor device 1, smaller than the width of the second portion 52, the ratio of the source layer 14 per unit area in the first region 101 is relatively higher than that in the second region 102, and an increase in the on-resistance can be suppressed.

[0041] FIG. 4 is a schematic plan view showing one configuration example in the vicinity of the corner portion 110 of the semiconductor portion 10. As shown in FIG.

[0042] The carrier extraction layer 15 has, in addition to the above-mentioned first portion 51 arranged in the first region 101 and the above-mentioned second portion 52 arranged in the second region 102, a third portion 53 arranged near a corner portion 110 in the second region 102 and connecting the first portion 51 and the second portion 52. The multiple gate electrodes 20 and the multiple third portions 53 are arranged alternately in the Y direction intersecting (for example, perpendicular to) the X direction in which the gate electrodes 20 extend.

[0043] The width in the X direction of the second portion 52 and the width in the X direction of the third portion 53 are greater than the width in the X direction of the first portion 51. The length in the Y direction of a region 55 in which the multiple third portions 53 are aligned in the Y direction with the gate electrode 20 interposed therebetween is longer the closer the region is to the corner portion 110. The length of the region 55 in the Y direction gradually becomes longer the closer it is to the corner portion 110 in the X direction.

[0044] With this configuration, the operation of the parasitic transistor Tr, which is likely to occur particularly in the region close to the corner portion 110, can be suppressed, and the breakdown resistance can be improved.

[0045] Furthermore, as shown in FIG. 5, the lengths in the Y direction of a plurality of regions 55 arranged near the corner portion 110 may be the same.

[0046] FIG. 7 is a graph showing the measurement results of the on-resistance and second breakdown voltage of the semiconductor device.

[0047] 7, white circles indicate measured values ​​in a semiconductor device of a comparative example. The ratio of the area N of the source layer 14 to the area P of the carrier extraction layer 15 is defined as N:P. In the semiconductor device of the comparative example, the ratio N:P in the second region 102 is set to be the same as the ratio N:P in the first region 101. In the comparative example, measured values ​​were obtained when the ratio N:P was 5:1, when the ratio N:P was 4:1, and when the ratio N:P was 3:1.

[0048] The measured value of the secondary breakdown capacity when the N:P ratio in the comparative example is 5:1 is set as a reference value (1.00), and the secondary breakdown capacity on the horizontal axis of the graph in Fig. 7 represents the ratio to the reference value. Also, the measured value of the on-resistance when the N:P ratio in the comparative example is 5:1 is set as a reference value (1.00), and the on-resistance on the vertical axis of the graph in Fig. 7 represents the ratio to the reference value.

[0049] In the comparative example, the on-resistance and the second breakdown capacity change along the dashed line shown in Fig. 7 as the ratio of the area N of the source layer 14 to the area P of the carrier removal layer 15 increases or decreases. That is, in the comparative example, as the ratio of the area N of the source layer 14 to the area P of the carrier removal layer 15 decreases, the second breakdown capacity increases, but the on-resistance also increases. In the comparative example, as the ratio of the area N of the source layer 14 to the area P of the carrier removal layer 15 increases, the on-resistance decreases, but the second breakdown capacity also decreases.

[0050] In the graph of Fig. 7, the black circles indicate the measured values ​​of the on-resistance and second breakdown voltage in the semiconductor device of the embodiment. An example of the layout of the first region 101 and the second region 102 in the semiconductor device for which these measured values ​​were measured is shown in Fig. 8.

[0051] The first transistor Q1 and the second transistor Q2 are aligned in the X direction. The first transistor Q1 is divided into three regions in the X direction (the first region 101, the second region 102a on the termination 100 side, and the second region 102b on the boundary side between the first transistor Q1 and the second transistor Q2). The second transistor Q2 is also divided into three regions in the X direction (the first region 101, the second region 102a on the termination 100 side, and the second region 102b on the boundary side between the first transistor Q1 and the second transistor Q2).

[0052] In each of the first transistor Q1 and the second transistor Q2, the ratio of the length a in the X direction of the second region 102a, the length b in the X direction of the second region 102b, and the length c in the X direction of the first region 101 is 1:1:7. The area of ​​the first region 101 is 5.5 times the area of ​​the second region 102a and 5.5 times the area of ​​the second region 102b.

[0053] In the semiconductor device of this embodiment, the ratio N:P in the first region 101 is 5:1, and the ratio N:P in the second region 102a and the second region 102b is 2.5:1. That is, in the semiconductor device of the embodiment, the ratio of the area P of the carrier extraction layer 15 to the area N of the source layer 14 in the second region 102 is made larger than the ratio of the area P of the carrier extraction layer 15 to the area N of the source layer 14 in the first region 101.

[0054] As can be seen from the results in Figure 7, the semiconductor device of the embodiment is able to achieve both reduced on-resistance and increased second breakdown voltage capability, compared to the comparative example in which the N:P ratio is the same in the first region 101 and the second region 102.

[0055] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0056] 1...semiconductor device, 10...semiconductor portion, 11...drain layer, 12...drift layer (first semiconductor layer), 13...base layer (second semiconductor layer), 14...source layer (third semiconductor layer), 15...carrier extraction layer (fourth semiconductor layer), 20...gate electrode, 21...gate wiring, 31...insulating film, 51...first portion, 52...second portion, 53...third portion, 61...common electrode, 62...upper electrode, 62a...first source electrode, 62b...second source electrode, 100...termination, 101...first region, 102...second region, 110...corner portion, 200...wiring substrate, Q1...first transistor, Q2...second transistor, Tr...parasitic transistor

Claims

1. a semiconductor section having an end, a first region, and a second region located between the first region and the end, the semiconductor section having a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, a third semiconductor layer of the first conductivity type provided on the second semiconductor layer, and a fourth semiconductor layer of a second conductivity type provided on the second semiconductor layer and having a higher second conductivity type impurity concentration than the second semiconductor layer, wherein a ratio of an area of ​​the fourth semiconductor layer to an area of ​​the third semiconductor layer in the second region is greater than a ratio of an area of ​​the fourth semiconductor layer to an area of ​​the third semiconductor layer in the first region; a gate electrode provided in the semiconductor portion and having a side surface facing the second semiconductor layer; an insulating film provided between the side surface of the gate electrode and the semiconductor portion; an upper electrode provided on the semiconductor portion and in contact with the third semiconductor layer and the fourth semiconductor layer; Equipped with the fourth semiconductor layer has a first portion disposed in the first region, a second portion disposed in the second region, and a third portion disposed in the second region and connecting the first portion and the second portion; a width of the second portion and a width of the third portion are greater than a width of the first portion; the gate electrodes and the third portions are alternately arranged in a second direction intersecting a first direction in which the gate electrodes extend, A semiconductor device in which a length in the second direction of a region in which the plurality of third portions are aligned in the second direction via the gate electrode is longer as the region approaches a corner portion of the semiconductor portion.

2. The semiconductor device according to claim 1 , wherein the first region is larger than the second region.

3. Further comprising a common electrode, a first gate pad, and a second gate pad; the upper electrode has a first source electrode and a second source electrode disposed on the semiconductor portion and separated from each other; the first gate pad is connected to the gate electrode of the first transistor region in which the first source electrode is disposed; the second gate pad is connected to the gate electrode of the second transistor region in which the second source electrode is disposed; 3 . The semiconductor device according to claim 1 , wherein the common electrode is provided on the lower surface of the semiconductor portion in common to both the first transistor region and the second transistor region.

4. a ratio of an area of ​​the third semiconductor layer to an area of ​​the fourth semiconductor layer in the first region is 5:1; The semiconductor device according to claim 1 , wherein a ratio of an area of ​​the third semiconductor layer to an area of ​​the fourth semiconductor layer in the second region is 2.5:1.

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