System and method for identifying a semiconductor switch in a non-switching state - Patents.com

Abstract

A system and method for identifying a semiconductor switch in a non-switching state is provided. The system includes a first acquisition component, a second acquisition component, and a determination unit. The first acquisition component is configured to acquire a profile of an electrical variable of a first semiconductor switch driven by a first drive signal. The second acquisition component is configured to acquire a profile of an electrical variable of a second semiconductor switch driven by a second drive signal and connected in parallel with the first semiconductor switch. The determination unit is configured to use the profile of the electrical variable of the first semiconductor switch and the profile of the electrical variable of the second semiconductor switch as criteria for determining an output signal that enables identification of the first semiconductor switch and / or the second semiconductor switch in a non-switching state.

Description

Detailed Description

[0001] The present invention relates generally to identifying a non-switching semiconductor switch from semiconductor switches connected in parallel, and more particularly to a system and method for identifying a non-switching semiconductor switch from at least two semiconductor switches connected in parallel.

[0002] In electronic power distributors, especially those with high demands on functional safety, it is particularly important to be able to know, as far as possible, the state of health (SoH) of the power semiconductors used. For this, it is important to know whether the power semiconductor acting as a switch can reliably switch, in particular switch off, in all operational situations. If this is not possible, the only feasible solution is to connect a second power semiconductor in series with the power semiconductor in question. This, however, increases the costs, the space required and the power losses of the channel. Furthermore, connecting a second power semiconductor in series only statistically reduces the probability of failure. The successful switching operation of the semiconductor can only be actually checked and / or diagnosed by switching it off.

[0003] DE 4301605 C1 discloses a method and an assembly for monitoring the switching on and off of a controllable power semiconductor component in a power electronic circuit. In the case of a control signal for switching on the power semiconductor component, a count signal is generated by a level change of the signal supplied to the gate electrode, which level change occurs at the output electrode during switching of the power semiconductor component. The count signal is summed in a first counter and compared with a predefined count value associated with the correct operation of the power semiconductor component. If there is a difference between the sum of the count signals and the predefined count value, a fault signal is indicated.

[0004] Such a method and the associated assembly have the disadvantage that they are only functional at least when the switch is switched continuously. In static operation, the system cannot directly diagnose faults. The method and assembly of DE 4301605 C1 are therefore not sufficiently reliable to identify faults, especially in static operation.

[0005] There is therefore a need for a reliable and accurate identification of semiconductor switches in a non-switching state, in particular without the need to switch off the associated load.

[0006] According to a first aspect of the present invention, there is provided a system for identifying a semiconductor switch in a non-switching state, the system comprising a first acquisition component, a second acquisition component and a decision unit, the first acquisition component configured to acquire a profile of an electrical variable of a first semiconductor switch controlled by a first control signal, the second acquisition component configured to acquire a profile of an electrical variable of a second semiconductor switch controlled by a second control signal and connected in parallel with the first semiconductor switch, the decision unit configured to use the profile of the electrical variable of the first semiconductor switch and the profile of the electrical variable of the second semiconductor switch as criteria for determining an output signal from the first semiconductor switch and / or the second semiconductor switch that allows or enables the identification of a semiconductor switch in a non-switching state.

[0007] In other words, the decision unit is configured to use the profile (over time) of the electrical variable of the first semiconductor switch and the profile (over time) of the electrical variable of the second semiconductor switch as a decision criterion for an output signal that allows or enables identifying a fault in the switching of the first semiconductor switch and / or the switching of the second semiconductor switch. The identification system for semiconductor switches in a non-switching state may therefore alternatively be referred to as an identification system for faults in the switching of semiconductor switches. The faults may be identified manually, for example by taking into account the determined output signal or a signal derived from the determined output signal. Alternatively, the faults may be identified in an automated manner by an identification component based on the determined output signal or a signal derived from the determined output signal.

[0008] The electrical variable may be a current, a voltage, an electrical resistance and / or a power. The profile is in particular a time profile.

[0009] The first semiconductor switch is capable of assuming an open / open switching state and a closed switching state. The first semiconductor switch can be moved from the open switching state to the closed switching state and vice versa by a first control signal. The second semiconductor switch is capable of assuming an open / open switching state and a closed switching state. The second semiconductor switch can be moved from the open switching state to the closed switching state and vice versa by a second control signal.

[0010] The first and / or second semiconductor switch may be part of a system or may be monitored by the system as a component that can be considered separate from the system, in other words, the system may have the first and / or second semiconductor switch or may monitor the first and / or second semiconductor switch as an external unit.

[0011] Although the present application describes a first and a second semiconductor switch, the present invention is not limited to identifying a semiconductor switch in a non-switching state from just two semiconductor switches connected in parallel. For example, more than two semiconductor switches may be connected in parallel. In other words, according to a first aspect of the present invention, there is provided a system for identifying a semiconductor switch in a non-switching state from at least two semiconductor switches connected in parallel.

[0012] For example, the first, second and at least third semiconductor switches may be connected in parallel with each other. In this case, the system can identify the semiconductor switches in a non-switching state from the first, second and at least third semiconductor switches. The first and / or second and / or at least third semiconductor switches may be part of the system or may be monitored by the system as a component that can be considered separate from the system. In other words, the system may have the first and / or second and / or at least third semiconductor switches or may monitor the first and / or second and / or at least third semiconductor switches as an external unit.

[0013] At least one third semiconductor switch may ensure a kind of emergency operation in case the first and / or second semiconductor switch can no longer transition from the open to the closed state. Without the at least third semiconductor switch, the load would be switched off at least briefly in the above mentioned cases.

[0014] The system can be part of an electrical power distribution system, for example one with high requirements regarding functional safety and / or reliability. In electrical power distribution systems in general, and particularly in those with high safety requirements, it is important to be able to identify and / or verify the functionality of the semiconductor switches used during operation, preferably without any particular adverse effects on the loads connected downstream of the semiconductor switches.

[0015] The first acquisition component may comprise or take the form of a first measurement amplifier. The first measurement amplifier may be configured, for example, to determine the profile of the current passing through a first current sense resistor connected in series with the first semiconductor switch as the profile of the electrical variable of the first semiconductor switch. The first measurement amplifier may be configured, for example, as a voltage measurement device to determine the profile of the voltage drop through a first current sense resistor connected in series with the first semiconductor switch as the profile of the electrical variable of the first semiconductor switch. From this voltage, the current through the first current sense resistor can be derived based on the known resistance value. For example, if the current is measured as the electrical variable or derived from the voltage, the current passing through the first current sense resistor corresponds to the current passing through the first semiconductor switch due to the series connection. For example, if the first semiconductor switch takes the form of a field effect transistor, it corresponds to the drain current passing through the first semiconductor switch.

[0016] The second acquisition component may comprise or may take the form of a second measurement amplifier. The second measurement amplifier may be configured, for example, to determine the profile of the electrical variable of the second semiconductor switch as a profile of the current passing through a second current sense resistor connected in series with the second semiconductor switch. The second measurement amplifier may be configured, for example, as a voltage measurement device to determine the profile of the electrical variable of the second semiconductor switch as a profile of the voltage drop passing through a second current sense resistor connected in series with the second semiconductor switch. From this voltage, the current through the second current sense resistor can be derived based on the known resistance value. For example, if the current is measured as the electrical variable or derived from the voltage, the current passing through the second current sense resistor corresponds to the current passing through the second semiconductor switch due to the series connection. For example, if the second semiconductor switch takes the form of a field effect transistor, it corresponds to the drain current passing through the second semiconductor switch.

[0017] The first and / or second current sense resistor may be in the form of a shunt or may have a shunt. Thus, the first and / or second current sense resistor may be in the form of a low-ohmic electrical measuring resistor with separate current and voltage terminals or may have such a measuring resistor. As an example of the first and / or second measuring amplifier, a voltage measuring device, for example connected in parallel with the shunt, may derive a negligibly small current in most cases.

[0018] The output signal determined by the decision unit may permit or enable the identification of faults during switching of the first semiconductor switch from a closed to an open switching state. Additionally or alternatively, the output signal determined by the decision unit may permit or enable the identification of faults during switching of the second semiconductor switch from a closed to an open switching state. In other words, it is possible to derive from the output signal determined by the decision unit whether the first and / or the second semiconductor switch can (correctly) pass from a closed to an open switching state.

[0019] Furthermore, the output signal determined by the decision unit may permit or enable the identification of faults during switching of the first semiconductor switch from an open switching state to a closed switching state. Additionally or alternatively, the output signal determined by the decision unit may permit or enable the identification of faults during switching of the second semiconductor switch from an open switching state to a closed switching state. In other words, it is possible to derive from the output signal determined by the decision unit whether the first and / or the second semiconductor switch can (correctly) pass from the open switching state to the closed switching state.

[0020] The system may further include an identification component configured to identify a fault in the switching of the first semiconductor switch based on the output signal. Additionally or alternatively, the identification component may be configured to identify a fault in the switching of the second semiconductor switch based on the output signal.

[0021] The system may further comprise a time delay element, also referred to herein for short as a delay element. The delay element may be configured to define a fault signal by combining the output signal with a switch-on delay. With the delay element, inaccurate diagnoses caused by signal propagation times and switching delays are at least reduced, if not completely prevented.

[0022] The decision unit may comprise a first comparison component and a second comparison component. The first comparison component may be configured to determine a first comparison profile for the electrical variable of the first semiconductor switch using a reference value or a profile of reference values. The comparison profile may for example be determined by comparing the profile of the electrical variable of the first semiconductor switch with an average profile of the profile of the electrical variable of the first semiconductor switch and the profile of the electrical variable of the second semiconductor switch. The second comparison component may be configured to determine a second comparison profile for the electrical variable of the second semiconductor switch using the reference value or the reference value profile. The second comparison profile may for example be determined by comparing the profile of the electrical variable of the second semiconductor switch with an average profile of the profile of the electrical variable of the first semiconductor switch and the profile of the electrical variable of the second semiconductor switch.

[0023] The first comparison component may include a comparator. Alternatively, the first comparison component may be configured as a comparator. The second comparison component may include a comparator. Alternatively, the second comparison component may be configured as a comparator. A comparator is also called an operational amplifier.

[0024] The decision unit may have a first logic component, a second logic component, and a third logic component. The first logic component may be configured to determine a first logic signal by combining the first comparison profile with a first control signal. The second logic component may be configured to determine a second logic signal by combining the second comparison profile with a second control signal. The third logic component may be configured to determine an output signal by combining the first logic signal with the second logic signal.

[0025] The first logic component may be an exclusive OR gate (XOR gate). Additionally or alternatively, the second logic component may be an XOR gate. Additionally or alternatively, the third logic component may be an OR gate.

[0026] The system may comprise a phase generator. The phase generator may be configured to generate a first control signal. Additionally or alternatively, the phase generator may be configured to generate a second control signal. As a result, the phase generator may be configured to ensure that at least one of the parallel connected semiconductor switches, i.e. one of the first semiconductor switch and the second semiconductor switch, and optionally at least one further semiconductor switch, is switched on.

[0027] The first semiconductor switch may take the form of a power semiconductor or a power semiconductor switch. Additionally or alternatively, the second semiconductor switch may take the form of a power semiconductor or a power semiconductor switch. The system may be integrated into a power distributor that is a complete system, for example it may be part of the power distributor of the complete system. The complete system may have a current source (power source) and at least one consumer. The power distributor may be arranged between the current source and the at least one consumer. The power distributor may distribute the current provided by the current source to the at least one consumer. The first semiconductor switch and / or the second semiconductor switch may be arranged in the power distributor such that the at least one consumer can be switched on (connected to the current source) or off (disconnected from the current source).

[0028] According to a second aspect of the present invention, a method for identifying a semiconductor switch in a non-switching state is provided. The method comprises obtaining a profile of an electrical variable for a first semiconductor switch controlled by a first control signal. The method further comprises obtaining a profile of an electrical variable for a second semiconductor switch controlled by a second control signal and connected in parallel with the first semiconductor switch. The method further comprises determining an output signal based on the profile of the electrical variable of the first semiconductor switch and the profile of the electrical variable of the second semiconductor switch. The output signal may allow or enable identification of a semiconductor switch in a non-switching state (a semiconductor switch in a non-switching state from the first semiconductor switch and / or the second semiconductor switch) being the first semiconductor switch and / or the second semiconductor switch. In other words, the output signal may allow or enable identification of a fault in switching of the first semiconductor switch and / or the second semiconductor switch. In other words, a fault in switching of the first semiconductor switch and / or the second semiconductor switch can be derived from the output signal. The faults can be derived from the output signal, for example, in an automated manner or manually.

[0029] The present disclosure is further described with reference to the drawings, which are shown in schematic form. [Brief description of the drawings]

[0030] [Figure 1] A complete system includes a current source, a power distributor and an electrical consumer. [Diagram 2] This is a possible configuration for the power splitter in FIG. [Diagram 3] 3 is a possible configuration of a switching system according to an example embodiment that can be used in the power splitter of FIG. 2. [Figure 4a] 4 is an exemplary signal profile of an electrical variable used in the system of FIG. 3. [Figure 4b] 4 is an exemplary signal profile of an electrical variable used in the system of FIG. 3. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] Specific details are described in the following text for the purpose of providing a thorough understanding of the present disclosure, without being limiting thereto. However, it will be apparent to those skilled in the art that the present disclosure can be used in other exemplary embodiments that differ from the details described below. For example, although a specific configuration and method of the system is described in the following text, this should not be considered limiting.

[0032] FIG. 1 shows in diagrammatic form a power distribution system comprising a current source 10, a power distributor 20 and an electrical consumer 40. The current source 10 has a positive terminal 12 and a negative terminal 14. The power distributor 20 has a positive terminal 22 and a negative terminal 26 on the input side. The power distributor 20 further has a positive terminal 24 on the output side. The power distributor 20 comprises a switching system 30 by means of which the consumer 40 can be switched on or off. The switching system 30 comprises a controller 28, which may be a higher order controller. The electrical consumer 40 has a positive terminal 42 and a negative terminal 44.

[0033] The negative terminal 14 of the current source 10, the negative terminal 26 of the power distributor 20 and the negative terminal 44 of the consumer 40 are each connected to earth / ground 50. Thus, in this case the reference potentials of the current source 10, the power distributor 20 and the consumer 40 are the same, e.g. ground / earth 50.

[0034] The current source 10 is connected via its positive terminal 12 to a positive terminal 22 at the input side of a power distributor 20. The power distributor 20 is connected at its output side via a positive terminal 24 to an electricity consumer 40. Although only one consumer 40 is shown by way of example, for example several electricity consumers 40 may be connected to the power distributor 20 via further positive terminals, not shown in FIG. 1 , at the output side of the power distributor 20. The switching system 30 is configured to switch the electricity consumer 40 on and off. In case of several electricity consumers, the system is likewise configured to switch each of the several electricity consumers on and off. To this end, one or more such switching systems may be provided. In case of failure to switch off, the switching system 30 provides a corresponding fault message to the controller 28. The power distribution system may in particular be a power distribution system with high demands with regard to safety (and / or with regard to reliability). In such a system, it is particularly important to be able to verify the functionality of the switches used (to switch the consumers 40 on and off).

[0035] FIG. 2 shows an exemplary configuration of the power splitter 20 from FIG. 1, which has a positive terminal 22 on the input side. The power splitter 20 further has a positive terminal 24 on the output side. The power splitter further comprises a controller 28. The negative terminal of the power splitter from FIG. 1 is not shown in FIG. 2 for the sake of simplicity. FIG. 2 shows an exemplary configuration of the switching system 30 from FIG. 1. According to this example, the switching system 30 comprises a phase generator 32, a first semiconductor switch 34a, a second semiconductor switch 34b and a comparator 38. The first semiconductor switch 34a and the second semiconductor switch 34b serve to switch an electrical consumer 40 on or off. In particular, the switch-off function is to be monitored for reliability. The first semiconductor switch 34a and the second semiconductor switch 34b are connected in parallel with each other.

[0036] The phase generator 32 controls the first semiconductor switch 34a and the second semiconductor switch 34b, for example, by using a control signal generated for each situation. The first acquisition component can acquire a profile of an electric variable of the first semiconductor switch 34a controlled by using the first control signal. The second acquisition component can acquire a profile of an electric variable of the second semiconductor switch 34b controlled by using the second control signal. The electric variable can be, for example, a current or a voltage. The first and / or second acquisition components can be, for example, part of the comparator 38 as shown in FIG. 2. That is, according to FIG. 2, the comparator 38 can have the first and / or second acquisition components. Alternatively, the first and / or second acquisition components can be configured and arranged in the manner of a device separate from the comparator 38.

[0037] The comparator 38, as an example of a decision unit, can determine an output signal based on a profile of the electrical variable of the first semiconductor switch 34a and on a profile of the electrical variable of the second semiconductor switch 34b. The output signal can allow or enable the identification of a fault in the switching of the first semiconductor switch 34a and / or the second semiconductor switch 34b. In other words, the output signals obtained of the first semiconductor switch 34a and the second semiconductor switch 34b are compared with each other in the comparator 38. From the output signals of the first and second semiconductor switches, the comparator 38 generates a comparison signal as an output signal. From such a comparison signal it can be inferred whether the first semiconductor switch 34a and / or the second semiconductor switch 34b actually switches as intended, in particular whether it switches off or is switched off as intended. If a switching fault, in particular a fault relating to switching off, is detected, the controller 28 is informed, for example. The controller 28, as a higher level entity, may for example take countermeasures such as switching off the power consumer 40 itself, disconnecting it from the power distributor 20 or moving the consumer 40 to a safer state.

[0038] FIG. 3 shows a specific configuration of the switching system 30, more precisely, a circuit that may be implemented in hardware. The switching system 30 includes a phase generator 32. The phase generator 32 is configured to generate a first control signal V_phase1 and a second control signal V_phase2. The first control signal V_phase1 is input to a first gate driver 62a. The second control signal V_phase2 is input to a second gate driver 62b. The first gate driver 62a is connected to a gate terminal of the first semiconductor switch 34a, and in the example of FIG. 3, takes the form of a first MOSFET 34a, and is therefore referred to as a first MOSFET 34a in the following description. The second gate driver 62b is connected to a gate terminal of the second semiconductor switch 34b, and in the example of FIG. 3, takes the form of a MOSFET 34b, and is therefore referred to as a second MOSFET 34b. The source terminal of the first MOSFET 34a is connected to ground / earth via a variable resistor, which in the circuit of FIG. 3 represents the load 40 in FIG. 1 and is therefore similarly referenced 40. The source terminal of the second MOSFET 34b is connected to ground / earth via a variable resistor. The drain terminal of the first MOSFET 34a is connected to a first current sense resistor 64a. The first MOSFET 34a and the first current sense resistor 64a are connected in series with each other. The drain terminal of the second MOSFET 34b is connected to a second current sense resistor 64b. The second MOSFET 34b and the second current sense resistor 64b are connected in series with each other. The current I1 is generated via a ground voltage source 10. The voltage source 10 may correspond to the current source 10 in FIG. 1 and is therefore indicated with the reference number 10 in FIG. 3.

[0039] The first measurement amplifier 66a and the second measurement amplifier 66b in FIG. 3 can be considered as specific implementations of the first acquisition component and the second acquisition component (e.g., in FIG. 2). The first measurement amplifier 66a is configured to acquire an electrical variable at the first current sense resistor 64a. For example, the first measurement amplifier 66a can be configured to acquire a voltage at the first current sense resistor 64a. Additionally or alternatively, the first measurement amplifier 66a can be configured to acquire a current through the first current sense resistor 64a. The second measurement amplifier 66b is configured to acquire an electrical variable at the second current sense resistor 64b. For example, the second measurement amplifier 66b can be configured to acquire a voltage at the second current sense resistor 64b. Additionally or alternatively, the second measurement amplifier 66b can be configured to acquire a current through the second current sense resistor 64b.

[0040] The first and second measurement amplifiers 66a, 66b input their acquired or measured values ​​to an averager 68. Furthermore, the profile of the electrical variable measured by the first measurement amplifier 66a is input to a positive (non-inverting) input of a first comparator 70a, which will be referred to hereinafter as op-amp 70a. Furthermore, the profile of the electrical variable measured by the second measurement amplifier 66b is input to a positive (non-inverting) input of a second comparator 70b, which will be referred to hereinafter as op-amp 70b. Both the negative (inverting) input of the first op-amp 70a and the negative (inverting) input of the second op-amp 70b are provided by the averager 68.

[0041] In the example shown in FIG. 3, the operational amplifiers 70a, 70b are configured as non-inverting operational amplifiers (non-inverting comparators). In such a non-inverting operational amplifier, a reference voltage, i.e. the average in the case of FIG. 3, can be connected to the inverting input of the operational amplifier. An input signal, here the respective profile of the electrical variable of the semiconductor switches 34a, 34b from the measurement amplifiers 66a, 66b, can be connected to the non-inverting input of each individual operational amplifier. In the non-inverting operational amplifier, if the input voltage is less than the reference voltage, a digital 0 (LOW level) is output as an output signal. On the other hand, if the input voltage is equal to or greater than the reference voltage, a digital 1 (HIGH level) is output. Alternatively, it would be possible to provide an inverting operational amplifier in FIG. 3.

[0042] The output of the first operational amplifier 70a is connected to the first XOR gate 72a. Thus, the first XOR gate 72a receives the output signal V_comp1 of the first operational amplifier 70a as a first input variable. The output of the second operational amplifier 70b is connected to the second XOR gate 72b. Thus, the second XOR gate 72b receives the output signal V_comp2 of the second operational amplifier 70b as a first input variable. The first XOR gate 72a receives the first control signal V_phase1 as a second input variable. The second XOR gate 72b receives the second control signal V_phase2 as a second input variable. Accordingly, the first XOR gate 72a performs an XOR operation between the output (signal V_comp1) of the first operational amplifier 70a and the first control signal V_phase1. Accordingly, the second XOR gate 72b performs an XOR operation on the output (signal V_comp2) of the second operational amplifier 70b and the second control signal V_phase2.

[0043] The outputs of the first XOR gate 72a (signal V_out1) and the second XOR gate 72b (signal V_out2) are input as input variables to the OR gate 74. Thus, the output of the OR gate 74 is an overlay of the outputs of the first and second XOR gates 72a, 72b.

[0044] Problems or faults in the switching of the first MOSFET 34a and / or the second MOSFET 34b can be inferred from the output signal of the OR gate (signal V_out3).

[0045] The discrimination of faults can be improved by connecting a time delay element 76 after the OR gate 74. This is achieved by ignoring so-called spikes (spikes can be understood as short peaks, i.e. peaks whose duration is less than a predefined time threshold) by the time delay element 76. The time delay element 76 will only identify as faults those anomalies with a duration exceeding a predefined time threshold. The signal output by the time delay element 76 can therefore be called the fault signal V_fehler. In other words, the time delay element 76 can be called a switch-on delayer that infers only fault signals above a certain length as valid, i.e. as real or valid fault signals.

[0046] Referring to Fig. 3, the comparator according to Fig. 2 can be embodied, for example, by the measurement amplifiers 66a, 66b, the averager 68, the operational amplifiers 70a, 70b, the XOR gates 72a, 72b, and the OR gate 74 in Fig. 3. Alternative implementations are possible that omit or replace one or more of the above-mentioned components and / or add further components. It should therefore be understood that Fig. 3 is only one example of a hardware implementation of the switching system of Fig. 2.

[0047] The operation of the arrangement of Fig. 3 will now be described in more detail with reference to the exemplary signal profiles of Fig. 4a and Fig. 4b. In Fig. 4a and Fig. 4b, the signal profile is shown over time for each case. The vertical axis of each case represents a respective electrical variable, e.g. current or voltage, and the horizontal axis represents time. The horizontal axis is divided into a number of regions, more specifically nine regions, referred to herein as time slots Z1 to Z9.

[0048] In this example, the two MOSFETs 34a, 34b are configured as self-locking n-channel MOSFETs, so they are closed and conduct current when the voltage between their gate and source exceeds a threshold, which in each case is less than 5V, obtained as the maximum value of the control signals V_phase1, V_phase2 in Figures 4a and 4b.

[0049] As can be seen in relation to the exemplary signal profiles of Figures 4a and 4b, the two control signals V_phase1, V_phase2 start at the first time slot Z1 with a value of about 5V, which corresponds to a high level, also referred to as HIGH (digital 1). Due to the high level of the control signals V_phase1, V_phase2, a voltage exceeding the threshold of the MOSFETs 34a, 34b is generated between the gate and source of the first MOSFET 34a and between the gate and source of the second MOSFET 34b. Thus, both MOSFETs 34a, 34b are in a closed state.

[0050] In the exemplary configuration of FIG. 3, the total resistance of the first current sense resistor 64a and the first MOSFET 34a is at least approximately exactly matched to the total resistance of the second current sense resistor 64b and the second MOSFET 34b. Therefore, when both MOSFETs 34a, 34b are closed, the current I1 is at least approximately equally distributed across the parallel circuit of the two MOSFETs 34a, 34b. Thus, at least about I1 / 2 flows through both branches of the circuit. The first measurement amplifier 66a can measure, for example, directly, the current through the first current sense resistor 64a. The second measurement amplifier 66b can measure, for example, directly, the current through the second current sense resistor 64b. Alternatively, the first measurement amplifier 66a can measure the voltage drop across the first current sense resistor 64a. Additionally, the second measurement amplifier 66b can measure the voltage drop across the second current sense resistor 64b. Regardless of the measurement method, the first measurement amplifier 66a and the second measurement amplifier 66b measure electrical variables that are at least approximately equal when both the first MOSFET 34a and the second MOSFET 34b are closed.

[0051] Some time later, the first control signal V_phase1 transitions to a timed Vlow in the first time slot Z1. During the period of 1, the voltage is set to approximately 0V. This is the low level also called the LOW level (digital 0). In this case, the voltage generated between the gate and source of the first MOSFET 34a is If any exists, it is very low and is below the threshold of the first MOSFET 34a. As a result, the MOSFET 34a changes to an open state. During this period, the second control signal V_phase2 remains at a HIGH level. Therefore, the second MOSFET The first MOSFET 34a is turned on during the first time slot Z1. The second MOSFET 34b is open during the first time slot Z1. Therefore, the second branch of the parallel circuit of the two MOSFETs is closed. At least almost the entire current I1 flows through the side where the MOSFET 34b is installed. Therefore, the first measurement amplifier 6 6 a is an electrical variable that has a value of at least approximately 0. 2, measuring amplifier 6 6 b is at the same time at least equal to the current I1 or the product of the current I1 and the current sense resistor 64b. The first measuring amplifier 6 determines a value that is approximately equal to the average. 6 a is , and measure an electrical variable having a value of at least approximately 0 during the same time period Vlow1.

[0052] The second control signal is low during the time period Vlow2, in the second time slot Z2. In this case, the gate of the second MOSFET 34b is switched to a LOW level (digital 0). The voltage developed between the source and the second MO is very low, if at all. The second time, the threshold voltage of MOSFET 34b drops below the threshold voltage of MOSFET 34b. Therefore, MOSFET 34b transitions to an open state. During the same time period Vlow2 in lot Z2, the first control signal V_phase1 is at a HIGH level. Therefore, the first MOSFET 34a is closed. The first MOSFET 34a is connected to the second time slot. The second MOSFET 34b is closed during the second time slot Z2. The time limit Vlow2 is open. Therefore, the branch of the parallel circuit of two MOSFETs At least almost the entire current I1 flows through the side where the first MOSFET 34a is installed. Therefore, the first measurement amplifier 6 6 a is the current I1 or the product of the current I1 and the current sense resistor 64a Measure an electrical variable that is at least approximately equal to , which is twice the average. Second measuring amplifier 6 6 b is the electrical variable measured to have a value of at least approximately 0 during the same time period Vlow2 do.

[0053] When the first MOSFET 34a and the second MOSFET 34b are in the closed state, as explained, the two measurement amplifiers 66a, 66b measure at least approximately equal values ​​for the measured electrical variables. The averager 68 forms an average from the measured variables. In the case of equal values, the average of the electrical variables corresponds at least approximately to the measured value itself. For this reason, the operational amplifier 70a does not determine the difference between the variable V_cs1 measured by the first measurement amplifier 66a and the average V_avg obtained from the averager 68, and therefore outputs a HIGH level (a1). Furthermore, the operational amplifier 70b does not determine the difference between the variable V_cs2 measured by the second measurement amplifier 66b and the average V_avg from the averager 68, and accordingly outputs a HIGH level (a1).

[0054] When the first MOSFET 34a is open and the second MOSFET 34b is closed (see, for example, the time period Vlow1 in the first time slot Z1 and the third time slot Z3), the first measurement amplifier 66a measures a minimum value 0 and the second measurement amplifier 66b measures a maximum value. The averager 68 forms an average from the measured variables. Thus, the first operational amplifier 70a determines that the value of the electrical output variable V_cs1 of the first measurement amplifier 66a is below the average and accordingly outputs a LOW level (digital 0). Furthermore, the operational amplifier 70b determines that the value of the electrical output variable V_cs2 of the second measurement amplifier 66b is not below the average obtained from the averager 68 and accordingly outputs a HIGH level (a 1) (see signal V_comp1).

[0055] When the first MOSFET 34a is closed and the second MOSFET 34b is open (see, for example, the time period Vlow2 in the second time slot Z2 and the fourth time slot Z4), the first measurement amplifier 66a measures a maximum value and the second measurement amplifier 66b measures a minimum value 0. The averager 68 calculates an average from the measured variables. The operational amplifier 70a therefore determines that the value of the electrical output variable V_cs1 of the first measurement amplifier 66a is not below the average and accordingly outputs a HIGH level (digital 1). Furthermore, the operational amplifier 70b determines that the value of the electrical output variable V_cs2 of the second measurement amplifier 66b is below the average value obtained from the averager 68 and accordingly outputs a LOW level (digital 0) (see signal V_comp2).

[0056] Thus, when the first MOSFET 34a is open, a double peak due to the propagation time delay and / or switching delay is obtained as the output variable V_out1 of the first XOR gate 72a at approximately the time level when the first control signal V_phase1 is at the LOW level, i.e., approximately at the timed Vlow1 level in the first time slot Z1 and the third time slot Z3. Thus, when the second MOSFET 34b is open, a double peak is obtained as the output variable V_out2 of the second XOR gate 72b at approximately the time level when the second control signal V_phase2 is at the LOW level, i.e., approximately at the timed Vlow2 level in the second time slot Z2 and the fourth time slot Z4 (similarly, the sixth time slot Z6 and the eighth time slot Z8). The outputs of the first XOR gate 72a and the second XOR gate 72b are input to the OR gate 74 as input variables. The output of the OR gate 74 is therefore an overlay of the outputs of the first XOR gate 72a and the second XOR gate 72b. The output signal V_out3 of the OR gate 74 therefore exhibits double peaks, each of which represents the opening of the first or second MOSFET 34a, 34b in the first time slot Z1 through the fourth time slot Z4 (as well as the sixth time slot Z6 and the eighth time slot Z8).

[0057] As an example, the fifth time slot Z5, the seventh time slot Z7, and the ninth time slot In lot Z9, the first control signal V_phase1 is at a LOW level during the time period Vlow1, but the second control signal V_phase2 is at a LOW level during the time period Vlow2. Assuming that MOSFET 34a does not open properly, MOSFET 34a will open in the fifth time slot. Z5, remains closed in the seventh time slot Z7 and the ninth time slot Z9 As explained above, the current I1 in this case flows at least approximately through the parallel circuit of the MOSFETs 34a and 34b. Therefore, the current that is at least about I1 / 2 flows through both MOSFETs 34a and 34b. current flows through each of the current sense resistors 64a, 64b. Therefore, the measurement amplifiers 66a, 66b measure values ​​that are at least approximately equal. The two operational amplifiers 70a, 70b determine the difference between the measurements of the measurement amplifiers 66a, 66b and the average value. Therefore, the fifth time slot Z5, the seventh time slot Z7 and the ninth time slot In the Z9th time slot, the two operational amplifiers 70a and 70b output the signals V_comp1 and V_co mp2 is output at a HIGH level. Therefore, the first control signal V_phase1 is used XOR Game R According to the XOR operation that is the output of 72a, the time period Vlow1 of the fifth time slot Z5 (V_out1) The middle is almost a (uniform) HIGH level and does not have a double peak. The second one using se2 XOR Gate The output of the XOR operation of 72b becomes a LOW level (V_out2). Therefore, by ORing the outputs of the two XOR gates 72a and 72b, the fifth time In slot Z5, the seventh time slot Z7 and the ninth time slot Z9, (a single ) Peak (5th time slot Z5, 7th time slot Z7 and 9th time slot (which is at least close to the level at time limit Vlow1 in time limit Z9). The propagation time of the output signal (V_out3) of the gate 74 (which has a smaller width at each peak) Such a single peak (rather than a double peak due to delay and / or switching delay) A peak indicates a disorder.

[0058] The discrimination of faults can be improved by connecting a time delay, sometimes referred to as time delay element 76 in the following description, after the OR gate 74. The time delay means that only peaks whose duration exceeds a predefined time threshold are discriminated as faults. The duration of the double peaks in the first time slot Z1 to the fourth time slot Z4 (as well as in the sixth time slot Z6 and the eighth time slot Z8) is in each case below the time threshold. The output of the time delay element 76 therefore outputs a LOW level (see signal V_fehler). On the other hand, the duration of the peaks in the fifth time slot Z5, the seventh time slot Z7 and the ninth time slot Z9 exceeds the time threshold. The time delay element 76 therefore outputs a HIGH level (see signal V_fehler) during certain times in the fifth time slot Z5, the seventh time slot Z7 and the ninth time slot Z9.

[0059] Depending on the particular implementation of the time delay, the time delay element 76 may take the configuration of a switch-on delay or may perform a switch-on delay. In this case, the time delay element 76 may, for example, perform a time-delayed switch-on or a switch-on with a time delay. The time delay may at least correspond to or exceed the magnitude (in terms of time) of one of the double pulses of the signals Vout1, Vout2, Vout3. As a result, each pulse of these double pulses is eliminated or weakened and only longer pulses (i.e. pulses with a width larger than the time delay width or larger than the width of each peak of the double peak) are output, in each case shortened by the time delay value in the fault signal V_fehler. This can be seen by FIG. 4b, where the effective fault signal V_fehler is shown. In the signal V_fehler, the rising edge of the fault pulse is always shifted or shortened with respect to the rising edge of the long peak, for example by the length of the switch-on delay in the signal Vout3 (i.e. shortened by at least the pulse width of the double pulse or double peak). On the other hand, the falling edge of the pulse of the fault signal V_fehler falls simultaneously with the corresponding pulse of the signal Vout3, since there is only a switch-on delay and not a switch-off delay. This concerns all time slots with faults, i.e. Z5, Z7 and Z9. On the other hand, the ripple of each double pulse is suppressed by the switch-on delay. These are not the final real or effective fault pulses.

[0060] As a result, the output signal V_fehler of the time delay element 76 is 3 4a, 3 One switch of 4b The signal will only show a peak if there is a fault in the signal path. Meanwhile, the propagation time delay is suppressed. Therefore, the output of the time delay circuit 76 can be called the fault signal V_fehler. The peaks of the fault signal V_fehler can be automatically identified by the peaks and the control signal Based on this, the discrimination circuit determines which of the two MOSFETs 34a, 34b is not switching correctly. Therefore, the fault can be identified quickly. Instead, switch out the component in question or use another method to resolve the fault. This allows for rapid response.

[0061] Figures 3, 4a and 4b can be summarised as follows: In the circuit shown in Figure 3, two power semiconductors (MOSFETs) 34a, 34b are connected in parallel with each other with a current sense resistor (shunt) 64a, 64b on each side. The two power semiconductors 34a, 34b are alternately switched off and on by a logic device. In an ideal state (no faults), at least one power semiconductor 34a, 34b is always on. The current flowing through each of the two parallel paths via the two shunts 64a, 64b is measured via current measuring amplifiers 66a, 66b for each path. When both MOSFETs 34a, 34b are on (closed), approximately the same current (half the load current I1 on each side) is measured via both measuring amplifiers 66a, 66b. As soon as one of the two MOSFETs 34a, 34b is switched off, the entire load current I1 flows through one of the two paths, while the other path does not conduct any more current. However, the average of the two currents remains the same. The output signals V_cs1, V_cs2 of the two current measuring amplifiers 66a, 66b are compared with the average value by the two comparators (op-amps) 70a, 70b and converted into digital signals by the comparators 70a, 70b. The signal waveforms of the comparators 70a, 70b therefore correspond approximately to the signal sequences V_phase1, V_phase2 controlling the respective MOSFETs 34a, 34b. By comparing the control signals V_phase1, V_phase2 of the MOSFETs 34a, 34b with the output signals V_comp1, V_comp2 of the respective comparators 70a, 70b using an exclusive OR operation (XOR operation), it is possible to detect whether the MOSFETs 34a, 34b are actually switched off or not. The two XOR signals V_out1, V_out2 from the two MOSFETs 34a, 34b are then combined by an OR operation into a signal V_out3, which is filtered by a switch-on delay 76. The switch-on delay 76 is advantageous in suppressing diagnostic inaccuracies caused by signal propagation times and / or switching delays.As output signal V_fehler, a pulse sequence is obtained which corresponds approximately (albeit shortened) to the control pulses of the defective MOSFETs 34a, 34b. The output signal V_fehler of the switch-on delay 76 may then be read and processed by a higher-order controller (not shown, see controller 28 in FIG. 2), or the pulse sequence may be converted to a fixed value by a recording element (not shown).

[0062] While the description of the exemplary embodiments of Figures 2 to 4b has been given with respect to identifying whether the first semiconductor switch 34a and / or the second semiconductor switch 34b properly transition from a closed state to an open state, it is similarly possible to identify from the signal profile whether the first semiconductor switch 34a and / or the second semiconductor switch 34b properly transition from an open state to a closed state.

[0063] The identification of the non-switching semiconductor switches as the first and / or second semiconductor switches 34a, 34b allows the use of simple and inexpensive components and, in each case, makes it possible to dispense with the series connection of further semiconductor switches for redundancy purposes.

[0064] Although reference is made to a first semiconductor switch 34a and a second semiconductor switch 34b throughout the description of the exemplary embodiments of Figures 2-4b, these exemplary embodiments and the present invention in general are not limited to just two semiconductor switches connected in parallel. More than two semiconductor switches may also be provided. Thus, in summary, at least two semiconductor switches may be provided, and from these at least two semiconductor switches connected in parallel, at least one semiconductor switch in a non-switching state may be identified.

[0065] The advantages of connecting at least a third semiconductor switch in parallel with the first semiconductor switch 34a and the second semiconductor switch 34b will now be explained with reference to Figures 3 to 4b, in which the at least third semiconductor switch is not shown.

[0066] As explained above, in the first time slot Z1, the first semiconductor switch 34a is opened when the first control signal V_phase1 assumes a LOW level at the time period Vlow1. After the time period Vlow1 has elapsed, the first control signal V_phase1 assumes a HIGH level again. In this case, the first semiconductor switch 34a closes again. However, if there is an abnormality in the first semiconductor switch 34a, the first semiconductor switch 34a remains open, i.e. it does not close even if the first control signal V_phase1 assumes a HIGH level again. As explained, the second semiconductor switch 34b is open during the time period Vlow2 in the second time slot Z2, since the second control signal assumes a LOW level during the time period Vlow2. As a result, during the time period Vlow2, the first semiconductor switch 34a is open (because it is no longer closed, even though it should actually be closed) and the second semiconductor switch 34b is also open (because the second control signal V_phase2 assumes a LOW level). Therefore the load is switched off (momentarily) during time period Vlow2 in timeslots Z2, Z4, Z6 and Z8.

[0067] On the other hand, if at least a third semiconductor switch is connected in parallel, this third semiconductor switch, if correctly switched, can realize a kind of emergency operation, since the at least third semiconductor switch assumes the closed state during the time period Vlow2 due to the at least a third control signal assuming a HIGH level during the time period Vlow2, so that the load is not disconnected from the system and the current source and therefore is not switched off.

Claims

1. 1. A system for identifying a semiconductor switch in a non-switching state, the system comprising: a first acquisition device configured to acquire a profile of an electrical variable of a first single semiconductor switch controlled by a first control signal; a second acquisition device configured to acquire a profile of an electrical variable of a second single semiconductor switch controlled by a second control signal and connected in parallel with the first single semiconductor switch; a determining unit configured to use the profile of the electrical variable of the first single semiconductor switch and the profile of the electrical variable of the second single semiconductor switch as a criterion for determining an output signal making it possible to distinguish a semiconductor switch in a non-switching state from the first single semiconductor switch and / or the second single semiconductor switch, the first acquisition device comprises or is configured with a first measurement amplifier, the first measurement amplifier being configured to determine a profile of a current passing through a first current sense resistor connected in series with the first single semiconductor switch as said profile of the electrical variable of the first single semiconductor switch; and / or the second acquisition device comprises or is configured with a second measurement amplifier, the second measurement amplifier being configured to determine, as said profile of the electrical variable of the second single semiconductor switch, a profile of a current passing through a second current sense resistor connected in series with the second single semiconductor switch; The determination unit is a first comparison device configured to determine a first comparison profile by comparing the profile of the electrical variable of a first single semiconductor switch with a profile that is an average of the profile of the electrical variable of the first single semiconductor switch and the profile of the electrical variable of a second single semiconductor switch; a second comparison device configured to determine a second comparison profile by comparing the profile of the electrical variable of the second single semiconductor switch with a profile that is an average of the profile of the electrical variable of the first single semiconductor switch and the profile of the electrical variable of the second single semiconductor switch; The determination unit further a first logic device configured to combine the first comparison profile and the first control signal to define a first logic signal; a second logic device configured to combine the second comparison profile and the second control signal to define a second logic signal; and a third logic device configured to combine the first logic signal and the second logic signal to define the output signal.

2. 2. The system of claim 1, wherein the output signal determined by the determination unit is capable of identifying a fault in switching of a first single semiconductor switch and / or a second single semiconductor switch from a closed state to an open state.

3. 3. The system according to claim 1 or 2, further comprising an identification device configured to identify a fault relating to switching of the first single semiconductor switch and / or the second single semiconductor switch based on the output signal.

4. 4. The system of claim 1, further comprising a delay element configured to define a fault signal by combining the output signal with a switch-on delay.

5. 5. The system of claim 4, The first comparison device comprises or is configured as a comparator, and / or The second comparison device is a system having a comparator or adopting a comparator configuration.

6. A system according to any one of claims 1 to 5, the first logic device is an XOR gate; and / or the second logic device being configured as an XOR gate; and / or The third logic device is a system that employs an OR gate configuration.

7. 7. The system of claim 1, further comprising a phase generator configured to generate the first control signal and / or the second control signal.

8. 8. A system according to claim 1, wherein the first single semiconductor switch and / or the second single semiconductor switch are of the form of a power semiconductor and / or the system further comprises: a first single semiconductor switch; and / or a second single semiconductor switch connected in parallel with the first single semiconductor switch; and / or A system having at least one third semiconductor switch connected in parallel with the first and second semiconductor switches.

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