Power Semiconductor Devices

Abstract

In at least one embodiment, a power semiconductor device (1) comprises: a semiconductor body (2); at least one source region (21) of a first conductivity type; at least one channel region (22) of a second conductivity type below the at least one source region (21); a drift region (23) of the first conductivity type below the at least one channel region (22); and at least one trench (4) extending from a top surface (20) of the semiconductor body (2), through the at least one source region (21) and the at least one channel region (22) and terminating in the drift region (23), wherein the at least one trench (4) accommodates a gate electrode (34); and when viewed in a top view of the top surface (20), the at least one trench (4) comprises a non-linearly extending sidewall (44).

Description

[Technical field]

[0001] A power semiconductor device is provided. [Background technology]

[0002] The following documents refer to the manufacture of SiC power devices: US Pat. No. 10,014,376 B2, US Patent Application Publication No. 2013 / 0062629 A1, and US Patent Application Publication No. 2013 / 0065384 A1.

[0003] The following documents refer to semiconductor devices having trench structures: US Patent Application Publication No. 2016 / 0260798 A1, US Pat. No. 6,060,747 A, WO 2005 / 048352 A1, JP 2009-260650 A, EP 2750198 A1 and WO 2020 / 135378 A1. Summary of the Invention [Problem to be solved by the invention]

[0004] A problem to be solved is to provide a power semiconductor device that has improved current density in the on-state. [Means for solving the problem]

[0005] This aim is achieved inter alia by a power semiconductor device as defined in the independent claims. Further exemplary developments form the subject matter of the dependent claims.

[0006] For example, power semiconductor devices based on wide bandgap materials, illustratively silicon carbide (SiC for short), include trenches with extended sidewall lengths compared to simply straight trenches, which can increase the effective contact area between the trench and the channel region, resulting in a larger effective channel width and lower on-state resistance of the power semiconductor device.

[0007] In at least one embodiment, a power semiconductor device comprises a semiconductor body, at least one source region of a first conductivity type at a top surface of the semiconductor body, at least one channel region of a second conductivity type in the semiconductor body below the at least one source region, a drift region of the first conductivity type in the semiconductor body below the at least one channel region, and at least one trench extending from the top surface through the at least one source region and the at least one channel region and terminating in the drift region. The at least one trench accommodates a gate electrode. When viewed in a top view of the top surface, the at least one trench comprises a non-linearly extending sidewall. Optionally, there is a shield region of the second conductivity type disposed below at least a portion of a bottom surface of the at least one trench, and when viewed in a top view of the top surface, the at least one trench comprises a plurality of branches, the shield region extending fully or partially, for example, below one, some, or all of the branches.

[0008] For example, the semiconductor body may be SiC. However, the semiconductor body may alternatively be Si or Ga. 2 O 3 Or it could be another semiconductor material with a wide bandgap, such as GaN.

[0009] For example, the first conductivity type is n-type and the second conductivity type is p-type. In the following, the description of the embodiment focuses on the aforementioned conductivity types, but it is also possible for the first conductivity type to be p-type and the second conductivity type to be n-type.

[0010] The top surface of the semiconductor body, in the region of the at least one trench, may be planar. There may be only one source region in the semiconductor body, i.e. a contiguous region of the same conductivity type and of the same or nearly the same doping concentration. However, there may also be multiple source regions separated from one another by other parts of the semiconductor body. The same applies analogously to the channel region or multiple channel regions.

[0011] Here and below, the term "source region" can refer to both the source of a field effect transistor as well as the emitter of a bipolar transistor.

[0012] It is possible for only one drift region to extend all the way across the semiconductor body in a direction perpendicular to the growth direction of the semiconductor body. In principle, however, there can be multiple drift regions. In the following examples, for simplicity, only one drift region is explicitly mentioned.

[0013] The maximum doping concentration of the at least one channel region and the at least one drift region may be lower than the maximum doping concentration of the at least one source region.

[0014] Along the growth direction and / or the direction perpendicular to the top surface, the at least one source region, the at least one channel region and the drift region may directly follow one another in that order, however, optionally, at least one buffer layer and / or transition layer may be present intermediate the at least one source region and the at least one channel region and / or the drift region.

[0015] The at least one trench may terminate within the drift region, and thus may not extend completely through the drift region, however, the trench may pass completely through (e.g., in a direction perpendicular to the top surface) at least one source region and at least one channel region.

[0016] A shield region of the second conductivity type may be present at a bottom surface of the trench, and may be coincident with the at least one trench when viewed in a top plan view of the top surface and may be completely embedded between the at least one trench and the drift region.

[0017] According to at least one embodiment, the shielding region extends partially or completely under the central pipe, for example the shielding region applies to at least 50% or 80% of the area of ​​the central pipe when viewed in top plan view on the top surface.

[0018] According to at least one embodiment, the shielding area is limited to the central pipe, i.e., when viewed in top plan view of the top surface, at least one branch is provided with a shielding area of ​​at most 10% or at most 20% of the area of ​​the at least one branch.

[0019] According to at least one embodiment, the shielding region extends partially or completely under the central pipe as well as the at least one branch, for example, the shielding region applies to at least 90% or 95% of the area of ​​the central pipe as well as the at least one branch when viewed in top plan view of the top surface.

[0020] According to at least one embodiment, the shielding area is limited to at least one branch, i.e. the central pipe is provided with a shielding area of ​​at most 10% or at most 20% of the area of ​​the central pipe, and at least one branch is provided with a shielding area of ​​at least 80% or at least 90% of the area of ​​the at least one branch, as viewed in top plan view of the top surface.

[0021] According to at least one embodiment in which multiple branches are present, the shielding area is limited to the branches and at least one area of ​​the central pipe between the respective branches located on either side of the central pipe, in other words, when seen in top view, the shielding area is formed by multiple bars oriented perpendicular to the central pipe, which bars connect two opposite branches.

[0022] According to at least one embodiment in which multiple branches are present, the shielding region is limited to at least one intersection region of a branch and a central pipe, i.e., the intersection region is under an inner corner of the branch of the central pipe, but the sidewalls of the branch and the sidewalls of the central pipe are substantially away from the intersection region, e.g., the shielding region is under at most 20% or at most 10% of the sidewalls of the branch and / or the sidewalls of the central pipe when viewed in top plan view.

[0023] According to at least one embodiment, the shielding region extends only partially under at least some of the branches, such that, when viewed in a top view of the top surface, at least one trench protrudes from the shielding region in place or all around, for example, when viewed in a top view of the top surface, the shielding region comprises at least 50% and / or at most 90% of the area of ​​each of the branches.

[0024] The gate electrode may be entirely contained within at least one trench. Otherwise, the gate electrode may protrude from at least one trench, for example to allow external electrical contact with the gate electrode. There may be exactly one gate electrode per trench. In case of multiple trenches, there may be one individual gate electrode per trench, a common gate electrode for all trenches, or a group of trenches sharing one gate electrode.

[0025] For example, the gate electrode is separated from the semiconductor body by a gate insulator, e.g., SiO 2 , Si 3 N 4 , Al 2 O 3 , Y 2 O 3 , ZrO 2 , HfO 2 , La 2 O 3 , Ta 2 O 5 , TiO 2 At least one of the following materials:

[0026] The sidewall of at least one trench extends non-linearly, which may mean, for example, that the sidewall has a stepped square wave, sawtooth wave or sinusoidal wave profile in the plane defined by the top surface, when viewed in a top view of the top surface. The trench or each of the trenches may have two sidewalls that extend non-linearly. When viewed in a top view of the top surface, the sidewalls may be connected by a front side, also referred to as a front edge or front face, of the respective trench.

[0027] In the power semiconductor device described herein, an extension of the effective channel region size, for example in a silicon carbide (SiC) trench MOSFET device, is proposed. The design introduces a rectangular or zigzag step feature that alternates back and forth around a plane perpendicular to the

[0001] direction, which may be the direction of the trench depth, so that the sidewalls are

[0028]

number

[0029] Not only that

[0030]

number

[0031] , where the semiconductor body can be 4H-SiC. This design can maximize the overall width of the channel region in a device of a given pitch dimension compared to trenches that are only stripes. The additional parallel conduction of the extra sidewall portions in the trenches allows for high current capability, thus reducing R ON The on-resistance, also referred to as on-resistance, is lower.

[0032] Trench-gate power MOSFET devices represent one of the most promising technologies to meet energy efficiency and performance requirements in power electronics. One of the development approaches for trench MOSFET devices is the so-called V-groove MOSFET (VMOSFET for short). The generation of high electric fields at the tip of a well-etched sharp V structure can be partially mitigated by prematurely terminating the etching step to produce a flat trench bottom, at the expense of reduced high integration capabilities. This design can be further improved by opening up a rectangular trench defining the MOS inversion channel, whose trench sidewalls are typically etched along non-polar crystallographic planes. This structure, called UMOSFET type, offers a smaller cell pitch due to the absence of a junction field effect transistor (JFET) region, and a significantly lower on-resistance per unit area due to the high mobility of charge carriers in the non-polar faces of SiC devices.

[0033] Some other promising designs include the so-called pn superjunction (SJ for short), which is intended to improve the trade-off between a specific on-resistance and the breakdown voltage. This can be achieved by forming a parallel arrangement of thin p-type and n-type doped layers inserted in the drift region. By properly controlling the maximum doping concentration and thickness of these layers, it is also possible to lower the on-resistance and increase the breakdown voltage.

[0034] Vertical trench-gate MOSFET devices based on the SJ structure are much more difficult to fabricate than planar devices, but they offer a significant advantage over conventional trench-gate structures. ON The SJ trench design shows promise but involves higher complexity during device processing.

[0035] Lateral scaling or pitch reduction is likely due to easier process realization. ONAlthough it is one of the most adopted approaches to reduce the gate charge, it is strongly limited by integration constraints and increases the gate charge. However, vertical trench MOSFETs offer much more versatility, and the combination of a larger effective channel area and higher mobility along the non-planar trench sidewalls allows for lower on-resistance compared to conventional planar MOSFETs.

[0036] In the semiconductor devices described herein, for example, the devices include trenches that are etched deep inside the semiconductor body in a

[0001] direction;

[0037]

number

[0038] and

[0039]

number

[0040] Thus, the orientation of the sidewalls alternates from one direction to the other, with the major axis of at least one trench being aligned parallel to the

[0041]

number

[0042] Advantages of the designs proposed herein include, for example, an increase in the resulting channel region width for a given pitch dimension compared to the estimated width of a conventional UMOSFET trench.

[0043] Therefore, in this proposed design,

[0044]

number

[0045] At least one trench sidewall area along is equal to the total trench sidewall area of ​​a standard striped trench design.

[0046]

number

[0047] Every etched sidewall portion along introduces an additional contribution, for example, approximately 40% increase in channel area for the same cell pitch.

[0048]

number

[0049] The optimum sidewall step length along the channel width may be selected by a tradeoff between increasing the channel width and avoiding excessive pitch dimensions.

[0050] According to at least one embodiment, the semiconductor body is made of SiC and the direction of the main extent of the at least one trench is the direction of the SiC

[0051]

number

[0052] The direction of primary extent may be the direction of the area in which the at least one trench has the largest geometric dimension and / or the direction of the longest axis of symmetry of the respective trench.

[0053] According to at least one embodiment, at least one or some, or each, of the sidewalls is made of SiC.

[0054]

number

[0055] At least one portion adjacent to at least one source region extending laterally relative to the at least one source region. For example, the portion

[0056]

number

[0057] For example, perpendicular to

[0058]

number

[0059] otherwise,

[0060]

number

[0061] and the side wall portion is at least 45°, at least 60°, or at least 70°, and / or at most 85°, or at most 75°.

[0062]

number

[0063] , and may have different angles to each other. According to at least one embodiment, the total length of at least one of the sidewalls, when viewed from a top view of the top surface, exceeds the length of the at least one trench by at least 1.2 times, at least 1.3 times, or at least 1.4 times. The length of the at least one trench may refer to the extent of the respective trench along the direction of its main extent. The length of the at least one trench may also be referred to as the effective extent or effective length. Illustratively, the non-linear sidewalls increase the total length of the sidewalls, for example, over the entire depth direction of the trench, compared to the effective length of the gate. Thus, the non-linearity of the sidewalls may significantly increase the length of the sidewalls, and thus the length of the channel region, when viewed from a top view of the top surface.

[0064] According to at least one embodiment, the sidewalls are oriented perpendicular to the top surface with a tolerance of at most 15° or at most 5°. Optionally, the bottom surface of the trench also runs parallel to the top surface, for example with a tolerance of at most 15° or at most 5°. The bottom surface may connect the two sidewalls of the respective trench. Thus, each trench, when viewed in a cross section perpendicular to the direction of main extent through the top surface, has a U-shape or

[0065]

number

[0066] Of course, the features in this paragraph may be combined with some or all of the features in, for example, the previous paragraphs.

[0067] According to at least one embodiment, when viewed in a top view of the top surface, at least one trench comprises a central pipe that extends straight, for example along the direction of the main extent. For example, when viewed in a top view of the top surface, the width of the central pipe is constant. Furthermore, the central pipe may be of constant thickness in a direction perpendicular to the top surface. That is, the central pipe may be formed as a straight bar.

[0068] According to at least one embodiment, at least one trench comprises a plurality of branches from a central pipe. The branches may be considered as lateral extensions of the central pipe. The branches may be regularly and / or equidistantly arranged in the central pipe. The branches and the central pipe may be integral, or may be otherwise composed of multiple parts.

[0069] If the trench comprises multiple branches on opposite sidewalls, the branches may be arranged symmetrically, i.e. opposite each other, or offset, i.e. displaced, on both sidewalls.

[0070] According to at least one embodiment, one or some or all of the branches are square or rectangular in shape when viewed in top plan view of the top surface, i.e., adjacent portions of at least one respective side wall are disposed perpendicular to one another.

[0071] According to at least one embodiment, one or some or all of the branches are trapezoidal in shape when viewed in top plan view of the top surface, each trapezoid being, for example, a symmetric trapezoid, the axis of symmetry being perpendicular to the direction of the main extent of the respective trench.

[0072] Alternatively, or in addition, one or some or all of the branches may be polygonal when viewed in a top plan view of the top surface.

[0073] According to at least one embodiment, one or some or all of the branches are trapezoidal in shape extending in a direction perpendicular to the central pipe when viewed in top plan view, such that the widest portion of each branch is away from the central pipe.

[0074] According to at least one embodiment, one or some or all of the branches are trapezoidal in shape, narrowing in a direction perpendicular to the central pipe, when viewed in top plan view on the top surface, such that the widest part of each branch is next to the central pipe.

[0075] According to at least one embodiment, one or some or all of the branches are triangular in shape when viewed in top view of the top surface. That is, each trench may appear as a single-edged or double-edged sawtooth when viewed in top view. At least one or some or all of the triangular branches may be shaped symmetrically with respect to an axis of symmetry perpendicular to the direction of the main extent of each trench. The opening angle of the triangle forming each branch at its tip away from the central pipe is, for example, at least 45°, at least 90° or at least 120°. Alternatively or in addition, said opening angle is at most 150°, at most 125° or at most 100°. For example, the opening angle is between 90° and 150° (inclusive) or between 45° and 125° (inclusive).

[0076] According to at least one embodiment, each of the sidewalls comprises a plurality of branches. All of the branches of each sidewall, or all of the branches of each channel, may be of the same shape. Alternatively, branches of different shapes may be combined in each trench.

[0077] According to at least one embodiment, at least one trench is serpentine when viewed in top view of the top surface, meaning, for example, that between opposite ends of said at least one trench there is no straight connecting line that runs all the way to the top of said at least one trench, in other words, it would not be possible to pull a rigid straight rod through the respective trench, even if the trench was empty.

[0078] According to at least one embodiment, when viewed in top view of the top surface, the at least one trench has at least one of a zigzag, a sinusoidal and a square wave shape, which may apply to trenches with or without straight connecting lines as defined above.

[0079] According to at least one embodiment, the power semiconductor device further comprises a plurality of plugs of a second conductivity type, e.g., at a top surface of the semiconductor body. The plugs may be configured to provide an electrical contact path from the top surface to the at least one channel region. Thus, the plugs may cross the at least one source region and directly contact the at least one channel region as well as the top surface. The plugs and the at least one source region may be at the same potential, and consequently the at least one channel region may also be at the same potential.

[0080] According to at least one embodiment, the plugs are arranged away from the at least one trench when viewed in a top view of the top surface. In this case, the plugs may not contact the at least one trench. At least one source region may be arranged between the plugs and the at least one trench. Otherwise, the plugs may contact the at least one trench, for example in a point-like manner, i.e. there may be no contact surface between the at least one trench and the respective plug, but only a contact line.

[0081] According to at least one embodiment, when viewed from a top view of the top surface, at least one trench is flanked by straight strips that may contact, for example at a point, at least one assigned trench or are spaced from the at least one assigned trench, and portions of the at least one source region and plugs may be alternated in the straight strips.

[0082] According to at least one embodiment, a power semiconductor device comprises a plurality of trenches and, optionally, a plurality of source regions or a single source region. When viewed in a top view of the top surface, the trenches and at least one associated source region may be arranged in alternating transverse directions relative to the trenches. The trenches may be arranged parallel to one another, i.e. in a direction parallel to their main extent, or with parallel axes of symmetry.

[0083] According to at least one embodiment, the power semiconductor device is a field effect transistor or an insulated gate bipolar transistor. For example, the power semiconductor device described herein is or is included in MOS-based SiC trench devices, such as MOSFETs and IGBTs. Thus, the power semiconductor device may be or be present in a device selected from the group including or consisting of metal oxide semiconductor field effect transistors (MOSFETs), metal insulator semiconductor field effect transistors (MISFETs), insulated gate bipolar transistors (IGBTs), bipolar junction transistors (BJTs), and junction gate field effect transistors (JFETs). The power semiconductor device described herein may be part of a thyristor, such as a gate turn-off thyristor (GTO) or a gate commutated thyristor (GCT).

[0084] According to at least one embodiment, the semiconductor body further comprises a collector region. The collector region is of the same conductivity type as the channel region. The collector region may be at a bottom surface of the semiconductor body opposite the top surface. In case of multiple source regions, there may be one collector region for every source region. A collector electrode may be provided directly to the collector region. In case of a collector region, the power semiconductor device may be an IGBT.

[0085] According to at least one embodiment, the semiconductor further comprises at least one drain region. The drain region is of the same conductivity type as the at least one source region. For example, the drain region is a layer at the bottom surface. For example, a drift region is disposed between the at least one source region and the drain region. In case of multiple source regions, there may be one common drain region for all source regions. The drain electrode may be in direct contact with the at least one drain region. In case of a drain region, the power semiconductor device may be a MOSFET or a MISFET.

[0086] According to at least one embodiment, the power semiconductor device comprises at least two source regions and a source electrode. The source electrode is in direct, e.g. electrical, contact with at least two or all of the source regions. Thus, the at least two source regions may be at the same potential. Optionally, the source electrode may be in direct contact with at least one plug.

[0087] According to at least one embodiment, a gate electrode is disposed between at least two source regions when viewed in a cross section perpendicular to the top surface. Thus, one gate electrode may be assigned to two source regions. The source regions may be disposed symmetrically next to each gate electrode.

[0088] According to at least one embodiment, the power semiconductor device is a power device. For example, the power semiconductor device is configured for a maximum current of at least 1 A or at least 20 A through at least one channel region. Alternatively, or in addition, the power semiconductor device is configured for a maximum voltage of at least 0.2 kV, at least 0.6 kV, or at least 1.2 kV.

[0089] The power semiconductor device may be, for example, a power module in a vehicle, for converting direct current from a battery to alternating current for an electric motor in, for example, a hybrid or plug-in electric vehicle. Furthermore, the power semiconductor device may be, for example, a fuse in a vehicle such as an automobile.

[0090] The power semiconductor device is described in more detail below as an exemplary embodiment with reference to the figures. Identical elements in the different figures are indicated with identical reference numerals. However, the relationships between the elements are not shown to scale and individual elements may be exaggerated to facilitate understanding. [Brief description of the drawings]

[0091] [Figure 1]1 is a schematic perspective view of an exemplary embodiment of a power semiconductor device described herein; [Diagram 2] FIG. 2 is a schematic top view of the power semiconductor device of FIG. [Diagram 3] FIG. 2 is a schematic cross-sectional view of the power semiconductor device of FIG. [Figure 4] FIG. 2 is a schematic cross-sectional view of the power semiconductor device of FIG. [Diagram 5] FIG. 1 is a schematic diagram of the crystal orientation of SiC. [Figure 6] 1 is a schematic top view of an exemplary embodiment of a power semiconductor device described herein; [Figure 7] 1 is a schematic top view of an exemplary embodiment of a power semiconductor device described herein; [Figure 8] 1 is a schematic top view of an exemplary embodiment of a power semiconductor device described herein; [Figure 9] 1 is a schematic top view of an exemplary embodiment of a power semiconductor device described herein; [Figure 10] 1 is a schematic top view of an exemplary embodiment of a power semiconductor device described herein; [Figure 11] 1 is a schematic top view of an exemplary embodiment of a power semiconductor device described herein; [Figure 12] 1 is a schematic top view of an exemplary embodiment of a power semiconductor device described herein; [Figure 13] 1 is a schematic top view of an exemplary embodiment of a power semiconductor device described herein; [Figure 14] 1 is a schematic perspective view of an exemplary embodiment of a power semiconductor device described herein; [Figure 15] FIG. 2 is a schematic diagram of simulated current density data for a power semiconductor device described herein. [Figure 16] FIG. 2 is a schematic diagram of a simulated current-voltage characteristic of a power semiconductor device described herein. [Figure 17]1 is a schematic top view of an exemplary embodiment of a power semiconductor device described herein; [Figure 18] 1 is a schematic top view of an exemplary embodiment of a power semiconductor device described herein; [Figure 19] 1 is a schematic top view of an exemplary embodiment of a power semiconductor device described herein; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0092] 1 to 4 an exemplary embodiment of a power semiconductor device 1 is shown. The power semiconductor device 1 comprises a semiconductor body 2. The semiconductor body 2 comprises a plurality of source regions 21 at a top surface 20. Optionally, the top surface 20 also comprises a plurality of plugs 25. The plugs 25 are configured to be in electrical contact with the source regions 21 and the channel region 22 located below the plugs 25. The plugs 25 and the source regions 21 may have the same or different thicknesses along a growth direction G of the semiconductor body 2.

[0093] Further, in the semiconductor body 2, below the channel region 22 is a drift region 23. The channel region 22 separates the source region 21 from the drift region 23.

[0094] If the power semiconductor device 1 is a MISFET or MOSFET, there may be an optional drain region 24 below the drift region 23 at a bottom surface 29 of the semiconductor body 2 opposite the top surface 20. The drain region 24 is electrically contacted by a drain electrode 32. For example, as seen in Figures 3 and 4, there is a source electrode 31 on the top surface that electrically contacts all of the source regions 21 as well as the plugs 25.

[0095] The aforementioned regions 21, 22, 23, 24 may directly follow each other from above along the growth direction G of the semiconductor body 2. Thus, the semiconductor body 2 may be at least partially grown epitaxially. Furthermore, the semiconductor body 2 may comprise the substrate shown here, on which other regions, e.g. regions 22, 21, 25, are grown.

[0096] Furthermore, a trench 4 in the semiconductor body 2 extends from the top surface 20 through the source region 21 and the channel region 22, terminating in the drift region 23. The trench 4 comprises a central pipe 41, which extends straight in the direction of primary extent L. To increase the effective channel width, the trench 4 comprises a number of branches 42 extending away from the central pipe 41. The branches 42 thus increase the length of the sidewalls 44 of the trench 4. Viewed in cross section, the trench 4 is approximately

[0097]

number

[0098] , so that bottom surface 46 of the trench extends parallel or nearly parallel to top surface 20. As a result, sidewalls 44 extend perpendicular or nearly perpendicular to top surface 20.

[0099] Within the trench 4 is a gate electrode 34. The gate electrode 34 is electrically isolated from the semiconductor body 2 by a gate insulator 35. A further insulator electrically isolating the source electrode 31 from the gate electrode 34 is not explicitly shown in the figures. For simplicity, the gate insulator 35 is not shown in the following figures.

[0100] Optionally, beneath the trench 4 is a shielding region 27 embedded in the drift region 23 at the bottom surface 46 of the trench. The shielding region 27 may underlie the central pipe 41 and the branches 42, or may underlie only the central pipe 41.

[0101] The shield region 27 below the bottom surface 46 of the trench may be created by ion implantation and may be used to shield the gate insulator 35 from high electric fields in the blocking state. The shield region 27 may be floating or may be contacted to the same source region potential. In cross section, the shield region 27 may be square or rectangular.

[0102] In top view, the branches 42 are rectangular and regularly arranged. The branches 42 on the two side walls 44 are opposite each other, so that the long axis of symmetry of the trench 4 runs along the direction of main extent L. The extent of the branches 42 in the direction away from the central pipe 41 can be greater than the width of the central pipe 41 without the branches 42. Furthermore, the distance between adjacent branches 42 in the direction perpendicular to the central pipe 41 can be greater than the length of the branches 42 and greater than the width of the central pipe 41.

[0103] Optionally, strips 48 extend parallel to the direction of main extent L. The strips 48 may be straight. In the strips 48, the source regions 41 and the plugs 25 are arranged alternately. In this respect, the source regions 41 may be present only at the front ends of the branches 42, so that at the corners of the branches 42 near the strips 48, the plugs 25 may contact the trenches 4, for example, in a point-like manner as seen in top view, compare FIG. 2. Thus, the strips 48 contact the trenches 4 only at the front ends of the branches 42. The areas between adjacent branches 42 may consist entirely of source regions 21.

[0104] In Figures 1 and 2, the semiconductor body 2 comprises only one trench 4. However, the configuration shown in Figures 1 and 2 can be considered as a basic unit that can be arranged, for example, adjacent to one another and repeated many times. The basic units can thus be adjacent to one another in a direction perpendicular to the main direction of extension L, and pairs of said basic units can follow one after the other. The pitch of the basic units, and therefore the pitch of the trenches, can therefore correspond to the width of the respective trench 4 in the branch 42 plus one or two times the width of the strip 48.

[0105] For example, the source region 21 and optional drain region 24 may be highly + doped, and the drift region 23 is lightly n-doped or - doped, the channel region 22 is p-doped, and the optional plug 25 as well as the optional shield region 27 are highly p + Otherwise, the doping types can all be reversed.

[0106] For example, the maximum doping concentration of the source region 21, the optional drain region 24 and the plug 25 is at least 1×10 18 cm -3 , at least 5 × 10 18 cm -3 , or at least 1×10 19 cm -3 and / or at most 5×10 20 cm -3 , at most 2×10 20 cm -3 Or at most 1×10 20 cm -3 In addition, the maximum doping concentration of the channel region 22 is at least 5×10 16 cm -3 Or at least 1×10 17 cm -3 and / or at most 5×10 19 cm -3 Or at most 5 x 10 18 cm -3The maximum doping concentration of the drift region 23 can be at least 1×10 14 cm -3 , at least 5 × 10 14 cm -3 , or at least 1×10 15 cm -3 and / or at most 1×10 17 cm -3 , at most 5×10 16 cm -3 , or at most 1×10 16 cm -3 It could be.

[0107] For better understanding, the power semiconductor device 1 described herein may be based on SiC, so that the basic crystal planes of SiC are shown in Fig. 5. The trenches 4 described herein may extend into the semiconductor body along the

[0001] direction, and the direction of main extent L is

[0108]

number

[0109] Therefore, the central pipe 41 is

[0110]

number

[0111] It is noted that the branch 42 shown in Figs. 1 and 2 is thus parallel to, e.g.

[0112]

number

[0113] All of the side walls 44 in the exemplary embodiment of FIGS.

[0114]

number

[0115] and

[0116]

number

[0117] It may extend along. In Fig. 6 another exemplary embodiment of the power semiconductor device 1 is shown in a top view on the top surface 20. Only one elementary cell is shown. A number of such elementary cells may follow one another along the direction of main extent L, so that the above-described elementary unit may consist of a number of such elementary cells, which may be arranged side by side, adjacent to one another.

[0118] According to FIG. 6, the spread of the branches 42 away from the central pipe 41 corresponds to the minimum size U of a structural unit. U may therefore describe the minimum step size of the channel width. For example, U is at least 0.2 μm or at least 0.5 μm and / or at most 5 μm or at most 2 μm. In the strips 48, the plugs 25 are spaced apart to prevent an increase in the pitch dimension.

[0119]

number

[0120] In top view, the plug 25 may contact the trench 4 at a contact point 51.

[0121] Otherwise, the same may be true for FIG. 6 as for FIGS. 1-5. 7, the source regions 21 in the laterally disposed strips 48 may extend toward the plug 25 along the direction of primary extent L, resulting in overlap regions 52. This helps to reduce the formation of extended depletion regions around the corners, ultimately reducing the effective channel width at those points. For example, the extent of the overlap regions 52 along the direction L is at least 0.1U and / or at most 0.5U. For example, the width of the stripes 48 is at least 0.2U and / or at most 0.8U.

[0122] Thus, because of the overlap regions 52 , the source regions 21 between adjacent branches 42 may merge with the source regions 21 in the strips 48 resulting in one continuous source region 21 per sidewall 44 .

[0123] Otherwise, the same may be true for FIG. 7 as for FIGS. 1-6. 8, the branches 42 extending away from the central pipe 41 are trapezoidal in shape narrowing in a direction perpendicular to the central pipe 41. The symmetry axes of the branches 42 are oriented perpendicular to the direction L. For example, the angle A between the direction L and the laterally extending sidewalls 44 is at least 45° and / or at most 80°, or at least 55° and / or at most 70°. Such a design of the branches 42 can be used to optimize trench performance while maintaining the same cell pitch.

[0124] 6, the plug 25 as well as the source region 21 contact the front end of the branch 42 at contact point 51. Again, said front end of the side wall 44 extends parallel to the direction L.

[0125] Thus, each sidewall 44 of at least one trench 4 is

[0126]

number

[0127] or

[0128]

number

[0129] Similarly, the angle A between alternating trench sidewalls 44 may be selected to explore benefits from different crystal planes perpendicular to top surface 20, such as the mobility improvement afforded by nonpolar planes of 4H—SiC.

[0130] Otherwise, the same may be true for FIG. 8 as for FIG. FIG. 9 shows that the strips 48 have overlap regions 52, similar to FIG.

[0131] Otherwise, the same may be true for FIG. 9 as for FIG. 10, the branches 42 are also trapezoidal, but widen in a direction perpendicular to the central pipe 41. Consequently, the angle A is greater than 90°, for example at least 100° and / or at most 135°, or at least 110° and / or at most 125°.

[0132] Although the configuration of FIG. 10 is shown with contact areas 52, it could of course be implemented using contact points 51 instead, compare for example FIG.

[0133] Otherwise, the same may be true for FIG. 10 as for FIGS. 1-9. According to FIG. 11, the branch 42 has a triangular shape in a top view. Thus, the trench 4 has

[0134]

number

[0135] Direction and

[0136]

number

[0137] There may be no side walls 44 extending along the direction. For example, angle A is at least 30° and / or at most 80°, or at least 45° and / or at most 70°.

[0138] 11, in top view, there is a continuous strip of plugs 25 along direction L on each side of trench 4. Thus, at the tips of branches 42, plugs 25 may contact sidewall 44. Otherwise, in FIG. 12, strips 48 alternate between source regions 21 and plugs 25, thus resulting in a merged, continuous source region 21 on each side of trench 4, in top view.

[0139] Otherwise, the same may be true for FIGS. 11 and 12 as for FIGS. 1-10. In the embodiments of Figures 1-4 and 6-12, there is always a continuous straight central pipe 41, so that the ends of the trench 4 can be connected by straight lines that run only inside the trench 4. In contrast, looking at Figure 13, the trench 4 is rectangular signal-shaped when viewed from the top. For example, when viewed from the top, the width of the trench 4 in the region extending parallel to the direction L is U or

[0140]

number

[0141] is smaller than the length B of the inner leg. Thus, in top view, the area of ​​trench 4 is U or

[0142]

number

[0143] The optional plugs 25 are formed with alternating orientations of U or

[0144]

number

[0145] or, unlike that shown in FIG. 13, in the range of U or

[0146]

number

[0147] It may be away from the inner portion of the Otherwise, the same may be true for FIG. 13 as for FIGS. 1-12.

[0148] The power semiconductor devices 1 in Figures 1-4 and 6-13 are configured as trench MISFETs or MOSFETs. In contrast, the power semiconductor device 1 in Figure 14 is an IGBT. Otherwise, all of the power semiconductor devices 1 in Figures 1-4 and 6-13 may also be IGBTs, and the power semiconductor device 1 in Figure 14 may be a trench MISFET or MOSFET.

[0149] Thus, according to Fig. 14, the power semiconductor device 1 comprises a collector region 26 at a bottom side 29 of the semiconductor body 2, in which there is a collector electrode 33. If the drift region 23 is n-doped, the collector region 26 is p-doped and vice versa. For example, for the highest doping concentration of the collector region 26, the same may apply to the at least one channel region 22. Optionally, between the collector region 26 and the drift region 23, a buffer region 28 of the first conductivity type may be present. For example, the highest doping concentration of such a buffer is higher than that of the drift region 23.

[0150] 14, trench 4 is shown to have a sawtooth shape when viewed from the top: inside trench 4 there are no straight lines simply extending along direction L connecting opposite ends of trench 4 as in FIG.

[0151] According to Fig. 14, when seen in top view, the trenches 4 have pointed tips away from the central axis along the direction L of the trenches 4. Besides what is shown, these tips may be rounded or replaced by sections extending parallel to the direction L. These modifications are possible in all other exemplary embodiments as well.

[0152] In FIG. 14, optional plug 25 may be separate from trench 4 as in the embodiments of FIGS. 6-13, or may contact trench 4. In FIG.

[0153] Otherwise, the same may be true for FIG. 14 as for FIGS. 1-13. FIG. 15 shows that the simulation data proves the advantage of the proposed trench design in a top view of the top surface 20, and therefore in the xy plane. As depicted in FIG. 15, only one slice of the basic unit was simulated. Although the simulation shows separate effects on current conduction due to thicker or thinner oxide at the corners of the trench, the output characteristics of FIG. 15 show that the overall effect is R ON In practice, the corners of the trench are typically rounded to minimize concentration of the electric field lines at sharp points, and the sidewalls 44 may also have various angles, see, e.g., FIGS. 8-12 and 14.

[0154] 16 shows a comparison of output current-voltage characteristics at a gate-source voltage of 15 V between the power semiconductor device 1 described herein and a device with only a striped trench structure. As shown by the drain current vs. source-drain voltage graph at a gate-source voltage of 15 V, the on-resistance R ONA decrease of about 36% in can be estimated.

[0155] In the example of Figures 17-19, there is a shield region 27 under a part of the trench 4. In Figures 17-19, the branches 42 are rectangular in top view and are paired and exactly opposite each other along the central pipe 41, but similarly the branches 42 can be trapezoidal as in Figures 8-10. Furthermore, the source regions 21 and plugs 25 can also be shaped as in Figure 7 or Figure 9. Opposite branches 42 can optionally be displaced along the central pipe 41 with respect to each other, for example by at most 20% or at most 40% of the extent of the respective branches 42 along the central pipe 41.

[0156] The function of the shield region 27 is to protect the bottom edges and corners of the trench 4 from high electric fields during blocking conditions. When a high voltage is applied between the source and drain during blocking, high electric field values ​​tend to form at the dielectric / semiconductor interface at the bottom of the trench 4, especially at the sharp corners and edges. Electric field concentrations at those points can lead to dielectric breakdown and device failure.

[0157] The layout that gives the best protection to the trench 4 would have a shielding region 27 (not shown) covering the entire bottom of the central pipe 41 as well as the branches 42, but with the disadvantage that during conduction a large depletion region would occur around the vertical channel, i.e. along the trench walls 44, potentially resulting in a high JFET effect and inhibiting current flow, i.e. increasing the overall on-resistance.

[0158] To minimize this effect, other layouts are possible that reduce the area of ​​the shielding region 27 under the trench 4. One possibility is to limit the extent of the shielding region 27 only to the intersection region between the central pipe 41 and the branches 42, see FIG. 17. In this case, the effect of the depletion regions created by the separate adjacent shielding regions 27 formed like separate islands, for example, can be minimized on the on-resistance at the trench wall 44, while the rest of the trench 4 can still be protected, if the doping, dimensions etc. parameters are appropriately selected.

[0159] 18, the shielding region 27 is formed as a bar under a pair of opposing branches 42 and a part of the central pipe 41 between said branches 42. That is to say, several of said bars may follow one after the other along the central pipe 41.

[0160] In FIG. 19, the shield region 27 is also island-like and is limited to a branch 42 .

[0161] Although not shown, in other designs, the trench 4 may be provided with a shielded region 27 entirely, or the shielded region 27 may be limited to the central pipe 41 as seen in a top view of the top surface 20.

[0162] The shielding regions 27 can be achieved by appropriate masking and implantation and / or epi implant-epi processing.

[0163] The device described herein is not limited by the description given with reference to the exemplary embodiments, but rather, the device includes every novel feature and every combination of these features, specifically including every combination of features in the claims, even if the feature or combination is not itself explicitly recited in the claims or in the exemplary embodiments.

[0164] This patent application claims priority to European Patent Application No. 21163959.6, the disclosure of which is incorporated herein by reference. [Explanation of symbols]

[0165] List of reference numbers 1. Power Semiconductor Devices 2. Semiconductor body 20 Top surface 21 Source Area 22 Channel Region 23 Drift Region 24 Drain Region 25 Plug 26 Collector Region 27 Shield Area 28 Buffer Space 29 Bottom 31 Source and channel region electrodes 32 Drain electrode 33 Collector electrode 34 Gate electrode 35 Gate insulator 4. Trench 41 Center Pipe 42 Branch 44 Trench Sidewall 46 Bottom of Trench 48 Strip 51 Contact Points 52 Overlap Area A Angle B Inner leg length G growth direction L Direction of longest extent of trench U Minimum size of structural unit x, y axes

Claims

1. a semiconductor body (2), a plurality of source regions (21) of a first conductivity type at a top surface (20) of said semiconductor body (2); at least one channel region (22) of a second conductivity type in said semiconductor body (2) beneath said source regions (21); in the semiconductor body (2), at the top surface (20) of the semiconductor body (2), a plurality of plugs (25) of a second conductivity type providing an electrical contact path from said top surface to said at least one channel region (22); a drift region (23) of said first conductivity type beneath said at least one channel region (22) in said semiconductor body (2); at least one trench (4) extending from said top surface (20) through said plurality of source regions (21) and said at least one channel region (22) and terminating in said drift region (23); a shielding region (27) of said second conductivity type arranged under at least a part of the bottom surface (29) of at least one of said trenches (4); A power semiconductor device (1) comprising: at least one of said trenches (4) accommodates a gate electrode (34), said gate electrode (34) being electrically isolated from said semiconductor body by a gate insulator (35); - when viewed in a top view of said top surface (20), at least one of said trenches (4) has side walls (44) which extend in a non-linear manner; - when viewed in a top view of said top surface (20), at least one of said trenches (4) comprises a plurality of branches (42) and further comprises a central pipe (41) extending straight, each of said plurality of branches (42) branching off from said central pipe (41), said shielding region (27) extending at least partially under at least one of said branches (42); - said shielding area (27), when viewed in a top view of said top surface (20), is limited to said branches (42), so that at least 90% of the area of ​​said central pipe (41) is free of said shielding area (27); - in a top view of said top surface (20), at least one of said trenches (4) is flanked on either side by rectilinear strips (48), said at least one of said trenches (4) being arranged between two adjacent rectilinear strips (48), in which parts of at least one of said source regions (21) and said plugs (25) of second conductivity type are arranged alternately in said rectilinear strips (48); - said plug (25) and said at least one channel region (22) are connected; the source regions (21) are arranged at the front ends of the branches (42) on the side of the rectilinear strip (48), so that at the corners of the branches (42) close to the rectilinear strip (48) the plugs (25) contact at least one of the trenches (4), or the source regions (21) between adjacent branches (42) merge with the source regions (21) in the rectilinear strip (48), so that one continuous source region (21) is provided per sidewall (44); the region between adjacent branches (42) consists of said source region (21); the branches are provided on both sides of the central pipe, whereby each of said side walls comprises a number of branches; Power semiconductor device (1).

2. 2. The power semiconductor device (1) of claim 1, wherein at least some of the branches (42) are trapezoidal in shape when viewed in a top view of the top surface (20), and the trapezoidal branches (42) extend relative to the central pipe (41) in a direction from the central pipe (41) towards the straight strips (48) when viewed in a top view of the top surface (20).

3. 2. The power semiconductor device (1) according to claim 1, wherein, when viewed in a top view of the top surface (20), at least some of the branches (42) are trapezoidal in shape, and the trapezoidal branches (42) narrow relative to the central pipe (41) in a direction from the central pipe (41) towards the straight strips (48) when viewed in a top view of the top surface (20).

4. The semiconductor body (2) is made of silicon carbide (SiC), and the direction of main extent (L) of at least one of the trenches (4) is [0010] Extends along the Each of the side walls (44) is made of the SiC. [0025] The power semiconductor device (1) according to any one of claims 1 to 3, comprising at least one portion adjacent to at least one said source region (21) extending laterally with respect to said power semiconductor device (1).

5. The power semiconductor device (1) according to any one of claims 1 to 4, wherein, when viewed in a top view of the top surface (20), the total length of each of the side walls (44) exceeds the length of at least one of the trenches (4) by at least 1.2 times.

6. The power semiconductor device (1) according to any one of claims 1 to 5, wherein the sidewalls (44) are oriented perpendicular to the top surface (20) with a tolerance of at most 15° and a bottom surface (46) of the trench extends parallel to the top surface (20).

7. 2. The power semiconductor device (1) according to claim 1, wherein at least some of the branches (42) are triangular, square or rectangular in shape when viewed in a top view of the top surface (20).

8. A power semiconductor device (1) comprising a plurality of said trenches (4), The power semiconductor device (1) according to any one of claims 1 to 7, wherein, when viewed in a top view of the top surface (20), the trenches (4) and the associated source regions (21) are alternately arranged in a direction perpendicular to the trenches (4).

9. The power semiconductor device (1) according to any one of claims 1 to 8, wherein the power semiconductor device (1) is a field effect transistor or an insulated gate bipolar transistor.

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