Low Power Cache

Abstract

The cache includes an upstream port, a cache memory for storing cache lines each having a line width, and a cache controller coupled to the upstream port and the cache memory. The upstream port transfers data words having a transfer width less than the line width. The cache controller selectively determines data bus inversion information for a sequence of data words having the transfer width in response to a cache line fill and stores the data bus inversion information in the cache memory along with the selected inverted data words for the cache line fill.

Description

[Background technology]

[0001] Computer systems such as laptops, notebooks, smartphones, tablets, etc. typically include a system-on-chip (SOC) that integrates many components of a computer system on a single integrated circuit chip. For example, a SOC may include one or more central processing unit (CPU) cores, a graphics controller, one or more memory controllers for interfacing to external memory components, and an input / output controller for interfacing to off-chip input / output peripherals. Because many of these devices operate in portable applications powered by batteries, low power consumption is an important feature of these SOCs.

[0002] Functional blocks within an SOC exchange data with each other across a wide internal bus. For example, a CPU may request data stored in an external memory through a cache, which brings the data on-chip through a memory controller and forwards the data to the CPU while keeping a copy for later access. These accesses typically occur over multiple cycles across the wide internal bus. When an SOC conducts data on a bus over multiple cycles, on average many data lines switch logic states, which repeatedly charges and discharges the highly capacitive bus lines, increasing power consumption. In addition, because these signal lines switch logic states nearly simultaneously, they cause power and ground bounce that can cause glitches, noise, signal skew, and other undesirable effects on adjacent signal lines and circuits within the SOC. [Brief description of the drawings]

[0003] [Figure 1] FIG. 1 is a block diagram of a cache line as known in the prior art. [Diagram 2]1 is a block diagram of a data processing system according to some embodiments. [Diagram 3] 3 is a block diagram of cache lines available in the cache of FIG. 2 according to some embodiments. [Figure 4] 3 is a flow diagram illustrating the operation of the cache of FIG. 2 in accordance with some embodiments. [Diagram 5] 3 is a block diagram of the cache of FIG. 2 according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0004] In the following description, the use of the same reference numbers in different figures indicates similar or identical items. Unless otherwise noted, the word "coupled" and its related verb forms include both direct and indirect electrical connections by means well known in the art, and unless otherwise noted, any description of a direct connection also refers to alternative embodiments using a suitable form of indirect electrical connection.

[0005] The cache includes an upstream port, a cache memory for storing cache lines each having a line width, and a cache controller. The cache controller is coupled to the upstream port and the cache memory. The upstream port transfers data words having a transfer width less than the line width. In response to a cache line fill, the cache controller selectively determines data bus inversion information for a series of data words having the transfer width and stores the data bus inversion information in the cache memory along with the selected inverted data words for the cache line fill.

[0006] The data processing system includes a plurality of memory access requesters, a plurality of memory access responders, a data fabric for selectively coupling the plurality of memory access requesters to the plurality of memory access responders, and a cache. The cache is coupled to the data fabric and includes a cache memory and a cache controller. The cache memories store cache lines, each having a line width. The cache controller is coupled to the cache memory and transfers data words having a transfer width less than the line width. In response to a cache line fill, the cache controller selectively determines data bus inversion information for a series of data words having the transfer width and stores the data bus inversion information in the cache memory along with the selected inverted data words for the cache line fill.

[0007] A method for reducing energy consumption in a data processing system having a cache includes receiving a cache line, the cache line including a plurality of data words. A state of the cache line is set to a data inversion mask state. For each data word, it is determined whether more than half of a plurality of data bits in the data word transition between a previous data word and the data word. If there is a transition, each of a plurality of data bits in the data word is inverted before storing the inverted data word in the cache, and a corresponding data bus inversion bit is set. If there is no transition, the data word is stored in the cache without inverting any of the plurality of data bits, and a corresponding data bus inversion bi is cleared.

[0008] 1 is a block diagram of a cache line 100 known in the prior art. The cache line 100 generally includes a line address 110, a line state 120, a least recently used (LRU) bit 130, and a data field 140.

[0009] The line address 110 indicates the location of a cache line in main memory and is part of a memory address. For example, if the data field 140 stores 64 bytes of data, the line address 110 includes all but the least significant 6 bits of the memory address, with the remaining address bits following the order of the data elements in the data field 140.

[0010] Line state 120 and LRU bits 130 store metadata for cache line 100. Line state 120 indicates the state of the cache line, which is useful for various purposes including line exchange and coherency between other caches in the system. In an exemplary embodiment, line state 120 stores a set of bits to implement the "MOESI" protocol. According to the MOESI protocol, line state 120 indicates what MOESI state the line is in, including bits indicating that the cache line has been modified (M), that the cache line is exclusive (E) or shared (S), or that the cache line is invalid (I). The owned (O) state indicates that the line has been modified in one cache, and that a shared copy may exist in another cache, causing the data in memory to be stale. Using this protocol, a cache can determine whether to find an updated copy in another cache in the system. The MOESI protocol and these particular bits are just examples of line states that may be used. LRU bits 130 indicate the staleness of the cache line. When the cache is full and data is requested from another line, the cache controller must find a place to store the new cache line and uses LRU bits 130 to determine which line to evict.

[0011] Data field 140 contains the data for the cache line. In the 64B cache line example above, a cache typically requires several cycles to store all 64B of data in data field 140 or to read all 64B of data from it. For example, if the cache's external data bus is 32 bits wide, a transfer of the cache line to another location takes 16 cycles. Such transfers may occur frequently during periods of high workload and may consume a significant amount of power during the bus transfer.

[0012] 2 is a block diagram of a data processing system 200, according to some embodiments. The data processing system 200 includes a data processor in the form of a SOC 210 and external memory 372, 283 in the form of low-power Double Data Rate synchronous dynamic random-access memory (LPDDRx SDRAM). Many other components of an actual data processing system would typically be present, but are not relevant to understanding the present disclosure and are not shown in FIG. 2 for ease of illustration.

[0013] SOC 210 generally includes a system management unit (SMU) 211, a system management network (SMN) 212, a central processing unit (CPU) core complex 220, labeled "CCX", a graphics controller 230, labeled "GFX", a real-time client subsystem 240, a memory / client subsystem 250, a data fabric 260, memory channels 270 and 280, a Peripheral Component Interface Express (PCIe) subsystem 290, and a cache 500, which acts as a last level cache and is labeled "LLC". As will be appreciated by those skilled in the art, SOC 210 may not have all of these elements present in all embodiments and may further have additional elements included therein.

[0014] SMU 211 is bidirectionally connected to the major components in SOC 210 via SMN 212. SMN 212 forms the control fabric for SOC 210. SMU 211 is a local controller that controls the operation of resources on SOC 210 and synchronizes communication between them. SMU 211 manages the power-up sequencing of the various processors on SOC 210 and controls multiple off-chip devices via reset, enable, and other signals. SMU 211 includes one or more clock sources (not shown), such as phase locked loops (PLLs), to provide clock signals to each of the components of SOC 210. SMU 211 can also receive measured power consumption values ​​from the CPU cores in CPU core complex 220 and graphics controller 230 to manage power for the various processors and other functional blocks and determine appropriate P-states.

[0015] CPU core complex 220 includes a set of CPU cores, each of which is bidirectionally connected to SMU 211 via SMN 212. Each CPU core may be a single core that shares only a last-level cache with the other CPU cores, or may be combined with some, but not all, of the other cores in a cluster.

[0016] Graphics controller 230 is bidirectionally connected to SMU 211 via SMN 212. Graphics controller 230 is a high-performance graphics processing unit capable of performing graphics operations such as vertex processing, fragment processing, shading, and texture blending in a highly integrated and parallel manner. Graphics controller 230 requires periodic access to external memory to perform its operations. In the embodiment shown in FIG. 2, graphics controller 230 shares a common memory subsystem with the CPU cores in CPU core complex 220, an architecture known as a unified memory architecture. Because SOC 210 includes both a CPU and a GPU, it is also referred to as an accelerated processing unit (APU).

[0017] Real-time client subsystem 240 includes a set of real-time clients, such as representative real-time clients 242 and 243, and a memory management hub, labeled "MM HUB," 241. Each real-time client is bidirectionally connected to SMU 211 via SMN 212, and bidirectionally connected to memory management hub 241. each A real-time client can be any type of peripheral controller that requires the periodic movement of data, such as an image signal processor (ISP), an audio coder-decoder (CODEC), a display controller that renders and rasterizes objects generated by the graphics controller 230 for display on a monitor, etc.

[0018] Memory / client subsystem 250 includes a set of memory elements or peripheral controllers, such as representative memory / client devices 252 and 253, and a system and input / output hub, labeled "SYSHUB / IOHUB," 251. Each memory / client device is bidirectionally connected to SMU 211 via SMN 212, and bidirectionally connected to system and input / output hub 251. A memory / client device is a circuit that stores or requires access to data on a non-periodic basis, such as non-volatile memory, static random-access memory (SRAM), external disk controllers such as a Serial Advanced Technology Attachment (SATA) interface controller, a universal serial bus (USB) controller, a system management hub, etc.

[0019] Data fabric 260 is an interconnect that controls the flow of traffic in SOC 210. Data fabric 260 is bidirectionally connected to SMU 211 via SMN 212, and bidirectionally connected to CPU core complex 220, graphics controller 230, memory management hub 241, system, and input / output hub 251. Data fabric 260 includes a crossbar switch for routing memory mapped access requests and responses between any of the various devices in SOC 210. Data fabric also includes a system memory map defined by the basic input / output system (BIOS) to determine where to send memory accesses based on the system configuration, and buffers for each virtual connection.

[0020] Memory channels 270 and 280 are circuits that control the transfer of data to and from external memories 273 and 283. Memory channel 270 is formed by memory controller 271 and physical interface circuit 272, labeled "PHY," connected to external memory 273. Memory controller 271 is bidirectionally connected to SMU 211 across SMN 212 and has an upstream port and a downstream port. Physical interface circuit 272 has an upstream port bidirectionally connected to memory controller 271 and a downstream port bidirectionally connected to external memory 273. Similarly, memory channel 280 is formed by memory controller 281 and physical interface circuit 282 connected to external memory 283. Memory controller 281 is bidirectionally connected to SMU 211 via SMN 212 and has an upstream port bidirectionally connected to data fabric 260 and a downstream port. Physical interface circuit 282 has an upstream port bidirectionally connected to memory controller 281 and a downstream port bidirectionally connected to external memory 283. Cache 500 is bidirectionally connected to SMU 211 across SMN 212, and has an upstream port bidirectionally connected to data fabric 260 and a downstream port connected to the upstream port of memory controller 271.

[0021] The peripheral component interface express (PCIe) subsystem 290 includes a PCIe controller 291 and a PCIe physical interface circuit 292. The PCIe controller 291 is bidirectionally connected to the SMU 211 via the SMN 212, and has an upstream port bidirectionally connected to the system and the input / output hub 251, and a downstream port. The PCIe physical interface circuit 292 has an upstream port bidirectionally connected to the PCIe controller 291, and a downstream port bidirectionally connected to a PCIe fabric, not shown in FIG. 2. PCIe Controller 291 can form a PCIe root complex of a PCIe system for connection to a PCIe network including PCIe switches, routers and devices.

[0022] In operation, SOC 210 integrates on a single chip a complex assortment of computing and storage devices, including CPU core complex 220 and graphics controller 230. Most of these controllers are well known and will not be described further. SOC 210 includes multiple internal buses for conducting data between these data elements at high speeds. For example, CPU core complex 220 accesses data via a high-speed 32-bit bus through an upstream port of data fabric 260. Data fabric 260 multiplexes accesses between any of multiple memory access agents connected to its upstream port and memory access responders connected to its downstream port. Due to the large number of memory access agents and memory access responders, the number of internal bus lines is likewise very large, and a crossbar switch in data fabric 260 multiplexes these wide buses to form virtual connections between memory access requesters and memory access responders.

[0023] The various processing nodes also maintain their own cache hierarchies. In a typical configuration, CPU core complex 220 includes four CPU cores, each with its own dedicated level 1 (L1) and level 2 (L2) caches, and a level 3 (L3) cache shared among the four CPU cores in the cluster. In this example, cache 500 forms a level 4 (L4) cache, but operates as a last level cache in the cache hierarchy, regardless of the internal organization of the cache hierarchy within CPU core complex 220. In one example, cache 500 implements an inclusive cache, where any cache line stored in any higher level cache in SOC 210 is also stored in cache 500. In another example, cache 500 is a victim cache, containing cache lines, each of which contained data requested by a data processor at an earlier time, but which eventually become the least recently used cache line and are evicted from all upper tier caches.

[0024] According to various embodiments described herein, cache 500 selectively stores data in each cache line in an inverted format to reduce the number of transitions when data is transferred across the internal bus. This is done by analyzing the number of transitions on the bus bit lanes between successive data elements and determining whether to invert the subsequent transition based on the least amount of energy consumed in the transfer. The decision to implement this feature is itself selected based on other characteristics of the data. Overall, for only a few extra metadata bits and a small number of formatting bits, the transfer of data through SOC 210 can be done in a more power efficient manner, significantly reducing the overall power consumption of SOC 210 under typical workloads. Power savings can be significant not only in data processing systems having buses to cache 500 that switch at a fast rate, but also in data processing systems having buses that may switch at a slower rate but that are larger and / or longer.

[0025] Figure 3 is a block diagram of a format of a cache line 300 that can be used in the cache 500 of Figure 2, according to some embodiments. The cache line 300 generally includes a line address 310, a line state 320, a data status field 330, an LRU bit 340, and a data field 350. The line address 310, the line state 320, and the LRU bit 340 function similarly to the line address 110, the line state 120, and the LRU bit 130 described above.

[0026] Data field 350 stores data and an additional special function bit labeled "SF" that indicates the status of the associated doubleword. For example, "SF 15 The special function bits labeled "DWORD 15 " and stores the special function bits for the doubleword of data labeled "SF 14 The special function bits labeled "DWORD 14 ", and so on. In the example shown in Figure 3, cache line 300 stores 64B of data organized into 16 double words, with each double word containing 32 bits. Thus, each double word stores a data element whose bits are transmitted during the same bus cycle on SOC 210's internal bus when the cache line is accessed and written back to main memory during a writeback or eviction, etc.

[0027] Data status field 330, along with line state 320 and LRU bits 340, stores metadata for cache line 300. Data status field 330 indicates how data is stored in data field 350. In the embodiment shown in Figure 3, data status field 330 includes two bits labeled "DS[1]" and "DS[0]" that encode one of four possible states.

[0028] In the first state, where DS[1:0]=00, data is stored normally, i.e., uninverted, in data field 350. SF bits are don't-cares, and data is stored in and read from data field 350 as normal.

[0029] In the second state, where DS[1:0]=01, data is stored with SF bits including a zero value mask (ZVM) bit for each doubleword. In a typical data structure, many data elements have a value of 0. When a doubleword has a value of 0, we explicitly store a 0 in the data field and do not need to toggle any bits on the bus during the transfer. Thus, cache 500 saves power by inhibiting the storing and retrieval of data because the extra ZVM bits make the actual value a don't care.

[0030] In the third state, where DS[1:0]=10, data is stored with SF bits including a data inversion mask (DIM) bit for each doubleword. In this case, the SF bit is 1 to indicate that the corresponding doubleword is stored in inverted format, and 0 to indicate that the corresponding doubleword is stored in non-inverted format. When in DIM mode, the decision as to whether to invert any particular data element is made by analyzing the number of transitions between a given doubleword and the following doubleword in the sequence pointed to by data field 350. For example, if the number of 32-bit transitions from DWORD0 to DWORD1 is greater than 16 bits, SF1 is set to 1 and DWORD1 is stored in that cache line in inverted format. Then, on subsequent accesses, the number of transitions on the data bus is reduced, saving power during operation.

[0031] In the fourth state, where DS[1:0]=11, the data is stored with the SF bit containing the write bit for every double word. In the write mask mode, double words that are not changed do not need to change the state of the value on the bus.

[0032] Cache 500 selectively sets the DATA STATUS state depending on the value of the data. The algorithm for determining the DATA STATUS state is now described.

[0033] Figure 4 is a flowchart of a flow 400 reflecting how the cache 500 of Figure 2 determines to set a data status field, according to some embodiments. The flow begins at box 410, which corresponds to the allocation of a cache line. In action box 420, the cache 500 receives a data element from main memory (e.g., in the case of a cache linefill operation) or from data fabric 260 (e.g., in the case of a writeback operation). In decision box 430, the cache 500 determines whether any dwords are masked, which would occur, for example, in the case of a writeback where only the particular dword is modified.

[0034] If any dwords are masked, then in action box 440, cache 500 writes the unmasked dwords to the cache line. In decision box 441, cache 500 determines whether any dwords are marked invalid. If so, flow proceeds to action box 442, which sets the line state to WM, and then to action box 443, where flow 400 ends. If not, flow proceeds to action box 444, which sets the line state to NORMAL, and then to action box 445, where flow 400 ends.

[0035] If the dword is not masked, then in decision box 450, cache 500 determines whether the number of dwords with all of their respective bits equal to zero is seven or greater. If so, then in action box 451, for each dword that is all zero, cache 500 sets the corresponding SF bit to one and inhibits writing the data word to the data portion of the cache line. In other words, for n=0-15, Dword n If =0x0, then SF n = 1, cache 500 is DWORD n data field 350. Next, in action box 452, the cache 500 sets the line state to ZVM, and in action box 453, the flow 400 ends.

[0036] If not, then in action box 454, the cache 500 determines, for each data transition, whether the number of transitions between each pair of doublewords is greater than half the data bus width, which in this example is 16. In other words, for n=0 to 15, n From DWORD n+1 If the number of transitions to DWORD ≥ 16, then the cache 15 inverts the bit before storing it in the data field 350 and n+1 Corresponding SF for n+1 If the bit is set to 1, otherwise the cache 500 stores the DWORD n+1 in the data field 350 and n+1 Corresponding SF for n+1 The cache 500 then sets the line state to DIM in action box 455 and the flow 400 ends in action box 456.

[0037] It should be apparent that flow 400 represents but one exemplary flow for data storage in cache 500 using selective data inversion masking in combination with other data storage modes. In other embodiments, flow 400 can be modified to support fewer or more selective data storage modes.

[0038] Figure 5 is a block diagram of the cache 500 of Figure 2, according to some embodiments. The cache 500 generally includes a coherent slave port 510, a master port 520, static random access memories (SRAMs) 530 and 532, and a cache controller 540.

[0039] Coherent slave port 510 is an upstream port bidirectionally connected to data fabric 260 and has a first input for receiving a signal labeled "CACHE RESPONSE", a second input for receiving a signal labeled "CACHE RESPONSE DATA", a first output for providing a signal labeled "DATA FABRIC REQUESTS", and a second output for providing a signal labeled "DATA FABRIC WRITE DATA". Master port 520 is a downstream port and has a first input for receiving a signal labeled "CACHE REQUESTS", a second input for receiving a signal labeled "CACHE WRITE DATA", a first output for providing a signal labeled "UMC RESPONSE", a second output for providing a signal labeled "UMC RESPONSE DATA", and a downstream port connected to memory controller 271. SRAM 530 has an input for receiving an address and data and an output for providing data. Multiplexer 531 is associated with SRAM 530 and has a first input, a second input, and an output connected to the input of SRAM 530. Similarly, SRAM 532 has an input for receiving an address and data and an output for providing data. Multiplexer 533 is associated with SRAM 532 and has a first input, a second input, and an output connected to the input of SRAM 532.

[0040] Cache controller 540 includes transaction queue / scheduler 541, victim queue 542, multiplexer 543, data buffer 544, response data buffer 545, OR gate 546, multiplexer 547, response scheduler 548, and data evaluation circuit 550. Transaction queue / scheduler 541 has a first input connected to a first output of coherent slave port 510 for receiving DATA FABRIC REQUESTS, a second input, a first output for providing a signal labeled "CACHE READ REQUESTS", a second output for providing a victim cache line, a third output for providing a response, and a fourth output for providing metadata for the cache line. Victim queue 542 has an input connected to a second output of transaction queue / scheduler 541 and an output for providing a value labeled "VICTIMS". Multiplexer 543 has a first input connected to a first output of transaction queue / scheduler 540 for receiving CACHE READ REQUESTS, a second input connected to an output of victim queue 542 for receiving VICTIMS, and an output connected to a first input of master port 520 for providing CACHE REQUESTS. Data buffer 544 has a first input, a second input connected to a second output of coherent slave port 510 for receiving DATA FABRIC WRITE DATA, a first output connected to first inputs of multiplexers 531 and 533, and a second output connected to a second input of master port 520 for providing CACHE WRITE DATA.

[0041] Response data buffer 545 has an input connected to the second output of master port 520 for receiving UMC RESPONSE DATA, a first output, and a second output connected to the second inputs of multiplexers 531 and 533. OR gate 546 has a first input connected to the output of SRAM 530, a second input connected to the output of SRAM 532, and an output connected to the first input of data buffer 544. Multiplexer 547 has a first input connected to the first output of data buffer 544, a second input connected to the first output of response data buffer 545, and an output connected to the second input of coherent slave port 510 for providing CACHE RESPONSE DATA. Response scheduler 548 has a first input connected to the first output of master port 520 for receiving a UMC RESPONSE, a second input connected to a third output of transaction queue / scheduler 541, and an output for providing a CACHE RESPONSE to the first input of coherent slave port 510.

[0042] Data evaluation circuit 550 has a first input connected to a first output of coherent slave port 510, a second input connected to a second output of coherent slave port 510, and an output connected to a second input of transaction queue / scheduler 541.

[0043] Cache 500 is a last-level cache (LLC) and coherency point in data processing system 200, although in accordance with the principles herein cache 500 may be at another level of a cache hierarchy. It has a large data store implemented using SRAMs 530 and 532 as a cache memory organized as a set-associative inclusive LLC and thus separated into two parts to facilitate routing delays. For example, in one embodiment cache 500 may be a 4MB (4 megabytes) 16-way set associative cache in a system having 4GB (4 gigabytes) of main memory. Thus, at any time cache 500 stores less than 1 / 1000th of the contents of main memory.

[0044] Data evaluation circuit 550 receives DATA FABRIC WRITE DATA from coherent slave port 510 and UMC RESPONSE DATA from response data buffer 545, and performs evaluation of the data to selectively set the DATA STATUS and SF bits according to flow 400 of Figure 4. In particular, data evaluation circuit 550 determines whether there are masked double words in the data, whether there are double words with a value of 0x0, and if so, how many. If the flow proceeds to the data inversion mask leg, data evaluation circuit 550 determines whether the number of data bit transitions of each pair of consecutive double words exceeds half the transfer width, and if so, sets the corresponding data bus inversion bit in the cache memory formed by SRAMs 530 and 532.

[0045] By performing selective data inversion masking of data stored internally, cache 500 allows fewer transitions in data signals transmitted continuously across large, highly capacitive buses that require significant energy to switch the logic state of signals on the bus. The data is not only inverted, but is pre-stored in an inverted form for faster access. The ZVM, DIM and SF bits are transmitted over some or all of the data path from cache 500 to the requesting device or a higher level cache, but are ultimately converted back to normal format before being read and processed by the requesting device. This technique reduces power consumption in modern complex SOCs, thereby contributing to longer battery life and a better user experience for the end products in which they are used.

[0046] An integrated circuit implementing SOC 210 or cache 500 or a portion thereof may be described or represented by a computer accessible data structure in the form of a database or other data structure that can be read by a program and used to directly or indirectly manufacture the integrated circuit. For example, the data structure may be a behavioral or register-transfer level (RTL) description of the hardware functionality in a high-level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool that can synthesize the description to generate a netlist that includes a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functionality of the hardware that comprises the integrated circuit. The netlist may then be placed and routed to generate a data set that describes the geometric shapes to be applied to a mask. The mask may then be used in various semiconductor manufacturing processes to manufacture the integrated circuit. Alternatively, the database on the computer accessible storage medium may be a netlist (with or without a synthesis library) or a data set, or Graphic Data System (GDS) II data, if desired.

[0047] Although specific embodiments have been described, various modifications to these embodiments will be apparent to those skilled in the art. For example, cache 500 may be an LLC or another cache higher in the cache hierarchy. In addition, the selective data inversion mask state may be combined with other selective encoding options, such as selective inversion to bias data words to a particular logic state, and other combinations of supported encoding options. Furthermore, although an inversion was selected when more than half the number of data bits changed logic state, the number of data bits that trigger an inversion may be greater to account for the extra energy required to perform the inversion. Although the disclosed technique was performed for an initial cache linefill operation, data inversion may be evaluated again after the data is modified while allocated in the cache.

[0048] Therefore, the appended claims are intended to cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.

Claims

1. A cache, An upstream port; a cache memory for storing cache lines, each cache line having a line width; a cache controller coupled to the upstream port and the cache memory, the upstream port transferring data words having a transfer width less than the line width, the cache controller selectively determining, in response to a cache line fill, data bus inversion information for a sequence of data words having the transfer width based on whether a number of transitions of data bits of each pair of consecutive data words exceeds half of the transfer width, and storing the data bus inversion information in the cache memory along with selected inverted data words for the cache line fill. cache.

2. The cache controller a data evaluation circuit coupled to said upstream port for determining whether a number of transitions of data bits of each pair of said consecutive data words exceeds half of said transfer width, and if so, setting a corresponding data bus inversion bit in said cache memory; The cache of claim 1.

3. the data evaluation circuit determines whether more than a threshold number of data words in the first cache line have a value of zero; the cache controller stores a zero value mask state of the first cache line if more than the threshold number of data words have a value of zero and a zero value bit of each data word indicating whether each data word has a value of zero; The cache of claim 2.

4. The data evaluation circuit includes: inhibiting, in response to the zero value mask state, determining the data bus inversion information for the sequence of data words and storing the data bus inversion information in the cache memory with the selected inverted data words for the cache line fill. The cache of claim 3.

5. the data evaluation circuitry inhibits determining the data bus inversion information for the sequence of data words in response to the zero value mask state and storing the data bus inversion information in the cache memory with the selected inverted data words for the cache line fill. The cache of claim 3.

6. 1. A data processing system comprising: A plurality of memory access requesters; A plurality of memory access responders; a data fabric for selectively coupling the plurality of memory access requesters to the plurality of memory access responders; a cache coupled to the data fabric, The cache includes: a cache memory for storing cache lines, each cache line having a line width; a cache controller coupled to the cache memory for transferring data words having a transfer width less than the line width, the cache controller selectively determining, in response to a cache line fill, data bus inversion information for a sequence of data words having the transfer width based on whether a number of transitions of data bits of each pair of consecutive data words exceeds half of the transfer width, and storing the data bus inversion information in the cache memory along with selected inverted data words for the cache line fill. Data processing system.

7. The cache controller a data evaluation circuit coupled to said data fabric for determining whether a number of data bit transitions of each pair of said successive data words exceeds one-half of said transfer width, and if so, setting a corresponding data bus inversion bit in said cache memory; 7. The data processing system of claim 6.

8. the data evaluation circuit determines whether more than a threshold number of data words in the first cache line have a value of zero; the cache controller stores a zero value mask state of the first cache line if more than the threshold number of data words have a value of zero, and a zero value bit of each data word indicating whether each data word has the value of zero.

8. The data processing system of claim 7.

9. The data evaluation circuit includes: inhibiting, in response to the zero value mask state, determining the data bus inversion information for the sequence of data words and storing the data bus inversion information in the cache memory with the selected inverted data words for the cache line fill.

9. The data processing system of claim 8.

10. the data evaluation circuitry inhibits determining the data bus inversion information for the sequence of data words in response to the zero value mask state and storing the data bus inversion information in the cache memory with the selected inverted data words for the cache line fill.

9. The data processing system of claim 8.

11. the data fabric establishes a virtual connection using crossbar switching between each of the plurality of memory access requesters and each of the plurality of memory access responders.

7. The data processing system of claim 6.

12. the plurality of memory access requesters comprise a plurality of central processing unit cores each having at least one cache, the cache being a last level cache (LLC) of a cache hierarchy; 7. The data processing system of claim 6.

13. 1. A method for reducing energy consumption in a data processing system having a cache, comprising: receiving a cache line, the cache line including a plurality of data words; setting the state of the cache line to a data inversion mask state; determining, for each data word, whether more than half of a plurality of data bits in the data word transition between a previous data word and said data word; if so, inverting each of the plurality of data bits in the data word and setting a corresponding data bus inversion bit before storing the inverted data word in the cache; if no transition occurs, storing the data word in the cache without inverting any of the plurality of data bits and clearing the corresponding data bus inversion bit. method.

14. determining whether a number of data words in the cache line having a value of zero is greater than or equal to a threshold; if the number of data words in the cache line having a value of zero is greater than or equal to the threshold; setting the state of the cache line to a zero value mask state; for each data word in the cache line having a non-zero value, clearing a corresponding inversion mask bit and writing the data word to the cache; and for each data word of the cache line having a value of zero, setting a corresponding invert mask bit to inhibit writing of the data word to the cache.

14. The method of claim 13.

15. determining whether any data words of the received cache line are masked; if any data word of the received cache line is masked, writing an unmasked data word to the cache; determining whether any data words in the cache line remain masked after writing the unmasked data word to the cache; setting the state of the cache line to a write masked state if at least one data word in the cache line remains masked; and if no data word in the cache line remains masked, setting the state of the cache line to a normal state.

14. The method of claim 13.

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