Image pickup device and method for manufacturing image pickup device

Abstract

To provide an imaging element capable of reducing the wiring capacity, and a method for manufacturing the imaging element.SOLUTION: An imaging element according to one embodiment comprises: a first wiring layer having a plurality of first wirings extending in one direction; a first insulating film laminated to the first wiring layer and forming a gap between adjacent first wirings; a second insulating film that is laminated to the first insulating film and has a flat surface; and a first electroconductive film facing at least a portion of the first wirings across the first insulating film and the second insulating film.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to, for example, an imaging element having gaps between wirings and a method for manufacturing the imaging element. [Background technology]

[0002] In semiconductor devices, the spacing between elements and the wiring connecting elements within an element is becoming narrower as semiconductor integrated circuit elements are miniaturized. In response to this, for example, Patent Document 1 discloses a semiconductor device in which an air gap is formed between the wiring to reduce the capacitance between the wiring. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2008-193104 A Summary of the Invention [Problem to be solved by the invention]

[0004] Incidentally, in recent years, stacked image sensors have become common, and there is a demand for reducing wiring capacitance.

[0005] It is desirable to provide an imaging device that can reduce wiring capacitance and a manufacturing method thereof. [Means for solving the problem]

[0006] An image sensor according to an embodiment of the present disclosure includes: embedded in a fifth insulating film formed using a low dielectric constant material having a dielectric constant k of 3.0 or less; a first wiring layer having a plurality of first wirings extending in one direction; A fifth insulating film and A first wiring layer is laminated thereon, and a gap is formed between adjacent first wirings. and a recess is formed above a plurality of first wirings, the recess being formed using a low dielectric constant material having a dielectric constant k of 3.0 or less. A first insulating film and a second insulating film laminated on the first insulating film Shown in Flat surface , which is formed using a material having a higher polishing rate than the first insulating film. The semiconductor device includes a second insulating film, and a first conductive film facing at least a portion of the plurality of first wirings with the first insulating film and the second insulating film therebetween.

[0007] A method for manufacturing an image sensor according to an embodiment of the present disclosure includes: A fifth insulating film formed using a low dielectric constant material having a dielectric constant k of 3.0 or less. A first wiring layer having a plurality of first wirings extending in one direction embedded forming a first opening between adjacent first wirings in a predetermined region of the first wiring layer; Using low dielectric constant material with dielectric constant k of 3.0 or less forming a gap between the first wirings adjacent to each other by forming a first insulating film; Using a material with a higher polishing rate than the first insulating film After forming a second insulating film covering the first insulating film, the surface of the second insulating film is planarized, and a first conductive film is formed in a position directly opposite at least a portion of the multiple first wirings with the first insulating film and the second insulating film therebetween.

[0008] In the imaging element according to the embodiment of the present disclosure and the manufacturing method of the imaging element according to the embodiment, a first insulating film that forms a gap between adjacent first wirings is provided on a first wiring layer having a plurality of first wirings extending in one direction, and a second insulating film having a flat surface is further provided. This makes it possible to form a first conductive film that can be used as, for example, a pad electrode for bonding, at a position directly opposite at least some of the plurality of first wirings with the first insulating film and the second insulating film interposed therebetween. [Brief description of the drawings]

[0009] [Figure 1] 1 is a schematic diagram illustrating an example of a vertical cross-sectional configuration of a wiring structure according to an embodiment of the present disclosure. [Figure 2A] 2 is a schematic diagram illustrating an example of a horizontal cross-sectional configuration of the wiring structure illustrated in FIG. 1. [Figure 2B] 1. FIG. 4 is a schematic diagram illustrating another example of the horizontal cross-sectional configuration of the wiring structure illustrated in FIG. [Figure 3A] 2A to 2C are schematic cross-sectional views illustrating an example of a manufacturing process for the wiring structure shown in FIG. [Figure 3B] FIG. 3B is a schematic cross-sectional view showing an example of the manufacturing process following FIG. 3A. [Figure 3C] FIG. 3C is a schematic cross-sectional view showing an example of the manufacturing process subsequent to FIG. 3B. [Figure 3D] FIG. 3D is a schematic cross-sectional view showing an example of a manufacturing process subsequent to FIG. 3C. [Figure 3E] FIG. 3E is a schematic cross-sectional view illustrating an example of a manufacturing process subsequent to FIG. 3D. [Figure 3F] FIG. 3F is a schematic cross-sectional view showing an example of the manufacturing process subsequent to FIG. 3E. [Figure 3G] FIG. 3C is a schematic cross-sectional view showing an example of the manufacturing process subsequent to FIG. 3F. [Figure 4] FIG. 2 is a diagram illustrating the layout of a resist film. [Figure 5A] 2A to 2C are schematic plan views showing an example of a layout of a resist film and the shape of an opening formed thereby. [Figure 5B] 11A to 11C are schematic plan views showing another example of a layout of a resist film and the shape of an opening formed thereby. [Figure 6] 1 is a diagram illustrating an example of a vertical cross-sectional configuration of an imaging element according to an embodiment of the present disclosure. [Figure 7] 5 is a diagram illustrating an example of a schematic configuration of the imaging element illustrated in FIG. 4. [Figure 8] 5 is a diagram in which the wiring structure shown in FIG. 1 is applied to the imaging element shown in FIG. 4. [Figure 9] 8 is a diagram illustrating an example of a sensor pixel and a readout circuit illustrated in FIG. 7. [Figure 10] 8 is a diagram illustrating an example of a sensor pixel and a readout circuit illustrated in FIG. 7. [Figure 11] 8 is a diagram illustrating an example of a sensor pixel and a readout circuit illustrated in FIG. 7. [Figure 12] 8 is a diagram illustrating an example of a sensor pixel and a readout circuit illustrated in FIG. 7. [Figure 13] 1 is a diagram illustrating an example of a connection mode between a plurality of readout circuits and a plurality of vertical signal lines. [Figure 14] 5 is a diagram illustrating an example of a horizontal cross-sectional configuration of the image sensor illustrated in FIG. 4. [Figure 15] 5 is a diagram illustrating an example of a horizontal cross-sectional configuration of the image sensor illustrated in FIG. 4. [Figure 16]5 is a diagram illustrating an example of a wiring layout in a horizontal plane of the image sensor illustrated in FIG. 4. [Figure 17] 5 is a diagram illustrating an example of a wiring layout in a horizontal plane of the image sensor illustrated in FIG. 4. [Figure 18] 5 is a diagram illustrating an example of a wiring layout in a horizontal plane of the image sensor illustrated in FIG. 4. [Figure 19] 5 is a diagram illustrating an example of a wiring layout in a horizontal plane of the image sensor illustrated in FIG. 4. [Figure 20A] 5A to 5C are diagrams illustrating an example of a manufacturing process for the image sensor illustrated in FIG. [Figure 20B] FIG. 20B is a diagram illustrating an example of a manufacturing process subsequent to FIG. 20A. [Figure 20C] FIG. 20C is a diagram illustrating an example of the manufacturing process following FIG. 20B. [Figure 20D] FIG. 20D is a diagram illustrating an example of the manufacturing process following FIG. 20C. [Figure 20E] FIG. 20E is a diagram illustrating an example of the manufacturing process following FIG. 20D. [Figure 20F] FIG. 20F is a diagram illustrating an example of the manufacturing process following FIG. 20E. [Figure 20G] FIG. 20C is a diagram showing an example of the manufacturing process following FIG. 20F. [Figure 21A] 1A to 1C are schematic cross-sectional views illustrating an example of a manufacturing process for a wiring structure according to Modification 1 of the present disclosure. [Figure 21B] FIG. 21B is a schematic cross-sectional view illustrating an example of the manufacturing process following FIG. 21A. [Figure 21C] FIG. 21C is a schematic cross-sectional view illustrating an example of the manufacturing process following FIG. 21B. [Figure 21D] FIG. 21D is a schematic cross-sectional view showing an example of the manufacturing process following FIG. 21C. [Figure 21E] FIG. 21E is a schematic cross-sectional view illustrating an example of the manufacturing process following FIG. 21D. [Figure 21F] FIG. 21F is a schematic cross-sectional view showing an example of the manufacturing process subsequent to FIG. 21E. [Figure 21G] FIG. 21C is a schematic cross-sectional view showing an example of the manufacturing process subsequent to FIG. 21F. [Fig. 21H] FIG. 21F is a schematic cross-sectional view showing an example of the manufacturing process following FIG. 21G. [Figure 21I] FIG. 21C is a schematic cross-sectional view showing an example of the manufacturing process following FIG. 21H. [Figure 21J] FIG. 21C is a schematic cross-sectional view showing an example of the manufacturing process following FIG. 21I. [Figure 21K] 21B is a schematic cross-sectional view showing an example of the manufacturing process following FIG. 21J. [Figure 22] 1A to 1C are schematic cross-sectional views illustrating a manufacturing process of a wiring structure as a reference example. [Figure 23A] 11A to 11C are schematic cross-sectional views illustrating an example of a manufacturing process for a wiring structure according to Modification 2 of the present disclosure. [Figure 23B] FIG. 23B is a schematic cross-sectional view illustrating an example of the manufacturing process following FIG. 23A. [Figure 23C] FIG. 23C is a schematic cross-sectional view illustrating an example of the manufacturing process following FIG. 23B. [Figure 23D] FIG. 23D is a schematic cross-sectional view illustrating an example of the manufacturing process following FIG. 23C. [Figure 23E] FIG. 23E is a schematic cross-sectional view illustrating an example of the manufacturing process following FIG. 23D. [Figure 23F] FIG. 23F is a schematic cross-sectional view illustrating an example of the manufacturing process following FIG. 23E. [Figure 24A] 11A to 11C are schematic cross-sectional views illustrating an example of a manufacturing process for a wiring structure according to Modification 3 of the present disclosure. [Figure 24B] FIG. 24B is a schematic cross-sectional view showing an example of the manufacturing process subsequent to FIG. 24A. [Figure 24C] FIG. 24C is a schematic cross-sectional view showing an example of the manufacturing process following FIG. 24B. [Figure 24D] FIG. 24D is a schematic cross-sectional view showing an example of the manufacturing process following FIG. 24C. [Figure 24E] FIG. 24E is a schematic cross-sectional view illustrating an example of the manufacturing process following FIG. 24D. [Figure 24F] FIG. 24F is a schematic cross-sectional view showing an example of the manufacturing process following FIG. 24E. [Figure 24G] FIG. 24F is a schematic cross-sectional view showing an example of the manufacturing process. [Fig. 24H] FIG. 24C is a schematic cross-sectional view showing an example of the manufacturing process following FIG. 24G. [Figure 25A]11A to 11C are schematic cross-sectional views illustrating an example of a manufacturing process for a wiring structure according to Modification 4 of the present disclosure. [Figure 25B] FIG. 25B is a schematic cross-sectional view showing an example of the manufacturing process following FIG. 25A. [Figure 25C] FIG. 25C is a schematic cross-sectional view showing an example of the manufacturing process subsequent to FIG. 25B. [Figure 25D] FIG. 25D is a schematic cross-sectional view illustrating an example of the manufacturing process following FIG. 25C. [Figure 25E] FIG. 25E is a schematic cross-sectional view illustrating an example of the manufacturing process subsequent to FIG. 25D. [Figure 25F] FIG. 25C is a schematic cross-sectional view illustrating an example of the manufacturing process subsequent to FIG. 25E. [Figure 25G] FIG. 25C is a schematic cross-sectional view showing an example of the manufacturing process subsequent to FIG. 25F. [Figure 26] 13 is a diagram illustrating an example of a vertical cross-sectional configuration of an imaging element according to a fifth modified example of the present disclosure. FIG. [Figure 27] 13 is a diagram illustrating an example of a vertical cross-sectional configuration of an imaging element according to a sixth modification of the present disclosure. FIG. [Figure 28] 13 is a diagram illustrating an example of a horizontal cross-sectional configuration of an imaging element according to a seventh modification of the present disclosure. FIG. [Figure 29] 13 is a diagram illustrating another example of the horizontal cross-sectional configuration of an image sensor according to Modification 7 of the present disclosure. FIG. [Diagram 30] 13 is a diagram illustrating an example of a horizontal cross-sectional configuration of an imaging element according to Modification 8 of the present disclosure. FIG. [Diagram 31] 13 is a diagram illustrating an example of a horizontal cross-sectional configuration of an imaging element according to a ninth modification of the present disclosure. FIG. [Diagram 32] 23 is a diagram illustrating an example of a horizontal cross-sectional configuration of an imaging element according to a tenth modification of the present disclosure. FIG. [Diagram 33] 23 is a diagram illustrating another example of the horizontal cross-sectional configuration of an image sensor according to the tenth modification of the present disclosure. FIG. [Diagram 34] 23 is a diagram illustrating another example of the horizontal cross-sectional configuration of an image sensor according to the tenth modification of the present disclosure. FIG. [Diagram 35] FIG. 23 is a diagram illustrating an example of a circuit configuration of an image sensor according to an eleventh modification of the present disclosure. [Diagram 36]FIG. 37 is a diagram illustrating an example in which the imaging element of FIG. 35 according to Modification 12 of the present disclosure is configured by stacking three substrates. [Figure 37] FIG. 23 is a diagram illustrating an example in which a logic circuit according to a thirteenth modification of the present disclosure is formed separately on a substrate on which sensor pixels are provided and a substrate on which a readout circuit is provided. [Figure 38] FIG. 23 is a diagram illustrating an example in which a logic circuit according to a fourteenth modification of the present disclosure is formed on a third substrate. [Figure 39] FIG. 1 is a diagram illustrating an example of a schematic configuration of an imaging system including an imaging element according to the above embodiment and its modified example. [Diagram 40] 40 is a diagram showing an example of an imaging procedure in the imaging system of FIG. 39. [Diagram 41] 1A to 1C are diagrams illustrating outlines of configuration examples of a non-stacked solid-state imaging element and a stacked solid-state imaging element to which the technology according to the present disclosure can be applied. [Diagram 42] 1 is a cross-sectional view showing a first configuration example of a stacked solid-state imaging element. [Diagram 43] FIG. 11 is a cross-sectional view showing a second configuration example of a stacked solid-state imaging element. [Diagram 44] FIG. 11 is a cross-sectional view showing a third configuration example of a stacked solid-state imaging element. [Diagram 45] 11 is a cross-sectional view showing another configuration example of a stacked solid-state imaging element to which the technology according to the present disclosure can be applied. [Figure 46] 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; [Figure 47] 4 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit; FIG. [Figure 48] 1 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system. [Figure 49] 2 is a block diagram showing an example of a functional configuration of a camera head and a CCU. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment of the present disclosure will be described in detail with reference to the drawings. The following description is a specific example of the present disclosure, and the present disclosure is not limited to the following aspect. Furthermore, the present disclosure is not limited to the arrangement, dimensions, dimensional ratios, etc. of each component shown in each drawing. The order of description is as follows. 1. Embodiment (An example of an image sensor in which an insulating film made of a different material is laminated on a wiring layer having a plurality of wirings that extend in one direction and have gaps between adjacent wirings, and a conductive film that serves as, for example, a pad electrode for bonding is disposed above the plurality of wirings with the insulating film in between) 1-1. Wiring structure configuration 1-2. Manufacturing method of wiring structure 1-3.Image sensor configuration 1-4. Manufacturing method of image sensor 1-5. Actions and Effects 2. Variations 2-1. Modification 1 (another example of the manufacturing process of the wiring structure) 2-2. Modification 2 (another example of the manufacturing process of the wiring structure) 2-3. Modification 3 (another example of the manufacturing process of the wiring structure) 2-4. Modification 4 (another example of the manufacturing process of the wiring structure) 2-5. Modification 5 (Example using a flat TG) 2-6. Modification 6 (Example of using Cu-Cu bonding on the outer edge of the panel) 2-7. Modification 7 (Example of providing an offset between sensor pixels and readout circuit) 2-8. Modification 8 (Example in which the silicon substrate on which the readout circuit is provided is island-shaped) 2-9. Modification 9 (Example in which the silicon substrate on which the readout circuit is provided is island-shaped) 2-10. Modification 10 (Example of sharing FD among eight sensor pixels) 2-11. Modification 11 (Example in which the column signal processing circuit is configured with a general column ADC circuit) 2-12. Modification 12 (Example of imaging device configured by stacking seven substrates) 2-13. Modification 13 (Logic circuit provided on first and second substrates) 2-14. Modification 14 (Example in which logic circuit is provided on seventh substrate) 3. Application Examples 4. Application Examples

[0011] <1. Preferred embodiment> Fig. 1 is a schematic diagram showing an example of a vertical cross-sectional configuration of a wiring structure (wiring structure 100) according to an embodiment of the present disclosure. Fig. 2A is a schematic diagram showing an example of a horizontal cross-sectional configuration of the wiring structure 100 shown in Fig. 1. Fig. 2B is a schematic diagram showing another example of a horizontal cross-sectional configuration of the wiring structure 100 shown in Fig. 1. Fig. 1 corresponds to a cross section taken along line II shown in Fig. 2A. The wiring structure 100 has, for example, a multilayer wiring structure in which a plurality of wiring layers are stacked, and is applicable, for example, to an image sensor 1 described later.

[0012] The wiring structure 100 of the present embodiment is formed by laminating an insulating film 123 that forms a gap G between adjacent wirings 112X2 and 112X3, between wirings 112X3 and 112X4, and between wirings 112X4 and 112X5 in this order on a wiring layer 112 having a plurality of wirings (e.g., wirings 112X1 to 112X6) extending in one direction (e.g., the Y-axis direction). Furthermore, a conductive film 127 (specifically, a conductive film 127X1) is provided with the insulating film 123 and the insulating film 124 between them at a position directly facing at least a portion of the plurality of wirings 112X1 to 112X6 extending in one direction (e.g., wirings 112X1 to 112X4 in FIG. 1). The multiple wirings 112X1 to 112X6 and the wiring layer 112 correspond to a specific example of a "first wiring" and a "first wiring layer" of the present disclosure, respectively. The insulating film 123 corresponds to a specific example of a "first insulating film" of the present disclosure, and the insulating film 124 corresponds to a specific example of a "second insulating film" of the present disclosure. Furthermore, the conductive film 127X1 corresponds to a specific example of a "first conductive film" of the present disclosure.

[0013] (1-1. Wiring Structure Configuration) The wiring structure 100 has a configuration in which a first layer 110 and a second layer 120 are laminated in this order on, for example, a silicon substrate (not shown). The first layer 110 has a wiring layer 112 consisting of a plurality of wirings (for example, wirings 112X1 to 112X6), and the second layer 120 has, for example, an insulating film 122 that forms a gap G between adjacent wirings of the plurality of wirings 112X1 to 112X5 provided on the first layer 110, an insulating film 123 that covers the insulating film 122 and has a flat surface, and a conductive film 127 formed between the insulating film 122 and the insulating film 123. The conductive film 127 has, for example, a conductive film 127X1 provided above the gap formation region 100X in which the gap G is formed, and a conductive film 127X2 provided above a wiring (for example, wiring 112X6) in which no gap G is formed.

[0014] The first layer 110 has a plurality of wirings (for example, wirings 112X1 to 112X6) in an insulating film 111. Wiring layer 112 is embedded and formed.

[0015] The insulating film 111 is formed using, for example, a low-dielectric constant material (Low-k material) having a relative dielectric constant (k) of 3.0 or less. Specifically, examples of the material for the insulating film 111 include SiOC, SiOCH, porous silica, SiOF, inorganic SOG, organic SOG, and organic polymers such as polyallyl ether.

[0016] The wiring layer 112 is made up of a plurality of wirings extending in one direction, for example, and has wirings 112X1 to 112X6 extending in the Y-axis direction. The wirings 112X1 to 112X6 are formed in parallel with, for example, Line (L) / Space (S)=40 to 200 nm / 40 to 200 nm. The wirings 112X1 to 112X6 are formed, for example, by embedding in an opening H1 provided in the insulating film 111, and are composed of, for example, a barrier metal 112A formed on the side and bottom of the opening H1, and a metal film 112B that embeds the opening H1. Examples of materials for the barrier metal 112A include simple substances such as Ti (titanium) or Ta (tantalum), or nitrides or alloys thereof. Examples of materials for the metal film 112B include metal materials mainly composed of low-resistance metals such as Cu (copper), W (tungsten), or aluminum (Al).

[0017] The first layer 110 has openings H2 for forming gaps G between adjacent wirings, specifically, for example, between the wirings 112X2 and 112X3, between the wirings 112X3 and 112X4, and between the wirings 112V4 and 112X5. The openings H2 correspond to gap formation regions 100X described later.

[0018] In the opening H2, the insulating film 111 between adjacent wirings (between the wiring 112X2 and the wiring 112X3, between the wiring 112X3 and the wiring 112X4, and between the wiring 112V4 and the wiring 112X5) is dug to a predetermined depth by dry etching using a photolithography technique described later. The wirings (wirings 112X2, 112X3, 112X4, and 112X5) in the opening H2 have their upper surfaces partially or entirely recessed by dry etching using a photolithography technique described later, and have a cross-sectional shape different from that of the wirings (e.g., wirings 112X1 and 112X6) outside the opening H2. In particular, as will be described in detail later, the ends of the opening H2 in the arrangement direction (X-axis direction) of the multiple wirings 112X1 to 112X6 are formed on the wirings (e.g., wirings 112X2 and 112X5) at both ends of the multiple wirings in which the gap G is formed. For this reason, the wirings 112X2 and 112X5 each have an asymmetric cross-sectional shape. Specifically, as shown in FIG. 1, the wirings 112X2 and 112X5 have a step formed at the end of the upper surface on the side adjacent to the gap G, and the end of the upper surface on the opposite side has a substantially right-angled cross-sectional shape.

[0019] The second layer 120 is formed by laminating a plurality of insulating films (insulating films 121 to 126) and, for example, a conductive film 127 is embedded in the uppermost insulating film 126. Specifically, the insulating films 121, 122, 123, 124, 125, and 126 are laminated in this order from the first layer 110 side. Openings H2 between the wiring 112X2 and the wiring 112X3, between the wiring 112X3 and the wiring 112X4, and between the wiring 112V4 and the wiring 112X5 are closed by the insulating film 123 constituting the second layer 120. As a result, gaps G that reduce the capacitance between the parallel wirings are formed between the wirings 112X2 and 112X3, between the wirings 112X3 and 112X4, and between the wirings 112V4 and 112X5 over the entire or partial region in the extension direction of the wirings 112X1 to 112X6 (gap formation region 100X).

[0020] Specifically, the gap formation region 100X is provided continuously between the wiring 112X2 and the wiring 112X3, between the wiring 112X3 and the wiring 112X4, and between the wiring 112V4 and the wiring 112X5, as shown in Fig. 2A. Alternatively, as in the image sensor 1 described later, a plurality of wirings (e.g., a pad electrode 58 and a plurality of vertical signal lines 24) are laminated with an insulating layer (e.g., an insulating layer 57) therebetween, and are electrically connected at substantially opposing positions through a via V, and in the case where a gap G is formed between a plurality of wirings (a plurality of vertical signal lines 24) on the lower layer side, it is preferable that the gap formation region 100X is formed avoiding the via V, as shown in Fig. 2B. In other words, the gap formation region 100X may be formed by dividing the via V into a plurality of regions.

[0021] The insulating film 121 is for preventing diffusion of copper (Cu) when the wirings 112X1 to 112X6 are formed using copper (Cu), for example. The insulating film 121 is provided so as to cover the insulating film 111, the buried wirings 112X1 and 112X6, and a part of the wirings 112X2 and 112X5 where the ends of the opening H2 are formed, except for the opening H2. The insulating film 121 is formed of, for example, silicon oxide (SiO x ), silicon nitride (SiN x ) or SiC x N y It is formed using the following:

[0022] The insulating film 122, like the insulating film 121, is intended to prevent diffusion of copper (Cu) when the wirings 112X1 to 112X6 are formed using copper (Cu), for example. The insulating film 122 is provided on the insulating film 121 and extends so as to cover the side and bottom surfaces of the opening H2. As described above, the insulating film 122 can be formed by using an insulating material that prevents diffusion of copper (Cu) and a manufacturing method that has excellent step coverage. Specifically, the insulating film 122 is made of, for example, silicon oxide (SiO x ), silicon nitride (SiN x ) or SiC x N yThe above are formed by using, for example, an ALD (Atomic Layer Deposition) method.

[0023] The insulating film 123 is provided on the insulating film 122 and serves to form a gap G between adjacent wirings in the opening H2. The insulating film 123 has low coverage and is formed using, for example, a low-k material having a relative dielectric constant (k) of 3.0 or less. Specifically, examples of materials for the insulating film 132A include SiOC, SiOCH, porous silica, SiOF, inorganic SOG, organic SOG, and organic polymers such as polyallyl ether.

[0024] The insulating film 124 is provided on the insulating film 123, and is intended to fill the irregularities of the insulating film 123 above the gap G and to form a flat surface above the gap G on which devices can be stacked using hybrid bonding such as Cu-Cu bonding, as will be described in detail later. As a material for the insulating film 124, for example, it is preferable to use a material that has a higher polishing rate than the insulating film 123 and has a relative dielectric constant (k) of, for example, about 4.0. As such a material, for example, silicon oxide (SiO x ), SiOC, SiOF, SiON, etc. The insulating film 124 may be a single layer film made of one of the above materials, or may be formed as a laminate film made of two or more of the above materials.

[0025] The insulating film 125 is intended to reduce warping due to stress that occurs when a conductive film 127, which will be described later, is formed. The insulating film 125 is formed by, for example, a CVD (Chemical Vapor Deposition) method, and is made of, for example, silicon oxide (SiO x ), silicon nitride (SiN x ) or the like.

[0026] The insulating film 126 is provided on the insulating film 125, and forms, for example, a bonding surface between a second substrate 20 and a third substrate 30 of the image sensor 1, which will be described later. The material of the insulating film 126 is preferably a material having a higher polishing rate than the insulating film 123 and a relative dielectric constant (k) of, for example, about 4.0, so that the bonding surface can be flattened. Examples of such materials include silicon oxide (SiO x ), SiOC, SiOF, SiON, etc. The insulating film 126 may be a single layer film made of one of the above materials, or may be formed as a laminated film made of two or more of the above materials.

[0027] The conductive film 127 is, for example, a wiring layer provided directly above the wiring layer 112 having the wirings 112X1 to 112X6 extending in one direction, and is formed by embedding in an opening H3 provided in a part of the insulating film 126 and the insulating film 125, and forms the same plane as the insulating film 126. The conductive film 127 has a plurality of conductive films (for example, the conductive film 127X1 and the conductive film 127X2), and at least a part of the conductive film 127 extends in one direction and is provided so as to face at least a part of the wirings 112X1 to 112X6. As an example, in FIG. 1, the conductive film 127X1 is formed, for example, at a position facing the wirings 112X2, 112X3, and 112X4 having the gap G between the wirings, extending in the Y-axis direction like the wirings 112X2 and 112X3. An opening H4 is further provided in the opening H3, penetrating the insulating films 121 to 125 and reaching the wiring 112X1. The conductive film 127X1 is also embedded in this opening H4 and is electrically connected to the wiring 112X1.

[0028] The conductive film 127 is composed of a barrier metal 127A formed on the side and bottom of the openings H3 and H4, and a metal film 127B filling the openings H3 and H4. Examples of materials for the barrier metal 127A include simple substances such as Ti (titanium) or Ta (tantalum), or nitrides or alloys thereof. Examples of materials for the metal film 127B include metal materials mainly made of low-resistance metals such as Cu (copper), W (tungsten), or aluminum (Al).

[0029] (1-2. Method for manufacturing wiring structure) First, the wiring layer 112 including the wirings 112X1 to 112X6 is embedded in the insulating film 111, and then the surface is polished by, for example, a chemical mechanical polishing (CMP) method to form the first layer 110. Next, as shown in Fig. 3A, the insulating film 121 is formed on the first layer 110 by, for example, a physical vapor deposition (PVD) method or a CVD method to a thickness of, for example, 5 nm to 250 nm.

[0030] Next, as shown in Fig. 3B, a resist film 131 having openings 131H at positions corresponding to the wirings 121X2 to 112X5 is patterned on the insulating film 121 using a photolithography technique. Then, as shown in Fig. 3C, the insulating film 121, parts of the wirings 112X2 to 112X5, and the insulating film 111 exposed in the openings 131H are, for example, dry etched to form openings H2 (void formation regions X). At this time, it is preferable to form the pattern of the resist film 131 so that the void formation regions 100X have the following pattern.

[0031] 4, it is preferable that the end 100Ex of the gap formation region 100X in the arrangement direction (X-axis direction) of the multiple wirings (e.g., wirings 112X2 to 112X5) is formed on both ends of the multiple wirings (wirings 112X2, 112X5) that form the gap G between the wirings. Furthermore, when other wirings (not shown) are formed above the multiple wirings (e.g., wirings 112X2, 112X5) with an insulating film therebetween and a via V is provided for electrically connecting the other wirings, it is preferable that the end 100Ey of the gap formation region 100X in the extension direction (Y-axis direction) of the multiple wirings is spaced a predetermined distance from the via V.

[0032] Specifically, the distance X between the end 100Ex of the void formation region 100X and the side of the wiring (for example, the wiring 112X2) on which the end 100Ex is formed on the side where the void G is formed is preferably smaller than the width D of the wiring 112X2 (D>X). In addition, the distance Y between the end 100Ey of the void formation region 100X and the via V is preferably smaller than the distance L from the midpoint of the void formation region 100X in the Y-axis direction to the via V (L>Y). Furthermore, it is preferable that X and Y respectively satisfy the following formulas (1) and (2). By satisfying the above, the end 100Ex of the void formation region 100X is formed on the wiring (wirings 112X2, 112X5) at both ends of the multiple wirings on which the void G is formed, and the end 100Ey of the void formation region 100X is formed to avoid the via V. (Number 1) X>√((CD 3σ_配線 / 2) 2 +(CD 3σ_空隙形成領域 / 2) 2 +(OVL 3σX / 2) 2 ) · · · (1) (Number 2) Y>√((CD 3σ_ヒ゛ア / 2) 2 +(CD 3σ_空隙形成領域 / 2) 2 +(OVL 3σY / 2) 2 ) · · · (2)

[0033] In addition, CD 3σ_配線 is the standard deviation (variation) of both ends of the wiring (e.g., wiring 112X2) in the X-axis direction × 3, and CD 3σ_空隙形成領域 is the standard deviation (variation) of both ends of the void formation region 100X in the X-axis direction × 3, and CD 3σ_ヒ゛ア is the standard deviation (variation) of both ends of the via V in the X-axis direction × 3. 3σX and L 3σY are respectively, for example, the standard deviation (variation) of the central position of the pattern of the resist film 131 in the X-axis direction and the Y-axis direction×3.

[0034] Furthermore, it is preferable that the opening 131H of the resist film 131 forming the gap formation region 100X has the following planar shape. For example, as shown in FIG. 5A, if the opening 131H of the resist film 131 is rectangular (A), the opening H2 formed thereby becomes substantially elliptical (B) due to the optical proximity effect, and the formation range of the gap G formed between each wiring line varies. For this reason, it is preferable that the planar shape of the opening 131H of the resist film 131 has a shape (A) in which optical proximity effect correction (OPC) is added to the four corners of the opening 131, as shown in FIG. 5B. As a result, the opening H2 (B) having a substantially rectangular shape is formed, and the formation range of the gap G formed between each wiring line becomes substantially uniform.

[0035] Next, after removing the resist film 131, as shown in Fig. 3D, an insulating film 122 is formed to a thickness of, for example, 0.5 nm to 15 nm, covering the insulating film 121 and the side and bottom surfaces of the opening H2, for example, by ALD. Then, as shown in Fig. 3E, an insulating film 123 is formed to a thickness of, for example, 100 nm to 500 nm, made of, for example, SiOC or silicon nitride, for example, by CVD. This closes the opening H2, and gaps G are formed between the wiring 112X2 and the wiring 112X3, between the wiring 112X3 and the wiring 112X4, and between the wiring 112X4 and the wiring 112V5.

[0036] Next, as shown in FIG. 3F, a film such as SiO x3G, the insulating film 124 is polished by, for example, CMP to flatten the surface.

[0037] Next, the insulating film 125 is formed on the insulating film 124 with a thickness of, for example, 50 nm to 500 nm by using, for example, a CVD method, and then the insulating film 126 is formed on the insulating film 125 with a thickness of, for example, 100 nm to 2 μm by using, for example, a CVD method. Next, using the same method as the opening H2, the insulating film 126 and a part of the insulating film 125 are, for example, dry-etched to form an opening H3, and then an opening H4 is formed in the opening H3, penetrating the insulating films 121 to 125 and reaching the wiring 112X1. Thereafter, a barrier metal 127A is formed on the side and bottom surfaces of the openings H3 and H4 by using, for example, a sputtering method, and then a metal film 127B is formed in the openings H3 and H4 by using, for example, plating. Finally, the barrier metal 127A and the metal film 127B formed on the insulating film 126 are polished and removed to form a flat surface on which the insulating film 126 and the conductive film 127 form the same plane. Through the above steps, the wiring structure 100 shown in FIG. 1 is completed.

[0038] (1-3. Configuration of the image sensor) FIG. 6 shows an example of a vertical cross-sectional configuration of an image sensor (image sensor 1) according to an embodiment of the present disclosure. FIG. 7 shows an example of a schematic configuration of the image sensor 1 shown in FIG. 6. The image sensor 1 is an image sensor having a three-dimensional structure in which a first substrate 10 having a sensor pixel 12 for performing photoelectric conversion on a semiconductor substrate 11, a second substrate 20 having a readout circuit 22 for outputting an image signal based on the charge output from the sensor pixel 12 on a semiconductor substrate 21, and a third substrate 30 having a logic circuit 32 for processing the pixel signal on a semiconductor substrate 31 are stacked. The wiring structure 100 is applied to a wiring structure near a bonding surface of the second substrate 20 bonded to the third substrate 30, for example, as shown in FIG. 8.

[0039] As described above, the first substrate 10 has a plurality of sensor pixels 12 that perform photoelectric conversion on the semiconductor substrate 11. The semiconductor substrate 11 corresponds to a specific example of the "first semiconductor substrate" of the present disclosure. The plurality of sensor pixels 12 are arranged in a matrix in the pixel region 13 of the first substrate 10. The second substrate 20 has a readout circuit 22 that outputs a pixel signal based on the charge output from the sensor pixel 12, one for every four sensor pixels 12, on the semiconductor substrate 21. The semiconductor substrate 21 corresponds to a specific example of the "second semiconductor substrate" of the present disclosure. The second substrate 20 has a plurality of pixel driving lines 23 extending in the row direction and a plurality of vertical signal lines 24 extending in the column direction. The third substrate 30 has a logic circuit 32 that processes pixel signals on the semiconductor substrate 31. The semiconductor substrate 31 corresponds to a specific example of the "third semiconductor substrate" of the present disclosure. The logic circuit 32 has, for example, a vertical driving circuit 33, a column signal processing circuit 34, a horizontal driving circuit 35, and a system control circuit 36. The logic circuit 32 (specifically, the horizontal drive circuit 35) outputs to the outside the output voltage Vout for each sensor pixel 12. In the logic circuit 32, for example, CoSi 2 Alternatively, a low resistance region made of silicide such as NiSi or NiAligned Silicide may be formed using a salicide (Self Aligned Silicide) process.

[0040] The vertical drive circuit 33, for example, sequentially selects the plurality of sensor pixels 12 on a row-by-row basis. The column signal processing circuit 34, for example, performs correlated double sampling (CDS) processing on pixel signals output from each sensor pixel 12 in the row selected by the vertical drive circuit 33. The column signal processing circuit 34, for example, performs CDS processing to extract a signal level of the pixel signal and holds pixel data according to the amount of light received by each sensor pixel 12. The horizontal drive circuit 35, for example, sequentially outputs the pixel data held in the column signal processing circuit 34 to the outside. The system control circuit 36, for example, controls the driving of each block (the vertical drive circuit 33, the column signal processing circuit 34, and the horizontal drive circuit 35) in the logic circuit 32.

[0041] Fig. 9 shows an example of the sensor pixels 12 and the readout circuit 22. Below, a case will be described in which four sensor pixels 12 share one readout circuit 22 as shown in Fig. 9. Here, "shared" refers to the outputs of the four sensor pixels 12 being input to a common readout circuit 22.

[0042] Each sensor pixel 12 has components in common with each other. In Fig. 9, in order to distinguish the components of each sensor pixel 12 from each other, identification numbers (1, 2, 3, 4) are added to the end of the reference numeral of the component of each sensor pixel 12. In the following, when it is necessary to distinguish the components of each sensor pixel 12 from each other, an identification number is added to the end of the reference numeral of the component of each sensor pixel 12, but when it is not necessary to distinguish the components of each sensor pixel 12 from each other, the identification number at the end of the reference numeral of the component of each sensor pixel 12 is omitted.

[0043] Each sensor pixel 12 has, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD that temporarily holds the charge output from the photodiode PD via the transfer transistor TR. The photodiode PD performs photoelectric conversion to generate a charge according to the amount of received light. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to a reference potential line (for example, ground). The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TR is electrically connected to a pixel drive line 23. The transfer transistor TR is, for example, a CMOS (Complementary Metal Oxide Semiconductor) transistor.

[0044] The floating diffusions FD of the sensor pixels 12 sharing one readout circuit 22 are electrically connected to each other and to an input terminal of the common readout circuit 22. The readout circuit 22 has, for example, a reset transistor RST, a selection transistor SEL, and an amplification transistor AMP. The selection transistor SEL may be omitted as necessary. The source of the reset transistor RST (the input terminal of the readout circuit 22) is electrically connected to the floating diffusion FD, and the drain of the reset transistor RST is electrically connected to a power supply line VDD and the drain of the amplification transistor AMP. The gate of the reset transistor RST is electrically connected to the pixel drive line 23. The source of the amplification transistor AMP is electrically connected to the drain of the selection transistor SEL, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. The source of the selection transistor SEL (the output terminal of the readout circuit 22) is electrically connected to the vertical signal line 24, and the gate of the selection transistor SEL is electrically connected to the pixel drive line 23.

[0045] When the transfer transistor TR is turned on, it transfers the charge of the photodiode PD to the floating diffusion FD. The gate (transfer gate TG) of the transfer transistor TR extends from the surface of the semiconductor substrate 11 to a depth reaching the PD 41 through the p-well layer 42, as shown in FIG. 6, for example. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, it resets the potential of the floating diffusion FD to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the readout circuit 22. The amplification transistor AMP generates a signal of a voltage corresponding to the level of the charge held in the floating diffusion FD as the pixel signal. The amplification transistor AMP constitutes a source follower type amplifier, and outputs a pixel signal of a voltage corresponding to the level of the charge generated in the photodiode PD. When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion FD and outputs a voltage according to the potential to the column signal processing circuit 34 via the vertical signal line 24. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, CMOS transistors.

[0046] As shown in FIG. 10, the selection transistor SEL may be provided between the power supply line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplification transistor AMP, and the gate of the selection transistor SEL is electrically connected to the pixel drive line 23. The source of the amplification transistor AMP (the output terminal of the readout circuit 22) is electrically connected to the vertical signal line 24, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. Also, as shown in FIG. 11 and FIG. 12, the FD transfer transistor FDG may be provided between the source of the reset transistor RST and the gate of the amplification transistor AMP.

[0047] The FD transfer transistor FDG is used to switch the conversion efficiency. In general, the pixel signal is small when shooting in a dark place. Based on Q=CV, when performing charge-voltage conversion, if the capacitance (FD capacitance C) of the floating diffusion FD is large, V when converted to voltage by the amplification transistor AMP will be small. On the other hand, in a bright place, the pixel signal becomes large, so if the FD capacitance C is not large, the floating diffusion FD cannot receive the charge of the photodiode PD. Furthermore, the FD capacitance C needs to be large so that V when converted to voltage by the amplification transistor AMP does not become too large (in other words, so that it becomes small). Considering these, when the FD transfer transistor FDG is turned on, the gate capacitance of the FD transfer transistor FDG increases, so the overall FD capacitance C becomes large. On the other hand, when the FD transfer transistor FDG is turned off, the overall FD capacitance C becomes small. In this way, by switching the FD transfer transistor FDG on and off, the FD capacitance C can be made variable and the conversion efficiency can be switched.

[0048] 13 shows an example of a connection between a plurality of readout circuits 22 and a plurality of vertical signal lines 24. When a plurality of readout circuits 22 are arranged side by side in the extension direction of the vertical signal lines 24 (for example, the column direction), a plurality of vertical signal lines 24 may be assigned to each readout circuit 22. For example, as shown in FIG. 13, when four readout circuits 22 are arranged side by side in the extension direction of the vertical signal lines 24 (for example, the column direction), a plurality of vertical signal lines 24 may be assigned to each readout circuit 22. In FIG. 13, in order to distinguish each vertical signal line 24, an identification number (1, 2, 3, 4) is added to the end of the reference numeral of each vertical signal line 24.

[0049] Next, the vertical cross-sectional configuration of the imaging element 1 will be described with reference to Fig. 6. As described above, the imaging element 1 has a configuration in which the first substrate 10, the second substrate 20, and the third substrate 30 are laminated in this order, and further includes a color filter 40 and a light receiving lens 50 on the back surface (light incident surface) side of the first substrate 10. For example, one color filter 40 and one light receiving lens 50 are each provided for each sensor pixel 12. In other words, the imaging element 1 is a back-illuminated imaging element.

[0050] The first substrate 10 is configured by laminating an insulating layer 46 on the surface (surface 11S1) of the semiconductor substrate 11. The first substrate 10 has the insulating layer 46 as a part of an interlayer insulating film 51. The insulating layer 46 is provided between the semiconductor substrate 11 and a semiconductor substrate 21 described later. The semiconductor substrate 11 is configured of a silicon substrate. The semiconductor substrate 11 has, for example, a p-well layer 42 in a part of the surface and in its vicinity, and has a PD 41 of a different conductivity type from the p-well layer 42 in the other region (region deeper than the p-well layer 42). The p-well layer 42 is configured of a p-type semiconductor region. The PD 41 is configured of a semiconductor region of a different conductivity type (specifically, n-type) from the p-well layer 42. The semiconductor substrate 11 has a floating diffusion FD in the p-well layer 42 as a semiconductor region of a different conductivity type (specifically, n-type) from the p-well layer 42.

[0051] The first substrate 10 has a photodiode PD, a transfer transistor TR, and a floating diffusion FD for each sensor pixel 12. The first substrate 10 is configured such that the transfer transistor TR and the floating diffusion FD are provided on a part of the surface 11S1 side (the side opposite to the light incident surface side, the second substrate 20 side) of the semiconductor substrate 11. The first substrate 10 has an element isolation portion 43 that isolates each sensor pixel 12. The element isolation portion 43 is formed extending in the normal direction of the semiconductor substrate 11 (the direction perpendicular to the surface of the semiconductor substrate 11). The element isolation portion 43 is provided between two sensor pixels 12 adjacent to each other. The element isolation portion 43 electrically isolates the sensor pixels 12 adjacent to each other. The element isolation portion 43 is made of, for example, silicon oxide. The element isolation portion 43 penetrates, for example, the semiconductor substrate 11. The first substrate 10 further includes, for example, a p-well layer 44 that is a side surface of the element isolation portion 43 and is in contact with the surface on the photodiode PD side. The p-well layer 44 is composed of a semiconductor region of a different conductivity type (specifically, p-type) from the photodiode PD. The first substrate 10 further includes, for example, a fixed charge film 45 that is in contact with the back surface (surface 11S2, other surface) of the semiconductor substrate 11. The fixed charge film 45 is negatively charged in order to suppress the generation of dark current caused by the interface state on the light-receiving surface side of the semiconductor substrate 11. The fixed charge film 45 is formed of, for example, an insulating film having a negative fixed charge. Examples of materials for such an insulating film include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide. A hole accumulation layer is formed at the interface on the light-receiving surface side of the semiconductor substrate 11 by an electric field induced by the fixed charge film 45. The hole accumulation layer suppresses the generation of electrons from the interface. The color filter 40 is provided on the back surface side of the semiconductor substrate 11. The color filter 40 is provided, for example, in contact with the fixed charge film 45, and is provided at a position facing the sensor pixel 12 via the fixed charge film 45. The light receiving lens 50 is provided, for example, in contact with the color filter 40, and is provided at a position facing the sensor pixel 12 via the color filter 40 and the fixed charge film 45.

[0052] The second substrate 20 is configured by laminating an insulating layer 52 on the semiconductor substrate 21. The second substrate 20 has the insulating layer 52 as a part of an interlayer insulating film 51. The insulating layer 52 is provided between the semiconductor substrate 21 and the semiconductor substrate 31. The semiconductor substrate 21 is configured by a silicon substrate. The second substrate 20 has one readout circuit 22 for every four sensor pixels 12. The second substrate 20 is configured such that the readout circuit 22 is provided on a part of the front surface (the surface 21S1, one surface facing the third substrate 30) side of the semiconductor substrate 21. The second substrate 20 is bonded to the first substrate 10 with the back surface (surface 21S2) of the semiconductor substrate 21 facing the front surface (surface 11S1) of the semiconductor substrate 11. That is, the second substrate 20 is bonded to the first substrate 10 face-to-back. The second substrate 20 further includes an insulating layer 53 that penetrates the semiconductor substrate 21 in the same layer as the semiconductor substrate 21. The second substrate 20 includes the insulating layer 53 as a part of the interlayer insulating film 51. The insulating layer 53 is provided so as to cover the side surfaces of the through wiring 54 described below.

[0053] The laminated body made of the first substrate 10 and the second substrate 20 has an interlayer insulating film 51 and a through wiring 54 provided in the interlayer insulating film 51. The laminated body has one through wiring 54 for each sensor pixel 12. The through wiring 54 extends in the normal direction of the semiconductor substrate 21 and is provided to penetrate a portion of the interlayer insulating film 51 including the insulating layer 53. The first substrate 10 and the second substrate 20 are electrically connected to each other by the through wiring 54. Specifically, the through wiring 54 is electrically connected to the floating diffusion FD and a connection wiring 55 described later.

[0054] The stacked body made of the first substrate 10 and the second substrate 20 further has through-wires 47, 48 (see FIG. 14 described later) provided in the interlayer insulating film 51. The stacked body has one through-wire 47 and one through-wire 48 for each sensor pixel 12. The through-wires 47, 48 each extend in the normal direction of the semiconductor substrate 21 and are provided penetrating a portion of the interlayer insulating film 51 including the insulating layer 53. The first substrate 10 and the second substrate 20 are electrically connected to each other by the through-wires 47, 48. Specifically, the through-wire 47 is electrically connected to the p-well layer 42 of the semiconductor substrate 11 and the wiring in the second substrate 20. The through-wire 48 is electrically connected to the transfer gate TG and the pixel driving line 23.

[0055] The second substrate 20 has, for example, a plurality of connection parts 59 electrically connected to the readout circuit 22 and the semiconductor substrate 21 in the insulating layer 52. The second substrate 20 further has, for example, a wiring layer 56 on the insulating layer 52. The wiring layer 56 has, for example, an insulating layer 57, and a plurality of pixel driving lines 23 and a plurality of vertical signal lines 24 provided in the insulating layer 57. The wiring layer 56 further has, for example, a plurality of connection wirings 55 in the insulating layer 57, one for each of the four sensor pixels 12. The connection wirings 55 electrically connect the through wirings 54 electrically connected to the floating diffusions FD included in the four sensor pixels 12 sharing the readout circuit 22 to each other. Here, the total number of the through wirings 54, 48 is greater than the total number of the sensor pixels 12 included in the first substrate 10, and is twice the total number of the sensor pixels 12 included in the first substrate 10. Furthermore, the total number of the through wirings 54, 48, and 47 is greater than the total number of the sensor pixels 12 included in the first substrate 10, and is three times the total number of the sensor pixels 12 included in the first substrate 10.

[0056] The wiring layer 56 further has, for example, a plurality of pad electrodes 58 in the insulating layer 57. Each pad electrode 58 is formed of, for example, a metal such as Cu (copper), tungsten (W), or Al (aluminum). Each pad electrode 58 is exposed on the surface of the wiring layer 56. Each pad electrode 58 is used for electrical connection between the second substrate 20 and the third substrate 30 and for bonding the second substrate 20 and the third substrate 30. For example, one pad electrode 58 is provided for each pixel driving line 23 and vertical signal line 24. Here, the total number of pad electrodes 58 (or the total number of connections between the pad electrodes 58 and pad electrodes 64 (described later)) is less than the total number of sensor pixels 12 included in the first substrate 10, for example.

[0057] 8 is a schematic diagram showing a cross-sectional configuration when the wiring structure 100 is applied to the image sensor 1. In this embodiment, for example, the vertical signal lines 24 correspond to the wirings 112X3 and 112X4 in the wiring structure 100, and the power supply lines VSS correspond to the wirings 112X2 and 112X5 in the wiring structure 100. Although not shown in FIG. 6, the insulating layer 57 includes a plurality of insulating films 151 to 157 as shown in FIG. 8, and the insulating film 154 among them forms a gap G between the power supply line VSS and the vertical signal line 24 running parallel to each other and between the wirings of the vertical signal lines 24. Each pad electrode 58 exposed on the surface of the wiring layer 56 corresponds to the conductive film 127X1 and the conductive film 127X2 in the wiring structure 100.

[0058] A part (pad electrode 58X1) of each pad electrode 58 is electrically connected to a ground line (wiring 112X1). The ground line is connected to, for example, a p-well or ground (GND) of the semiconductor substrate 11, although not shown. This allows the pad electrode 58X1 to be used as a shield wiring for the stacking direction of the vertical signal line 24, making it possible to reduce the generation of noise in the vertical signal line 24.

[0059] Furthermore, the pad electrode 58X1 functioning as the shield wiring is joined to a pad electrode 64X1 on the third substrate 30 side, which will be described later. This makes it possible to reduce the impedance of the shield wiring, compared to when the shield wiring is formed by the pad electrode 58X1 alone. Furthermore, the pad electrode 58X1 functioning as the shield wiring is provided so as to traverse the pixel region 13, similar to the vertical signal line 24, for example, and terminates near the periphery beyond the edge of the pixel region 13.

[0060] The third substrate 30 is configured, for example, by laminating an interlayer insulating film 61 on a semiconductor substrate 31. As described later, the third substrate 30 is bonded to the second substrate 20 with the surfaces on the front side facing each other, so that when describing the internal configuration of the third substrate 30, the description of the up and down direction is reversed from the up and down direction in the drawings. The semiconductor substrate 31 is configured of a silicon substrate. The third substrate 30 is configured such that a logic circuit 32 is provided on a part of the front surface (surface 31S1) side of the semiconductor substrate 31. The third substrate 30 further has, for example, a wiring layer 62 on the interlayer insulating film 61. The wiring layer 62 has, for example, an insulating layer 63 and a plurality of pad electrodes 64 (for example, pad electrodes 64X1 and pad electrodes 64X2) provided in the insulating layer 63. The plurality of pad electrodes 64 are electrically connected to the logic circuit 32. Each pad electrode 64 is formed of, for example, Cu (copper). Each pad electrode 64 is exposed on the surface of the wiring layer 62. Each pad electrode 64 is used for electrical connection between the second substrate 20 and the third substrate 30 and for bonding the second substrate 20 and the third substrate 30. The number of pad electrodes 64 does not necessarily need to be multiple, and even one pad electrode 64 can be electrically connected to the logic circuit 32. The second substrate 20 and the third substrate 30 are electrically connected to each other by bonding the pad electrodes 58 and 64 to each other. That is, the gate (transfer gate TG) of the transfer transistor TR is electrically connected to the logic circuit 32 via the through wiring 54 and the pad electrodes 58 and 64. The third substrate 30 is bonded to the second substrate 20 with the surface (surface 31S1) of the semiconductor substrate 31 facing the surface (surface 21S1) of the semiconductor substrate 21. That is, the third substrate 30 is bonded to the second substrate 20 face-to-face.

[0061] 14 and 15 show an example of a cross-sectional configuration of the imaging element 1 in the horizontal direction. The upper diagrams of FIG. 14 and FIG. 15 show an example of a cross-sectional configuration at the cross section Sec1 of FIG. 1, and the lower diagrams of FIG. 14 and FIG. 15 show an example of a cross-sectional configuration at the cross section Sec2 of FIG. 1. FIG. 14 shows an example of a configuration in which two sets of four 2×2 sensor pixels 12 are arranged in the second direction H, and FIG. 15 shows an example of a configuration in which four 2×2 sensor pixels 12 are arranged in the first direction V and the second direction H. In the upper cross-sectional views of FIG. 14 and FIG. 15, a diagram showing an example of a surface configuration of the semiconductor substrate 11 is superimposed on a diagram showing an example of a cross-sectional configuration at the cross section Sec1 of FIG. 1, and the insulating layer 46 is omitted. In the lower cross-sectional views of FIG. 14 and FIG. 15, a diagram showing an example of a surface configuration of the semiconductor substrate 21 is superimposed on a diagram showing an example of a cross-sectional configuration at the cross section Sec2 of FIG. 1.

[0062] As shown in FIG. 14 and FIG. 15, the plurality of through wirings 54, the plurality of through wirings 48, and the plurality of through wirings 47 are arranged in a band shape in the first direction V (the vertical direction in FIG. 14, the horizontal direction in FIG. 15) in the plane of the first substrate 10. Note that FIG. 14 and FIG. 15 illustrate a case in which the plurality of through wirings 54, the plurality of through wirings 48, and the plurality of through wirings 47 are arranged in two columns in the first direction V. The first direction V is parallel to one of the two arrangement directions (e.g., the row direction and the column direction) of the plurality of sensor pixels 12 arranged in a matrix shape (e.g., the column direction). In the four sensor pixels 12 sharing the readout circuit 22, the four floating diffusions FD are arranged close to each other, for example, via the element isolation portion 43. In the four sensor pixels 12 sharing the readout circuit 22, the four transfer gates TG are arranged to surround the four floating diffusions FD, and are shaped into a ring shape by the four transfer gates TG, for example.

[0063] The insulating layer 53 is composed of a plurality of blocks extending in the first direction V. The semiconductor substrate 21 is composed of a plurality of island-shaped blocks 21A extending in the first direction V and arranged in a line in a second direction H perpendicular to the first direction V via the insulating layer 53. Each block 21A is provided with, for example, a plurality of sets of a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. One readout circuit 22 shared by four sensor pixels 12 is composed of, for example, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL in an area facing the four sensor pixels 12. One readout circuit 22 shared by four sensor pixels 12 is composed of, for example, an amplification transistor AMP in a block 21A to the left of the insulating layer 53, and a reset transistor RST and a selection transistor SEL in a block 21A to the right of the insulating layer 53.

[0064] Figures 16, 17, 18, and 19 show examples of wiring layouts in the horizontal plane of the image sensor 1. Figures 16 to 19 show an example in which one readout circuit 22 shared by four sensor pixels 12 is provided in a region facing the four sensor pixels 12. The wirings shown in Figures 16 to 19 are provided in different layers of the wiring layer 56, for example.

[0065] The four mutually adjacent through-wires 54 are electrically connected to a connection wire 55, for example, as shown in Fig. 16. The four mutually adjacent through-wires 54 are further electrically connected to the gate of the amplification transistor AMP included in the block 21A to the left of the insulating layer 53 and the gate of the reset transistor RST included in the block 21A to the right of the insulating layer 53, via the connection wire 55 and a connection portion 59, for example, as shown in Fig. 16.

[0066] The power supply line VDD is disposed at a position facing each of the readout circuits 22 arranged side by side in the second direction H, as shown in FIG. 17, for example. The power supply line VDD is electrically connected to the drain of the amplification transistor AMP and the drain of the reset transistor RST of each of the readout circuits 22 arranged side by side in the second direction H via a connection portion 59, as shown in FIG. 17, for example. Two pixel driving lines 23 are disposed at a position facing each of the readout circuits 22 arranged side by side in the second direction H, as shown in FIG. 17, for example. One pixel driving line 23 (second control line) is a wiring RSTG electrically connected to the gate of the reset transistor RST of each of the readout circuits 22 arranged side by side in the second direction H, as shown in FIG. 17, for example. The other pixel driving line 23 (third control line) is a wiring SELG electrically connected to the gate of the selection transistor SEL of each of the readout circuits 22 arranged side by side in the second direction H, as shown in FIG. 17, for example. In each read circuit 22, the source of the amplification transistor AMP and the drain of the selection transistor SEL are electrically connected to each other via a wiring 25, for example, as shown in FIG.

[0067] Two power supply lines VSS are arranged at positions facing the readout circuits 22 arranged side by side in the second direction H, as shown in FIG. 18, for example. Each power supply line VSS is electrically connected to a plurality of through-wires 47 at a position facing the sensor pixels 12 arranged side by side in the second direction H, as shown in FIG. 18, for example. Four pixel drive lines 23 are arranged at positions facing the readout circuits 22 arranged side by side in the second direction H, as shown in FIG. 18, for example. Each of the four pixel drive lines 23 is a line TRG electrically connected to the through-wire 48 of one of the four sensor pixels 12 corresponding to each readout circuit 22 arranged side by side in the second direction H, as shown in FIG. 18, for example. That is, the four pixel drive lines 23 (first control lines) are electrically connected to the gates (transfer gates TG) of the transfer transistors TR of the sensor pixels 12 arranged side by side in the second direction H. In FIG. 18, in order to distinguish each wiring TRG, an identifier (1, 2, 3, 4) is added to the end of each wiring TRG.

[0068] The vertical signal line 24 is disposed at a position facing each readout circuit 22 arranged side by side in the first direction V, as shown in Fig. 19. The vertical signal line 24 (output line) is electrically connected to the output terminal (the source of the amplification transistor AMP) of each readout circuit 22 arranged side by side in the first direction V, as shown in Fig. 19.

[0069] (1-4. Manufacturing method of image sensor) Next, a description will be given of a manufacturing method of the imaging element 1. Figures 20A to 20G show an example of a manufacturing process of the imaging element 1.

[0070] First, a p-well layer 42, an element isolation portion 43, and a p-well layer 44 are formed on the semiconductor substrate 11. Next, a photodiode PD, a transfer transistor TR, and a floating diffusion FD are formed on the semiconductor substrate 11 (FIG. 20A). As a result, a sensor pixel 12 is formed on the semiconductor substrate 11. At this time, CoSi 2It is preferable not to use a material with low heat resistance such as NiSi. Rather, it is preferable to use a material with high heat resistance as the electrode material used for the sensor pixels 12. An example of a material with high heat resistance is polysilicon. After that, an insulating layer 46 is formed on the semiconductor substrate 11 (FIG. 20A). In this manner, the first substrate 10 is formed.

[0071] Next, the semiconductor substrate 21 is bonded onto the first substrate 10 (insulating layer 46B) (FIG. 20B). Thereafter, the semiconductor substrate 21 is thinned as necessary. At this time, the thickness of the semiconductor substrate 21 is set to a film thickness required for forming the readout circuit 22. The thickness of the semiconductor substrate 21 is generally about several hundreds of nm. However, depending on the concept of the readout circuit 22, an FD (Fully Depletion) type is also possible, in which case the thickness of the semiconductor substrate 21 may be in the range of several nm to several μm.

[0072] Next, an insulating layer 53 is formed in the same layer as the semiconductor substrate 21 (FIG. 20C). The insulating layer 53 is formed, for example, in a location facing the floating diffusion FD. For example, a slit (opening 21H) penetrating the semiconductor substrate 21 is formed in the semiconductor substrate 21 to separate the semiconductor substrate 21 into a plurality of blocks 21A. Then, the insulating layer 53 is formed so as to fill the slit. Then, a readout circuit 22 including an amplifying transistor AMP and the like is formed in each block 21A of the semiconductor substrate 21 (FIG. 20C). At this time, if a metal material with high heat resistance is used as the electrode material of the sensor pixel 12, the gate insulating film of the readout circuit 22 can be formed by thermal oxidation.

[0073] Next, an insulating layer 52 is formed on the semiconductor substrate 21. In this manner, an interlayer insulating film 51 consisting of insulating layers 46, 52, and 53 is formed. Then, through holes 51A and 51B are formed in the interlayer insulating film 51 (FIG. 20D). Specifically, a through hole 51B penetrating the insulating layer 52 is formed in a portion of the insulating layer 52 facing the readout circuit 22. Also, a through hole 51A penetrating the interlayer insulating film 51 is formed in a portion of the interlayer insulating film 51 facing the floating diffusion FD (i.e., a portion facing the insulating layer 53).

[0074] Next, a conductive material is filled into the through holes 51A and 51B to form a through wiring 54 in the through hole 51A and a connection portion 59 in the through hole 51B (FIG. 20E). Furthermore, a connection wiring 55 that electrically connects the through wiring 54 and the connection portion 59 to each other is formed on the insulating layer 52 (FIG. 20E). Thereafter, a wiring layer 56 is formed on the insulating layer 52 (FIG. 20F). In this manner, the second substrate 20 is formed.

[0075] Next, the second substrate 20 is attached to the third substrate 30 on which the logic circuit 32 and the wiring layer 62 are formed, with the surface of the semiconductor substrate 21 facing the surface side of the semiconductor substrate 31 (FIG. 20G). At this time, the pad electrodes 58 of the second substrate 20 and the pad electrodes 64 of the third substrate 30 are joined to each other, thereby electrically connecting the second substrate 20 and the third substrate 30 to each other. In this manner, the image sensor 1 is manufactured.

[0076] (1-5. Actions and Effects) In the wiring structure 100 of the present embodiment and the image sensor 1 to which the same is applied, an insulating film 123 forming a gap G and an insulating film 124 having a flat surface are laminated in this order, for example, between adjacent wirings 112X2 and 112X3, between wirings 112X3 and 112X4, and between wirings 112X4 and 112X5 on a wiring layer 112 having a plurality of wirings (for example, wirings 112X1 to 112X6) extending in one direction (for example, the Y-axis direction). Furthermore, a conductive film 127 is provided at a position directly facing at least a part of the plurality of wirings 112X1 to 112X6 (for example, wirings 112X2, 112X3, and 112X4 having a gap G between them) with the insulating film 123 and insulating film 124 between them. This makes it possible to apply the wiring structure 100 to the bonding surface between the second substrate 20 of the image sensor 1 and the third substrate 30 and the wiring structure in the vicinity thereof. Specifically, the conductive film 127 can be used as a pad electrode 58 for Cu-Cu bonding between the second substrate 20 and the third substrate 30. This will be described below.

[0077] As mentioned above, in recent years, in semiconductor devices, the spacing between elements and between wirings connecting elements has become narrower with the miniaturization of semiconductor integrated circuit elements, and the capacitance (parasitic capacitance) between wirings tends to increase. For this reason, in general semiconductor devices, low-k materials are used to electrically insulate wirings in the stacking direction, and gaps are provided between parallel wirings to reduce the parasitic capacitance between wirings. In such semiconductor devices, unevenness is formed on the surface above the gaps of the insulating film made of low-k material that forms the gaps.

[0078] In the above-mentioned semiconductor device, when hybrid bonding, which is one of the three-dimensional connection technologies, is applied directly above a wiring layer having a gap between the wiring, the wafer-on-wafer (WoW) bonding property is significantly deteriorated due to the step above the gap. One method to improve the WoW bonding property is to planarize the surface of the insulating film, but it is difficult to planarize the surface of an insulating film made of a low-k material to a level that allows WoW bonding.

[0079] In contrast, in the present embodiment, an insulating film 124 having a flat surface is provided on an insulating film 123 that forms gaps G between the wirings 112X1 to 112X6 extending in one direction, and a conductive film 127 that can be used for WoW bonding is formed between the insulating film 123 and the insulating film 124. The conductive film 127 is embedded in an insulating film 126 that is laminated on the insulating film 124, and the conductive film 127 and the insulating film 126 can form the same plane at a level that allows WoW bonding. This makes it possible to form gaps G between the wirings of the vertical signal lines 24 that run vertically through the pixel region 13 in an image sensor 1 having a three-dimensional structure, and to form pad electrodes 58 used for Cu-Cu bonding directly above the vertical signal lines 24.

[0080] As a result, in the image sensor 1 of the present embodiment, it is possible to reduce the wiring capacitance between the multiple vertical signal lines 24 that run vertically through the pixel region 13. In addition, since the pad electrodes 58 for Cu-Cu bonding can be formed directly above the vertical signal lines 24, for example, with gaps G between the wirings, without sandwiching another wiring layer, it is possible to shorten the length of the through wirings 47, 48 that extend in the normal direction of the semiconductor substrate 21, etc., for example. This makes it possible to reduce the wiring capacitance between the through wirings 47, 48.

[0081] In addition, in this embodiment, one of the pad electrodes 58 used for Cu-Cu bonding with the third substrate 30 (for example, the pad electrode 58X1) is electrically connected to the p-well of the semiconductor substrate 11 or to a ground line connected to the ground (GND), so that the pad electrode 58X1 can be given a function as a shield wiring in the stacking direction of the vertical signal line 24. Therefore, the generation of noise in the vertical signal line 24 is reduced, and for example, the image quality of the image sensor 1 can be improved.

[0082] In addition, by using the pad electrode 58X1 for Cu-Cu bonding as a shielding wire, the pad electrode 64X1 on the third substrate 30 side bonded to the pad electrode 58X1 can also be used as a shielding wire in the stacking direction of the vertical signal line 24. This makes it possible to reduce the impedance of the shielding wire. Therefore, it becomes possible to further reduce the generation of noise in the vertical signal line 24.

[0083] In addition, when providing a gap between wirings, the gap between the wirings is generally formed by processing the insulating film between the wirings by dry etching after patterning by lithography technology. However, if the overlapping position of the wiring and the pattern forming the gap is misaligned, there is a risk of the gap being formed in an unintended location. For example, if the end of the pattern forming the gap is located between the wirings, a part of the insulating film remains between the wirings, and the shape of the gap formed between each wiring becomes uneven. If the shape of the gap becomes uneven, the wiring capacitance between the wirings changes, and the electrical characteristics deteriorate. In addition, if a gap is formed at a position where a via that conducts between upper and lower wirings is formed, there is a concern that the wiring will be processed during dry etching, which may deteriorate the electrical characteristics or cause a break in the wiring.

[0084] In contrast, in this embodiment, in consideration of the variation in the manufacturing process, the end 100Ex of the gap formation region 100X in the arrangement direction (X-axis direction) of a plurality of wirings (for example, wirings 112X2 to 112X5) is formed on the wirings at both ends where the gap G is formed between the wirings, and the end 100Ey of the gap formation region 100X in the extension direction (Y-axis direction) of the plurality of wirings is formed to avoid the via V. Specifically, the pattern of the resist film 131 is formed so that, with respect to the wiring width D, the distance X from the side surface adjacent to the gap G to the end 100Ex of the gap formation region 100X satisfies D>X, and, with respect to the distance L from the midpoint of the gap formation region 100X in the Y-axis direction to the via V, the distance Y from the end 100Ey of the gap formation region 100X to the via V satisfies L>Y, and further, X and Y respectively satisfy the above mathematical expressions (1) and (2). As a result, gaps G of a substantially uniform shape are formed between the wirings in a self-aligned manner, making it possible to reduce variations in wiring capacitance caused by variations in the shape of the gap.

[0085] The following describes Modifications 1 to 14. In the following description, the same components as those in the above embodiment are given the same reference numerals, and the description thereof will be omitted as appropriate.

[0086] <2. Modifications> (2-1. Variation 1) 21A to 21K show a modified example (modification 1) of the manufacturing process of the wiring structure (wiring structure 100A) of the present disclosure.

[0087] First, in the same manner as in the above embodiment, an insulating film 123 is formed (FIG. 3E) to form gaps G between wiring 112X2 and wiring 112X3, between wiring 112X3 and wiring 112X4, and between wiring 112X4 and wiring 112X5. Then, as shown in the cross-sectional view (A) and plan view (B) of FIG. 21A, a resist film 132 having an opening equal to or larger than the wiring width of wiring 112X1 is patterned on the insulating film 123 by lithography at a position directly opposite wiring 112X1.

[0088] 21B, the insulating film 123 and a part of the insulating film 122 above and around the wiring 112X1 exposed from the resist film 132 are, for example, dry-etched to form an opening H5, and the resist film 132 is removed by, for example, ashing. Next, as shown in FIG. 21C, a CVD method is used to deposit, for example, SiO x After forming the insulating film 124 having a thickness of 50 nm to 2 μm, as shown in FIG. 21D, the insulating film 124 is polished by, for example, CMP to flatten the surface.

[0089] Next, as shown in FIG. 21E, insulating films 125 and 126 are formed on insulating film 124 using a method similar to that of the above embodiment, and then a resist film 133 having openings directly opposite wiring 112X1 to wiring 112X4 and above wiring 112X6 is patterned on insulating film 126 by, for example, photolithography technology.

[0090] Next, as shown in Fig. 21F, a portion of the insulating film 126 and the insulating film 125 is, for example, dry-etched to form an opening H6, and then the resist film 133 is removed, for example, by ashing. Then, as shown in Fig. 21G, a resist film 134 having an opening at a position directly opposite the wiring 112X1 is patterned on the insulating film 125 and the insulating film 126 in the opening H6 by, for example, photolithography. Next, as shown in Fig. 21H, the insulating films 122 to 125 on the wiring 112X1 are etched to form an opening H7.

[0091] 21I, the resist film 134 is removed by, for example, ashing, and then, as shown in FIG. 21J, the insulating film 121 exposed in the opening H7 is removed by, for example, dry etching to expose the surface of the wiring 112X1. Next, a barrier metal 127A is formed on the side and bottom surfaces of the openings H6 and H7 by, for example, sputtering, and then a metal film 127B is formed in the openings H6 and H7 by, for example, plating. Finally, the barrier metal 127A and the metal film 127B formed on the insulating film 126 are polished. As a result, the wiring structure 100A is completed, as shown in FIG. 21K, in which the insulating film 123 made of a low dielectric constant material (Low-k material) is not formed around the connection portion that electrically connects the wiring 112X1 and the conductive film 127.

[0092] Generally, when forming an opening for electrically connecting a lower wiring (wiring 112X1) and an upper wiring (conductive film 127) as shown in FIG. 1, an ashing process for removing remaining resist film is performed under room temperature conditions as a post-processing step after the opening processing.

[0093] In the image sensor 1 shown in FIG. 6, the size of the pad electrodes 58, 64 used for Cu-Cu bonding between the second substrate 20 and the third substrate 30 is on the order of μm, so from the viewpoint of cost, an exposure machine with a long wavelength light source is selected in the lithography process. When an exposure machine with a long wavelength light source is selected, a thicker resist film is required. In that case, ashing in an atmosphere of 200° C. or higher is required in the process of removing the resist film after dry etching.

[0094] 1, if the insulating film 123 made of a low dielectric constant material (Low-k material) is exposed in an opening forming a connection part that electrically connects the wiring 112X1 and the conductive film 127X1, when ashing is performed under high temperature conditions as described above, the insulating film 123 portion will have a bowing shape, for example, as shown in FIG. 22. This is because the methyl group (Si-CH x) is broken, and the film recession is accelerated by the subsequent wet process.

[0095] In this state, if a barrier metal 127A is deposited in the opening H7, the coverage of the barrier metal 127A is deteriorated in the bow-shaped portion, and the barrier properties are deteriorated. If a metal film 127B made of copper (Cu), for example, is embedded in the bow-shaped portion with the barrier properties deteriorated, copper is likely to diffuse into the insulating film, and for example, concerns about time dependent dielectric breakdown (TDDB) are heightened. Furthermore, in the distorted bow-shaped portion, embedding of the metal film 127B is likely to be insufficient, which may cause, for example, a conductive failure of wiring.

[0096] In contrast, in this modification, the insulating film 123 around the opening H7 that electrically connects the wiring 112X1 and the conductive film 127 is removed in advance, and a low-k material having a higher ashing resistance than the insulating film 123 made of a low-dielectric constant material (Low-k material), such as SiO x The insulating film 124 is embedded in the insulating film 124. This makes it possible to form an opening H7 having a desired shape. This makes it possible to improve the manufacturing yield and electrical reliability of the wiring structure 100A shown in FIG. 21K and the image sensor 1 to which the wiring structure is applied.

[0097] (2-2. Variation 2) 23A to 23F show a modified example (modification 2) of the manufacturing process of the wiring structure (wiring structure 100B) of the present disclosure.

[0098] First, in the same manner as in the above embodiment, the surface of the insulating film 124 is planarized, and then the insulating films 125 and 126 are formed in this order (FIG. 3G). Next, in the same manner as in the above modification 1, the insulating films 126 and a part of the insulating film 125 are etched to form an opening H6, and then, for example, a resist film 134 having an opening at a position directly opposite the wiring 112X1 is patterned in the opening H6 and on the insulating film 126 by photolithography, and the insulating films 123 to 126 on the wiring 112X1 are etched to form an opening H7 as shown in FIG.

[0099] 23B, the resist film 134 is removed by, for example, room temperature ashing. At this time, if the resist film 134 is formed to be a thick film, for example, the resist film 134 having a large formation area may partially remain as shown in FIG. 23B. Next, as shown in FIG. 23C, for example, SiO 2 is deposited on the remaining resist film 134, the upper surface of the insulating film 126, and the side and bottom surfaces of the openings H6 and H7 by, for example, the ALD method. x The protective film 128 is formed from an insulating material having ashing resistance. x In addition, for example, SiN, SiCN, etc. can be used.

[0100] Next, as shown in Fig. 23D, the protective film 128 formed on the upper surface is removed, for example, by etching back the entire surface. Then, as shown in Fig. 23E, the resist film 134 remaining at and near the outer circumferential edge is removed by high-temperature ashing, and the insulating film 121 and insulating film 122 exposed in the opening H7 are removed. At this time, since the insulating film 123 made of a low dielectric constant material (Low-k material) in the opening H7 is covered with the protective film 128, the recession of the insulating film 123 as described above does not occur.

[0101] Next, a barrier metal 127A is formed on the side and bottom of the openings H6 and H7 by, for example, sputtering, and then a metal film 127B is formed in the openings H6 and H7 by, for example, plating. Finally, the barrier metal 127A and the metal film 127B formed on the insulating film 126 are polished. Finally, the barrier metal 127A and the metal film 127B formed on the insulating film 126 are polished. As a result, the wiring structure 100B having the protective film 128 around the connection portion electrically connecting the wiring 112X1 and the conductive film 127 as shown in FIG. 23F is completed. Therefore, as in the above modification 1, it is possible to improve the manufacturing yield and electrical reliability of the wiring structure 100B and the image sensor 1 to which it is applied.

[0102] (2-3. Variation 3) 24A to 24H show a modified example (modification 3) of the manufacturing process of the wiring structure (wiring structure 100C) of the present disclosure.

[0103] First, the insulating film 124 is formed in the same manner as in the above embodiment, and then the surface of the insulating film 124 is planarized (FIG. 3G). Then, as shown in FIG. 24A, a resist film 135 having an opening at a position directly opposite the wiring 112X1 on the insulating film 124 is formed by photolithography in the same manner as in the above modification example 1.

[0104] Next, as shown in FIG. 24B, the insulating films 121 to 124 on the wiring 112X1 are etched to form an opening H8, and then the resist film 135 is removed by ashing. At this time, since the ashing is performed at room temperature, the insulating film 123 made of a low dielectric constant material (Low-k material) does not retreat. Next, as shown in FIG. 24C, a barrier metal 129A is formed on the side and bottom surfaces of the opening H8 and on the insulating film 124 by, for example, sputtering, and then a metal film 129B made of, for example, tungsten (W) is formed in the opening H68 and on the barrier metal 129A by, for example, CVD or sputtering.

[0105] Next, as shown in Fig. 24D, the barrier metal 129A and the metal film 129B on the insulating film 124 are polished and removed by, for example, CMP. This forms a connection portion (via 129) that electrically connects the wiring 112X1 and the conductive film 127. Subsequently, as shown in Fig. 24E, for example, the insulating film 125 and the insulating film 126 are formed on the insulating film 124 and the via 129 by, for example, a CVD method, and then, as shown in Fig. 24F, a resist film 136 having openings at positions directly opposite the wirings 112X1 to 112X4 and above the wiring 112X6 is patterned on the insulating film 126 by, for example, a photolithography technique.

[0106] Next, as shown in FIG. 24G, an opening 9 is formed by, for example, dry etching, penetrating the insulating film 126 and the insulating film 125 to expose the via 129. Then, as shown in FIG. 24H, a conductive film 127 (conductive films 127X1, 127X2) made of a barrier metal 127A and a metal film 127B is formed by using a method similar to that of the above-mentioned modified example 2. As a result, a wiring structure 100C is completed in which the wiring 112X1 and the conductive film 127 are electrically connected by a via 129 made of tungsten (W). Therefore, as in the above-mentioned modified example 1, it is possible to improve the manufacturing yield and electrical reliability of the wiring structure 100C and the image sensor 1 to which the wiring structure 100C is applied.

[0107] In addition, in this modification, unlike the wiring structure 100A of the above embodiment, the wiring 112X1, the conductive film 127, and the connection portion (via 129) are not formed simultaneously. However, since the connection portion (via 129) is formed using tungsten (W), it is possible to omit the formation of an insulating film for preventing copper (Cu) diffusion. Since an insulating film having a property of preventing Cu diffusion has a relatively high dielectric constant, for example, a relative dielectric constant of 5.0 or more, there is a risk that the effective dielectric constant will increase. In contrast, in this modification, it is possible to form the wiring structure 100C without increasing the effective dielectric constant.

[0108] (2-4. Variation 4) 25A to 25G show a modified example (modification 4) of the manufacturing process of the wiring structure (wiring structure 100D) of the present disclosure.

[0109] First, in the same manner as in the third modification, as shown in Fig. 25A, the insulating films 121 to 124 on the wiring 112X1 are etched to form an opening H8, and then the resist film 135 is removed by room temperature ashing. Next, as shown in Fig. 25B, a barrier metal 130A is formed on the side and bottom surfaces of the opening H8 and on the insulating film 124 by, for example, sputtering, and then a metal film 130B made of, for example, copper (Cu) is formed in the opening H8 and on the barrier metal 130A by, for example, plating.

[0110] Next, as shown in FIG. 25C, the barrier metal 130A and the metal film 130B on the insulating film 124 are polished and removed by, for example, CMP. As a result, the via 130 that electrically connects the wiring 112X1 and the conductive film 127 is formed. Then, as shown in FIG. 25D, the insulating film 141, the insulating film 125, and the insulating film 126 are formed in this order on the insulating film 124 and the via 130 by, for example, a CVD method. The insulating film 141 is for preventing the diffusion of copper (Cu), and has, for example, a relative dielectric constant (k) of 5.0 or more. The insulating film 141 is made of, for example, silicon nitride (SiN x ), SiC x N y etc. are used.

[0111] 25E, a resist film 137 having openings at positions directly opposite the wirings 112X1 to 112X4 and above the wiring 112X6 is patterned by, for example, photolithography on the insulating film 126. Next, as shown in FIG. 25F, an opening 9 that penetrates the insulating film 126, the insulating film 125, and the insulating film 141 and exposes the via 130 is formed by, for example, dry etching.

[0112] 25G, a conductive film 127 (conductive films 127X1, 127X2) made of a barrier metal 127A and a metal film 127B is formed using a method similar to that of the above-mentioned modified example 2. As a result, a wiring structure 100D in which the wiring 112X1 and the conductive film 127 are electrically connected is completed without receding the insulating film 123 made of a low dielectric constant material (Low-k material) during ashing. Therefore, as in the above-mentioned modified example 1, it is possible to improve the manufacturing yield and electrical reliability of the wiring structure 100D and the image sensor 1 to which the same is applied.

[0113] (2-5. Variation 5) 26 shows an example of a vertical cross-sectional configuration of an image sensor (image sensor 1) according to a modification (modification 5) of the above embodiment. In this modification, the transfer transistor TR has a planar transfer gate TG. Therefore, the transfer gate TG does not penetrate the p-well layer 42, but is formed only on the surface of the semiconductor substrate 11. Even when a planar transfer gate TG is used for the transfer transistor TR, the image sensor 1 has the same effects as the above embodiment.

[0114] (2-6. Variation 6) FIG. 27 shows an example of a vertical cross-sectional configuration of an image sensor (image sensor 1) according to a modified example (modified example 6) of the above-described embodiment. In this modified example, the second substrate 20 and the third substrate 30 are electrically connected to each other in a region facing the peripheral region 14 of the first substrate 10. The peripheral region 14 corresponds to a frame region of the first substrate 10 and is provided on the periphery of the pixel region 13. In this modified example, the second substrate 20 has a plurality of pad electrodes 58 in a region facing the peripheral region 14, and the third substrate 30 has a plurality of pad electrodes 64 in a region facing the peripheral region 14. The second substrate 20 and the third substrate 30 are electrically connected to each other by bonding the pad electrodes 58, 64 provided in the region facing the peripheral region 14.

[0115] In this manner, in this modification, the second substrate 20 and the third substrate 30 are electrically connected to each other by bonding the pad electrodes 58, 64 provided in the region facing the peripheral region 14. This reduces the risk of hindering miniaturization of the area per pixel compared to the case where the pad electrodes 58, 64 are bonded to each other in the region facing the pixel region 13. Therefore, in addition to the effects of the above embodiment, it is possible to provide an image sensor 1 with a three-layer structure that does not hinder miniaturization of the area per pixel with a chip size equivalent to that of the conventional embodiment.

[0116] (2-7. Variation 7) FIG. 28 shows an example of a vertical cross-sectional configuration of an imaging element (imaging element 1) according to a modified example (modified example 7) of the above embodiment. FIG. 29 shows another example of a vertical cross-sectional configuration of an imaging element (imaging element 1) according to a modified example (modified example 7) of the above embodiment. The upper views of FIG. 28 and FIG. 29 show a modified cross-sectional configuration at section Sec1 of FIG. 1, and the lower view of FIG. 28 shows a modified cross-sectional configuration at section Sec2 of FIG. 1. In the upper cross-sectional views of FIG. 28 and FIG. 29, a view showing a modified surface configuration of the semiconductor substrate 11 of FIG. 1 is superimposed on a view showing a modified cross-sectional configuration at section Sec1 of FIG. 1, and the insulating layer 46 is omitted. In the lower cross-sectional views of FIG. 28 and FIG. 29, a view showing a modified surface configuration of the semiconductor substrate 21 is superimposed on a view showing a modified cross-sectional configuration at section Sec2 of FIG. 1.

[0117] As shown in FIG. 28 and FIG. 29, the plurality of through wirings 54, the plurality of through wirings 48, and the plurality of through wirings 47 (the plurality of dots arranged in a matrix in the figures) are arranged in a band shape in the first direction V (the left-right direction in FIG. 28 and FIG. 29) in the plane of the first substrate 10. Note that FIG. 28 and FIG. 29 illustrate a case in which the plurality of through wirings 54, the plurality of through wirings 48, and the plurality of through wirings 47 are arranged in two rows in the first direction V. In the four sensor pixels 12 sharing the readout circuit 22, the four floating diffusions FD are arranged close to each other, for example, via the element isolation portion 43. In the four sensor pixels 12 sharing the readout circuit 22, the four transfer gates TG (TG1, TG2, TG3, TG4) are arranged to surround the four floating diffusions FD, and are shaped like a ring by the four transfer gates TG, for example.

[0118] The insulating layer 53 is composed of a plurality of blocks extending in a first direction V. The semiconductor substrate 21 is composed of a plurality of island-shaped blocks 21A extending in the first direction V and arranged side by side in a second direction H perpendicular to the first direction V via the insulating layer 53. Each block 21A includes, for example, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. One readout circuit 22 shared by four sensor pixels 12 is, for example, not arranged directly opposite the four sensor pixels 12 but arranged shifted in the second direction H.

[0119] 28, one readout circuit 22 shared by four sensor pixels 12 is configured with a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL located in an area of ​​the second substrate 20 shifted in the second direction H from an area facing the four sensor pixels 12. One readout circuit 22 shared by the four sensor pixels 12 is configured with, for example, an amplification transistor AMP, a reset transistor RST, and a selection transistor SEL in one block 21A.

[0120] 29, one readout circuit 22 shared by four sensor pixels 12 is configured with a reset transistor RST, an amplification transistor AMP, a selection transistor SEL, and an FD transfer transistor FDG in an area on the second substrate 20 shifted in the second direction H from an area facing the four sensor pixels 12. One readout circuit 22 shared by the four sensor pixels 12 is configured with, for example, an amplification transistor AMP, a reset transistor RST, a selection transistor SEL, and an FD transfer transistor FDG in one block 21A.

[0121] In this modification, one readout circuit 22 shared by four sensor pixels 12 is not disposed directly opposite the four sensor pixels 12, but is disposed shifted in the second direction H from a position directly opposite the four sensor pixels 12. In this case, the wiring 25 can be shortened, or the wiring 25 can be omitted and the source of the amplification transistor AMP and the drain of the selection transistor SEL can be configured with a common impurity region. As a result, the size of the readout circuit 22 can be reduced, or the size of other parts in the readout circuit 22 can be increased.

[0122] (2-8. Variation 8) Fig. 30 shows an example of a horizontal cross-sectional configuration of an image sensor (image sensor 1) according to a modification (modification 8) of the above embodiment. Fig. 30 shows a modification of the cross-sectional configuration of Fig. 16.

[0123] In this modification, the semiconductor substrate 21 is composed of a plurality of island-shaped blocks 21A arranged side by side in the first direction V and the second direction H with an insulating layer 53 interposed therebetween. Each block 21A is provided with, for example, a set of a reset transistor RST, an amplifying transistor AMP, and a selection transistor SEL. In this case, crosstalk between adjacent readout circuits 22 can be suppressed by the insulating layer 53, and degradation of image quality due to reduced resolution and color mixing on a reproduced image can be suppressed.

[0124] (2-9. Variation 9) Fig. 31 shows an example of a horizontal cross-sectional configuration of an image sensor (image sensor 1) according to a modification (modification 9) of the above embodiment. Fig. 31 shows a modification of the cross-sectional configuration of Fig. 30.

[0125] In this modification, one readout circuit 22 shared by four sensor pixels 12 is not disposed directly opposite the four sensor pixels 12, but is disposed shifted in the first direction V. In this modification, similar to the modification 8, the semiconductor substrate 21 is further configured with a plurality of island-shaped blocks 21A arranged in the first direction V and the second direction H with an insulating layer 53 interposed therebetween. Each block 21A is provided with, for example, a set of a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. In this modification, a plurality of through wirings 47 and a plurality of through wirings 54 are also arranged in the second direction H. Specifically, the plurality of through wirings 47 are disposed between four through wirings 54 sharing a certain readout circuit 22 and four through wirings 54 sharing another readout circuit 22 adjacent to the readout circuit 22 in the second direction H. In this case, crosstalk between adjacent readout circuits 22 can be suppressed by the insulating layer 53 and the through wirings 47, and degradation of image quality due to a decrease in resolution and color mixing on a reproduced image can be suppressed.

[0126] (2-10. Variation 10) Fig. 32 shows an example of a horizontal cross-sectional configuration of an image sensor (image sensor 1) according to a modification (modification 10) of the above embodiment. Fig. 32 shows a modification of the cross-sectional configuration of Fig. 14.

[0127] In this modification, the first substrate 10 has a photodiode PD and a transfer transistor TR for each sensor pixel 12, and a floating diffusion FD is shared by every four sensor pixels 12. Therefore, in this modification, one through wiring 54 is provided for every four sensor pixels 12.

[0128] In the plurality of sensor pixels 12 arranged in a matrix, the four sensor pixels 12 corresponding to an area obtained by shifting a unit area corresponding to four sensor pixels 12 sharing one floating diffusion FD in the first direction V by one sensor pixel 12 will be referred to as four sensor pixels 12A for convenience. In this modification, the first substrate 10 shares the through wiring 47 with each of the four sensor pixels 12A. Therefore, in this modification, one through wiring 47 is provided for each of the four sensor pixels 12A.

[0129] In this modification, the first substrate 10 has an element isolation section 43 that isolates the photodiode PD and the transfer transistor TR for each sensor pixel 12. When viewed from the normal direction of the semiconductor substrate 11, the element isolation section 43 does not completely surround the sensor pixel 12, and has gaps (unformed regions) near the floating diffusion FD (through wiring 54) and near the through wiring 47. The gaps allow four sensor pixels 12 to share one through wiring 54, and four sensor pixels 12A to share one through wiring 47. In this modification, the second substrate 20 has a readout circuit 22 for each of the four sensor pixels 12 that share the floating diffusion FD.

[0130] Fig. 33 shows another example of the horizontal cross-sectional configuration of the image sensor 1 according to this modification. Fig. 33 shows a modification of the cross-sectional configuration of Fig. 30. In this modification, the first substrate 10 has a photodiode PD and a transfer transistor TR for each sensor pixel 12, and a floating diffusion FD is shared by every four sensor pixels 12. Furthermore, the first substrate 10 has an element isolation portion 43 that isolates the photodiode PD and the transfer transistor TR for each sensor pixel 12.

[0131] Fig. 34 shows another example of the horizontal cross-sectional configuration of the image sensor 1 according to this modification. Fig. 34 shows a modification of the cross-sectional configuration of Fig. 31. In this modification, the first substrate 10 has a photodiode PD and a transfer transistor TR for each sensor pixel 12, and a floating diffusion FD is shared by every four sensor pixels 12. Furthermore, the first substrate 10 has an element isolation portion 43 that isolates the photodiode PD and the transfer transistor TR for each sensor pixel 12.

[0132] (2-11. Variation 11) 35 illustrates an example of a circuit configuration of an image sensor (image sensor 1) according to a modification (modification 11) of the above-described embodiments and modifications 5 and 6. The image sensor 1 according to this modification is a CMOS image sensor equipped with a column-parallel ADC.

[0133] As shown in Figure 35, the imaging element 1 of this modified example has a pixel area 13 in which a plurality of sensor pixels 12, each including a photoelectric conversion unit, are arranged two-dimensionally in a matrix, as well as a vertical driving circuit 33, a column signal processing circuit 34, a reference voltage supply unit 38, a horizontal driving circuit 35, a horizontal output line 37, and a system control circuit 36.

[0134] In this system configuration, the system control circuit 36 ​​generates clock signals and control signals, etc. that serve as standards for the operation of the vertical drive circuit 33, the column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, etc., based on the master clock MCK, and provides them to the vertical drive circuit 33, the column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, etc.

[0135] The vertical drive circuit 33 is formed on the first substrate 10 together with each sensor pixel 12 in the pixel region 13, and is also formed on the second substrate 20 on which the readout circuit 22 is formed. The column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, the horizontal output line 37, and the system control circuit 36 ​​are formed on the third substrate 30.

[0136] Although not shown here, the sensor pixel 12 may have, for example, a photodiode PD and a transfer transistor TR that transfers the charge obtained by photoelectric conversion in the photodiode PD to the floating diffusion FD. Although not shown here, the readout circuit 22 may have, for example, a three-transistor configuration that includes a reset transistor RST that controls the potential of the floating diffusion FD, an amplification transistor AMP that outputs a signal according to the potential of the floating diffusion FD, and a selection transistor SEL that selects pixels.

[0137] In the pixel region 13, the sensor pixels 12 are arranged two-dimensionally, and pixel drive lines 23 are wired for each row in this pixel arrangement of m rows and n columns, and vertical signal lines 24 are wired for each column. One end of each of the pixel drive lines 23 is connected to an output terminal corresponding to each row of a vertical drive circuit 33. The vertical drive circuit 33 is composed of a shift register or the like, and controls row addresses and row scanning of the pixel region 13 via the pixel drive lines 23.

[0138] The column signal processing circuit 34 has, for example, ADCs (analog-to-digital conversion circuits) 34-1 to 34-m provided for each pixel column in the pixel region 13, i.e., for each vertical signal line 24, and converts analog signals output for each column from each sensor pixel 12 in the pixel region 13 into digital signals and outputs them.

[0139] The reference voltage supply unit 38 has, for example, a DAC (digital-analog conversion circuit) 38A as a means for generating a reference voltage Vref having a so-called ramp waveform whose level changes in a sloping manner as time passes. Note that the means for generating the reference voltage Vref having a ramp waveform is not limited to the DAC 38A.

[0140] The DAC 38A generates a reference voltage Vref having a ramp waveform based on a clock CK provided from the system control circuit 36 ​​under the control of a control signal CS1 provided from the system control circuit 36, and supplies the reference voltage Vref to the ADCs 34-1 to 34-m of the column signal processing circuit 34.

[0141] Each of the ADCs 34-1 to 34-m is configured to selectively perform AD conversion operations corresponding to each operation mode, namely, a normal frame rate mode in a progressive scanning system in which information of all the sensor pixels 12 is read out, and a high frame rate mode in which the exposure time of the sensor pixels 12 is set to 1 / N and the frame rate is increased to N times, for example, 2 times, compared to the normal frame rate mode. This switching of the operation mode is executed under the control of control signals CS2 and CS3 provided from the system control circuit 36. Also, an external system controller (not shown) provides the system control circuit 36 ​​with instruction information for switching between the normal frame rate mode and the high frame rate mode.

[0142] The ADCs 34-1 to 34-m all have the same configuration, and the ADC 34-m will be described here as an example. The ADC 34-m includes a comparator 34A, a counting means such as an up / down counter (denoted as U / DCNT in the drawing) 34B, a transfer switch 34C, and a memory device 34D.

[0143] The comparator 34A compares the signal voltage Vx of the vertical signal line 24 corresponding to the signal output from each sensor pixel 12 in the nth column of the pixel area 13 with a ramp-wave reference voltage Vref supplied from the reference voltage supply unit 38, and, for example, when the reference voltage Vref is greater than the signal voltage Vx, the output Vco becomes an “H” level, and when the reference voltage Vref is equal to or lower than the signal voltage Vx, the output Vco becomes an “L” level.

[0144] The up / down counter 34B is an asynchronous counter, and under the control of a control signal CS2 provided from the system control circuit 36, a clock CK is provided from the system control circuit 36 ​​simultaneously with the DAC 18A, and the up / down counter 34B measures the comparison period from the start of the comparison operation in the comparator 34A to the end of the comparison operation by counting down (DOWN) or counting up (UP) in synchronization with the clock CK.

[0145] Specifically, in the normal frame rate mode, in the readout operation of a signal from one sensor pixel 12, the comparison time during the first readout operation is measured by counting down during the first readout operation, and the comparison time during the second readout operation is measured by counting up during the second readout operation.

[0146] On the other hand, in the high-speed frame rate mode, the count result for the sensor pixels 12 in a certain row is retained as is, and then, for the sensor pixels 12 in the next row, counting down from the previous count result during the first read operation is performed to measure the comparison time during the first read operation, and counting up during the second read operation is performed to measure the comparison time during the second read operation.

[0147] In the normal frame rate mode, under the control of a control signal CS3 provided from the system control circuit 36, the transfer switch 34C turns on (closed) when the counting operation of the up / down counter 34B for a certain row of sensor pixels 12 is completed, and transfers the counting result of the up / down counter 34B to the memory device 34D.

[0148] On the other hand, at a high frame rate of, for example, N=2, the up / down counter 34B remains in the off (open) state when it completes its counting operation for the sensor pixels 12 in a certain row, and then turns on when it completes its counting operation for the sensor pixels 12 in the next row, and transfers the counting result of the up / down counter 34B for two vertical pixels to the memory device 34D.

[0149] In this manner, the analog signals supplied for each column from each sensor pixel 12 in the pixel area 13 via the vertical signal line 24 are converted into N-bit digital signals by the operation of each of the comparators 34A and the up / down counters 34B in the ADCs 34-1 to 34-m, and stored in the memory device 34D.

[0150] The horizontal drive circuit 35 is configured with a shift register and the like, and controls the column addresses and column scanning of the ADCs 34-1 to 34-m in the column signal processing circuit 34. Under the control of the horizontal drive circuit 35, the N-bit digital signals AD converted by each of the ADCs 34-1 to 34-m are sequentially read out to a horizontal output line 37 and output as imaging data via the horizontal output line 37.

[0151] In addition, although not specifically shown because it is not directly related to the present disclosure, it is also possible to provide circuits, etc. that perform various types of signal processing on the imaging data output via the horizontal output line 37 in addition to the above-mentioned components.

[0152] In the image sensor 1 equipped with a column-parallel ADC according to this modified example of the above configuration, the count result of the up / down counter 34B can be selectively transferred to the memory device 34D via the transfer switch 34C, so that it is possible to independently control the count operation of the up / down counter 34B and the read operation of the count result of the up / down counter 34B to the horizontal output line 37.

[0153] (2-12. Variation 12) FIG. 36 shows an example of the imaging element of FIG. 35 formed by stacking three substrates (first substrate 10, second substrate 20, third substrate 30). In this modification, in the first substrate 10, a pixel region 13 including a plurality of sensor pixels 12 is formed in the center, and a vertical drive circuit 33 is formed around the pixel region 13. In addition, in the second substrate 20, a readout circuit region 15 including a plurality of readout circuits 22 is formed in the center, and the vertical drive circuit 33 is formed around the readout circuit region 15. In the third substrate 30, a column signal processing circuit 34, a horizontal drive circuit 35, a system control circuit 36, a horizontal output line 37, and a reference voltage supply unit 38 are formed. As a result, as in the above embodiment and its modification, the chip size does not increase and the area per pixel is not hindered from being reduced in size due to the structure electrically connecting the substrates. As a result, it is possible to provide an imaging element 1 having a three-layer structure that does not hinder the area per pixel from being reduced in size with the same chip size as before. The vertical drive circuit 33 may be formed only on the first substrate 10 or only on the second substrate 20.

[0154] (2-13. Variation 13) FIG. 37 shows an example of a cross-sectional configuration of an imaging element (imaging element 1) according to the above embodiment and a modification (modification 13) of the modifications 5 to 12. In the above embodiment and modifications 5 to 12, the imaging element 1 is configured by stacking three substrates (first substrate 10, second substrate 20, third substrate 30). However, as in the imaging elements 5 and 6 in the above fifth embodiment, the imaging element 1 may be configured by stacking two substrates (first substrate 10, second substrate 20). In this case, the logic circuit 32 may be formed, for example, on the first substrate 10 and the second substrate 20 as shown in FIG. 37. Here, in the logic circuit 32, the circuit 32A provided on the first substrate 10 side is provided with a transistor having a gate structure in which a high dielectric constant film made of a material (e.g., high-k) that can withstand high-temperature processes and a metal gate electrode are stacked. On the other hand, in the circuit 32B provided on the second substrate 20 side, CoSi 2A low-resistance region 26 made of silicide formed by a salicide (Self Aligned Silicide) process such as NiSi or NiSi is formed. The low-resistance region made of silicide is formed of a compound of the material of the semiconductor substrate and a metal. This allows a high-temperature process such as thermal oxidation to be used when forming the sensor pixel 12. In addition, in the circuit 32B of the logic circuit 32 provided on the second substrate 20 side, when the low-resistance region 26 made of silicide is provided on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode, the contact resistance can be reduced. As a result, the operation speed in the logic circuit 32 can be increased.

[0155] (2-14. Variation 14) 38 shows a modification of the cross-sectional configuration of the image sensor 1 according to the modification (modification 14) of the above-described embodiment and modifications 5 to 12. In the logic circuit 32 of the third substrate 30 according to the above-described embodiment and modifications 5 to 12, CoSi 2 Alternatively, a low-resistance region 39 made of silicide formed using a salicide (Self Aligned Silicide) process such as NiSi or NiAl may be formed. This allows a high-temperature process such as thermal oxidation to be used when forming the sensor pixels 12. Furthermore, when the low-resistance region 39 made of silicide is provided on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode in the logic circuit 32, the contact resistance can be reduced. As a result, the operation speed in the logic circuit 32 can be increased.

[0156] In the above embodiment and its modified examples 5 to 14, the conductivity types may be reversed. For example, in the description of the above embodiment and its modified examples 5 to 14, p-type may be read as n-type, and n-type may be read as p-type. Even in this case, the same effects as those of the above embodiment and its modified examples 5 to 14 can be obtained.

[0157] <3. Application Examples> FIG. 39 shows an example of a schematic configuration of an imaging system 7 including the imaging element (imaging element 1) according to the above embodiment and modifications 5 to 14.

[0158] The imaging system 7 is, for example, an electronic device such as an imaging element of a digital still camera or a video camera, or a mobile terminal device such as a smartphone or a tablet terminal. The imaging system 7 includes, for example, an optical system 241, a shutter device 242, an imaging element 1, a DSP circuit 243, a frame memory 244, a display unit 245, a storage unit 246, an operation unit 247, and a power supply unit 248. In the imaging system 7, the shutter device 242, the imaging element 1, the DSP circuit 243, the frame memory 244, the display unit 245, the storage unit 246, the operation unit 247, and the power supply unit 248 are connected to each other via a bus line 249.

[0159] The imaging element 1 outputs image data according to incident light. The optical system 241 has one or more lenses, and guides light (incident light) from a subject to the imaging element 1, forming an image on the light receiving surface of the imaging element 1. The shutter device 242 is disposed between the optical system 241 and the imaging element 1, and controls the light irradiation period and the light blocking period to the imaging element 1 according to the control of the operation unit 247. The DSP circuit 243 is a signal processing circuit that processes a signal (image data) output from the imaging element 1. The frame memory 244 temporarily holds the image data processed by the DSP circuit 243 on a frame-by-frame basis. The display unit 245 is formed of a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays a moving image or a still image captured by the imaging element 1. The storage unit 246 records the image data of the moving image or the still image captured by the imaging element 1 in a recording medium such as a semiconductor memory or a hard disk. The operation unit 247 issues operation commands for various functions of the imaging system 7 according to the operation by the user. The power supply unit 248 appropriately supplies various types of power to the imaging element 1, the DSP circuit 243, the frame memory 244, the display unit 245, the storage unit 246 and the operation unit 247 as operating power sources to these objects.

[0160] Next, the imaging procedure in the imaging system 7 will be described.

[0161] 40 shows an example of a flowchart of the imaging operation in the imaging system 7. The user issues an instruction to start imaging by operating the operation unit 247 (step S101). Then, the operation unit 247 transmits an imaging command to the imaging element 1 (step S102). Upon receiving the imaging command, the imaging element 1 (specifically, the system control circuit 36) executes imaging in a predetermined imaging method (step S103).

[0162] The imaging element 1 outputs light (image data) imaged on the light receiving surface via the optical system 241 and the shutter device 242 to the DSP circuit 243. Here, the image data is data for all pixels of pixel signals generated based on charges temporarily stored in the floating diffusion FD. The DSP circuit 243 performs predetermined signal processing (e.g., noise reduction processing, etc.) based on the image data input from the imaging element 1 (step S104). The DSP circuit 243 stores the image data that has been subjected to the predetermined signal processing in the frame memory 244, and the frame memory 244 stores the image data in the storage unit 246 (step S105). In this manner, imaging is performed in the imaging system 7.

[0163] In this application example, the imaging element 1 is applied to an imaging system 7. This allows the imaging element 1 to be made smaller or have higher definition, so that a small or high-definition imaging system 7 can be provided.

[0164] FIG. 41 is a diagram showing an outline of a configuration example of a non-stacked solid-state imaging element (solid-state imaging element 23210) and a stacked solid-state imaging element (solid-state imaging element 23020) to which the technology according to the present disclosure can be applied.

[0165] A in Fig. 41 shows a schematic configuration example of a non-stacked solid-state imaging element. As shown in A in Fig. 41, a solid-state imaging element 23010 has one die (semiconductor substrate) 23011. This die 23011 is equipped with a pixel region 23012 in which pixels are arranged in an array, a control circuit 23013 that drives the pixels and performs various other controls, and a logic circuit 23014 that processes signals.

[0166] B and C of Fig. 41 show a schematic configuration example of a stacked type solid-state imaging element. As shown in B and C of Fig. 41, the solid-state imaging element 23020 is configured as one semiconductor chip by stacking two dies, a sensor die 23021 and a logic die 23024, and electrically connecting them. The sensor die 23021 and the logic die 23024 correspond to a specific example of the "first substrate" and the "second substrate" of the present disclosure.

[0167] 41B, a pixel region 23012 and a control circuit 23013 are mounted on a sensor die 23021, and a logic circuit 23014 including a signal processing circuit that performs signal processing is mounted on a logic die 23024. Furthermore, the sensor die 23021 may be mounted with, for example, the above-mentioned readout circuit 22, etc.

[0168] In FIG. 41C, a pixel region 23012 is mounted on a sensor die 23021, and a control circuit 23013 and a logic circuit 23014 are mounted on a logic die 23024.

[0169] FIG. 42 is a cross-sectional view showing a first configuration example of a stacked solid-state imaging element 23020. As shown in FIG.

[0170] The sensor die 23021 is formed with a PD (photodiode), an FD (floating diffusion), a Tr (MOS FET), and a Tr that constitute a pixel that becomes a pixel region 23012, and a Tr that constitutes a control circuit 23013. Furthermore, the sensor die 23021 is formed with a wiring layer 23101 having multiple layers, three layers in this example, of wiring 23110. Note that the control circuit 23013 (Tr that constitutes the control circuit) can be formed in the logic die 23024, not in the sensor die 23021.

[0171] The logic die 23024 is formed with transistors that constitute the logic circuit 23014. Furthermore, the logic die 23024 is formed with a wiring layer 23161 having multiple layers, three layers in this example, of wiring 23170. Furthermore, the logic die 23024 is formed with a connection hole 23171 having an insulating film 23172 formed on its inner wall surface, and a connection conductor 23173 that is connected to the wiring 23170 and the like is embedded in the connection hole 23171.

[0172] The sensor die 23021 and the logic die 23024 are bonded together so that their wiring layers 23101 and 23161 face each other, thereby forming a stacked solid-state imaging element 23020 in which the sensor die 23021 and the logic die 23024 are stacked. A film 23191 such as a protective film is formed on the surface where the sensor die 23021 and the logic die 23024 are bonded together.

[0173] The sensor die 23021 is formed with a connection hole 23111 penetrating the sensor die 23021 from the rear side (the side where light is incident on the PD) (upper side) of the sensor die 23021 to the wiring 23170 of the top layer of the logic die 23024. Furthermore, the sensor die 23021 is formed with a connection hole 23121 adjacent to the connection hole 23111, the connection hole 23121 reaching the wiring 23110 of the first layer from the rear side of the sensor die 23021. An insulating film 23112 is formed on the inner wall surface of the connection hole 23111, and an insulating film 23122 is formed on the inner wall surface of the connection hole 23121. Then, connection conductors 23113 and 23123 are embedded in the connection holes 23111 and 23121, respectively. The connection conductor 23113 and the connection conductor 23123 are electrically connected on the back side of the sensor die 23021, thereby electrically connecting the sensor die 23021 and the logic die 23024 via the wiring layer 23101, the connection hole 23121, the connection hole 23111, and the wiring layer 23161.

[0174] FIG. 43 is a cross-sectional view showing a second configuration example of a stacked solid-state imaging element 23020. As shown in FIG.

[0175] In a second configuration example of the solid-state imaging element 23020, a single connection hole 23211 formed in the sensor die 23021 electrically connects the sensor die 23021 (the wiring layer 23101 (the wiring 23110)) and the logic die 23024 (the wiring layer 23161 (the wiring 23170)).

[0176] 43, the connection hole 23211 is formed so as to penetrate the sensor die 23021 from the back surface side of the sensor die 23021 to reach the uppermost wiring 23170 of the logic die 23024 and also to reach the uppermost wiring 23110 of the sensor die 23021. An insulating film 23212 is formed on the inner wall surface of the connection hole 23211, and a connection conductor 23213 is embedded in the connection hole 23211. In the above-mentioned FIG. 42, the sensor die 23021 and the logic die 23024 are electrically connected by two connection holes 23111 and 23121, but in FIG. 43, the sensor die 23021 and the logic die 23024 are electrically connected by one connection hole 23211.

[0177] FIG. 44 is a cross-sectional view showing a third configuration example of a stacked solid-state imaging element 23020. As shown in FIG.

[0178] The solid-state imaging element 23020 in Figure 44 differs from the case of Figure 42 in that a film 23191 such as a protective film is not formed on the surface where the sensor die 23021 and the logic die 23024 are bonded to each other, in that a film 23191 such as a protective film is not formed on the surface where the sensor die 23021 and the logic die 23024 are bonded to each other.

[0179] The solid-state imaging element 23020 in FIG. 44 is constructed by overlapping a sensor die 23021 and a logic die 23024 so that the wirings 23110 and 23170 are in direct contact with each other, and heating them while applying a required load, thereby directly bonding the wirings 23110 and 23170.

[0180] FIG. 45 is a cross-sectional view showing another configuration example of a stacked solid-state imaging element to which the technology according to the present disclosure can be applied.

[0181] In FIG. 45, the solid-state imaging element 23401 has a three-layer stacked structure in which three dies, a sensor die 23411, a logic die 23412, and a memory die 23413, are stacked.

[0182] The memory die 23413 has, for example, a memory circuit that stores data temporarily required for signal processing performed in the logic die 23412.

[0183] In FIG. 45, the logic die 23412 and the memory die 23413 are stacked in that order below the sensor die 23411, but the logic die 23412 and the memory die 23413 can be stacked below the sensor die 23411 in the reverse order, i.e., the memory die 23413 and the logic die 23412.

[0184] In FIG. 45, the sensor die 23411 has PDs that serve as photoelectric conversion units of pixels and source / drain regions of pixel Tr formed thereon.

[0185] A gate electrode is formed around the PD with a gate insulating film interposed therebetween, and pixels Tr23421 and Tr23422 are formed by the gate electrode and a pair of source / drain regions.

[0186] The pixel Tr2 3421 adjacent to the PD is a transfer Tr, and one of the pair of source / drain regions constituting the pixel Tr2 3421 is an FD.

[0187] An interlayer insulating film is formed on the sensor die 23411, and a connection hole is formed in the interlayer insulating film. A connection conductor 23431 connected to the pixel Tr23421 and the pixel Tr23422 is formed in the connection hole.

[0188] Furthermore, the sensor die 23411 is formed with a wiring layer 23433 having multiple layers of wiring 23432 connected to each of the connection conductors 23431 .

[0189] Furthermore, an aluminum pad 23434 serving as an electrode for external connection is formed on the bottom layer of the wiring layer 23433 of the sensor die 23411. That is, on the sensor die 23411, the aluminum pad 23434 is formed at a position closer to the bonding surface 23440 with the logic die 23412 than the wiring 23432. The aluminum pad 23434 is used as one end of a wiring related to input / output of a signal to / from the outside.

[0190] Furthermore, a contact 23441 used for electrical connection with the logic die 23412 is formed on the sensor die 23411. The contact 23441 is connected to a contact 23451 of the logic die 23412 and is also connected to an aluminum pad 23442 of the sensor die 23411.

[0191] The sensor die 23411 has a pad hole 23443 formed therein so as to reach the aluminum pad 23442 from the rear surface side (upper side) of the sensor die 23411 .

[0192] The technology according to the present disclosure can be applied to the above-mentioned solid-state imaging element. For example, the wiring 23110 and the wiring layer 23161 may be provided with, for example, the above-mentioned plurality of pixel driving lines 23 and the plurality of vertical signal lines 24. In this case, the capacitance between the wirings can be reduced by forming the gap G as shown in FIG. 1 between the wirings of the plurality of vertical signal lines 24. In addition, by suppressing the increase in the capacitance between the wirings, the variation in the wiring capacitance can be reduced.

[0193] <4. Application Examples> (Application example 1) The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, etc.

[0194] FIG. 46 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving object control system to which the technology according to the present disclosure can be applied.

[0195] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 46, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also, as functional configurations of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053 are illustrated.

[0196] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0197] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as head lamps, back lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves or signals of various switches transmitted from a portable device that replaces a key may be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, and the like of the vehicle.

[0198] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for a person, a car, an obstacle, a sign, or characters on a road surface, based on the received image.

[0199] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of the received light. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0200] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing.

[0201] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the outside-of-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0202] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0203] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0204] The audio / video output unit 12052 transmits at least one output signal of audio and video to an output device capable of visually or audibly notifying information to passengers in the vehicle or the outside of the vehicle. In the example of Fig. 46, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as the output device. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

[0205] FIG. 47 is a diagram showing an example of the installation position of the imaging unit 12031.

[0206] In FIG. 47, a vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as an imaging unit 12031.

[0207] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The images of the front acquired by the imaging units 12101 and 12105 are mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

[0208] 47 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, image data captured by the imaging units 12101 to 12104 are superimposed to obtain an overhead image of the vehicle 12100 viewed from above.

[0209] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of a plurality of imaging elements, or may be an imaging element having pixels for detecting a phase difference.

[0210] For example, the microcomputer 12051 can extract, as a preceding vehicle, a three-dimensional object that is the closest three-dimensional object on the travel path of the vehicle 12100 and travels at a predetermined speed (for example, 0 km / h or more) in approximately the same direction as the vehicle 12100, by calculating the distance to each three-dimensional object in the image capture ranges 12111 to 12114 and the change over time of this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the image capture units 12101 to 12104. Furthermore, the microcomputer 12051 can set a vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving that travels autonomously without relying on the driver's operation.

[0211] For example, the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0212] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured images of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

[0213] An example of a mobile object control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 in the configuration described above. Specifically, the imaging element 1 according to the above embodiment and its modified example can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, a high-definition captured image with little noise can be obtained, and therefore, high-precision control using the captured image can be performed in the mobile object control system.

[0214] (Application example 2) FIG. 48 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0215] 48 shows a state in which an operator (doctor) 11131 is performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0216] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the illustrated example, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may be configured as a so-called flexible scope having a flexible lens barrel.

[0217] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an observation target in the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0218] An optical system and an image sensor are provided inside the camera head 11102, and reflected light (observation light) from an observation target is collected on the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to an observation image. The image signal is transmitted to a camera control unit (CCU) 11201 as RAW data.

[0219] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and performs overall control of the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102, and performs various types of image processing on the image signal, such as development processing (demosaic processing), for example, in order to display an image based on the image signal.

[0220] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0221] The light source device 11203 is composed of a light source such as an LED (Light Emitting Diode), and supplies the endoscope 11100 with irradiation light when photographing an operation site or the like.

[0222] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiated light, magnification, focal length, etc.) of the endoscope 11100.

[0223] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 sends gas into the body cavity of the patient 11132 via the insufflation tube 11111 to inflate the body cavity for the purpose of securing the field of view of the endoscope 11100 and securing the working space of the surgeon. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various formats such as text, image, or graph.

[0224] The light source device 11203 that supplies irradiation light to the endoscope 11100 when photographing the surgical site can be composed of a white light source composed of, for example, an LED, a laser light source, or a combination of these. When the white light source is composed of a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so that the white balance of the captured image can be adjusted in the light source device 11203. In this case, it is also possible to capture images corresponding to each of the RGB colors in a time-division manner by irradiating the observation object with laser light from each of the RGB laser light sources in a time-division manner and controlling the driving of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter to the image sensor.

[0225] The light source device 11203 may be controlled to change the intensity of the light it outputs at predetermined time intervals. The driving of the image sensor of the camera head 11102 may be controlled in synchronization with the timing of the change in the light intensity to obtain images in a time-division manner, and the images may be synthesized to generate an image with a high dynamic range that is free of so-called blackout and whiteout.

[0226] The light source device 11203 may be configured to supply light of a predetermined wavelength band corresponding to the special light observation. In the special light observation, for example, by utilizing the wavelength dependency of light absorption in body tissue, a narrow band light is irradiated compared to the irradiated light (i.e., white light) during normal observation, and a predetermined tissue such as blood vessels on the mucous membrane surface is photographed with high contrast, so-called narrow band imaging is performed. Alternatively, in the special light observation, a fluorescent observation may be performed in which an image is obtained by fluorescence generated by irradiating an excitation light. In the fluorescent observation, it is possible to irradiate an excitation light to a body tissue and observe the fluorescence from the body tissue (autofluorescence observation), or to locally inject a reagent such as indocyanine green (ICG) into the body tissue and irradiate the body tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow band light and / or excitation light corresponding to such special light observation.

[0227] FIG. 49 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0228] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other by a transmission cable 11400 so as to be able to communicate with each other.

[0229] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is configured by combining a plurality of lenses including a zoom lens and a focus lens.

[0230] The imaging unit 11402 is composed of an imaging element. The imaging element constituting the imaging unit 11402 may be one (so-called single-plate type) or multiple (so-called multi-plate type). When the imaging unit 11402 is composed of a multi-plate type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining the image signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (Dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical site. Note that when the imaging unit 11402 is composed of a multi-plate type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0231] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately behind the objective lens.

[0232] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be appropriately adjusted.

[0233] The communication unit 11404 is configured by a communication device for transmitting and receiving various information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0234] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201, and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of capturing the image, and / or information specifying the magnification and focus of the captured image.

[0235] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by a user, or may be automatically set by the control unit 11413 of the CCU 11201 based on an acquired image signal. In the latter case, the endoscope 11100 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0236] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404.

[0237] The communication unit 11411 is configured with a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0238] Furthermore, the communication unit 11411 transmits, to the camera head 11102, a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0239] The image processing unit 11412 performs various types of image processing on the image signal, which is RAW data sent from the camera head 11102 .

[0240] The control unit 11413 performs various controls related to imaging of the surgical site etc. by the endoscope 11100 and display of the captured image obtained by imaging the surgical site etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0241] Further, the control unit 11413 causes the display device 11202 to display the captured image showing the surgical site, etc., based on the image signal that has been image-processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition techniques. For example, the control unit 11413 can recognize surgical tools such as forceps, specific living body parts, bleeding, mist when the energy treatment tool 11112 is used, etc., by detecting the shape and color of the edge of an object included in the captured image. When the control unit 11413 causes the display device 11202 to display the captured image, it may use the recognition result to superimpose various types of surgery support information on the image of the surgical site. By superimposing and presenting the surgery support information to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0242] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for communication of electrical signals, an optical fiber for optical communication, or a composite cable of these.

[0243] Here, in the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0244] An example of an endoscopic surgery system to which the technology according to the present disclosure can be applied has been described above. Of the configurations described above, the technology according to the present disclosure can be suitably applied to the imaging unit 11402 provided in the camera head 11102 of the endoscope 11100. By applying the technology according to the present disclosure to the imaging unit 11402, the imaging unit 11402 can be made smaller or have higher resolution, so that a small or high-resolution endoscope 11100 can be provided.

[0245] The present disclosure has been described above by giving the embodiment and its modifications 1 to 14, application examples, and application examples, but the present disclosure is not limited to the above-mentioned embodiment, etc., and various modifications are possible. For example, in the above modifications 1 to 4, a manufacturing method thereof has been described as a modification of the wiring structure 100 having the gap G between the wirings shown in the above-mentioned embodiment, but the present technology can be applied to any wiring structure using an insulating film made of a dielectric constant material (low-k material) regardless of the presence or absence of the gap G between the wirings, and the same effects as those of the above modifications 1 to 4 can be obtained.

[0246] In the above embodiment, the pixel driving lines 23 extend in the row direction and the vertical signal lines extend in the column direction. However, the pixel driving lines 23 may extend in the same direction. The pixel driving lines 23 may extend in a different direction, such as vertically, as needed.

[0247] Furthermore, in the above-mentioned embodiment, the present technology has been described taking an image sensor having a three-dimensional structure as an example, but is not limited thereto. The present technology can be applied to any semiconductor device that is a three-dimensional stacked large-scale integrated (LSI) semiconductor device.

[0248] Note that the effects described in this specification are merely examples. The effects of the present disclosure are not limited to the effects described in this specification. The present disclosure may have effects other than the effects described in this specification.

[0249] The present disclosure can also be configured as follows. According to the present technology configured as follows, a first insulating film is provided on a first wiring layer having a plurality of first wirings extending in one direction, forming a gap between the adjacent first wirings, and a second insulating film having a flat surface is further provided, so that a first conductive film that can be used as, for example, a bonding pad electrode can be formed at a position directly opposite at least a part of the plurality of first wirings with the first insulating film and the second insulating film in between. Therefore, for example, it is possible to shorten the length of the through wiring extending in the stacking direction, and the wiring capacitance can be reduced. (1) embedded in a fifth insulating film formed using a low dielectric constant material having a dielectric constant k of 3.0 or less; a first wiring layer having a plurality of first wirings extending in one direction; The fifth insulating film, and A gap is formed between the first wirings. and a recess is formed above the plurality of first wirings, the recess being formed using a low dielectric constant material having a dielectric constant k of 3.0 or less. A first insulating film; A second insulating film is laminated on the first insulating film. Shown in Flat surface The first insulating film is formed using a material having a higher polishing rate than the first insulating film. A second insulating film; a first conductive film facing at least a part of the plurality of first wirings with the first insulating film and the second insulating film therebetween; An imaging element comprising: (2) The (1) further has a connection portion that penetrates the first insulating film and the second insulating film and electrically connects a part of the plurality of first wirings to the first conductive film. ) The imaging element described herein. (3) the connection portion is integrally formed with the first conductive film; (2) The imaging element according to claim 1. (4) the connection portion is formed using a material different from that of the first conductive film. (2) or (3) above The imaging element according to claim 1. (5) An insulating film different from the first insulating film is formed around the connection portion. Any one of (2) to (4) above The imaging element according to claim 1. (6) Among the plurality of first wirings, the first wirings at both ends where the gap is formed between adjacent wirings each have an asymmetric cross-sectional shape. Any one of (1) to (5) above The imaging element according to claim 1. (7) the first wirings at both ends where the gap is formed between adjacent wirings have a step at an upper surface end adjacent to the gap, and the upper surface end opposite the gap has a substantially right-angled cross-sectional shape; (6) The imaging element according to claim 1. (8) The void is provided in a void formation region including the plurality of first wirings. Any one of (1) to (7) above The imaging element according to claim 1. (9) the void formation region has an end portion on the first wiring in a parallel direction of the first wiring, (8) The imaging element according to claim 1. (10) The void formation region is formed in a plurality of regions in an extension direction of the plurality of first wirings. (8) or (9) above The imaging element according to claim 1. (11) the first insulating film and the second insulating film are disposed between the first wiring and the second wiring, and the second wiring is electrically connected to the first wiring through a via. The void formation region is formed by being divided into a plurality of regions with the vias therebetween. Any one of (8) to (10) above The imaging element according to claim 1. (12) Further comprising a third insulating film; the first conductive film is embedded in the third insulating film, and a surface of the first conductive film forms the same plane as the third insulating film; Any one of (1) to (11) above The imaging element according to claim 1. (13) The second insulating film is made of silicon oxide (SiO x), SiOC, SiOF or SiON, Any one of (1) to (12) above The imaging element according to claim 1. (14) The semiconductor device further includes a fourth insulating film between the second insulating film and the third insulating film for correcting warpage. (12) or (13) above The imaging element according to claim 1. (15) a first substrate having sensor pixels for performing photoelectric conversion on a first semiconductor substrate; a second substrate having a readout circuit on a second semiconductor substrate, the readout circuit outputting a pixel signal based on the charge output from the sensor pixel; a third semiconductor substrate having at least one of a logic circuit for processing the pixel signals and a memory circuit for holding the pixel signals; The first substrate, the second substrate, and the third substrate are laminated in this order. Any one of (1) to (14) above The imaging element according to claim 1. (16) Furthermore, the second substrate has a multi-layer wiring layer including a third insulating film in which the first conductive film is embedded on a side facing the third substrate; the third substrate has, on a side facing the second substrate, a multilayer wiring layer including a second conductive film that forms the same plane as a surface facing the second substrate; the second substrate and the third substrate are electrically connected to each other by bonding between the first conductive film and the second conductive film. (15) The imaging element according to claim 1. (17) A fifth insulating film formed using a low dielectric constant material having a dielectric constant k of 3.0 or less. A first wiring layer having a plurality of first wirings extending in one direction embedded Formation, forming a first opening between adjacent ones of the first wirings in a predetermined region of the first wiring layer; Using low dielectric constant material with dielectric constant k of 3.0 or less forming a first insulating film to form a gap between the adjacent first wirings; A material having a higher polishing rate than the first insulating film is used.forming a second insulating film covering the first insulating film, and then planarizing a surface of the second insulating film; A first conductive film is formed at a position directly facing at least a part of the plurality of first wirings with the first insulating film and the second insulating film therebetween. A method for manufacturing an imaging element. (18) A third insulating film is further formed on the second insulating film; providing a second opening penetrating the third insulating film, the second insulating film, and the first insulating film and reaching any one of the plurality of first wirings, and a third opening penetrating a part of the third insulating film, and then burying the first conductive film in the second opening and the third opening; (17) A method for manufacturing the imaging element according to claim 1. (19) After planarizing the second insulating film, forming a connection portion that penetrates the second insulating film and the first insulating film and reaches any one of the plurality of first wirings, and electrically connects the first wiring layer and the first conductive film; (17) or (18) above A method for manufacturing the imaging element according to claim 1. (20) After forming the first insulating film, forming a fourth opening reaching any one of the plurality of first wirings, and depositing the second insulating film; Any one of (17) to (19) above A method for manufacturing the imaging element according to claim 1. (21) A third insulating film is further formed on the second insulating film, forming a fifth opening by two-step etching, the fifth opening penetrating the second insulating film and the first insulating film and reaching any one of the plurality of first wirings; After forming a protective film covering the side and bottom surfaces of the fifth opening, forming the first conductive film so as to face at least a portion of the plurality of first wirings and to fill the fifth opening; Any one of (17) to (20) above A method for manufacturing the imaging element according to claim 1. [Explanation of symbols]

[0250] 1...imaging element, 7...imaging system, 10...first substrate, 11, 21, 31...semiconductor substrate, 12...sensor pixel, 13...pixel region, 20...second substrate, 22...readout circuit, 23...pixel drive line, 24...vertical signal line, 30...third substrate, 32...logic circuit, 40...color filter, 49, 49A, 49B, 49C...insulating layer, 49A1, 49A2, 49C1, 49C2...insulating film, 50...light receiving lens, 51, 61...interlayer insulating film, 100...wiring structure, 110...first layer, 111, 121, 122, 123, 124, 125, 126, 141...insulating film, 112...wiring layer, 112A, 127A, 129A...barrier metal, 112B, 127B, 129B...metal film, 112X1 to 112X6, 112Y...wiring, 120...second layer, 127...conductive film, 128...protective film, 129, 130...via, G...gap.

Claims

1. A first wiring layer having a plurality of first wirings extending in one direction and embedded in a fifth insulating film formed using a low dielectric constant material having a dielectric constant k of 3.0 or less; a first insulating film that is laminated on the fifth insulating film and the first wiring layer, that forms gaps between the first wirings adjacent to each other, and that is formed using a low dielectric constant material having a dielectric constant k of 3.0 or less and has a recess above the first wirings; a second insulating film laminated on the first insulating film, having a flat surface, and formed using a material having a higher polishing rate than the first insulating film; a first conductive film facing at least a part of the first wirings with the first insulating film and the second insulating film interposed therebetween; An imaging element comprising:

2. The image sensor according to claim 1 , further comprising a connection portion that penetrates the first insulating film and the second insulating film and electrically connects a part of the plurality of first wirings to the first conductive film.

3. The image sensor according to claim 2 , wherein the connection portion is integrally formed with the first conductive film.

4. The image sensor according to claim 2 , wherein the connection portion is formed using a material different from that of the first conductive film.

5. The image sensor according to claim 2 , further comprising an insulating film different from the first insulating film formed around the connecting portion.

6. The image sensor according to claim 1 , wherein the first wirings at both ends where the gap is formed between adjacent wirings among the plurality of first wirings have an asymmetric cross-sectional shape.

7. 7. The imaging element according to claim 6, wherein the first wirings at both ends where the gap is formed between adjacent wirings have a step at an upper surface end adjacent to the gap, and the upper surface end opposite the gap has a cross-sectional shape that is approximately right-angled.

8. The image sensor according to claim 1 , wherein the gap is provided in a gap forming region including the plurality of first wirings.

9. The image sensor according to claim 8 , wherein the gap forming region has an end portion on the first wiring in a parallel direction of the first wiring.

10. The image sensor according to claim 8 , wherein the void formation region is formed in a direction in which the first wirings extend and is divided into a plurality of regions.

11. the first insulating film and the second insulating film are disposed between the first wiring and the second wiring, and the second wiring is electrically connected to the first wiring through a via. The image sensor according to claim 8 , wherein the void formation region is formed in a plurality of separate regions with the vias between them.

12. Further comprising a third insulating film; 2 . The image sensor according to claim 1 , wherein the first conductive film is embedded in the third insulating film, and a surface of the first conductive film forms the same plane as the third insulating film.

13. The second insulating film is made of silicon oxide (SiO ｘ 2. The image sensor according to claim 1, wherein the image sensor is formed using one of a nitride semiconductor layer, a silicon oxide layer, a silicon carbide ... and a silicon oxynitride layer.

14. The image sensor according to claim 12 , further comprising a fourth insulating film between the second insulating film and the third insulating film for correcting warpage.

15. a first substrate having sensor pixels for performing photoelectric conversion on a first semiconductor substrate; a second substrate having a readout circuit on a second semiconductor substrate, the readout circuit outputting a pixel signal based on the charge output from the sensor pixel; a third semiconductor substrate having at least one of a logic circuit for processing the pixel signals and a memory circuit for holding the pixel signals; The imaging element according to claim 1 , wherein the first substrate, the second substrate, and the third substrate are laminated in this order.

16. Furthermore, the second substrate has a multi-layer wiring layer including a third insulating film in which the first conductive film is embedded on a side facing the third substrate; the third substrate has, on a side facing the second substrate, a multilayer wiring layer including a second conductive film that forms the same plane as a surface facing the second substrate; The image sensor according to claim 15 , wherein the second substrate and the third substrate are electrically connected to each other by bonding the first conductive film and the second conductive film.

17. A first wiring layer having a plurality of first wirings extending in one direction is embedded in a fifth insulating film formed using a low dielectric constant material having a dielectric constant k of 3.0 or less; forming a first opening between adjacent ones of the first wirings in a predetermined region of the first wiring layer; forming a first insulating film using a low dielectric constant material having a dielectric constant k of 3.0 or less, thereby forming a gap between the adjacent first wirings; forming a second insulating film covering the first insulating film using a material having a higher polishing rate than the first insulating film, and then planarizing a surface of the second insulating film; A first conductive film is formed at a position directly facing at least a part of the first wirings with the first insulating film and the second insulating film interposed therebetween. A method for manufacturing an imaging element.

18. A third insulating film is further formed on the second insulating film; 18. The method for manufacturing an image sensor according to claim 17, further comprising the steps of: providing a second opening penetrating the third insulating film, the second insulating film, and the first insulating film and reaching any one of the plurality of first wirings; and providing a third opening penetrating a part of the third insulating film, and then burying the first conductive film in the second opening and the third opening.

19. After planarizing the second insulating film, forming a connection portion that penetrates the second insulating film and the first insulating film and reaches any one of the plurality of first wirings, and electrically connects the first wiring layer and the first conductive film; The method for manufacturing the imaging device according to claim 17 .

20. After forming the first insulating film, The method for manufacturing an image sensor according to claim 17 , further comprising forming a fourth opening that reaches any one of the plurality of first wirings, and depositing the second insulating film.

21. A third insulating film is further formed on the second insulating film, forming a fifth opening penetrating the second insulating film and the first insulating film by two-step etching and reaching any one of the plurality of first wirings; After forming a protective film covering the side and bottom surfaces of the fifth opening, 18. The method for manufacturing an image sensor according to claim 17, further comprising forming the first conductive film so as to face at least a portion of the plurality of first wirings and to fill the fifth opening.

Images