MEMORY ARRAY COMPRISING STRINGS OF MEMORY CELLS AND METHODS USED IN FORMING MEMORY ARRAY COMPRISING STRINGS OF MEMORY CELLS - Patent application

Abstract

A memory array including strings of memory cells and a method used to form the memory array including the strings of memory cells. The method used to form the memory array including the strings of memory cells includes forming a conductor tier including a conductive material on a substrate. Laterally isolated memory block regions are formed, each including a vertical stack including alternating first and second tiers directly above the conductor tiers. Channel material strings of the memory cells extend through the first and second tiers. Horizontally extending lines are formed in the conductive material between the laterally isolated memory block regions. The horizontally extending lines are of a different composition than the upper portions of the conductive material laterally between the horizontally extending lines. After the horizontally extending lines are formed, a bottom first tier of conductive material is formed that directly electrically couples together the channel material of the individual channel material strings and the conductive material of the conductor tiers. Other embodiments are disclosed, including method-independent structures.

Description

[Technical field]

[0001] SUMMARY OF THE DISCLOSURE The embodiments disclosed herein relate to memory arrays and methods used in forming memory arrays. [Background technology]

[0002] A memory is a type of integrated circuit used in computer systems to store data. A memory may be fabricated with one or more arrays of individual memory cells. The memory cells may be written to or read from using digit lines (which may also be referred to as bit lines, data lines, or sense lines) and access lines (which may also be referred to as word lines). The sense lines may conductively interconnect the memory cells along columns of the array, and the access lines may conductively interconnect the memory cells along rows of the array. Each memory cell may be uniquely addressed through a combination of sense lines and access lines.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for long periods of time in the absence of power. Non-volatile memory is conventionally designated as memory that has a retention period of at least about 10 years. Volatile memory dissipates and therefore must be refreshed / rewritten to maintain data storage. Volatile memory can have a retention time of a few milliseconds or less. Nevertheless, memory cells are configured to hold or store memory in at least two different selectable states. In a binary system, a state is considered to be either a "0" or a "1". In other systems, at least some individual memory cells can be configured to store more than two levels or states of information.

[0004] Field effect transistors are a type of electronic component that may be used in memory cells. These transistors include a pair of conductive source / drain regions with a semiconducting channel region between them. A conductive gate is adjacent to the channel region and separated from the channel region by a thin gate insulator. Application of an appropriate voltage to the gate allows current to flow from one of the source / drain regions through the channel region to the other. When the voltage is removed from the gate, current is significantly prevented from flowing through the channel region. Field effect transistors may also include additional structures, such as a reversibly programmable charge storage region as part of the gate construct between the gate insulator and the conductive gate.

[0005] Flash memory is a type of memory that has many uses in modern computers and devices. As an example, modern personal computers may have their BIOS stored on a flash memory chip. As another example, it is becoming increasingly common for computers and other devices to utilize flash memory in solid-state drives to replace traditional hard drives. As yet another example, flash memory is popular in wireless electronic devices because it allows manufacturers to support new communication protocols as they become standardized and provides the ability to remotely upgrade devices for enhanced features.

[0006] NAND may be the basic architecture of integrated flash memory. A NAND cell unit includes at least one selection device coupled in series to a serial combination of memory cells (the serial combination is commonly referred to as a NAND string). The NAND architecture may be configured in a three-dimensional array including vertically stacked memory cells each including a reversibly programmable vertical transistor. Control or other circuitry may be formed below the vertically stacked memory cells. Other volatile or non-volatile memory array architectures may also include vertically stacked memory cells each including a transistor.

[0007] The memory array may be arranged in memory pages, memory blocks and sub-blocks (e.g., sub-blocks), and memory planes, as shown and described in, for example, any of U.S. Patent Application Publication Nos. 2015 / 0228651, 2016 / 0267984, and 2017 / 0140833. The memory blocks may at least partially define the longitudinal contours of individual word lines within individual word line tiers of vertically stacked memory cells. Connections to these word lines may occur at so-called "stair step structures" at the ends or edges of the array of vertically stacked memory cells. The stair step structures include individual "stairs" (alternatively referred to as "steps" or "stair step") that define contact areas of individual word lines that are contacted by height-extending conductive vias to provide electrical access to the word lines. [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic cross-sectional view of a portion of a substrate during processing in accordance with an embodiment of the invention, taken through line 1-1 in FIG. 2; [Diagram 2] FIG. 2 is a schematic cross-sectional view taken through line 2-2 of FIG. 1. [Diagram 3] 2A-2C are schematic sequential partial views of the structure of FIG. 1 in a process according to some embodiments of the invention. [Figure 4] 3A-3C are schematic sequential cross-sectional views of the construction of FIG. 2 during a process according to some embodiments of the invention. [Diagram 5] 2A-2C are schematic sequential partial views of the structure of FIG. 1 in a process according to some embodiments of the invention. [Figure 6] 3A-3C are schematic sequential cross-sectional views of the construction of FIG. 2 during a process according to some embodiments of the invention. [Figure 7] 3 is a schematic enlarged view of the construction of a portion of FIG. 2 in a process according to some embodiments of the invention. [Figure 8]2A-2C are schematic sequential partial views of the structure of FIG. 1 in a process according to some embodiments of the invention. [Figure 9] 3A-3C are schematic sequential cross-sectional views of the construction of FIG. 2 during a process according to some embodiments of the invention. [Figure 10] 2 is a schematic enlarged view of the construction of a portion of FIG. 1 in a process according to some embodiments of the invention. [Figure 11] 3 is a schematic enlarged view of the construction of a portion of FIG. 2 in a process according to some embodiments of the invention. [Figure 12] 3A-3C are schematic sequential cross-sectional views of the construction of FIG. 2 during a process according to some embodiments of the invention. [Figure 13] 3 is a schematic enlarged view of the construction of a portion of FIG. 2 in a process according to some embodiments of the invention. [Figure 14] 3A-3C are schematic sequential cross-sectional views of the construction of FIG. 2 during a process according to some embodiments of the invention. [Figure 15] 3 is a schematic enlarged view of the construction of a portion of FIG. 2 in a process according to some embodiments of the invention. [Figure 16] 2A-2C are schematic sequential partial views of the structure of FIG. 1 in a process according to some embodiments of the invention. [Figure 17] 3A-3C are schematic sequential cross-sectional views of the construction of FIG. 2 during a process according to some embodiments of the invention. [Figure 18] 2A-2C are schematic sequential partial views of the structure of FIG. 1 in a process according to some embodiments of the invention. [Figure 19] 3A-3C are schematic sequential cross-sectional views of the construction of FIG. 2 during a process according to some embodiments of the invention. [Figure 20] 2A-2C are schematic sequential partial views of the structure of FIG. 1 in a process according to some embodiments of the invention. [Figure 21] 3A-3C are schematic sequential cross-sectional views of the construction of FIG. 2 during a process according to some embodiments of the invention. [Figure 22]3 is a schematic enlarged view of the construction of a portion of FIG. 2 in a process according to some embodiments of the invention. [Figure 23] 2 is a schematic enlarged view of the construction of a portion of FIG. 1 in a process according to some embodiments of the invention. [Figure 24] 3 is a schematic enlarged view of the construction of a portion of FIG. 2 in a process according to some embodiments of the invention. [Diagram 25] 3 is a schematic enlarged view of the construction of a portion of FIG. 2 in a process according to some embodiments of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Embodiments of the invention include methods used to form memory arrays, e.g., arrays of NAND or other memory cells (e.g., CMOS under-arrays) that may have at least some peripheral control circuitry beneath the array. Embodiments of the invention include so-called "gate-last" or "replacement gate" processes, so-called "gate-first" processes, and other processes, whether existing or developed in the future, that are independent of when the transistor gates are formed. Embodiments of the invention also include memory array (e.g., NAND architecture) that are independent of the manufacturing method. A first exemplary method embodiment may be considered a "gate-last" or "replacement gate" process and will be described with reference to Figures 1-25, beginning with Figures 1 and 2.

[0010] 1 and 2 show a structure 10 having an array or array region 12 in which vertically extending strings of transistors and / or memory cells may be formed. Structure 10 includes a base substrate 11 having any one or more of conductive, semiconductive, or insulating (i.e., electrical, as used herein) materials. Various materials are formed above the height of base substrate 11. The materials may be beside the materials depicted in FIGS. 1-5, inwardly in the height, or outwardly in the height. For example, other partially or entirely fabricated components of an integrated circuit may be provided anywhere above, around, or within base substrate 11. Control and / or other peripheral circuitry for operating components in an array of vertically extending strings of memory cells (e.g., array 12) may also be fabricated and may be entirely or partially within the array or subarray. Additionally, multiple subarrays may also be fabricated and operated independently, in tandem, or otherwise in relation to one another. In this document, a "sub-array" may also be considered an array.

[0011] A conductive tier 16 including a conductive material 17 is formed above the substrate 11. In one embodiment, the conductive material 17 is a metal material 15 (e.g., WSi x 3. Conductor tier 16 includes a conductively doped semiconductor material 13 (e.g., n-type conductively doped polysilicon) on (directly above, e.g., directly in contact with) conductor tier 16. Conductor tier 16 may include portions of control circuitry (e.g., peripheral under-array circuitry and / or a common source line or plate) used to control read and write access to transistors and / or memory cells that will be formed in array 12.

[0012] 3 and 4, in one embodiment, a patterned masking material 66 having mask openings 67 is formed over conductive tiers 16. As shown in FIG.

[0013] 5-7, the construct 10 is then ion implanted (indicated by downward arrows 68 in FIG. 2) to form horizontally extending lines 72 in the conductor material 17 between what would otherwise be laterally isolated memory block regions (not yet shown) thereover. The horizontally extending lines 72 are of a different composition than the top (at least the top) of the conductor material 17 laterally between the horizontally extending lines 72. In one embodiment, as shown, the horizontally extending lines 72 are not as vertically thick as the conductor tiers 16. In one embodiment, the horizontally extending lines 72 have a higher content of one or more of C, N, B, As, Sb, Bi, Li, Al, In, or metallic materials than is present (if any) in the conductor material 17 laterally between the horizontally extending lines 72. In one embodiment, the horizontally extending lines 72 are not conductive (i.e., insulating or semiconductive), and in another embodiment, are conductive.

[0014] In one embodiment, the top 77 (at least the top) of the horizontally extending lines 72 comprises a conductively doped semiconductor material (e.g., conductively doped polysilicon) having one of a primary n-type conductivity generating dopant or a primary p-type conductivity generating dopant (e.g., 31) therein. A primary n-type dopant or a primary p-type dopant in this context is one that causes what would otherwise be a semiconductive material to become conductive as a result of the concentration of such primary dopant type. At least the top of the horizontally extending lines 72 comprises a secondary dopant (e.g., 33) of a composition different from that of the primary dopant. In one embodiment, one is a primary n-type conductivity generating dopant and in one embodiment, one is a primary p-type conductivity generating dopant. In one embodiment, the different primary and secondary dopants are the same n or p type and in another embodiment, are of different n or p type. In one embodiment, the secondary dopant is one or more of C, N, B, As, or a metallic material. In one embodiment, the secondary dopant is one or more of Sb, Bi, Li, Al, or In. In one embodiment, the secondary dopant in the top portion of the horizontally extending lines is at least 1×10 14 atoms / cm3 In one embodiment, these include a plurality of different compositions of secondary dopants.

[0015] The above process is only one example for forming horizontally extending lines 72 and having one or more of the above exemplary attributes. Any alternative existing or future developed methods and attributes may be used or provided. For example, by way of example only, masking material 66 having openings 67 therein is used as an etch mask while performing a timed etch into conductor material 17 to form trenches (not shown) therein. Such trenches may be filled with a material of a composition different from that of material 13, which is then planarized back to at least the top surface of material 13 to form lines 72.

[0016] Referring to FIGS. 8 to 11, insulating tier 20 * and Conductive Tier 22 * A stack 18 including alternating vertical layers is formed above the conductor tiers 16 ( * is used as an inclusive subscript for all components specified with that same subscript, which may or may not have other subscripts.) Tier 20 * and 22 * Exemplary thicknesses for each of the tiers are 22 to 60 nanometers. * and 22 * Only 18 stacks are shown, but there are dozens, hundreds, and more tiers in the 20s * and 22 * Other circuitry, which may or may not be part of the peripheral and / or control circuitry, may be between conductor tier 16 and stack 18. For example, multiple vertically alternating tiers of conductive and insulating material in such circuitry may be represented by conductive tiers 22. * and / or below the bottom of the conductive tier 22 * For example, one or more select gate tiers (not shown) may be disposed above the top of conductive tier 16 and bottom conductive tier 22. *and one or more select gate tiers may be between conductive tier 22 * Alternatively or additionally, the depicted top and bottom conductive tiers 22 may be above the top of the conductive tiers 22. * At least one of the conductive tiers 22 may be a select gate tier. * (alternatively referred to as the first tier) may not include conductive material, and insulating tier 20 * (alternatively referred to as the second tier) may not include insulating material or may not be insulating at this point in the process in conjunction with the exemplary method embodiments described herein first being "gate last" or "replacement gate". * The insulating tier 20 includes a first material 26 (e.g., silicon nitride), which may be wholly or partially sacrificial. * includes a second material 24 (e.g., silicon dioxide) that is of a different composition than the composition of the first material 26 and may be sacrificial in whole or in part. In an embodiment, the bottom first tier 22z includes a sacrificial material of a different composition than the composition of the topmost portions of the horizontally extending lines 72 in the conductor material 17.

[0017] In some embodiments, the bottom first tier 22z is a first tier 22 * In one such embodiment, the first tier 22 * 1. In one embodiment, as shown, the bottom first tier 22z does not directly contact the conductive material 17 of the conductor tier 16, e.g., the bottom second tier 20z is vertically between the conductive material 17 of the conductor tier 16 and the bottom first tier 22z. Alternatively, the bottom first tier may directly contact the conductive material of the conductor tier (not shown). In one embodiment, the bottom second tier 20z directly contacts the top 19 of the conductive material 17 of the conductor tier 16. In one embodiment ... *In one embodiment, the second tier 20x immediately above the lowest first tier 22z (e.g., the next higher second tier 20x) is thinner than the second tier 20 above it. * Thicker than.

[0018] The second tier material of second tier 20x immediately above bottom first tier 22z (i.e., there are no other second tiers vertically between bottom first tier 22z and the second tier 20x immediately above it) includes top first insulating material 21 and bottom second material 23 below top first insulating material 21, the bottom second material 23 being of a different composition than the composition of top first insulating material 21. Top insulating material 21 may be of the same composition as material 24. In some embodiments, the second tier material of the second tier 20x immediately above the bottom first tier 22z may be considered to include an upper insulating material 21, a lower material 27, and an intermediate material 23 vertically between the upper insulating material 21 and the lower material 27, the intermediate material 23 being of a different composition than the composition of the lower material 27 and the composition of the upper insulating material 21 (the lower material 27 is optional in some embodiments). The upper insulating material 21 and the lower material 27 may be of the same thickness as each other, or may be of different thicknesses. The lower second material 23 may be thinner than each of the upper first insulating material 21 and the lower material 27 (as shown), or may be thicker than each of the upper first insulating material 21 and the lower material 27 (not shown). Nevertheless, in some embodiments, the upper insulating material 21 and the lower material 27 are of the same composition as one another (e.g., the same composition as material 24), and in other embodiments, are of different compositions from one another. In some embodiments, the lower second material 23 / intermediate material 23 comprises at least one of conductively doped polysilicon, conductively undoped polysilicon, carbon doped polysilicon, silicon nitride, undoped silicon nitride, carbon doped silicon nitride, and a metallic material.

[0019] The channel opening 25 is formed by insulating tier 20 * and Conductive Tier 22* 1 through the stack 18 to the conductor tier 16 (e.g., by etching). The channel opening 25 may taper radially inward to move deeper within the stack 18 (not shown). In some embodiments, the channel opening 25 may extend into the conductor material 17 of the conductor tier 16 as shown, or may stop thereon (not shown). Alternatively, as an example, the channel opening 25 may stop on or within the bottom insulating tier 20. The reason for extending the channel opening 25 at least into the conductor material 17 of the conductor tier 16 is to provide an anchoring effect for the material that is within the channel opening 25. An etch stop material (not shown) may be in or on the conductor material 17 of the conductor tier 16 to facilitate stopping the etching of the channel opening 25 to the conductor tier 16 if such is desired. Such an etch stop material may be sacrificial or non-sacrificial.

[0020] Horizontally extending trenches 40 are formed (e.g., by anisotropic etching) in stack 18 to form laterally isolated memory block regions 58. Horizontally extending trenches 40 are individually directly above respective horizontally extending lines 72. In one embodiment, as shown, horizontally extending lines 72 extend laterally into the regions of memory blocks 58 above them. Horizontally extending lines 72 may be formed before or after forming vertical stack 18. By way of example and for simplicity only, channel openings 25 are shown arranged in staggered row groups or columns of four and five channel openings 25 per row, arranged into laterally isolated memory block regions 58 that will comprise laterally isolated memory blocks 58 in the completed circuit structure. In this document, "block" is a generic term that includes "sub-blocks." The trenches 40 will typically be wider than the channel openings 25 (e.g., 10-20 times wider, although such width is not shown for simplicity). The memory block regions 58 and resulting memory blocks 58 (not shown yet) may be considered to extend and be oriented longitudinally, for example, along a direction 55. Any alternative existing or future developed arrangements and constructions may be used. The trenches 40 may have a separate bottom that directly abuts the first material 26 (on or within) the lowermost first tier 22z.

[0021] The trench 40 is lined with a thin lining material 35 (e.g., doped or undoped polysilicon or metal material), which may be partially or wholly sacrificial and is ideally of a composition other than that of materials 24 and 26. Such may be conformally deposited and then substantially removed from above the horizontal surfaces, for example, by a maskless anisotropic spacer-like etch thereof or by a short wet etch. Some aspects of the invention are motivated at least in part to overcome problems associated with removing the lining material 35 from the bottom of the trench 40. In particular, such removal of the lining material 35 may be performed using etching chemistries that may undesirably etch through the materials 26 and 24 of the tiers 22z and 20z, respectively, exposing the underlying conductor material 17. Such etching chemistries may then also undesirably etch the conductor material 17, ultimately leading to the destruction of the circuit being fabricated. Providing the horizontally extending lines 72 to be of a different etch resistant composition compared to the materials 13 laterally adjacent to them can reduce or eliminate such undesirable etching of such materials 13 when exposed when etching material 35.

[0022] The transistor channel material may be formed in each channel opening along the height of the insulating and conductive tiers, thus comprising each individual string of channel material that is directly electrically coupled to the conductive material in the conductive tiers. Each memory cell of the formed exemplary memory array may include a gate region (e.g., a control gate region) and a memory structure laterally between the gate region and the channel material. In one such embodiment, the memory structure is formed to include a charge blocking region, a storage material (e.g., a charge storage material), and an insulating charge passing material. The storage material of each memory cell (e.g., a floating gate material such as doped or undoped silicon, or a charge trapping material such as silicon nitride, metal dots, etc.) is along the height of each individual charge blocking region. The insulating charge passing material (e.g., a band gap engineered structure in which a nitrogen-containing material [e.g., silicon nitride] is sandwiched between two insulating oxides [e.g., silicon dioxide]) is laterally between the channel material and the storage material.

[0023] 8-11 show a charge blocking material 30, a storage material 32, and a charge passing material 34 in an insulating tier 20. * and Conductive Tier 22 * 1 shows one embodiment in which transistor materials 30, 32, and 34 (e.g., memory cell materials) are formed along the height direction in respective channel openings 25. Transistor materials 30, 32, and 34 (e.g., memory cell materials) may be formed, for example, by depositing respective thin layers thereof above stack 18 and into respective openings 25, and then planarizing such back surface at least to the top surface of stack 18.

[0024] The channel material 36 also comprises insulating tier 20 * and Conductive Tier 22 *1 and 2. The channel material 36 is formed in the channel opening 25 along a height direction and thus includes individual operable channel material strings 53 within the channel opening 25. The channel material 36 may be considered to have its bottom surface 71. The channel material strings 53 in one embodiment have memory cell materials (e.g., 30, 32, and 34) along them, and the second tier material (e.g., 24) is horizontally between immediately adjacent channel material strings 53. Materials 30, 32, 34, and 36 are shown collectively as material 37 in FIGS. 1 and 2 and designated only as material 37 due to scale. Exemplary channel materials 36 include appropriately doped crystalline semiconductor materials such as one or more of silicon, germanium, and so-called III / V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). Exemplary thicknesses for each of materials 30, 32, 34, and 36 are between 25 and 100 Angstroms. A punch etch may be performed to remove materials 30, 32, and 34 from the base of channel opening 25 (not shown) to expose conductor tier 16 such that channel material 36 directly contacts conductor material 17 of conductor tier 16. Such a punch etch may occur for each of materials 30, 32, and 34 separately (as shown), or for only some (not shown). Alternatively, by way of example only, a punch etch may not be performed and channel material 36 may be directly electrically coupled to conductor material 17 of conductor tier 16 only by separate conductive interconnects (as yet not shown). Channel opening 25 is shown as including a radially central solid dielectric material 38 (e.g., spin-on dielectric, silicon dioxide, and / or silicon nitride). Alternatively, by way of example only, the radially central portion within channel opening 25 may include void space (not shown) and / or may be devoid of solid material (not shown).

[0025] 12 and 13, first tier material 26 in bottom first tier 22z (not shown) is isotropically etched selectively to second tier material 24, lining material 35, and underlying material 27 (e.g., using liquid or vapor H3PO4 as a primary etchant when material 26 is silicon nitride and other exposed materials include one or more oxides or polysilicon). As identified in the problem above, if material 24 of bottom second tier 20z was previously etched down to conductor tier 16 (not shown), horizontally extending lines 72 may eliminate or at least reduce etching of the material of conductor tier 16.

[0026] 14 and 15 show an exemplary subsequent processing in which, in one embodiment, material 30 (e.g., silicon dioxide), material 32 (e.g., silicon nitride), and material 34 (e.g., silicon dioxide or a combination of silicon dioxide and silicon nitride) are etched to expose sidewalls 41 of channel material 36 of channel material string 53. Nevertheless, in one embodiment in which lower material 27 is present as shown in FIGS. 12 and 13, lower material 27 in second tier 20x immediately above bottom first tier 22z (not shown in FIGS. 14 and 15) is etched selectively to lower surface 31 of intermediate material 23 to expose lower surface 31 of intermediate material 23. As an example, consider an embodiment in which material 23 is polysilicon, materials 21, 24, and 27 are silicon dioxide, and memory cell materials 30, 32, and 34 are one or more of silicon dioxide and silicon nitride layers, respectively. In such examples, the depicted structures may result from the use of altered or different chemistries for selectively etching silicon dioxide and silicon nitride in sequence relative to the other. As an example, a 100:1 solution (by volume) of water to HF would selectively etch silicon dioxide relative to silicon nitride, while a 1000:1 solution (by volume) of water to HF would selectively etch silicon nitride relative to silicon dioxide. Thus, in such examples, such etching chemistries may be used in alternative ways as desired to achieve the exemplary structures shown in FIGS. 14 and 15. One skilled in the art can select other chemistries for etching other different materials when structures such as those shown in FIGS. 14 and 15 are desired. Although the bottom material 27 (not shown) is shown as being removed in the processing of FIGS. 14 and 15, such may not be removed until later in some embodiments. The material 24 of the bottom tier 20z as shown in FIGS. 12 and 13 has also been removed (not shown) in FIGS. 14 and 15.

[0027] 16 and 17, a conductive material 42 is formed in the bottom first tier 22z to directly electrically couple together the channel material 36 of each channel material string 53 and the conductive material 17 of the conductor tier 16. Exemplary conductive materials include conductively doped semiconductor materials (e.g., conductively doped polysilicon, such as containing a sufficient amount / concentration of dopant 31 to make the polysilicon conductive) and metallic materials. In one embodiment, the conductive material 42 in the bottom first tier 22z directly contacts the sidewall 41 of the channel material 36 of the channel material string 53, and in one embodiment, the conductive material 42 in the bottom first tier 22z directly contacts the top surface (e.g., 19) of the top of the conductive material 17 of the conductor tier 16.

[0028] 18 and 19, conductive material 42 has been removed from trench 40 by, for example, an anisotropic etch or a timed isotropic etch that may be selective to materials 35 and 13 and horizontally extending lines 72. One skilled in the art can select any suitable etch chemistry.

[0029] 20-25, lining material 35 (not shown) is removed. Material 26 (not shown) of conductive tier 22 is then removed, for example, by isotropically etching away through trench 40, ideally selectively to other exposed materials (e.g., using liquid or vapor H3PO4 as a primary etchant where material 26 is silicon nitride and the other materials include one or more oxides or polysilicon). Material 26 (not shown) in conductive tier 22 in the exemplary embodiment is sacrificial and replaced with conductive material 48, which is then removed from trench 40, thus forming individual conductive lines 29 (e.g., word lines) and vertically extending strings 49 of individual transistors and / or memory cells 56.

[0030] Prior to forming the conductive material 48, a thin insulating liner (e.g., Al2O3, not shown) may be formed. The approximate locations of the transistors and / or memory cells 56 are indicated by brackets in FIG. 25 and some are indicated by dashed outlines in FIGS. 20, 21, 23, and 24, with the transistors and / or memory cells 56 essentially ring-shaped or annular in the depicted example. Alternatively, the transistors and / or memory cells 56 may not be completely surrounded by the respective channel openings 25, such that each channel opening 25 may have two or more height-extending strings 49 (e.g., multiple transistors and / or memory cells around individual channel openings in individual conductive tiers, with possibly multiple word lines per channel opening in each conductive tier, not shown). The conductive material 48 may be considered to have ends 50 (FIG. 25) corresponding to the control gate regions 52 of the individual transistors and / or memory cells 56. The control gate regions 52 in the depicted embodiment include individual portions of the individual conductive lines 29. Materials 30, 32, and 34 may be considered memory structure 65 that is laterally between control gate region 52 and channel material 36. In one embodiment, as shown for an exemplary "gate-last" process, conductive material 48 of conductive tier 22 is formed after forming channel opening 25 and / or trench 40. Alternatively, conductive material of the conductive tier may be formed prior to forming channel opening 25 and / or trench 40 (not shown), for example, for a "gate-first" process.

[0031] A charge blocking region (e.g., charge blocking material 30) is between the storage material 32 and the respective control gate region 52. The charge blocking may have the following functions within the memory cell: in a program mode, the charge blocking may prevent charge carriers from passing from the storage material (e.g., floating gate material, charge trapping material, etc.) towards the control gate, and in an erase mode, the charge blocking may prevent charge carriers from flowing from the control gate into the storage material. Thus, the charge blocking may function to block charge transfer between the control gate region and the storage material of the respective memory cell. An exemplary charge blocking region as shown includes an insulator material 30. As a further example, the charge blocking region may include a laterally (e.g., radially) outer portion of the storage material (e.g., material 32) when such storage material is insulating (e.g., when there is no material of different composition between the insulating storage material 32 and the conductive material 48). Yet, as an additional example, the interface between the storage material and the conductive material of the control gate may be sufficient to function as a charge blocking region even in the absence of any distinct composition insulator material 30. Additionally, the interface (if any) of the conductive material 48 in combination with the insulator material 30 may function together as a charge blocking region and alternatively or additionally as a laterally outer region of the insulating storage material (e.g., silicon nitride material 32). Exemplary materials 30 are one or more of hafnium silicon oxide and silicon dioxide.

[0032] In one embodiment, as shown, the bottom surface 71 of the channel material 36 of the channel material string 53 does not directly contact any of the conductive material 17 of the conductive tiers 16 .

[0033] Intervening material 57 is formed within trenches 40, thereby forming a longitudinal line between immediately laterally adjacent memory blocks 58. Intervening material 57 may provide lateral electrical isolation (insulation) between immediately laterally adjacent memory blocks. Such may include one or more of insulating, semiconducting, and conductive materials, yet still provide a conductive tier 22 in the completed circuit construction. *intervening material 57 may facilitate shorting to each other. Exemplary insulating materials are one or more of SiO2, Si3N4, Al2O3, and undoped polysilicon. Intervening material 57 may include through-array vias (not shown). Some material within trenches 40 formed prior to forming what is designated as intervening material 57 may remain, thereby including a portion of intervening material 57.

[0034] Any other attributes or aspects shown and / or described herein with respect to other embodiments may be used in the embodiments shown and described with reference to the above embodiments.

[0035] In one embodiment, a method used to form a memory array (e.g., 12) including strings (e.g., 49) of memory cells (e.g., 56) includes forming a conductor tier (e.g., 16) including a conductor material (e.g., 17) on a substrate (e.g., 11). Directly above the conductor tier, laterally isolated memory block regions (e.g., 58) are formed each including a vertical stack (e.g., 18) including alternating first tiers (e.g., 22) and second tiers (e.g., 20). Channel material strings (e.g., 53) of memory cells extend through the first tier and second tier. Horizontally extending lines (e.g., 72) are formed in the conductor material between the laterally isolated memory block regions. The horizontally extending lines are of a different composition than the top portions (at least the top portions, e.g., 77) of the conductor material laterally between the horizontally extending lines. After forming the horizontally extending lines, a bottom first tier (e.g., 22z) of conductive material (e.g., 42) is formed that directly electrically couples together the channel material of the individual channel material strings and the conductor material of the conductor tiers. Any other attributes or aspects shown and / or described herein with respect to other embodiments may be used.

[0036] Alternative embodiment constructions may result from the method embodiments described above, or from other methods. Yet, inventive embodiments encompass memory arrays independent of the manufacturing method. Such memory arrays may nevertheless have any of the attributes as described herein in the method embodiments. Similarly, the method embodiments described above may incorporate, form, and / or have any of the attributes described with respect to the device embodiments.

[0037] In one embodiment, a memory array (e.g., 12) including strings (e.g., 49) of memory cells (e.g., 56) includes conductor tiers (e.g., 16) including conductor material (e.g., 17). The memory array includes laterally isolated memory blocks (e.g., 58) each including a vertical stack (e.g., 18) including alternating insulating tiers (e.g., 20) and conductive tiers (e.g., 22). Channel material strings (e.g., 53) of memory cells (e.g., 56) extend through the insulating and conductive tiers. Conductive material (e.g., 42) of the bottom conductive tier (e.g., 22z) directly electrically couples together the channel material (e.g., 36) of the individual channel material strings and the conductive material in the conductor tiers. Intervening material (e.g., 57) is laterally between and longitudinally along immediately laterally adjacent memory blocks. The intervening material includes insulating material. There are horizontally extending lines (e.g., 72) in the conductive material between the laterally isolated memory blocks. The horizontally extending lines are of a different composition than the conductive material laterally between the horizontally extending lines. Any other attributes or aspects shown and / or described herein with respect to other embodiments may be used.

[0038] In one embodiment, a memory array (e.g., 12) including strings (e.g., 49) of memory cells (e.g., 56) includes conductor tiers (e.g., 16) including n-type conductively doped polysilicon (e.g., 13) having a primary n-type conductivity generating dopant (e.g., 31) therein. The memory array includes laterally isolated memory blocks (e.g., 58) each including a vertical stack (e.g., 18) including alternating insulating tiers (e.g., 20) and conductive tiers (e.g., 22) directly above the conductor tiers. Channel material strings (e.g., 53) of memory cells (e.g., 56) extend through the insulating and conductive tiers. A bottom conductive tier (e.g., 22z) includes n-type conductively doped polysilicon directly abutting the n-type conductively doped polysilicon of the conductor tiers and directly abutting a sidewall (e.g., 41) of the channel material (e.g., 36) of the channel material string of the bottom conductive tier. Intervening material (e.g., 57) is laterally between and longitudinally aligned with immediately laterally adjacent memory blocks. The intervening material includes insulating material. Within the conductive material between the laterally isolated memory blocks are horizontally extending lines (e.g., 72). The horizontally extending lines include n-type conductively doped polysilicon that includes a secondary dopant (e.g., 33) of a composition different from that of the primary dopant. Any other attributes or aspects shown and / or described herein with respect to other embodiments may be used.

[0039] The above processes or constructions may be considered in relation to a single stack or deck of components (although a single stack / deck may have multiple tiers) above or as part of an underlying base substrate, or an array of such components formed therein. Control and / or other peripheral circuitry for operating or accessing such components in the array may also be formed anywhere as part of the completed construction, and in some embodiments may be below the array (e.g., CMOS under-array). Nevertheless, one or more additional such stacks / decks may be provided or fabricated above and / or below the one shown in the figures or described above. Furthermore, the arrays of components may be the same or different from one another in the different stacks / decks, and the different stacks / decks may be of the same or different thickness from one another. Intervening structures (e.g., additional circuitry and / or dielectric layers) may be provided between immediately vertically adjacent stacks / decks. Also, the different stacks / decks may be electrically coupled to one another. Multiple stacks / decks can be manufactured separately in series (eg, stacked on top of one another) or two or more stacks / decks can be manufactured essentially simultaneously.

[0040] The assemblies and structures discussed above may be used in integrated circuits / circuits and may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application specific modules, and may include multi-layer, multi-chip modules. The electronic systems may be any of a wide range of systems, such as, for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0041] In this document, unless otherwise specified, "height", "higher", "top", "bottom", "top", "top", "top", "top", "upper", "lower", "lower", "upper", and "lower" generally refer to a vertical direction. "Horizontal" refers to a general direction (i.e., within 10 degrees) along the main substrate surface and may be the relative direction to which the substrate is processed during manufacturing, and vertical is generally a direction perpendicular thereto. References to "exactly horizontal" are directions along (i.e., no angle therefrom) the main substrate surface and may be the relative direction to which the substrate is processed during manufacturing. Furthermore, "vertical" and "horizontal" as used herein generally refer to directions perpendicular to each other, regardless of the orientation of the substrate in three-dimensional space. Additionally, "elevationally-extending" and "extend(ing) elevationally" refer to a direction that is at an angle of at least 45° away from the exact horizontal direction. Additionally, with respect to field effect transistors, "extending in the height direction", "extending in the height direction", "extend(ing) horizontally", and "horizontally-extending", etc., refer to the orientation of the channel length of the transistor, through which current flows between the source / drain regions during operation. With respect to bipolar junction transistors, "extending in the height direction", "extending in the height direction", "extending horizontally", and "horizontally-extending", etc., refer to the orientation of the base length, through which current flows between the emitter and collector during operation. In some embodiments, any component, feature, and / or region that extends in the height direction extends in the vertical direction or within 10° of the vertical direction.

[0042] Additionally, "directly above," "directly below," and "directly under" require at least some lateral overlap (i.e., horizontally) of the two described regions / materials / components with respect to one another. Also, the use of "above" without "directly" precedes only requires that some portion of a described region / material / component that is above the other be exterior to the height of the other (i.e., regardless of whether there is any lateral overlap of the two described regions / materials / components). Similarly, the use of "below" and "under" without "directly" precedes only requires that some portion of a described region / material / component that is below / under the other be interior to the height of the other (i.e., regardless of whether there is any lateral overlap of the two described regions / materials / components).

[0043] Any of the materials, regions, and structures described herein may be homogeneous or heterogeneous, and yet continuous or discontinuous across any material overlying them. Where one or more exemplary compositions are provided for any material, the material may comprise, consist essentially of, or consist of such one or more compositions. Furthermore, unless otherwise specified, each material may be formed using any suitable existing or future developed technique, examples being atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation.

[0044] Also, "thickness" itself (without a preceding directional adjective) is defined as the average linear distance through a given material or region perpendicular to the nearest surface of immediately adjacent materials or regions of different composition. Also, the various materials or regions described herein may be of substantially constant thickness or of variable thickness. If of variable thickness, thickness refers to the average thickness unless otherwise specified, and such materials or regions will have some minimum thickness and some maximum thickness due to the variable thickness. As used herein, "different composition" requires only that only those portions of two described materials or regions that may be in direct contact with each other are chemically and / or physically different, for example, if such materials or regions are not homogeneous. If two described materials or regions are not in direct contact with each other, "different composition" requires only that those portions of two described materials or regions that are closest to each other are chemically and / or physically different, if such materials or regions are not homogeneous. In this document, materials, regions, or structures are "directly in contact" with one another if the described materials, regions, or structures are in at least some physical contact with one another. In contrast, "over," "on," "adjacent," "along," and "in contact" without being preceded by "directly" encompass constructions in which intervening materials, regions, or structures do not result in any physical contact of the described materials, regions, or structures with one another.

[0045] As used herein, regions-materials-components are "electrically coupled" to one another if, during normal operation, electrical current can flow continuously from one to the other, and does so primarily by the transfer of subatomic positive and / or negative charges when sufficient to do so are generated. Another electronic component may be between the region-material-components and electrically coupled to them. In contrast, when region-material-components are referred to as "directly electrically coupled," there are no intervening electronic components (e.g., diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled region-material-components.

[0046] The use of either "row" and "column" in this document is for convenience in distinguishing one series or orientation of features from another series or orientation of features along which a component is or may be formed. "Row" and "column" are used synonymously with respect to any series of regions, components, and / or features regardless of function. Nevertheless, rows may be straight and / or curved and / or parallel and / or may not be parallel to one another, as may columns. Additionally, rows and columns may intersect one another at 90° or at one or more other angles (i.e., not a linear angle).

[0047] Any of the compositions of conductive / conductor / conductive materials herein may be metallic materials and / or conductively doped semiconductive / semiconductive materials. A "metallic material" is any one or combination of an elemental metal, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compounds.

[0048] As used herein, any use of "selectively" with respect to etching, etching, removing, removing, depositing, forming, and / or forming is such action of one described material relative to another described material such that the action is in a ratio of at least 2:1 by volume. Additionally, any use of selectively depositing, selectively growing, or selectively forming is depositing, growing, or forming one material relative to another described material or materials in a ratio of at least 2:1 by volume for at least the first 75 Angstroms of the depositing, growing, or forming.

[0049] Unless otherwise stated, the use of "or" herein includes either and both.

[0050] [Conclusion] In some embodiments, a method used to form a memory array including strings of memory cells includes forming a conductor tier including a conductor material on a substrate. Laterally isolated memory block regions are formed, each including a vertical stack including alternating first and second tiers directly above the conductor tiers. Channel material strings of memory cells extend through the first and second tiers. Horizontally extending lines are formed in the conductor material between the laterally isolated memory block regions. The horizontally extending lines are of a different composition than an upper portion of the conductor material laterally between the horizontally extending lines. After the horizontally extending lines are formed, a bottom first tier of conductive material is formed that directly electrically couples together the channel material of the individual channel material strings and the conductor material of the conductor tiers.

[0051] In some embodiments, a method used to form a memory array including strings of memory cells includes forming a conductor tier including a conductor material on a substrate. Horizontally extending lines are formed in the conductor material between what would include laterally isolated memory block regions thereover. The horizontally extending lines are of a different composition than the tops of the conductor material laterally between the horizontally extending lines. After the horizontally extending lines are formed, a stack including vertically alternating first and second tiers is formed above the conductor tiers. The bottom first tier includes a sacrificial material of a different composition than the composition of the tops of the horizontally extending lines in the conductor material. The stack includes laterally isolated memory block regions having horizontally extending trenches therebetween directly above each of the respective horizontally extending lines in the conductor material within the conductor tier. A channel material string extends through the first tier and the second tier. The material of the first tier is of a different composition than the material of the second tier. The sacrificial material is isotropically etched from the bottom first tier. After the isotropic etch, conductive material is formed in the bottom first tier that directly electrically couples together the channel material of the individual channel material strings and the conductor material of the conductor tier.

[0052] In some embodiments, a memory array including strings of memory cells includes a conductive tier including a conductive material. The laterally isolated memory blocks each include a vertical stack including alternating insulating and conductive tiers directly above the conductive tiers. The channel material strings of memory cells extend through the insulating and conductive tiers. The conductive material of the bottom conductive tier directly electrically couples together the channel material of the individual channel material strings and the conductive material of the conductive tiers. Intervening material is laterally between and longitudinally aligned with immediately laterally adjacent memory blocks. The intervening material includes an insulating material. Horizontally extending lines in the conductive material are between the laterally isolated memory blocks. The horizontally extending lines are of a different composition than the conductive material laterally between the horizontally extending lines.

[0053] In some embodiments, a memory array including strings of memory cells includes a conductor tier including n-type conductively doped polysilicon having a primary n-type conductivity generating dopant therein. The laterally isolated memory blocks each include a vertical stack including alternating insulating and conductive tiers directly above the conductor tiers. A channel material string of memory cells extends through the insulating and conductive tiers. A bottom conductive tier includes n-type conductively doped polysilicon directly in contact with the n-type conductively doped polysilicon of the conductor tier and directly in contact with a sidewall of the channel material of the channel material string in the bottom conductive tier. Intervening material is laterally between and along the length of immediately laterally adjacent memory blocks. The intervening material includes insulating material. Horizontally extending lines in the conductor material are between the laterally isolated memory blocks. The horizontally extending lines include n-type conductively doped polysilicon including a secondary dopant of a composition different from that of the primary dopant.

Claims

1. forming a conductive tier on a substrate comprising a conductive material; forming laterally isolated memory block regions each including a vertical stack of alternating first and second tiers directly above the conductive tiers, with channel material strings of memory cells extending through the first and second tiers; forming horizontally extending lines in the conductive material between the laterally isolated memory block regions, the horizontally extending lines being of a different etch resistant composition than an upper portion of the conductive material laterally between the horizontally extending lines; forming a conductive material in the lowermost first tier after forming the horizontally extending lines that directly electrically couples together channel material of each of the channel material strings and the conductor material of the conductor tiers, wherein the conductive material is further formed in horizontally extending trenches, each of the horizontally extending trenches including a lining material; etching the conductive material from the horizontally extending trenches directly above the formed horizontally extending lines, wherein the etching is selective to the lining material and the horizontally extending lines; A method used to form a memory array including strings of memory cells, comprising:

2. The method of claim 1 , further comprising forming the horizontally extending lines prior to forming the vertical stacks.

3. The method of claim 1 , further comprising forming the horizontally extending lines after forming the vertical stacks.

4. 2. The method of claim 1, wherein the horizontally extending lines extend laterally into areas of the memory block regions above them.

5. The method of claim 1 , wherein the horizontally extending lines are not as vertically thick as the conductor tiers.

6. 2. The method of claim 1 , wherein the horizontally extending lines have a greater content of one or more of C, N, B, As, Sb, Bi, Li, Al, In, or metallic materials than is present in the conductive material laterally between the horizontally extending lines.

7. The method of claim 1 , wherein the horizontally extending lines are not conductive.

8. The method of claim 1 , wherein the horizontally extending lines are conductive.

9. The method of claim 1 , wherein the horizontally extending lines are formed by ion implantation into the conductive material through mask openings in a masking material.

10. The method of claim 1 , wherein a bottom surface of the channel material of the string of channel material does not directly contact any of the conductive material of the conductor tiers.

11. forming a conductive tier on a substrate comprising a conductive material; forming horizontally extending lines in the conductive material between what will be included laterally isolated memory block regions thereover, the horizontally extending lines being of a different etch resistant composition than an upper portion of the conductive material laterally between the horizontally extending lines; forming a stack including vertically alternating first and second tiers above the conductor tiers after forming the horizontally extending lines, the bottom first tier including a sacrificial material of a different composition than a composition of a topmost portion of the horizontally extending lines in the conductor tiers, the stack including the laterally isolated memory block regions having horizontally extending line trenches therebetween directly above each of the horizontally extending lines in the conductor material within the conductor tiers, a channel material string extending through the first tier and the second tier, the material of the first tier being of a different composition than the material of the second tier; isotropically etching the sacrificial material from the bottom first tier; forming a conductive material in the lowermost first tier after said isotropically etching that directly electrically couples together channel material of each of said channel material strings and said conductor material of said conductor tiers, wherein said conductive material is further formed into horizontally extending trenches, each of said horizontally extending trenches including a lining material; etching the conductive material from the horizontally extending trenches directly above the formed horizontally extending lines, wherein the etching is selective to the lining material and the horizontally extending lines; A method used to form a memory array including strings of memory cells, comprising:

12. a conductive tier including a conductive material; laterally isolated memory blocks each including a vertical stack including alternating insulating and conductive tiers directly above the conductor tiers, where channel material strings of memory cells extend through the insulating tiers and the conductive tiers, and where conductive material of a bottom conductive tier directly electrically couples together channel material of each of the channel material strings and the conductive material of the conductor tiers; horizontally extending lines in the conductive material between the laterally isolated memory blocks, the horizontally extending lines being of a different etch resistant composition than the conductive material laterally between the horizontally extending lines; horizontally extending trenches directly above the horizontally extending lines, each of the horizontally extending trenches including a lining material and a conductive material, the conductive material of the horizontally extending trenches being selectively etched relative to the lining material and the horizontally extending lines; an intervening material formed in the horizontally extending trench and located laterally between immediately laterally adjacent memory blocks along a longitudinal direction, the intervening material comprising an insulating material; A memory array including strings of memory cells,

13. 13. The memory array of claim 12, wherein said horizontally extending lines extend laterally into the area of ​​the memory blocks above them.

14. The memory array of claim 12 , wherein said horizontally extending lines are not as vertically thick as said conductor tiers.

15. 13. The memory array of claim 12, wherein the horizontally extending lines have a greater content of one or more of C, N, B, As, Sb, Bi, Li, Al, In, or a metallic material than is present in the conductive material laterally between the horizontally extending lines.

16. a conductor tier comprising n-type conductively doped polysilicon having a primary n-type conductivity generating dopant therein; a laterally isolated memory block including individual vertical stacks including alternating insulating and conductive tiers directly above the conductive tiers, a channel material string of a memory cell extending through the insulating and conductive tiers, a bottom conductive tier including n-type conductively doped polysilicon directly abutting the n-type conductively doped polysilicon of the conductive tiers and directly abutting a sidewall of the channel material of the channel material string in the bottom conductive tier; horizontally extending lines in the n-type conductively doped polysilicon between the laterally isolated memory blocks, the horizontally extending lines comprising n-type conductively doped polysilicon including a secondary dopant of a composition different than a composition of the primary n-type conductivity generating dopant; horizontally extending trenches directly above the horizontally extending lines, each of the horizontally extending trenches including a lining material and a conductive material including n-type conductively doped polysilicon, the conductive material of the horizontally extending trenches being selectively etched relative to the lining material and the horizontally extending lines; an intervening material formed in the horizontally extending trench and located laterally between immediately laterally adjacent memory blocks along a longitudinal direction, the intervening material comprising an insulating material; A memory array including strings of memory cells,

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