Pointer transfer device and pointer transfer method

Abstract

A read-side read pointer synchronization unit (109) synchronizes a read pointer (208) with a write clock (WCLK) and takes in the result, said read pointer (208) having been generated on the side of a memory read circuit (201) which synchronizes with a read clock (RCLK). A write-side agreement detection unit (113) performs an agreement comparison between the value of a write-side read pointer (110) that is calculated by a write-side read pointer calculation unit (112), and the value of a read-side read pointer (111) that was taken in by the read-side read pointer synchronization unit (109). As long as the write-side agreement detection unit (113) detects non-agreement, the write-side read pointer calculation unit (112) changes the write-side read pointer (110) by one each cycle of the write clock (WCLK).

Description

[Technical field]

[0001] The present disclosure relates to a pointer transfer device, a pointer transfer method, and a memory control device including the pointer transfer device. [Background technology]

[0002] Data synchronization is performed when data is transferred between asynchronous clocks in a logic circuit. As one data synchronization method, as described in Japanese Patent Application Laid-Open No. 2007-233636 (Patent Document 1), a synchronization method is known in which data is transferred between asynchronous clocks via a memory, typically a FIFO (First In First Out) memory.

[0003] Normally, in such a synchronization method, it is necessary to use pointers generated by both clocks to determine whether the memory used for data transfer has free space to write to and whether the data to be read is stored in it. In this case, Gray code is sometimes used to transfer data between different asynchronous clocks without the pointer value being corrupted.

[0004] In Japanese Patent Laid-Open No. 2006-074758 (Patent Document 2), n A method for generating a Gray code is described that enables the Gray code corresponding to an item to be expanded into an even-numbered item, and a technique is described in which this reduced Gray code is used to correctly synchronize pointer values ​​between asynchronous clocks. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2007-233636 A [Patent Document 2] JP 2006-074758 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, although Patent Document 1 shows an asynchronous transfer unit that performs synchronization before performing an operation using a pointer, it does not show a specific circuit configuration, and as a result, it does not describe how erroneous transfer of the pointer value is realized. For this reason, it is unclear whether correct data transfer is possible.

[0007] Furthermore, Patent Document 2 describes a technology for preventing erroneous transfer of pointer values ​​by using a Gray code corresponding to the above-mentioned even-numbered items. However, even if an odd number of items is sufficient, it is necessary to use a memory capacity that is one address larger, which poses issues such as increased circuit size and power consumption.

[0008] The present disclosure has been made to solve such problems, and an object of the present disclosure is to provide a memory control device and a memory control method that can perform correct pointer synchronization while avoiding erroneous transfer of pointer values ​​between asynchronous clocks through simple configuration and control. [Means for solving the problem]

[0009] According to an aspect of the present disclosure, a pointer transfer device is provided. The pointer transfer device includes a first pointer generation unit, a second pointer generation unit, a first synchronization unit, a first circuit side pointer value calculation unit, and a first match detection unit. The first pointer generation unit changes the second pointer by one in a predetermined direction, either an increase direction or a decrease direction, every time the first circuit executes a first operation according to the first clock. The second pointer generation unit changes the second pointer by one in a predetermined direction every time the second circuit executes a second operation according to the second clock. The first synchronization unit captures the value of the second pointer by the second pointer generation unit to the first circuit side in synchronization with the first clock. The first circuit side pointer value calculation unit calculates the value of the second pointer on the first circuit side. The first match detection unit performs a match comparison between the value of the second pointer in the first circuit side pointer value calculation unit and the value of the second pointer captured by the first synchronization unit. The first circuit side pointer value calculation unit changes the value of the second pointer by one in a predetermined direction for each cycle of the first clock while a mismatch is detected by the first match detection unit, while maintaining the value of the second pointer when a match is detected by the first match detection unit.

[0010] According to another aspect of the present disclosure, there is provided a pointer transfer method in which a first operation is performed in a first circuit according to a first clock and a second operation is performed in a second circuit according to a second clock. The pointer transfer method includes the steps of: changing a first pointer by one in a predetermined direction, either an increase or decrease, on the first circuit side every time the first operation is performed; changing a second pointer by one in a predetermined direction on the second circuit side every time the second operation is performed; fetching a value of the second pointer on the second circuit side into the first circuit side in synchronization with the first clock; calculating a value of the second pointer on the first circuit side; and performing a match comparison between the value of the second pointer calculated on the first circuit side and the value of the second pointer fetched from the second circuit side. The step of calculating the value of the second pointer includes the steps of changing the value of the second pointer by one in a predetermined direction for each cycle of the first clock while a mismatch is detected in the step of performing the match comparison; and maintaining the value of the second pointer when a match is detected in the step of performing the match comparison. Effect of the Invention

[0011] According to the present disclosure, in pointer transfer between asynchronous clocks, a change in the pointer value on the transmitting side is detected and the pointer value calculated on the receiving side is changed by one at a time, thereby achieving correct pointer synchronization that avoids erroneous transfer of pointer values ​​between the transmitting side and the receiving side. [Brief description of the drawings]

[0012] [Figure 1] 1 is a block diagram illustrating a configuration of a memory control device according to an embodiment of the present invention. [Diagram 2] 11 is a table for explaining a process of calculating the number of writable data in a data write; [Diagram 3] 11 is a table illustrating an example of changes in a write pointer, a read pointer, a number of writable bytes, and a number of readable bytes, which occur when data is written and read; [Figure 4]11 is a timing chart illustrating a specific example of a process for transferring a read pointer from a memory read circuit to a memory write circuit. [Diagram 5] 11 is a table for explaining a calculation process of the number of readable data in a data read; [Figure 6] 11 is a timing chart illustrating a specific example of a process for transferring a write pointer from a memory write circuit to a memory read circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings are denoted by the same reference characters, and their description will not be repeated in principle.

[0014] 1 is a block diagram illustrating the configuration of a memory control device 100 according to this embodiment. As will become clear from the following description, the memory control device 100 can be used, for example, for data transfer between logic circuits that operate on different asynchronous clocks and are used in electronic devices.

[0015] (Circuit configuration explanation) As shown in Fig. 1, the memory control device 100 operates by receiving a write clock WCLK and a read clock RCLK that are different from each other and asynchronous. The memory control device 100 includes a memory 300 for temporarily storing data, a memory write circuit 101 for writing data to the memory 300 in synchronization with the write clock WCLK, and a memory read circuit 201 for reading data from the memory 300 in synchronization with the read clock RCLK. The write clock WCLK and the read clock RCLK are generated for each clock cycle and input to the memory control device 100. In the following, for each signal and clock, a logical high level is also represented as "1" and a logical low level is also represented as "0".

[0016] The memory write circuit 101 includes a write-side access control unit 103 , a write-side write pointer generation unit 107 , a read-side read pointer synchronization unit 109 , a write-side read pointer calculation unit 112 , and a write-side match detection unit 113 .

[0017] The write-side access control unit 103 executes overall control regarding data writing to the memory 300. Specifically, the write-side access control unit 103 outputs a write permission WPRM (WRPM="1") according to the result of the determination of whether writing to the memory 300 is possible, as described below. When the write-side access control unit 103 receives a write command WCMD and the state is writable (WPRM="1"), the write-side access control unit 103 enables (sets to "1") the write-side write enable 104. When the write-side write enable 104 is enabled, the write-side access control unit 103 further outputs a write-side write pointer increment 106. The write-side write pointer generation unit 107 generates a write-side write pointer 108 that indicates a write address of the memory 300.

[0018] When the write-side write enable 104 is enabled, in response to a rising edge of the write clock WCLK, the write data WDAT is written to a write address of the memory 300 indicated by the write-side write pointer 108, thereby executing a data write. The write-side write pointer 108 is incremented by 1 in synchronization with the write clock WCLK every time the write data WDAT is written, that is, when the write-side write pointer increment 106 is output (that is, during the period when 106="1").

[0019] The read-side read pointer synchronization unit 109 receives the read-side read pointer 208 generated in accordance with the read clock RCLK in the memory read circuit 201. The read-side read pointer synchronization unit 109 generates the read-side read pointer 111 by synchronizing the read-side read pointer 208 with the write clock WCLK.

[0020] The write side consistency detection unit 113 outputs a write side read pointer increment 114 based on the consistency detection result between the value of the read side read pointer 111 generated by the read side read pointer synchronization unit 109 and the value of the write side read pointer 110 by the write side read pointer calculation unit 112.

[0021] The write-side read pointer calculation unit 112 calculates the value of a write-side read pointer 110 synchronized with the write clock WCLK, based on a write-side read pointer increment 114 from a write-side match detection unit 113. The write-side access control unit 103 uses the write-side read pointer 110 calculated by the write-side read pointer calculation unit 112, rather than the read-side read pointer 111 generated by the read-side read pointer synchronization unit 109, to determine whether or not write data WDAT can be written to the memory 300.

[0022] The memory read circuit 201 includes a read-side access control unit 203 , a read-side read pointer generation unit 207 , a write-side write pointer synchronization unit 209 , a read-side write pointer calculation unit 212 , and a read-side match detection unit 213 .

[0023] The read side access control unit 203 executes overall control regarding data reading from the memory 300. Specifically, the read side access control unit 203 outputs a read permission RPRM (RRPM="1") according to the result of the determination of whether reading from the memory 300 is possible, as described below. When the read side access control unit 203 receives a read command RCMD, if the read is possible (RPRM="1"), it enables ("1") the read side read enable 204. When the read side read enable 204 is enabled, the read side access control unit 203 further outputs a read side read pointer increment 206. The read side read pointer generation unit 207 generates a read side read pointer 208 indicating a read address of the memory 300.

[0024] When the read-side read enable 204 is enabled, in response to the rising edge of the read clock RCLK, the read data RDAT is read from the read address of the memory 300 indicated by the read-side read pointer 208, thereby executing a data read. The read-side read pointer 208 is incremented by 1 in synchronization with the read clock RCLK every time the read data RDAT is read, that is, when the read-side read pointer increment 206 is output (i.e., during the period when 206="1").

[0025] The write side write pointer synchronization unit 209 receives the write side write pointer 108 generated in accordance with the write clock WCLK in the memory write circuit 101. The write side write pointer synchronization unit 209 generates a write side write pointer 211 by synchronizing the write side write pointer 108 with the read clock RCLK. The read side match detection unit 213 outputs a read side write pointer increment 214 based on the match detection result between the write side write pointer 211 generated by the write side write pointer synchronization unit 209 and the read side write pointer 210 by the read side write pointer calculation unit 212.

[0026] The read side write pointer calculation unit 212 calculates the value of the read side write pointer 210 synchronized with the read clock RCLK, based on the read side write pointer increment 214 from the read side match detection unit 213. The read side access control unit 203 uses the read side write pointer 210 by the read side write pointer calculation unit 212, not the write side write pointer 211 generated by the write side write pointer synchronization unit 209, to determine whether or not the read data RDAT can be read from the memory 300.

[0027] In this manner, the memory write circuit 101 executes a data write to an address in the memory 300 indicated by the write-side write pointer 108 in accordance with the write clock WCLK. Similarly, the memory read circuit 201 executes a data read to an address in the memory 300 indicated by the read-side read pointer 208 in accordance with the read clock RCLK.

[0028] The data write by the memory write circuit 101 must be performed by grasping the read status from the memory 300 by the memory read circuit 201 so as not to overwrite and erase data that has not been read from the memory 300. At this time, the read status is grasped using the write side read pointer 110 recognized on the memory write circuit 101 side by an operation synchronized with the write clock WCLK. Therefore, it is important to synchronize the read side read pointer 208, which is incremented in synchronization with the read clock RCLK and prevents erroneous transfer of the pointer value, with the write side read pointer 110.

[0029] Similarly, data read by the memory read circuit 201 must be performed while grasping the write status of the memory write circuit 101 to the memory 300, so as not to erroneously read data from the memory 300 when there is no read data in the memory 300; in other words, it must be performed so as to read unread data sequentially. At this time, the write status is grasped by the read side write pointer 210 recognized on the memory read circuit 201 side by an operation synchronized with the read clock RCLK. Therefore, synchronization processing between the write side write pointer 108, which is incremented in synchronization with the write clock WCLK and which prevents erroneous transfer of the pointer value, and the read side write pointer 210 is important.

[0030] Next, a more detailed explanation will be given of the circuit operation related to pointer transfer in the memory control device 100 shown in Fig. 1. It is assumed that the memory 300 has a depth of 7 stages, and that each pointer value is initialized to "0" in the initial state.

[0031] Hereinafter, the write pointer and read pointer will be considered to have a pointer section that changes within a range of values ​​according to the memory depth, and a flag section that is set to "0" or "1". The value of the flag section is inverted each time the pointer section goes through one cycle. As described above, when the memory depth is 7, the value of the pointer section is initialised at "0" and increases by 1 each time data is written or read. Then, when data is written or read while the pointer section has a value of "6", the value of the pointer section returns to "0" and the value of the flag section is inverted from "0" to "1" or from "1" to "0".

[0032] First, the write operation will be described. In a write operation, a write command WCMD is input to the write-side access control unit 103. At this time, if writing is possible, the write-side access control unit 103 activates the write-side write enable 104 (104="1"). When the write-side write enable 104 is activated, the write data WDAT is written to the address of the memory 300 indicated by the write-side write pointer 108. At this time, if writing is not possible, no particular processing is performed on the memory 300 even if the write command WCMD is input.

[0033] An example of the calculation process for the number of writable bits in a data write is shown in Fig. 2. The possibility of writing can be determined according to the calculated value of the number of writable bits shown in Fig. 2.

[0034] In FIG. 2, wpf indicates the value of the flag part of the write-side write pointer 108, and wpp indicates the value of the pointer part of the write-side write pointer 108. Also, rpf indicates the value of the flag part of the write-side read pointer 110, and rpp indicates the value of the pointer part of the write-side read pointer 110. N is the memory depth. The write permission determination result based on the writable number determined according to FIG. 2 is reflected in the write permission WPRM and output from the write-side access control unit 103. Specifically, when the writable number is 0, WPRM is set to "0", while when the writable number is equal to or greater than an arbitrary natural number determined in advance, WPRM is set to "1".

[0035] FIG. 3 shows a chart for explaining an example of changes in the write pointer (wpf, wpp) and read pointer (rpf, rpp), as well as the writable number and readable number, associated with data writing and data reading.

[0036] In the memory write circuit 101, the writable number is obtained according to FIG. 2 using the values of the flag part wpf and pointer part wpp of the write-side write pointer 108 and the flag part rpf and pointer part rpp of the write-side read pointer 110, thereby performing the write permission determination.

[0037] In the example of FIG. 3, from the initial state where wpf = wpp = rpf = rpp = 0 (initial value) and there is no data in the memory 300, data writing is performed 5 times. Accordingly, wpp increases by 1 from 0 to 5 for each data write. At this time, since wpp < N, wpf is maintained at 0, and since data reading is not being performed, rpf = rpp = 0 is also maintained.

[0038] At this time, the writable number is 7, which is equal to N in the initial state, and then decreases by 1 for each data write according to the arithmetic expression N - (wpp - rpp) shown in FIG. 2. After 5 data writes, the writable number has decreased to N - 5 = 2.

[0039] After the above five data writes, five data reads are also executed. Accordingly, rpp increases by 1 from 0 to 5 for each data read. At this time, since it is within the range of rpp < N, rpf is maintained at 0, and since no data write is being executed, the value of the write pointer remains at the previous wpf = 0, wpp = 5.

[0040] At this time, for each data read, the writable count increases by 1 according to the arithmetic expression N - (wpp - rpp) shown in FIG. 2. When the same number of data reads as data writes are completed, wpp = rpp (= 5), and wpf = wpf (= 0), and the writable count has returned to N (= 7).

[0041] Subsequently, when seven data writes are performed starting from the state of wpp = 5 (wpf = 0), in the second data write, when wpp is incremented from 6, wpp is returned to 0 and the flag part wpf is inverted from "0" to "1". Thereafter, under wpf = 1, wpp is incremented, so after the seventh data write, wpf = 1, wpp = 5. Also, for the write - side read pointer 110, rpf = 0, rpp = 5 is maintained.

[0042] At this time, the writable count decreases by 1 for each data write according to the arithmetic expressions N - (wpp - rpp) (when wpf = rpf, wpp > rpp) shown in FIG. 2, -(wpp - rpp) (when wpf ≠ rpf, wpp < rpp), and 0 (when wpf ≠ rpf, wpp = rpp). After seven data writes, the writable count has decreased to N - 7 = 0. At this time, the write permission WPRM is set to "0".

[0043] After the seven data writes mentioned above, seven data reads are also executed. If seven data reads are executed from the state of rpp=5 (rpf=0), when rpp is incremented from 6 in the second data read, it is returned to rpp=0 and the flag section rpf is inverted from "0" to "1". From then on, rpp is incremented under rpf=1, so after the seventh data read, rpf=1, rpp=5. At this time, the number of writable bits is calculated using the formula shown in Figure 2, -(wpp-rpp)(wpf ≠ rpf, wpp<rppのとき)、N-(wpp-rpp)(wpf=rpf,wpp> The number of writes allowed is increased by 1 for each data read according to N (when wpf=rpf, wpp=rpp) and N (when wpf=rpf, wpp=rpp). The write permission WPRM is also set to "1". After seven data reads, the number of writes allowed returns to N (=7).

[0044] Next, the synchronization process between the read side and the write side of the read pointer will be described. 1 again, when data is read, the read-side read pointer 208 changes. Since the read-side read pointer 208 is synchronized with the read clock RCLK, it must be synchronized with the write clock WCLK by the read-side read pointer synchronization unit 109.

[0045] For example, the configuration of the read-side read pointer synchronization unit 109 shown in Fig. 1 can be a commonly known two-stage flip-flop. The write-side coincidence detection unit 113 executes a coincidence comparison between the value of the read-side read pointer 111 synchronized on the write side according to the write clock WCLK and the value of the write-side read pointer 110. If the value of the read-side read pointer 111 does not match the value of the write-side read pointer 110, the write-side coincidence detection unit 113 enables the write-side read pointer increment 114 (114 = "1"). On the other hand, if the value of the read-side read pointer 111 matches the value of the write-side read pointer 110, the write-side read pointer increment 114 is disabled (114 = "0").

[0046] When the write-side read pointer increment 114 is valid (="1"), the write-side read pointer calculation unit 112 increments the write-side read pointer 110 (flag section rpf, pointer section rpp) for each cycle of the write clock WCLK. As described above, when the value of the pointer section rpp after increment becomes memory depth N, rpp is returned to 0 without being set to rpp=N, and the value of the flag section rpf is inverted.

[0047] When the write side read pointer 110 catches up with the read side read pointer 111 synchronized on the write side and the two match, the write side read pointer increment 114 becomes invalid (="0") and the write side read pointer 110 is not incremented. In other words, the value of the write side read pointer 110 is maintained.

[0048] Here, the read side read pointer 208, which is made up of multiple bits, is also synchronized by the read side read pointer synchronization unit 109, for example, by a two-stage flip-flop. For this reason, if the timing of the change in the read side read pointer 208 overlaps with the timing of the rising edge of the write clock WCLK, a so-called meta-stable state occurs, and there is a possibility that the value of the read side read pointer 208 cannot be correctly transferred to the value of the read side read pointer 111 synchronized on the write side. For this reason, if the write side read pointer 110 is used to determine whether or not writing is possible while retaining the incorrect value, there is a possibility that data writing will be performed even if there is no free space in the memory 300.

[0049] Therefore, in this embodiment, the value of the read-side read pointer 111 synchronized according to the write clock WCLK is not used as it is as the write-side read pointer 110, but when the write-side match detection unit 113 detects that the read-side read pointer 111 synchronized on the write side differs from the write-side read pointer 110, the values ​​of the pointer section wpp and flag section wpf are changed so that the write-side read pointer 110 is changed by 1 until the read-side read pointer 111 and the write-side read pointer 110 become equal. By adding such processing, it becomes possible for the write-side read pointer 110 to follow the read-side read pointer 208 and be transferred from the read side to the write side without any value errors.

[0050] As described above, a two-stage flip-flop can be applied to the read-side read pointer synchronization unit 109 as a synchronization circuit, but it is also possible to configure the read-side read pointer synchronization unit 109 using other synchronization methods. Furthermore, since the write-side coincidence detection unit 113 is configured to make the value of the write-side read pointer 110 follow the value read from the read side when there is a mismatch between the values ​​of the read-side read pointer 111, which have been synchronized according to the write clock WCLK, and the write-side read pointer 110, the read-side read pointer synchronization unit 109 can also be configured without using a synchronization circuit.

[0051] Next, a specific example of the transfer process of the read pointer from the memory read circuit 201 to the memory write circuit 101 will be described with reference to Fig. 4. In Fig. 4, the values ​​of the flag section rpf and the pointer section rpp for each of the read side read pointer 208, the read side read pointer 111 synchronized on the write side, and the write side read pointer 110 are represented as "rpf-rpp".

[0052] 4, the read side read pointer 208 has a flag section rpf=0 and a pointer section rpp=3 ("0-3"), and similarly, the read side read pointer 111 and the write side read pointer 110 synchronized on the write side have a flag section rpf=0 and a pointer section rpp=3 ("0-3"). That is, the read pointers are correctly recognized as a common value between the memory write circuit 101 and the memory read circuit 201.

[0053] From this state, in the memory read circuit 201, during the period in which the read-side read pointer increment 206 is valid (="1"), data is read from the memory 300 at each rising edge of the read clock RCLK. In response to the execution of the data read, the read-side read pointer 208 is incremented at each rising edge (RCLK).

[0054] 4, first, three data reads are executed at each of the three rising edges (RCLK), and the read side read pointer 208 is incremented at each clock edge. As a result, the read side read pointer 208 changes from "0-3" to "0-6". After that, one data read is executed twice, and the read side read pointer 208 changes from "0-6" to "1-0", and further changes from "1-0" to "1-1".

[0055] The read-side read pointer synchronization unit 109 of the memory write circuit 101 captures the value of the read-side read pointer 208 in response to the rising edge of the write clock WCLK, which is asynchronous with the read clock RCLK, thereby generating the read-side read pointer 111 synchronized with the write clock WCLK.

[0056] However, in the example of Figure 4, at time t1, the timing when the read side read pointer 208 changes from "0-3" to "0-4" coincides with the rising edge of the write clock WCLK. This creates a metastable state, so the value of the read side read pointer 111 synchronized on the write side is not fixed to one. This phenomenon is represented in Figure 4 as "≠0-3" because it becomes an indefinite value from "0-3".

[0057] In the example of FIG. 4, the other change timings of the read side read pointer 208 do not overlap with the rising edge of the write clock WCLK, so the value of the read side read pointer 208 is correctly captured in the read side read pointer 111 synchronized on the write side. Specifically, "0-6", "1-0", and "1-1" of the read side read pointer 208 are captured by the read side read pointer synchronization unit 109 at the rising edges (WCLK) of times t2, t5, and t7, and are reflected in the read side read pointer 111 synchronized on the write side at the next rising edges, times t3, t6, and t8, respectively. As described above, since the read side read pointer synchronization unit 109 is assumed to be configured with two-stage flip-flops, the value of the read side read pointer 208 is reflected in the read side read pointer 111 synchronized on the write side with the above-mentioned delay.

[0058] The write side read pointer increment 114 is set to valid (="1") in a cycle in which the read side read pointer 111 synchronized on the write side by the write side match detection unit 113 has a different value from the write side read pointer 110. Conversely, in a cycle in which the read side read pointer 111 and the write side read pointer 110 synchronized on the write side are the same, the write side read pointer increment 114 is set to invalid (="0").

[0059] When the write side read pointer calculation unit 112 confirms that the write side read pointer increment 114 is valid (="1"), it increments the write side read pointer 110 at the next rising edge of the write clock WCLK. On the other hand, when the write side read pointer increment 114 is invalid (="0"), the value of the write side read pointer 110 is maintained.

[0060] 4, the write side read pointer 110 is incremented at each rising edge of the write clock WCLK from time t3 to t5. As a result, the write side read pointer 110 changes to "0-6" at time t5, which is the value of the read side read pointer 111 synchronized on the write side and coincides with the read side read pointer 208. In this way, the undefined value ("≠ 0-3") that has become metastable is not directly captured in the read side read pointer 111 synchronized on the write side.

[0061] Subsequent changes in the read side read pointer 208 to "1-0" and "1-1" due to data reads are captured in the read side read pointer 111 synchronized on the write side in accordance with the write clock WCLK. Furthermore, the value of the write side read pointer 110 is incremented by enabling (="1") the write side read pointer increment 114 by the write side match detection unit 113 until it catches up with the value of the read side read pointer 111 synchronized on the write side.

[0062] In this manner, in this embodiment, the value of the read side read pointer 208 acquired in synchronization with the write clock WCLK is not used as is, but rather, when the acquired read pointer value (i.e., the value of the read side read pointer 111) differs from the value of the write side read pointer 110, a process is executed to change the write side read pointer 110 by 1. This allows the value of the write side read pointer 110 to change without error, following the change in the read side read pointer 208 accompanying the execution of a data read in the memory read circuit 201.

[0063] In this way, the memory read circuit 201 and the memory write circuit 101, which operate on different clocks, transfer the read pointer from the memory read circuit 201 to the memory write circuit 101 without error, thereby achieving synchronization of the pointers. As a result, by accurately determining whether data can be written in the memory write circuit 101, it becomes possible to correctly transfer data between asynchronous clocks via the memory 300.

[0064] Next, the read operation will be described with reference to Fig. 1 again. In a read operation, a read command RCMD is input to the read-side access control unit 203. At this time, if reading is possible, the read-side read enable 204 is enabled ("1") from the read-side access control unit 203. When the read-side read enable 204 is enabled, the read data RDAT is read from the read address of the memory 300 indicated by the read-side read pointer 208. At this time, if reading is not possible, no particular processing is performed on the memory 300 even if the read command RCMD is input.

[0065] An example of a calculation process for the number of reads possible in data reading is shown in Fig. 5. The readability can be determined according to the calculated value of the number of reads possible shown in Fig. 5.

[0066] 5, wpf indicates the value of the flag section of the read side write pointer 210, and wpp indicates the value of the pointer section of the read side write pointer 210. Also, rpf indicates the value of the flag section of the read side read pointer 208, and rpp indicates the value of the pointer section of the read side read pointer 208. N indicates the memory depth as in FIG. 2. The result of the determination of readability based on the readable number calculated according to FIG. 5 is reflected in the read permission RPRM and is output from the read side access control unit 203. Specifically, when the readable number is 0, RPRM is set to "0", while when the readable number is equal to or greater than any predetermined natural number, RPRM is set to "1".

[0067] Referring to FIG. 3 again, an example of the change in the write pointer (wpf, wpp) and read pointer (rpf, rpp) associated with data write and data read, as well as the number of readable data, will be described.

[0068] In the memory read circuit 201, the determination of whether reading is possible is executed by obtaining the number of readable data described in FIG. 5 using the values of the flag part wpf and pointer part wpp of the read-side write pointer 210 and the flag part rpf and pointer part rpp of the read-side read pointer 208.

[0069] As described above, in the example of FIG. 3, data writing is executed 5 times from the initial state where wpf = wpp = rpf = rpp = 0 (initial value). During this period, since data reading is not executed, rpf = rpp = 0 is also maintained. On the other hand, while wpf remains 0, wpp increases by 1 from 0 to 5 for each data write. At this time, the number of readable data is 0 in the initial state, but thereafter, it increases by 1 for each data write according to the arithmetic expression wpp - rpp shown in FIG. 5. After 5 data writes, the number of readable data has increased to wpp - rpp = 5.

[0070] Next, when 5 data reads are also executed after 5 data writes, rpp increases by 1 from 0 to 5 for each data read. Since rpp is within the range of rpp < N, rpf is maintained at 0. On the other hand, since data writing is not executed, the values of the write pointers are maintained at wpf = 0, wpp = 5 as before.

[0071] At this time, for each data read, the number of readable data decreases by 1 according to the arithmetic expression wpp - rpp shown in FIG. 5. In the state where the same number of data reads as data writes is completed, wpp = rpp (= 5), and wpf = wpf (= 0), and the number of readable data has returned to 0. At this time, the read permission RPRM is set to "0".

[0072] Subsequently, when seven data writes are performed from the state of rpp = 5 (rpf = 0), for the read - side read pointer 208, rpf = 0 and rpp = 5 are maintained. On the other hand, for the read - side write pointer 210, as described above, in the second data write, wpp is reset to 0 and the flag part wpf is inverted from "0" to "1". Then, after the seventh data write, wpf = 1 and wpp = 5. At this time, the number of readable data increases by 1 for each data write according to the arithmetic expressions shown in FIG. 5, specifically, wpp - rpp (when wpf = rpf and wpp > rpp), N+(wpp - rpp) (when wpf ≠ rpf and wpp < rpp), and N (when wpf ≠ rpf and wpp = rpp). After seven data writes, the number of readable data has increased to N = 7.

[0073] After the above - mentioned seven data writes, when seven data reads are also executed, as described above, in the second data read, rpp is reset to 0 and the flag part rpf is inverted from "0" to "1". Thereafter, under rpf = 1, rpp is incremented, and after the seventh data read, rpf = 1 and rpp = 5. At this time, the number of readable data decreases by 1 for each data read according to the arithmetic expressions shown in FIG. 5, specifically, N+(wpp - rpp) (when wpf ≠ rpf and wpp < rpp), wpp - rpp (when wpf = rpf and wpp > rpp), and 0 (when wpf = rpf and wpp = rpp). After the seventh data read, the number of readable data becomes 0. At this time, the read permission RPRM is set to "0".

[0074] Next, the synchronization process between the write - side and read - side of the write pointer will be described. Referring to FIG. 1 again, when data writing is performed, the write - side write pointer 108 changes. Since the write - side write pointer 108 is synchronized with the write clock WCLK, it is necessary to synchronize it with the read clock RCLK by the write - side write pointer synchronization unit 209.

[0075] The configuration of the write side write pointer synchronization unit 209 shown in Fig. 1 can also be a two-stage flip-flop, as described for the read side read pointer synchronization unit 109. The read side coincidence detection unit 213 executes a coincidence comparison between the value of the write side write pointer 211 synchronized on the read side according to the read clock RCLK and the value of the read side write pointer 210. If the value of the write side write pointer 211 and the value of the read side write pointer 210 do not match, the read side coincidence detection unit 213 enables the read side write pointer increment 214 (214 = "1"). On the other hand, if the value of the write side write pointer 211 and the value of the read side write pointer 210 do not match, the read side write pointer increment 214 is disabled (214 = "0").

[0076] When the read side write pointer increment 214 is valid (="1"), the read side write pointer calculation unit 212 increments the read side write pointer 210 (flag section wpf, pointer section wpp) for each cycle of the read clock RCLK. When the read side write pointer 210 catches up with the write side write pointer 211 synchronized on the read side and the two match, the read side write pointer increment 214 becomes invalid (="0") and the read side write pointer 210 is not incremented. That is, the value of the read side write pointer 210 is maintained.

[0077] Here, the write-side write pointer 108, which is made up of multiple bits, is also synchronized by the write-side write pointer synchronization unit 209, for example, by a two-stage flip-flop. For this reason, if the timing of the change in the write-side write pointer 108 overlaps with the timing of the rising edge of the read clock RCLK, a so-called meta-stable state occurs, and there is a possibility that the value of the write-side write pointer 108 cannot be correctly transferred to the value of the write-side write pointer 211 synchronized on the read side. For this reason, if the read-side write pointer 210 is used to determine whether or not a read is possible while the incorrect value remains, there is a possibility that a data read will be executed even if there is no unread data in the memory 300.

[0078] Therefore, in this embodiment, the value of the write side write pointer 211 synchronized according to the read clock RCLK is not used as it is as the read side write pointer 210, but when the read side coincidence detection unit 213 detects that the write side write pointer 211 synchronized on the read side is different from the read side write pointer 210, the values ​​of the pointer section rpp and the flag section rpf are changed so that the read side write pointer 210 is changed by 1 until the write side write pointer 211 synchronized on the read side becomes equal to the read side write pointer 210. By adding such processing, it becomes possible for the read side write pointer 210 to also follow the write side write pointer 108 and be transferred from the write side to the read side without any value error.

[0079] As described above, a two-stage flip-flop can be applied as a synchronization circuit to the write-side write pointer synchronization unit 209, but it is also possible to configure the write-side write pointer synchronization unit 209 using other synchronization methods. Furthermore, since the read-side match detection unit 213 is configured to make the value of the read-side write pointer 210 follow the value on the write side when the values ​​of the write-side write pointer 211 synchronized on the read side and the read-side write pointer 210 do not match, the write-side write pointer synchronization unit 209 can also be configured without using a synchronization circuit.

[0080] Next, a specific example of the transfer process of the write pointer from the memory write circuit 101 to the memory read circuit 201 will be described with reference to Fig. 6. In Fig. 6, the values ​​of the flag section wpf and the pointer section wpp for the write side write pointer 108, the write side write pointer 211 synchronized on the read side, and the read side write pointer 210 are expressed as "wpf-wpp" in the same manner as in Fig. 4.

[0081] 6, in the initial state, the write side write pointer 108 has a flag section wpf=0 and a pointer section wpp=3 ("0-3"), and similarly, the write side write pointer 211 and the read side write pointer 210 synchronized on the read side have a flag section wpf=0 and a pointer section wpp=3 ("0-3"). That is, the write pointers are in a state where a common value is correctly recognized between the memory read circuit 201 and the memory write circuit 101.

[0082] From this state, in the memory write circuit 101, during the period in which the write-side write pointer increment 106 is valid (="1"), data is written to the memory 300 at each rising edge of the write clock WCLK. In response to the execution of the data write, the write-side write pointer 108 is incremented at each rising edge (WCLK).

[0083] 6, first, three data writes are executed at each of the three rising edges (WCLK), and the write side write pointer 108 is incremented at each clock edge. As a result, the write side write pointer 108 changes from "0-3" to "0-6". After that, one data write is executed twice, and the write side write pointer 108 changes from "0-6" to "1-0", and further changes from "1-0" to "1-1".

[0084] The write-side write pointer synchronization unit 209 of the memory read circuit 201 captures the value of the write-side write pointer 108 in response to the rising edge of the read clock RCLK, which is asynchronous with the write clock WCLK. This generates a write-side write pointer 211 that is synchronized on the read side in accordance with the read clock RCLK.

[0085] 6, however, at time t10, the timing when the write pointer 108 on the write side changes from "0-3" to "0-4" coincides with the rising edge of the read clock RCLK. This causes a metastable state, so the value of the write pointer 211 on the read side that is synchronized is not fixed to one digit but becomes an indefinite value (expressed as "≠ 0-3" as in FIG. 4).

[0086] In the example of FIG. 6, the change timing of the other write side write pointers 108 does not overlap with the rising edge of the read clock RCLK, so the value of the write side write pointer 108 is correctly introduced into the write side write pointer 211 synchronized on the read side. Specifically, "0-4", "0-5", "0-6", "1-0", and "1-1" of the write side write pointer 108 are taken into the write side write pointer synchronization unit 209 at the rising edges (RCLK) of times t11, t13, t15, t18, and t21, and are reflected in the write side write pointer 211 synchronized on the read side at the next rising edges, times t12, t14, t16, t19, and t22. As described above, since the write side write pointer synchronization unit 209 is also assumed to be configured with a two-stage flip-flop, the value of the write side write pointer 108 is reflected in the write side write pointer 211 synchronized on the read side with the above-mentioned delay.

[0087] The read side write pointer increment 214 is set to valid (="1") in a cycle in which the write side write pointer 211 synchronized on the read side by the read side match detection unit 213 has a different value from the read side write pointer 210. Conversely, in a cycle in which the write side write pointer 211 and the read side write pointer 210 synchronized on the read side are the same, the read side write pointer increment 214 is set to invalid (="0").

[0088] When the read side write pointer calculation unit 212 confirms that the read side write pointer increment 214 is valid (="1"), it increments the read side write pointer 210 at the next rising edge of the read clock RCLK. On the other hand, when the read side write pointer increment 214 is invalid (="0"), the value of the read side write pointer 210 is maintained.

[0089] 6, the read side write pointer 210 is incremented at each rising edge of the read clock RCLK at times t12, t15, t17, t20, and t23. As a result, the read side write pointer 210 changes to "1-1" at time t23, which is the value of the write side write pointer 211 synchronized on the read side and coincides with the write side write pointer 108. In this way, the indefinite value ("≠ 0-3") that has become a metastable state is not directly captured by the write side write pointer 211 synchronized on the read side.

[0090] Furthermore, when the value of the read side write pointer 210 does not match the value of the write side write pointer 211 into which the correct value of the write side write pointer 108 has been captured, the read side match detection unit 213 enables (= "1") the read side write pointer increment 214, thereby incrementing the value until it catches up with the value of the write side write pointer 211 synchronized on the read side.

[0091] In this way, instead of using the value of the write side write pointer 108 captured in synchronization with the read clock RCLK as is, when the captured write pointer value (i.e., the value of the write side write pointer 211) differs from the value of the read side write pointer 210, the read side write pointer 210 is changed by 1. This makes it possible to change the value of the read side write pointer 210 without error by making it follow the change in the write side write pointer 108 that accompanies the execution of a data write in the memory write circuit 101.

[0092] This makes it possible to realize correct pointer synchronization that avoids erroneous transfer of pointer values ​​by transferring the write pointer from the memory write circuit 101 to the memory read circuit 201 without error between the memory write circuit 101 and the memory read circuit 201 that operate on different clocks. As a result, by accurately determining whether data can be read in the memory read circuit 201, it becomes possible to transfer data correctly between asynchronous clocks via the memory 300.

[0093] As described above, according to this embodiment, in the pointer transfer between asynchronous clocks, a change in the value of the pointer on the sending side is detected, and the pointer value on the receiving side is changed by 1 to follow the change, thereby preventing erroneous transfer and correctly synchronizing the pointers. As a result, correct data transfer via memory 300 becomes possible.

[0094] Furthermore, since the Gray code as in Patent Document 2 is not used, there is no need to use a memory capacity that is one address larger than the memory capacity accessed when there is an odd number of pointers, which prevents an increase in circuit size and power consumption.

[0095] In the present embodiment described above, the write clock WCLK corresponds to an example of the “first clock”, the read clock RCLK corresponds to an example of the “second clock”, the memory write circuit 101 corresponds to an example of the “first circuit”, and the memory read circuit 201 corresponds to an example of the “second circuit”.

[0096] Furthermore, in the memory write circuit 101, the write-side write pointer 108 corresponds to the "first pointer", the write-side write pointer generation unit 107 corresponds to the "first pointer generation unit", the read-side read pointer synchronization unit 109 corresponds to the "first synchronization unit", the write-side read pointer calculation unit 112 corresponds to the "first circuit-side pointer value calculation unit", and the write-side match detection unit 113 corresponds to an embodiment of the "first match detection unit". Also, the write-side read pointer 110 corresponds to the "second pointer calculated by the first circuit-side pointer value calculation unit", and the read-side read pointer 111 generated by the read-side read pointer synchronization unit 109 corresponds to the "second pointer taken in by the first synchronization unit".

[0097] Similarly, in the memory read circuit 201, the read-side read pointer 208 corresponds to the "second pointer", the read-side read pointer generation unit 207 corresponds to the "second pointer generation unit", the write-side write pointer synchronization unit 209 corresponds to the "second synchronization unit", the read-side write pointer calculation unit 212 corresponds to the "second circuit-side pointer value calculation unit", and the read-side match detection unit 213 corresponds to an embodiment of the "second match detection unit". Also, the read-side write pointer 210 corresponds to the "first pointer calculated by the second circuit-side pointer value calculation unit", and the write-side write pointer 211 generated by the write-side write pointer synchronization unit 209 corresponds to the "first pointer captured by the second synchronization unit".

[0098] In this embodiment, an example is shown in which each pointer is incremented for each data write and each data read, but even if each pointer is decremented for each data write and each data read, the memory control according to this embodiment can be applied. In this case, the same memory control can be realized by appropriately replacing "increment" with "decrement" in the description of this embodiment. That is, in this embodiment, each pointer value changes by 1 in a predetermined direction, either an increase direction or a decrease direction.

[0099] Furthermore, in this embodiment, the number of data stored in the memory 300 is not output to the outside, but information indicating the number of data stored may be output from the memory control device 100 to the outside. The number of clock cycles required for the operation of each circuit block is not limited to the above description and can be freely set. In addition, in the above, an example has been described in which the pointer transfer according to this embodiment is applied to both the transfer of the write pointer and the transfer of the read pointer, that is, to each of the bidirectional pointer transfers, but it is also possible to apply this embodiment to only one of the transfer of the write pointer and the transfer of the read pointer. For example, when this embodiment is applied only to the transfer of the write pointer, the arrangement of the write-side read pointer calculation unit 112 and the write-side coincidence detection unit 113 on the write side can be omitted from the configuration example of FIG. 1. Conversely, when this embodiment is applied only to the transfer of the read pointer, the arrangement of the read-side write pointer calculation unit 212 and the read-side coincidence detection unit 213 on the read side can be omitted from the configuration example of FIG. 1.

[0100] In addition, in this embodiment, memory control has been described as involving data write and data read to memory 300, but it is also possible to provide a pointer transfer device and pointer control method according to this embodiment by applying this embodiment only to the portion of pointer transfer between asynchronous clocks. In this case, too, the pointer transfer device and pointer control method can be configured so that this embodiment is applied to only one-way pointer transfer of bidirectional pointer transfer.

[0101] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0102] 100 memory control device, 101 memory write circuit, 103 write side access control unit, 104 write side write enable, 106 write side write pointer increment, 107 write side write pointer generation unit, 108 write side write pointer, 109 read side read pointer synchronization unit, 110 write side read pointer, 111 read side read pointer (write circuit side synchronization), 112 write side read pointer calculation unit, 113 write side match detection unit, 114 write side read pointer increment, 201 memory read circuit, 203 read side access control unit, 204 read side read enable, 206 read side read pointer increment, 207 read side read pointer generation unit, 208 read side read pointer, 209 write side write pointer synchronization unit, 210 read side write pointer, 211 write side write pointer (read circuit side synchronization), 212 read side write pointer calculation unit, 213 Read side match detection section, 214 read side write pointer increment, 300 memory, N memory depth, RCLK read clock, RCMD read instruction, RDAT read data, RPRM read enable, WCLK write clock, WCMD write instruction, WDAT write data, WPRM write enable, rpf flag section (read pointer), rpp pointer section (read pointer), rpf flag section (write pointer), wpp pointer section (write pointer).

Claims

1. A pointer transfer device disposed between a first circuit that performs a first operation, which is one of writing data to a memory and reading data from the memory, and a second circuit that performs a second operation, which is the other of writing data to the memory and reading data from the memory, The pointer transfer device includes: a first pointer generation unit that changes a first pointer by one in a predetermined direction, that is, an increase direction or a decrease direction, every time the first operation is executed by the first circuit in accordance with a first clock; a second pointer generation unit that changes a second pointer by one in the predetermined direction every time the second operation is executed by the second circuit in accordance with a second clock; a first synchronization unit that captures the value of the second pointer generated by the second pointer generation unit into the first circuit side in synchronization with the first clock; a first circuit side pointer value calculation unit that calculates a value of the second pointer on the first circuit side; a first coincidence detection unit that executes a coincidence comparison between the value of the second pointer calculated by the first circuit-side pointer value calculation unit and the value of the second pointer acquired by the first synchronization unit, the first circuit-side pointer value calculation unit changes the value of the second pointer by one in the predetermined direction for each cycle of the first clock while a mismatch is detected by the first match detection unit, and maintains the value of the second pointer when a match is detected by the first match detection unit; A pointer transfer device in which the first circuit grasps the status of the second operation on the memory by the second circuit using the value of the second pointer calculated by the first circuit side pointer value calculation unit, and then performs the first operation targeting the address of the memory indicated by the first pointer by the first pointer generation unit so that data is transferred correctly between the first circuit and the second circuit.

2. the one operation is the data writing, the other operation is the data read; 2. The pointer transfer device according to claim 1, wherein the first circuit performs the data writing using the value of the second pointer calculated by the first circuit side pointer value calculation unit so that the second circuit does not overwrite and erase data at addresses that have not been read from the memory.

3. The one operation is the data read, the other operation is the data writing, 2. The pointer transfer device of claim 1, wherein the first circuit performs the data read using the value of the second pointer calculated by the first circuit side pointer value calculation unit so as not to read data from an address to which no data has been written in the memory from the first circuit.

4. The pointer transfer device comprises: a second synchronization unit that captures the value of the first pointer generated by the first pointer generation unit into the second circuit side in synchronization with the second clock; a second circuit side pointer value calculation unit that calculates a value of the first pointer on the second circuit side; a second coincidence detection unit that executes a coincidence comparison between the value of the first pointer calculated by the second circuit-side pointer value calculation unit and the value of the first pointer acquired by the second synchronization unit, the second circuit-side pointer value calculation unit changes the value of the first pointer by one in the predetermined direction for each cycle of the second clock while a mismatch is detected by the second match detection unit, and maintains the value of the first pointer when a match is detected by the second match detection unit; The pointer transfer device of claim 1, wherein the second circuit grasps the status of the first operation on the memory by the first circuit using the value of the first pointer calculated by the second circuit side pointer value calculation unit, and then performs the second operation targeting the address of the memory indicated by the second pointer generated by the second pointer generation unit so that data is correctly transferred between the first circuit and the second circuit.

5. The first operation is the data writing, the second operation is the data read; the first circuit executes the data writing using the value of the second pointer calculated by the first circuit side pointer value calculation unit so that the second circuit does not overwrite and erase data at an address that has not been read from the memory; 5. The pointer transfer device of claim 4, wherein the second circuit performs the data read using the value of the first pointer calculated by the second circuit side pointer value calculation unit so as not to read data from an address to which no data has been written in the memory from the first circuit.

6. 6. The pointer transfer device of claim 5, wherein the first circuit calculates the possible number of times that data can be written to the memory based on the value of the first pointer generated by the first pointer generation unit, the value of the second pointer calculated by the first circuit side pointer value calculation unit, and a memory depth corresponding to the number of addresses of the memory.

7. 6. The pointer transfer device according to claim 5, wherein the second circuit calculates the possible number of times data can be read from the memory based on the value of the second pointer generated by the second pointer generation unit, the value of the first pointer calculated by the second circuit side pointer value calculation unit, and a memory depth corresponding to the number of addresses of the memory.

8. 1. A method for transferring a pointer between a first circuit that executes a first operation, which is one of writing data to a memory and reading data from the memory, in accordance with a first clock, and a second circuit that executes a second operation, which is the other of writing data and reading data, in accordance with a second clock, comprising: a step of changing a first pointer by one in a predetermined direction, that is, an increase direction or a decrease direction, on the first circuit side every time the first operation is executed; changing a second pointer by one in the predetermined direction on the second circuit side every time the second operation is executed; fetching the value of the second pointer on the second circuit side into the first circuit side in synchronization with the first clock; calculating a value of the second pointer on the first circuit side; a step of executing a comparison between the value of the second pointer calculated on the first circuit side and the value of the second pointer acquired from the second circuit side; The step of calculating the value of the second pointer includes: while a mismatch is detected in the step of performing the match comparison, changing the value of the second pointer by one in the predetermined direction for each cycle of the first clock; maintaining the value of the second pointer if a match is detected in the step of performing a match comparison; A pointer transfer method in which the first circuit uses the value of the second pointer calculated on the first circuit side to grasp the status of the second operation on the memory by the second circuit, and then performs the first operation targeting the address of the memory indicated by the first pointer on the first circuit side so that data is transferred correctly between the first circuit and the second circuit.

9. The method of claim 1, wherein the one operation is the data writing operation, the other operation is the data read; 9. The pointer transfer method according to claim 8, wherein the first circuit performs the data writing using the value of the second pointer calculated on the first circuit side so that the second circuit does not overwrite and erase data at addresses that have not been read from the memory.

10. the one operation is the data read; the other operation is the data writing, 9. The pointer transfer method according to claim 8, wherein the first circuit performs the data read using the value of the second pointer calculated on the first circuit side so as not to read data from an address to which no data has been written in the memory from the first circuit.

11. The pointer transfer method comprises: fetching the value of the first pointer on the first circuit side into the second circuit side in synchronization with the second clock; calculating a value of the first pointer on the second circuit side; and performing a comparison between the value of the first pointer calculated on the second circuit side and the value of the first pointer acquired from the first circuit side, The step of calculating the value of the first pointer includes: while a mismatch is detected in the step of performing the match comparison, changing the value of the first pointer by one in the predetermined direction for each cycle of the second clock; maintaining the value of the first pointer when a match is detected in the step of performing the match comparison; 9. The pointer transfer method of claim 8, wherein the second circuit grasps the status of the first operation on the memory by the first circuit using the value of the first pointer calculated on the second circuit side, and then performs the second operation on the address of the memory indicated by the second pointer on the second circuit side so that data is correctly transferred between the first circuit and the second circuit.

12. The method according to claim 1, wherein the first operation is the data writing, the second operation is the data read; the first circuit executes the data writing using the value of the second pointer calculated on the first circuit side so that the second circuit does not overwrite and erase data at an address that has not been read from the memory; The pointer transfer method according to claim 11, wherein the second circuit performs the data read using the value of the first pointer calculated on the second circuit side so as not to read data from an address to which no data has been written in the memory from the first circuit.

13. 13. The pointer transfer method according to claim 12, wherein the number of times data can be written to the memory is calculated on the first circuit side based on the value of the first pointer generated on the first circuit side, the value of the second pointer calculated on the first circuit side, and a memory depth corresponding to the number of addresses of the memory.

14. 13. The pointer transfer method according to claim 12, wherein the number of times data can be read from the memory is calculated on the second circuit side based on the value of the second pointer generated on the second circuit side, the value of the first pointer calculated on the second circuit side, and a memory depth corresponding to the number of addresses of the memory.

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