Memory System

Abstract

To provide a memory system capable of reducing current consumption of a memory controller.SOLUTION: A memory system according to an embodiment comprises a non-volatile memory which stores table data, and a controller which performs prescribed control including data writing into the non-volatile memory and data reading from the non-volatile memory on the basis of a request from a host. The controller comprises a volatile memory which can use a retention state in which power is supplied and a part of the table data is retained and a power-down state in which the power is cut off when the memory system makes a transition to a low power state, a timer which starts measurement when the memory system makes a transition to the low power state, and a register which stores a history of time at which the memory system recovers from the low power state. When a measured value of the timer is higher than or equal to a threshold value calculated on the basis of an average value of the history, the controller causes the non-volatile memory to make a transition from the retention state to the power-down state.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present invention relate to a memory system. [Background technology]

[0002] 2. Description of the Related Art A memory system including a nonvolatile memory such as a NAND flash memory and a memory controller is known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-156707 A [Patent Document 2] JP 2015-232772 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a memory system capable of reducing the current consumption of a memory controller. [Means for solving the problem]

[0005] A memory system according to an embodiment is a memory system that can be connected to a host and can transition to a low power state or a power off state when a command is received from the host. The memory system has a non-volatile memory that stores table data, and performs predetermined control including writing and reading data to the non-volatile memory based on a request from the host. Memory and a controller. Memory The controller has a volatile memory that can take either a retention state in which power is supplied and a portion of the table data is retained, or a power-down state in which power is cut off when the memory system transitions to a low-power state, a timer that begins measuring when the memory system transitions to the low-power state, and a register that stores a history of the time it takes to return from the low-power state. Memory When the measured value of the timer is equal to or greater than a threshold calculated based on an average value of the history, the controller transitions the volatile memory from the retention state to the power-down state. [Brief description of the drawings]

[0006] [Figure 1] 1 is a diagram illustrating an example of the overall configuration of a memory system according to a first embodiment. [Diagram 2] 2 is a diagram showing a current-carrying state of each block in the memory system of FIG. 1 in a retention state; FIG. [Diagram 3] 2 is a diagram showing a current-carrying state of each block in the memory system of FIG. 1 in a power-down state. [Figure 4] 1 is a circuit diagram of a retention SRAM according to a first embodiment. [Diagram 5] 11A and 11B are diagrams illustrating updating of a timer threshold and an outlier value in the memory system according to the first embodiment. [Figure 6] FIG. 2 is a diagram illustrating an example of the configuration of a storage unit according to the first embodiment. [Figure 7] 1 is a diagram showing an example of the configuration of a memory chip according to a first embodiment; [Figure 8] FIG. 2 is a diagram illustrating an example of the operation of the memory system according to the first embodiment. [Figure 9] 11 is a timing chart of a memory system according to a comparative example. [Figure 10] 4 is a timing chart of the memory system according to the first embodiment. [Figure 11] FIG. 11 is a diagram illustrating an example of the overall configuration of a memory system according to a second embodiment. [Figure 12] FIG. 11 is a diagram illustrating an example of the operation of the memory system according to the second embodiment. [Figure 13] FIG. 11 is a diagram illustrating an example of the operation of a memory system according to a modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, the embodiments will be described with reference to the drawings. In the following description, components having the same functions and configurations are given the same reference numerals. Furthermore, each embodiment shown below is an example of an apparatus or method for embodying the technical idea of ​​this embodiment, and the arrangement of each component and the connection relationship between each component are not limited to the form described below.

[0008] In addition, each functional block can be realized as either hardware or computer software, or a combination of both. For this reason, each functional block is generally described in terms of its function so that it is clear that each functional block can be either of these. Furthermore, each functional block does not necessarily have to be divided as in the illustrated embodiment. For example, some functions may be performed in cooperation with a functional block other than the illustrated functional block. Furthermore, the illustrated functional blocks may be further divided into smaller functional subblocks.

[0009] (1) First embodiment The memory system of the first embodiment will be described with reference to FIGS.

[0010] (1)-(a) Example of memory system configuration 1 is a block diagram showing an example of the overall configuration of a memory system 1 connected to a host 4. The memory system 1 is connected to the host 4 via a communication line 5 and functions as an external storage device for the host 4. The memory system 1 is an embedded flash memory or a solid state drive (SSD) that complies with the UFS (Universal Flash Storage) standard or the eMMC (embedded Multi Media Card) standard. The memory system 1 includes a memory controller 2 and a nonvolatile memory 3.

[0011] The host 4 may be, for example, an information processing device such as a personal computer, a mobile phone, an imaging device, a portable terminal such as a tablet computer or a smartphone, a game device, or an in-vehicle terminal such as a car navigation system. The host 4 and the memory system 1 can transmit and receive packets conforming to, for example, the UFS standard, the SAS (Serial Attached SCSI) standard, the SATA (Serial Advanced Technology Attachment) standard, the PCIe (registered trademark) (Peripheral Component Interconnect express) standard, and the NVMe (registered trademark) (Non-Volatile Memory express) standard via the communication line 5.

[0012] The memory system 1 transitions to the hibernation state upon receiving a command (Hibernate enter request) from the host 4 to transition to the hibernation state. The memory system 1 returns from the hibernation state upon receiving a command (Hibernate exit request) from the host 4. The hibernation state is a state (low power state) in which power consumption is reduced when the memory system 1 is not in use. Furthermore, the memory system 1 may transition from the hibernation state to a power off state upon request from the host 4. The power off state is a state in which the power supply of the memory system 1 is completely cut off. In particular, in a memory system that is not connected to an AC power source and is powered by a battery, the power supply can be made to last longer by appropriately entering the hibernation state.

[0013] The memory controller 2 includes, for example, a host interface (I / F) circuit 21, a timer 22, an oscillator 23, a CPU (Central Processing Unit) 24, a table cache 25, a memory interface (I / F) circuit 26, a storage unit 27, and an SRAM (Static Random Access Memory) power supply control circuit 28. These are connected by a bus 29. The memory controller 2 can be implemented as a controller package including, for example, a SoC (System-on-a-Chip).

[0014] The host I / F circuit 21 performs interface processing between the memory controller 2 and the host 4. The host I / F circuit 21 is connected to the host 4 via a communication line 5. Note that a wireless connection may be used without using the communication line 5. The host I / F circuit 21 has a communication detection unit 212. The communication detection unit 212 checks the amplitude of the signal line connected to the host 4. When the memory system 1 checks the amplitude of the signal line from the host 4, it assumes that communication with the host 4 has started, and returns from the hibernation state.

[0015] The timer 22 starts measuring when the memory system 1 transitions to the hibernation state, and initializes the measured value when the memory system 1 returns from the hibernation state.

[0016] The oscillator 23 is connected to the timer 22. The oscillator 23 is, for example, an RC oscillator. The oscillator 23 can operate even when the memory system 1 is in a hibernation state. Therefore, the operation of the oscillator 23 allows the timer 22 to continue measuring. The oscillator 23 stops operating when the table cache 25, which will be described later, transitions to a power-down state.

[0017] The CPU 24 controls the operation of the entire memory controller 2. The program that controls the CPU 24 uses firmware (control program, etc.) stored in a ROM (Read Only Memory) 272 (described later), or loads a program held in the ROM 272 onto a RAM (Random Access Memory) 274 (described later) to execute a predetermined process. That is, the CPU 24 creates various tables on the RAM 274, receives a write command, a read command, and an erase command from the host 4, and writes, reads, and erases data from the nonvolatile memory 3. The commands may also be called, for example, instructions or requests. Data transfers such as writing data to the nonvolatile memory 3 and reading data from the nonvolatile memory 3 are performed between the CPU 24 and the external host 4 via the memory I / F circuit 26 and the host I / F circuit 21.

[0018] The table cache 25 temporarily holds table data. The table data is a data set having a predetermined size. The table data is, for example, at least a part of a logical-to-physical address conversion table (L2P table) described later.

[0019] The table cache 25 is composed of a volatile memory such as an SRAM or a register, etc. In this embodiment, a case where the table cache 25 is composed of a retention SRAM 25 will be described.

[0020] The retention SRAM 25 includes a storage unit 252 and a control circuit 254. The storage unit 252 temporarily stores table data. The storage unit 252 may also be referred to as a data retention circuit 252. The control circuit 254 performs control required for writing and reading data to and from the storage unit 252. The control circuit 254 performs, for example, addressing and clock gating control.

[0021] 2 and 3 are diagrams showing the energization state of each block in FIG. 1 when the memory system 1 is in a hibernation state. FIG. 2 shows the energization state when the retention SRAM 25 is in a retention state. In the retention state, in the table cache 25, power is supplied to the storage unit 252 to temporarily hold table data, while power supply to the control circuit 254 is stopped, thereby reducing power consumption. Data cannot be input or output to the storage unit 252. FIG. 3 shows the energization state when the retention SRAM 25 is in a power-down state. In the power-down state, power supply to the storage unit 252 and the control circuit 254 is stopped in the table cache 25, thereby reducing power consumption even more than in the retention state. The table data held by the storage unit 252 is lost. When the memory system 1 is in hibernation state, power is cut off to the host I / F circuit 21 (excluding the communication detection unit 212), CPU 24, table cache 25 (part or all), memory I / F circuit 26, and non-volatile memory 3, as shown by the shaded areas in Figures 2 and 3.

[0022] When the memory system 1 transitions to the hibernation state, the retention SRAM 25 can be in one of two states: a retention state or a power-down state.

[0023] The timing at which the retention SRAM 25 transitions from the retention state to the power-down state is determined by the threshold value of the timer 22 set by the CPU 24. In the following description, the time from when the retention SRAM 25 transitions to the retention state until the memory system 1 returns from the hibernation state or when the retention SRAM 25 transitions to the power-down state is referred to as the retention residence time.

[0024] 4 is a circuit diagram of the retention SRAM 25. The following description will focus on the main components of the retention SRAM 25 circuit, but the retention SRAM 25 circuit may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0025] A power supply voltage VDD is applied to a power supply line 256 , and a ground voltage VSS is applied to a ground line 258 .

[0026] A power supply voltage VDD is supplied to the power switch PWS1 via a source terminal. The power switch PWS1 supplies or cuts off the power supply voltage VDD to the storage unit 252 in response to a control signal PWS1EN supplied to the gate terminal. That is, when the retention SRAM 25 transitions to a power-down state, the power switch PWS1 is turned off by the control signal PWS1EN. Then, the power supply to the storage unit 252 is stopped.

[0027] A power supply voltage VDD is supplied to the power switch PWS2 via a source terminal. The power switch PWS2 supplies or cuts off the power supply voltage VDD to the control circuit 254 in response to a control signal PWS2EN supplied to a gate terminal. That is, when the retention SRAM 25 transitions to the retention state, the power switch PWS2 is turned off by the control signal PWS2EN. Then, the power supply to the control circuit 254 is stopped.

[0028] When the memory system 1 returns from the hibernation state, the CPU 24 updates the hibernation return time in the register 276, which will be described later. Furthermore, the CPU 24 updates the threshold and outlier of the timer 22. The timer 22 determines by itself whether a measured value is equal to or greater than the threshold. The timer 22 determines by itself whether a measured value corresponds to an outlier. The host 4 sets the initial values ​​of the threshold and outlier of the timer 22 to arbitrary values. These initial values ​​are used when the memory system 1 transitions to the hibernation state for the first time.

[0029] The threshold of the timer 22 is, for example, n_times times the average value (average hibernation return time) of the history of hibernation return times held in the register 276. n_times is a positive integer value greater than x_range, which will be described later. When the measured value of the timer 22 becomes equal to or greater than the threshold, the retention SRAM 25 transitions from the retention state to the power-down state.

[0030] The outlier of the timer 22 is, for example, a value that falls within a range of x_range times or more of the average hibernation recovery time and less than a threshold value. x_range is a positive integer value smaller than n_times. If the memory system 1 requires a time that falls within the outlier to recover from the hibernation state, the CPU 24 discards the history of the hibernation recovery time held in the register 276. Then, the CPU 24 updates the timer measurement value as a new history in the register 276. Note that this operation is performed while power is being supplied to the CPU 24.

[0031] 5 is a diagram for explaining updating of the threshold and outlier of the timer 22. For example, the CPU 24 sets n_times to 10 and x_range to 4. If the average hibernation recovery time is 15 ms, the CPU 24 sets the threshold of the timer 22 to 15 ms×10=150 ms. The CPU 24 also sets the range corresponding to the outlier of the timer 22 to 15 ms×4=60 ms or more and less than 150 ms.

[0032] When the hibernation return time is 75 ms, it is an outlier and is a value that is significantly different from the average hibernation return time of 15 ms. Therefore, the CPU 24 discards the history of the hibernation return time stored in the register 276, and then updates the history in the register 276 with the measurement value of the timer 22. Thereafter, every time the memory system 1 repeats transitions to and returns from the hibernation state, the history of the hibernation return time is accumulated in the register 276.

[0033] When the measured value of the timer 22 reaches or exceeds the threshold value of 150 ms, the retention SRAM 25 transitions from the retention state to the power down state. Note that, if the hibernation return time is equal to or greater than the threshold value, the CPU 24 does not discard or update the history of the hibernation return time stored in the register 276.

[0034] The CPU 24 can change the values ​​of n_times and x_range as appropriate. The host 4 may also change the values ​​of n_times and x_range. The threshold value of the timer 22 is determined based on the average hibernation recovery time, so an upper limit and a lower limit are set for the threshold value. The upper limit and lower limit of the threshold value can be changed by the host 4.

[0035] 6 is a diagram showing an example of the configuration of the storage unit 27. The storage unit 27 has a ROM 272, a RAM 274, and a register 276. The register 276 stores, for example, the upper and lower limit values ​​of the threshold of the timer 22 and a history of the hibernation return time.

[0036] When the measured value of the timer 22 becomes equal to or greater than the threshold value, the SRAM power supply control circuit 28 transitions the retention SRAM 25 from the retention state to the power down state.

[0037] The memory I / F circuit 26 performs interface processing between the memory controller 2 and the nonvolatile memory 3. The memory I / F circuit 26 is connected via a communication line 6 to a memory chip 30, which will be described later.

[0038] The nonvolatile memory 3 is, for example, a NAND type flash memory including memory cells with a stacked gate structure or memory cells with a MONOS structure. In a NAND type flash memory, writing and reading are generally performed in data units called pages, and erasure is performed in data units called blocks. The nonvolatile memory 3 may be disposed outside the memory controller 2 and implemented as a nonvolatile memory package. The nonvolatile memory 3 includes one or more memory chips 30. FIG. 1 illustrates memory chips 30-1 to 30-n (n is a natural number equal to or greater than 1) as an example. Each of the memory chips 30 can operate independently of the others.

[0039] The non-volatile memory 3 stores, for example, user data and management information such as a logical-physical address conversion table. The logical-physical address conversion table is referred to as an address conversion table in the following description. The address conversion table manages the mapping between each logical address and each physical address of the non-volatile memory 3. The logical address is an address used by the host 4 to address a location in the logical space of the memory system 1. As this logical address, an LBA (Logical Block Address) may be used. The physical address indicates a physical storage location in the non-volatile memory 3 where data is stored. The address conversion table is used to convert the logical address into a physical address that indicates a physical storage location in the non-volatile memory 3 where the data corresponding to this logical address is stored.

[0040] Usually, in an initial state such as immediately after the memory system 1 is powered on, the table cache 25 is empty. Address conversion data (table data) used for logical-physical address conversion is cached in the table cache 25. If a physical address (table data including at least this physical address) corresponding to a logical address specified by the host 4 exists in the table cache 25, the memory controller 2 reads this physical address (table data) from the table cache 25 instead of reading the address conversion table of the nonvolatile memory 3. This can reduce the number of times the address conversion table of the nonvolatile memory 3 is read when a read command is received from the host 4, thereby improving the performance of the memory system 1.

[0041] Next, a configuration example of the memory chip 30 will be described with reference to Fig. 7. Fig. 7 is a block diagram showing an example of the configuration of the memory chip 30. The memory chip 30 includes an input / output circuit 31, a logic controller 32, a ready / busy control circuit 33, a register 34, a sequencer 35, a voltage generation circuit 36, a sense amplifier module 37, a row decoder module 38, and a memory cell array 39.

[0042] The input / output circuit 31 transmits and receives, for example, 8-bit input / output signals I / O (I / O1 to I / O8) to and from the memory controller 2. For example, the input / output circuit 31 transfers write data DAT included in the input / output signals I / O received from the memory controller 2 to the sense amplifier module 37. In addition, the input / output circuit 31 transmits read data DAT transferred from the sense amplifier module 37 to the memory controller 2 as the input / output signals I / O.

[0043] The logic controller 32 controls the input / output circuit 31 and the sequencer 35 based on various control signals received from the memory controller 2. For example, a chip enable signal / CE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal / WE, a read enable signal / RE, and a write protect signal / WP are used as various control signals. The signal / CE is a signal for enabling the memory chip 30. The signal CLE is a signal for notifying the input / output circuit 31 that a signal input to the memory chip 30 in parallel with the asserted signal CLE is a command CMD. The signal ALE is a signal for notifying the input / output circuit 31 that a signal input to the memory chip 30 in parallel with the asserted signal ALE is address information ADD. The signals / WE and / RE are signals for instructing the input / output circuit 31 to input and output, for example, the input / output signal I / O, respectively. The signal / WP is a signal for putting the memory chip 30 into a protected state when, for example, the power is turned on and off.

[0044] The ready / busy control circuit 33 generates a ready / busy signal RBn based on the operation state of the sequencer 35. The signal RBn is a signal that notifies the memory controller 2 whether the memory chip 30 is in a ready state in which it can accept commands from the memory controller 2, or in a busy state in which it cannot accept commands.

[0045] The register 34 includes a status register 34A, an address register 34B, and a command register 34C. The status register 34A holds, for example, status information STS of the sequencer 35, and transfers the status information STS to the input / output circuit 31 based on an instruction from the sequencer 35. The address register 34B holds address information ADD transferred from the input / output circuit 31. The block address, column address, and page address included in the address information ADD are used by the row decoder module 38, the sense amplifier module 37, and the voltage generation circuit 36, respectively. The command register 34C holds a command CMD transferred from the input / output circuit 31.

[0046] The sequencer 35 controls the operation of the entire memory chip 30 based on the command CMD held in the command register 34C. For example, the sequencer 35 controls the voltage generation circuit 36, the sense amplifier module 37, the row decoder module 38, etc., to execute various operations such as a write operation and a read operation.

[0047] The voltage generation circuit 36 ​​generates a desired voltage based on the control of the sequencer 35, and supplies the generated voltage to the sense amplifier module 37, the row decoder module 38, the memory cell array 39, etc. For example, the voltage generation circuit 36 ​​applies a desired voltage to a signal line corresponding to a selected word line and a signal line corresponding to an unselected word line based on a page address held in the address register 34B.

[0048] The sense amplifier module 37 outputs data DAT read from the memory cell array 39 to the memory controller 2 via the input / output circuit 31. In addition, the sense amplifier module 37 transfers write data DAT received from the memory controller 2 via the input / output circuit 31 to the memory cell array 39.

[0049] The row decoder module 38 selects a block BLK on which various operations are to be performed based on the block address held in the address register 34B. Then, the row decoder module 38 transfers the voltage supplied from the voltage generating circuit 36 ​​to the selected block BLK.

[0050] The memory cell array 39 includes a plurality of blocks BLK, each including a plurality of non-volatile memory cells associated with rows and columns. In Fig. 7, blocks BLK0 to BLKn (n is a natural number equal to or greater than 1) are illustrated as an example. The memory cell array 39 stores data provided by the memory controller 2.

[0051] (1)-(b) Example of memory system operation Next, an example of the operation of the memory system 1 will be described with reference to FIG. First, when the memory system 1 receives a Hibernate enter request command from the host 4 and transitions to a hibernation state, the timer 22 starts measuring (S11). If the measured value of the timer 22 corresponds to the outlier (Yes in S12), the process proceeds to S15. If the measured value of the timer 22 does not fall under the outlier (No in S12), the process proceeds to S13. If the memory system 1 has not received the Hibernate exit request command from the host 4 and has not returned from the hibernation state (No in S13), the process returns to S12 and the same process as described above is performed. When the memory system 1 receives a Hibernate exit request command from the host 4 and returns from the hibernation state (Yes in S13), the CPU 24 updates the hibernation return time in the register 276, and the timer 22 initializes the measured value (S14). Then, the process ends. If the measured value of the timer 22 is less than the threshold value (No in S15), the process proceeds to S16. If the memory system 1 has not received the Hibernate exit request command from the host 4 and has not returned from the hibernation state (No in S16), the process returns to S15 and the same process as described above is performed. When the memory system 1 receives a Hibernate exit request command from the host 4 and returns from the hibernation state (Yes in S16), the CPU 24 discards the history of the hibernation return time stored in the register 276 (S17). Then, the CPU 24 updates the hibernation return time in the register 276 when Yes is determined in S16 (S17). The timer 22 initializes the measured value (S17). Then, the process ends. If the measured value of the timer 22 is equal to or greater than the threshold value (Yes in S15), the SRAM power supply control circuit 28 cuts off the power supply to the storage unit 252 of the retention SRAM 25, causing the retention SRAM 25 to transition to a power-down state (S18). Then, the timer 22 initializes the measured value (S18). Then, the process ends. It is advisable to start with a larger threshold value and gradually narrow it down to a smaller value depending on the usage of the memory system. The memory system 1 is controlled in the above manner.

[0052] Fig. 9 is a timing chart of a memory system according to a comparative example. Fig. 10 is a timing chart of the memory system 1 according to this embodiment. In Fig. 9 and Fig. 10, when each memory system or retention SRAM transitions to a certain state, it is shown at a High ("H") level, and when it returns from a certain state, it is shown at a Low ("L") level.

[0053] In the memory system of the comparative example, table data is held in a retention SRAM in order to shorten the recovery time from the hibernation state. At this time, if the hibernation state continues for a long time, the retention SRAM consumes a corresponding amount of current. However, after the memory system returns from the hibernation state, the table data held in the retention SRAM may not be referenced. In the memory system of the comparative example, even if there is a high possibility that the table data held in the retention SRAM will not be referenced, the retention state is maintained until the system returns from the hibernation state.

[0054] On the other hand, in the memory system 1 according to the present embodiment, a threshold is set for the retention residence time of the retention SRAM 25. The threshold is calculated based on the average value of the history of hibernation recovery times. If the retention residence time of the retention SRAM 25 exceeds the set threshold, there is a high possibility that the table data held by the retention SRAM 25 will not be referenced after the memory system 1 returns from the hibernation state. Therefore, the SRAM power supply control circuit 28 cuts off the power supply to the storage unit 252 of the retention SRAM 25, and transitions the retention SRAM 25 to a power-down state. As a result, it is possible to reduce the current consumption by the amount equivalent to cutting off the power supply to the data retention circuit of the retention SRAM 25.

[0055] (2) Second embodiment The memory system of the second embodiment will be described with reference to FIGS.

[0056] (2)-(a) Example of memory system configuration 11 is a block diagram showing an example of the overall configuration of a memory system 1a connected to a host 4. The memory system 1a according to the second embodiment is basically configured similarly to the memory system 1 according to the first embodiment, but differs in that it has a counter 52 and a counter 54.

[0057] The counter 52 counts the number of times the table data is newly updated in the retention SRAM 25. The table data is, for example, at least a part of a logical-physical address conversion table. The counter 54 counts the number of memory accesses. The memory access means writing data to the non-volatile memory 3 and reading data. When the memory system 1a transitions to the hibernation state, the power supply to the counter 52 and the counter 54 may be cut off. The values ​​measured by the counter 52 and the counter 54 become 0 (initial value) after the memory system 1a returns from the hibernation state. Then, the counter 52 and the counter 54 count again the number of times the table data is newly updated in the retention SRAM 25 and the number of memory accesses, respectively.

[0058] (2)-(b) Example of memory system operation Next, an example of the operation of the memory system 1a will be described with reference to FIG. First, the memory system 1a receives a Hibernate enter request command from the host 4 and transitions to a hibernation state (S22). Next, the memory system 1a receives a Hibernate exit request command from the host 4 and returns from the hibernation state (S23). Next, when the memory system 1a receives a Hibernate enter request command from the host 4 after returning from the hibernation state (Yes in S24), the process returns to S22 and the same process as described above is performed. Next, if the memory system 1a has not received a Hibernate enter request command from the host 4 after returning from the hibernation state (No in S24), the process proceeds to S25. If memory access has not been performed N_count times (No in S25), the process returns to S24 and the same process as described above is performed. If memory access has been performed N_count times (Yes in S25), proceed to S26. When the table data has been updated M_count times (Yes in S26), the CPU 24 decreases the threshold value of the timer 22 by d_time (S27), and then ends the process. If the table data has not been updated M_count times (No in S26), the CPU 24 increments the threshold value i_time of the timer 22 (S28), and then ends the process. The memory system 1a is controlled in the above manner.

[0059] The CPU 24 can change the values ​​of N_count, M_count, i_time, and d_time as appropriate. Note that the host 4 may also change the values ​​of N_count, M_count, i_time, and d_time.

[0060] In the memory system 1a according to this embodiment, a threshold is set for the retention residence time of the retention SRAM 25. The threshold is calculated based on the number of times table data is newly updated in the retention SRAM 25. If the retention residence time of the retention SRAM 25 exceeds the set threshold, there is a high possibility that the table data held by the retention SRAM 25 will not be referenced after the memory system 1a returns from the hibernation state. Therefore, the SRAM power supply control circuit 28 cuts off the power supply to the storage unit 252 of the retention SRAM 25, and transitions the retention SRAM 25 to a power-down state. As a result, it is possible to reduce the current consumption by the amount of the power supply to the data holding circuit of the retention SRAM 25 being cut off.

[0061] (3) Modifications In the above embodiment, every time the threshold value of the timer 22 is updated, the threshold value of the timer 22 may be written to the non-volatile memory 3. Then, the threshold value of the timer 22 written in the non-volatile memory 3 may be read out and used as necessary.

[0062] An example of the operation of the memory system 1 (1a) according to the modified example will be described with reference to FIG. If the threshold value of the timer 22 needs to be updated (Yes in S31), the updated threshold value of the timer 22 is written to the non-volatile memory 3 (S32). Then, the process ends. Next, if the threshold value of the timer 22 has not been updated (No in S31), the process ends. As described above, the memory system 1 (1a) according to the modified example is controlled.

[0063] The CPU 24 of the memory system 1(1a) sets the threshold value of the timer 22 based on the likelihood that the memory system 1(1a) will refer to the table data stored in the retention SRAM 25 after returning from the hibernation state. If the memory system 1(1a) continues to be completely unused, it may enter a power-off state in which the power supply to the memory system 1(1a) is completely cut off. When the memory system 1(1a) transitions to the power-off state, values ​​such as the history of the hibernation return time stored in the register 276 are erased. Therefore, it is not possible to refer to the threshold value of the timer 22 before the memory system 1(1a) transitioned to the power-off state.

[0064] In this modified example, when the memory system 1 (1a) is used again, by referring to the threshold value of the timer 22 that has been made nonvolatile, it is possible to operate the memory system 1 (1a) in accordance with the way it was used before it transitioned to the power-off state. That is, by writing the threshold value of the timer 22 to the nonvolatile memory 3 and making it nonvolatile, it is possible to carry over the same setting even if, for example, the power of the host 4 is turned off once and then turned on again.

[0065] According to at least one embodiment of the memory system described above, when the memory system transitions to a low power state, the current consumption of the table cache can be reduced by controlling the timing of transitioning the table cache from a retention state to a power down state based on either (1) a threshold using the average value of the history of the time it takes to return from a low power state, or (2) the number of times data is written to and read from the non-volatile memory and the number of times a portion of the table data is updated in the table cache.

[0066] The above-described embodiments and modifications may be combined to the extent possible. For example, the modifications may be combined with either the first embodiment or the second embodiment.

[0067] In the above embodiments and variant examples, the term "connection" is not limited to cases where two components are directly connected without any other elements being involved, but may also include cases where two components are indirectly connected via other elements, as appropriate, depending on the relationship between the components.

[0068] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0069] 1. Memory System 2. Memory Controller 3. Non-volatile memory 4 Host 5, 6 Communication lines 21 Host I / F circuit 22 Timer 23 Oscillators 24 CPU 25 Table Cache 26 Memory I / F circuit 27 Memory section 28 SRAM power supply control circuit 29 Bus 30 Memory chips 31 Input / Output Circuit 32 Logic Controller 33 Ready / Busy Control Circuit 34 Registers 35 Sequencer 36 Voltage Generation Circuit 37 Sense Amplifier Module 38 Row Decoder Module 39 Memory Cell Array 52, 54 Counter 212 Communication detection unit 252 Storage section 254 Control circuit 256 Power line 258 Grand Line 272 ROM 274 RAM 276 Registers

Claims

1. 1. A memory system connectable to a host and capable of transitioning to a low power or powered off state upon receiving a command from the host, comprising: A non-volatile memory for storing table data; a memory controller that executes a predetermined control including writing and reading data to the non-volatile memory based on a request from the host; The memory controller includes: a volatile memory that can take either a retention state in which power is supplied and a portion of the table data is retained, or a power-down state in which power is cut off, when the memory system transitions to the low power state; a timer that starts measuring when the state transitions to the low power state; a register for storing a history of the time taken to return from the low power state; the memory controller transitions the volatile memory from the retention state to the power down state when the measured value of the timer is equal to or greater than a threshold calculated based on an average value of the history; Memory system.

2. 2. The memory system according to claim 1, wherein the threshold value is a value that is set based on the average value and a first value.

3. 3. The memory system of claim 2, wherein the memory controller discards the history if the measurement value of the timer when returning from the low power state corresponds to an outlier that is greater than or equal to a value set based on a second value smaller than the first value and the average value and less than the threshold.

4. 4. The memory system of claim 3, wherein the memory controller stores the time to return from the low power state in the register if the measured value of the timer when returning from the low power state is less than a value set based on the average value and the second value.

5. 2. The memory system according to claim 1, wherein the table data is a logical-physical address conversion table.

6. The volatile memory includes: a storage unit for temporarily storing a portion of the table data; A control circuit for controlling input and output of data to the storage unit, The memory system according to any one of claims 1 to 5, which is a retention SRAM that can take either the retention state in which power is supplied to the memory unit and the power supply to the control circuit is cut off during the low power state, or the power down state in which power supply to both the memory unit and the control circuit is cut off.

7. 6. The memory system of claim 1, wherein the memory controller writes the threshold to the non-volatile memory each time the threshold is updated, and reads the threshold written to the non-volatile memory when returning from the low power state or the power off state.

8. the low power state is a hibernation state; 6. The memory system according to claim 1, wherein the non-volatile memory is a NAND type flash memory.

9. 1. A memory system connectable to a host and capable of transitioning to a low power or powered off state upon receiving a command from the host, comprising: A non-volatile memory for storing table data; a memory controller that executes a predetermined control including writing and reading data to the non-volatile memory based on a request from the host; The memory controller includes: a volatile memory that can take either a retention state in which power is supplied and a portion of the table data is retained, or a power-down state in which power is cut off, when the memory system transitions to the low power state; a timer that starts measuring when the state transitions to the low power state; a first counter for measuring the number of times data is written to and read from the non-volatile memory; a second counter that measures the number of times a part of the table data is updated in the volatile memory; the memory controller controls a timing for transitioning the volatile memory from the retention state to the power-down state based on the number of times measured by the first counter and the second counter. Memory system.

10. 10. The memory system of claim 9, wherein the memory controller transitions the volatile memory from the retention state to the power-down state when the measurement value of the timer exceeds a threshold calculated based on the number of times the second counter measures.

11. 11. The memory system of claim 10, wherein the memory controller subtracts the threshold by a fifth value when the first counter measures a third value or greater and the second counter measures a fourth value or greater, and adds a sixth value to the threshold when the first counter measures a third value or greater and the second counter measures less than the fourth value.

12. 10. The memory system according to claim 9, wherein the table data is a logical-physical address conversion table.

13. The volatile memory includes: A storage unit for temporarily storing the table data; A control circuit for controlling input and output of data to the storage unit, The memory system according to any one of claims 9 to 12, which is a retention SRAM that can take a retention state in which power is supplied to the memory unit during the low power state and power supply to the control circuit is cut off, and a power down state in which power supply to both the memory unit and the control circuit is cut off.

14. The memory system of claim 10 or 11, wherein the memory controller writes the threshold to the non-volatile memory each time the threshold is updated, and reads the threshold written in the non-volatile memory when returning from the low power state or the power off state.

15. the low power state is a hibernation state; 13. The memory system according to claim 9, wherein the non-volatile memory is a NAND type flash memory.

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