Semiconductor memory device

Abstract

To improve characteristics of a memory cell.SOLUTION: A semiconductor storage device of an embodiment comprises a laminate in which a plurality of conductive layers and a plurality of insulation layers are alternately laminated, a channel layer extending in the laminate in a lamination direction of the plurality of conductive layers, a memory layer provided on a side surface of the channel layer, and a pillar provided on the channel layer and including a cap layer connected to upper layer wiring of the laminate. The channel layer extends into the laminate from a height position of at least the uppermost conductive layer among the plurality of conductive layers. A grain diameter of a crystal included in the channel layer is larger than a grain diameter of a crystal included in the cap layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor memory device. [Background technology]

[0002] In a three-dimensional non-volatile memory, for example, a pillar is inserted through a stack of multiple conductive layers, and a memory cell is formed at the intersection of the pillar and at least a part of the conductive layer. It is desirable that the memory cell has a steep threshold voltage distribution and a large cell current. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2014-179465 A [Patent Document 2] Patent Publication No. 2021-048196 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment is to provide a semiconductor memory device capable of improving the characteristics of a memory cell. [Means for solving the problem]

[0005] A semiconductor memory device according to an embodiment includes a stack of a plurality of conductive layers and a plurality of insulating layers stacked alternately, a channel layer extending in the stack in a stacking direction of the plurality of conductive layers, a memory layer provided on a side of the channel layer, and a pillar including a cap layer provided on the channel layer and connected to an upper layer wiring of the stack, the channel layer extending into the stack from a height position of at least an uppermost conductive layer of the plurality of conductive layers, and a grain size of crystals included in the channel layer being larger than a grain size of crystals included in the cap layer. At least one dopant selected from carbon, nitrogen, and oxygen is contained in the crystal of the channel layer, and the volume density of the dopant in the crystal of the channel layer is 3×10 18 atoms / cm3 5×10 or more 20 atoms / cm 3 is less than or equal to . [Brief description of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view showing an example of a configuration of a semiconductor memory device according to an embodiment. [Diagram 2] 4A to 4C are cross-sectional views taken along the Y direction showing an example of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Diagram 3] 4A to 4C are cross-sectional views taken along the Y direction showing an example of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 4] 4A to 4C are cross-sectional views taken along the Y direction showing an example of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Diagram 5] 4A to 4C are cross-sectional views taken along the Y direction showing an example of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 6] FIG. 11 is a cross-sectional view showing an example of a configuration of a semiconductor memory device according to a modified example of the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] The present invention will be described in detail below with reference to the drawings. Note that the present invention is not limited to the following embodiments. In addition, the components in the following embodiments include those that a person skilled in the art can easily imagine or that are substantially the same.

[0008] (Example of the configuration of a semiconductor memory device) Fig. 1 is a cross-sectional view showing an example of the configuration of a semiconductor memory device 1 according to an embodiment. Fig. 1(a) is a cross-sectional view showing the overall structure of a pillar PL of the semiconductor memory device 1. Fig. 1(b) is an enlarged cross-sectional view of a pillar PL near select gate lines SGD0 and SGD1, Fig. 1(c) is an enlarged cross-sectional view of a pillar PL near a word line WL, and Fig. 1(d) is an enlarged cross-sectional view of a pillar PL near select gate lines SGS0 and SGS1.

[0009] 1(a), the semiconductor memory device 1 includes a source line SL, a stacked body LM, insulating layers 51-53, and a bit line BL. In this specification, the direction toward the source line SL on the source side is defined as the downward direction of the semiconductor memory device 1, and the direction toward the bit line BL on the drain side is defined as the upward direction of the semiconductor memory device 1.

[0010] The source line SL as a conductive film is provided at a lower position of the laminate LM, and is a laminate film in which a lower source line DSLb, an intermediate source line BSL, and an upper source line DSLt are laminated in this order from the lower side. The lower source line DSLb, the intermediate source line BSL, and the upper source line DSLt are, for example, a conductive polysilicon layer.

[0011] The laminate LM has a configuration in which a plurality of word lines WL, a plurality of select gate lines SGD, SGS, and a plurality of insulating layers OL are alternately laminated one by one. One or more select gate lines SGD are provided in a layer above the top word line WL, and one or more select gate lines SGS are provided in a layer below the bottom word line WL.

[0012] The word lines WL as a plurality of conductive layers and the select gate lines SGD, SGS as a plurality of conductive layers are, for example, tungsten layers or molybdenum layers, etc. The insulating layer OL is, for example, a silicon oxide layer, etc.

[0013] In the example of Fig. 1(a), five word lines WL are provided in the laminate LM. Two select gate lines SGD1, SGD0 are provided in sequence from the word line WL side. Two select gate lines SGS1, SGS0 are provided in sequence from the source line side. However, the number of layers of the word lines WL and select gate lines SGD, SGS is arbitrary and does not depend on the example of Fig. 1(a).

[0014] On the laminate LM, insulating layers 51 to 53 are laminated in this order. Bit lines BL, which are upper layer wiring of the laminate LM, are provided in the insulating layers 53. The insulating layers 51 to 53 are, for example, silicon oxide layers, and the bit lines BL are metal layers.

[0015] The laminate LM is provided with a plurality of plate-shaped contacts LI extending in the stacking direction of the layers of the laminate LM and in the X direction as a first direction along the layers of the laminate LM. The plate-shaped contacts LI penetrate the insulating layers 52, 51, the laminate LM, and the upper source line DSLt at positions spaced apart from each other in the Y direction as a second direction intersecting with the X direction, and reach the intermediate source line BSL. In this way, the laminate LM is divided in the Y direction by the plurality of plate-shaped contacts LI.

[0016] An insulating layer 54 such as a silicon oxide layer is provided on the sidewall of the plate contact LI. A conductive layer 21 such as a tungsten layer is filled inside the insulating layer 54. The conductive layer 21 of the plate contact LI is connected to an upper wiring via a plug or the like (not shown). The lower end of the conductive layer 21 is connected to the intermediate source line BSL.

[0017] With the above configuration, the plate-shaped contact LI functions as, for example, a source line contact. However, instead of the plate-shaped contact LI, an insulating layer or the like that does not function as a source line contact may divide the laminate LM in the Y direction.

[0018] Between two plate-like contacts LI adjacent in the Y direction, a separation layer SHE is provided which penetrates the select gate lines SGD0, SGD1 and extends in the X direction. The separation layer SHE is made of an insulating layer such as a silicon oxide layer, and penetrates one or more conductive layers including the topmost conductive layer of the laminate LM, separating these conductive layers in the Y direction between the two plate-like contacts LI to partition them into the pattern of the select gate lines SGD.

[0019] In addition, a plurality of pillars PL are provided between the two plate-shaped contacts LI, for example, in a staggered manner when viewed from the stacking direction of the laminate LM. The pillars PL include a channel layer CN, a cap layer CP, a memory layer ME, and a core layer CR, and reach the lower source line DSLb through the insulating layer 51, the laminate LM, the upper source line DSLt, and the middle source line BSL.

[0020] The channel layer CN as the second region extends in the stacking direction of the stack LM in the stack LM. More specifically, the channel layer CN extends from at least the height of the select gate line SGD0 in the uppermost layer of the stack LM into the stack LM and reaches the lower source line DSLb.

[0021] The cap layer CP as the first region is provided on the channel layer CN. That is, the cap layer CP extends from a position higher than the select gate line SGD0 in the uppermost layer of the stack LM to the upper end of the pillar PL.

[0022] The channel layer CN and the cap layer CP are semiconductor layers such as silicon layers, etc. The crystals of silicon or the like contained in the channel layer CN have a larger grain size than the crystals of silicon or the like contained in the cap layer CP, for example.

[0023] Such comparison of crystal grain sizes is based on, for example, the average grain size of the crystals, which is calculated by averaging the grain sizes of the crystals present per unit volume, with the maximum diameter of each individual crystal being taken as the grain size of each crystal.

[0024] The crystals in the channel layer CN may have an average grain size of, for example, 100 nm or more, and more preferably, the channel layer CN may be a substantially single-crystal silicon layer. The average grain size of the cap layer CP is less than 100 nm, and the cap layer CP may be, for example, a polysilicon layer having an average grain size of 20 nm or less. The cap layer CP may be a layer in which polysilicon and amorphous silicon are mixed.

[0025] In addition, a dopant DPa such as arsenic is diffused in the crystal of the cap layer CP, and the upper end of the cap layer CP is connected to the bit line BL via a plug CH provided in the insulating layers 53 and 52. By diffusing the dopant DPa in the cap layer CP, the contact resistance between the cap layer CP and the plug CH can be reduced. However, the dopant DPa in the cap layer CP may be other N-type impurities such as phosphorus other than arsenic.

[0026] A core layer CR is provided in the center of the pillar PL as a core material extending in the stacking direction of the laminate LM, and the above-mentioned channel layer CN is provided so as to cover the side and lower end of the core layer CR. The height position of the upper end of the core layer CR is different from the height position of the upper end of the channel layer CN, for example, and the upper end of the core layer CR protrudes into the cap layer CP, for example. The core layer CN is an insulating layer such as a silicon oxide layer.

[0027] The thickness of the channel layer CN covering the core layer CR is preferably, for example, 5 nm or less, which allows the depletion layer to be made thinner than the length of the channel layer CN in the stacking direction, which corresponds to the gate length, and thus makes it possible to suppress the short channel effect.

[0028] The memory layer ME is provided on the side of the channel layer CN. More specifically, as shown in Figures 1(b) to (d), the memory layer ME has a laminated structure in which a block insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN are laminated in this order from the outer periphery side of the pillar PL. The block insulating layer BK and the tunnel insulating layer TN are, for example, silicon oxide layers, and the charge storage layer CT is, for example, a silicon nitride layer or a silicon oxynitride layer.

[0029] As described above, the memory layer ME covers the side surface of the channel layer CN, reaches the lower source line DSLb, and also covers the lower end of the channel layer CN. However, the memory layer ME is not provided at the depth position of the intermediate source line BSL in the source line SL, and the intermediate source line BSL is in contact with the channel layer CN. As a result, the channel layer CN is connected to the source line SL at the side surface via the intermediate source line BSL.

[0030] With the above configuration, a plurality of memory cells MC are formed on the side surface of the pillar PL at the height position of the word line WL. In this manner, the semiconductor memory device 1 is configured as, for example, a three-dimensional nonvolatile memory in which the memory cells MC are arranged in a three-dimensional manner.

[0031] 1(c) shows a state in which a memory cell MC is formed at a height position opposite to the word line WL on the side surface of the pillar PL. Data is written to and read from the memory cell MC by applying a predetermined voltage through the word line WL.

[0032] In other words, when writing "H" level data to a memory cell MC, a write voltage is applied to the connected word line WL. At this time, a ground potential is supplied to the channel layer CN to form a channel, and electrons in the channel pass through the tunnel insulating layer TN and are injected into and stored in the charge storage layer CT. This causes the threshold voltage Vth of the memory cell MC to rise, and "H" level data is written.

[0033] When writing “L” level data to the memory cell MC, the channel of the channel layer CN is set to a floating state, so that electrons are not injected into the charge storage layer CT, and the threshold voltage Vth of the memory cell MC remains low, maintaining the state in which “L” level data is written.

[0034] When reading data from a memory cell MC, a read voltage is applied to the connected word line WL. The read voltage is a voltage that turns on memory cells MC that hold "L" level data and does not turn on memory cells MC that hold "H" level data. Therefore, if a cell current flows through the bit line BL, it means that "L" level data has been read, and if no cell current flows through the bit line BL, it means that "H" level data has been read.

[0035] As shown in Fig. 1(b), select gates STD0 and STD1 are formed on the side surface of the pillar PL at height positions facing the select gate lines SGD0 and SGD1, respectively. Also, as shown in Fig. 1(d), select gates STS0 and STS1 are formed on the side surface of the pillar PL at height positions facing the select gate lines SGS0 and SGS1, respectively.

[0036] When a predetermined voltage is applied via the select gate lines SGD, SGS, the select gates STD, STS are turned on or off, and the memory cells MC of the pillar PL to which those select gates STD, STS belong are selected or unselected.

[0037] The laminate LM has, for example, a staircase portion (not shown) in which a plurality of word lines WL and select gate lines SGD, SGS are drawn out in a staircase shape. The individual word lines WL and select gate lines SGD, SGS of the staircase portion are connected to peripheral circuits via upper layer wiring (not shown). The memory cells MC of the pillars PL are connected to the peripheral circuits via the bit lines BL described above.

[0038] The peripheral circuit includes, for example, transistors (not shown) and is provided below or above the stack LM. The peripheral circuit controls the voltages applied to the word lines WL and the select gate lines SGD and SGS to control the operation of the memory cells MC and the select gates STD and STS. The peripheral circuit also senses the cell current flowing through the bit lines BL to read data from the memory cells MC.

[0039] (Method of manufacturing semiconductor memory device) Next, an example of a method for manufacturing the semiconductor memory device 1 according to the embodiment will be described with reference to Figures 2 to 5. Figures 2 to 5 are cross-sectional views taken along the Y direction, showing an example of a procedure for the method for manufacturing the semiconductor memory device 1 according to the embodiment.

[0040] 2(a), the lower source line DSLb, the intermediate layer SCN, and the upper source line DSLt are formed in this order. The intermediate layer SCN is a sacrificial layer such as a silicon nitride layer, and is later replaced with a conductive polysilicon layer or the like to form the intermediate source line BSL.

[0041] Further, a laminate LMs is formed on the upper source line DSLt, in which a plurality of insulating layers NL and a plurality of insulating layers OL are alternately laminated one by one. The insulating layer NL is a sacrificial layer such as a silicon nitride layer, and is later replaced with a tungsten layer or a molybdenum layer to form the word line WL and the select gate lines SGD, SGS. An insulating layer 51 is formed on the laminate LMs.

[0042] As shown in FIG. 2(b), a memory hole MH is formed penetrating the insulating layer 51, the stacked body LMs, the upper source line DSLt, and the intermediate layer SCN to reach the lower source line DSLb.

[0043] 2(c), a block insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN (see FIGS. 1(b) to (d)) are stacked in this order on the sidewall and bottom surface of the memory hole MH to form a memory layer ME. The memory layer ME is also formed on the upper surface of the insulating layer 51.

[0044] In addition, a channel layer CNa is formed on the sidewall and bottom surface of the memory hole MH via the memory layer ME. The channel layer CNa is an amorphous silicon layer or the like that will be crystallized later to become the channel layer CN. The channel layer CNa is also formed on the upper surface of the insulating layer 51 via the memory layer ME.

[0045] In addition, the inside of the channel layer CNa of the memory hole MH is filled with a core layer CRs. The core layer CRs is a sacrificial layer such as a silicon oxide layer, and is removed in a later process. The core layer CRs is also formed on the upper surface of the insulating layer 51 via the channel layer CNa and the memory layer ME.

[0046] 2(d), the core layer CRs is etched back and removed from the upper surface of the insulating layer 51 and the upper surface of the memory hole MH. This exposes the channel layer CNa on the upper surface of the insulating layer 51. In addition, the upper end of the core layer CRs is positioned at a predetermined depth within the memory hole MH, and a recess RCc is formed above the core layer CRs.

[0047] The recess RCc in the memory hole MH can be obtained by continuing overetching for a predetermined time even after the core layer CRs on the upper surface of the insulating layer 51 is removed, for example.

[0048] 2(e), a cap layer CPs is formed to cover the channel layer CNa on the upper surface of the insulating layer 51. The cap layer CPs is a sacrificial layer such as an amorphous silicon layer, and is removed in a later process. The cap layer CPs is also filled in the recess RCc in the memory hole MH.

[0049] 2(f), the channel layer CNa and the cap layer CPs are crystallized by, for example, annealing to form the channel layer CN. In order to promote the crystallization during the annealing, for example, a MILC technique may be used in combination.

[0050] At this point, the channel layer CNa is covered with the memory layer ME at the depth positions of the upper source line DSLt and the lower source line DSLb, and is not in contact with the upper source line DSLt and the lower source line DSLb, which are, for example, polysilicon layers, etc. This makes it easier to obtain a relatively homogeneous, substantially single-crystalline channel layer CN.

[0051] 3(a), the channel layer CN and the memory layer ME are etched back and removed from the upper surface of the insulating layer 51. This exposes the upper surface of the insulating layer 51. At this time, the channel layer CN and the core layer CRs are also etched back in the memory hole MH. As a result, the upper ends of the channel layer CN and the core layer CRs are positioned at a predetermined depth in the memory hole MH, and a recess RCm is formed above the channel layer CN and the core layer CRs.

[0052] The recess RCm in the memory hole MH can be obtained by continuing overetching for a predetermined time even after the channel layer CN on the upper surface of the insulating layer 51 is removed, for example. At this time, the overetching time and the like are controlled to maintain the upper ends of the channel layer CN and the core layer CRs at a height position at least higher than the uppermost insulating layer NL of the laminate LMs.

[0053] As shown in FIG. 3(b), a sidewall layer SW is formed to cover the upper surface of the insulating layer 51. The sidewall layer SW is also formed in the recess RCm at the upper end of the memory hole MH so as to cover the side wall of the memory hole MH, and protects the memory layer ME in a slimming process of the channel layer CN, which will be described later. The sidewall layer SW is, for example, an amorphous silicon layer. Note that the thickness of the sidewall layer SW is adjusted by controlling the processing time, etc., so that the recess RCm is not completely blocked.

[0054] As shown in Fig. 3(c), the core layer CRs in the memory hole MH is removed and the channel layer CN is thinned by wet etching or isotropic dry etching. At this time, the memory layer ME on the side wall of the memory hole MH is protected by the sidewall layer SW. It is preferable to perform the slimming process so that the layer thickness of the channel layer CN is, for example, 5 nm or less.

[0055] In this way, the crystallization of the channel layer CNa is easily promoted by initially forming a thick channel layer CNa and then performing an annealing process, etc. Also, by slimming the crystallized channel layer CN, as described above, the depletion layer can be made thinner with respect to the gate length, and the short channel effect can be suppressed.

[0056] 3(d), the core layer CRs is removed, and the gap in the memory hole MH resulting from the slimming of the channel layer CN is filled with an insulating layer or the like to form the core layer CR. At this time, the height position of the upper end of the core layer CR does not have to be equal to the height position of the upper end of the channel layer CN, and for example, the upper end of the core layer CR may be located above the upper end of the channel layer CN.

[0057] 3(e), a cap layer CPa is formed to cover the sidewall layer SW on the upper surface of the insulating layer 51. The cap layer CPa is an amorphous silicon layer or the like that will be crystallized later to become the cap layer CP. The cap layer CPa is also filled into the recess RCm at the upper end of the memory hole MH.

[0058] 3(f), the cap layer CPa and the sidewall layer SW are etched back and removed from the upper surface of the insulating layer 51. At this time, the amount of overetching is suppressed and controlled so that the cap layer CPa and the sidewall layer SW in the memory hole MH are not also removed.

[0059] As shown in Fig. 4(a), the remaining cap layer CPa and sidewall layer SW are crystallized by, for example, annealing to form a cap layer CP. The degree of crystallization in the cap layer CP does not need to be as high as that of the above-mentioned channel layer CN, and the cap layer CP may be, for example, a polysilicon layer. An amorphous silicon layer may remain in part of the cap layer CP.

[0060] If the height position of the upper end of the core layer CR is, for example, lower than the top insulating layer NL, the inside of the channel layer CN is filled with the cap layer CP at the height position of the top insulating layer NL that will later become the select gate line SGD0, and the channel layer CN is not formed in a circular ring shape. As described above, since the upper end of the core layer CR is protruded from the upper end of the channel layer CN, for example, as described above, such formation defects of the channel layer CN can be suppressed.

[0061] An N-type dopant DPa, such as arsenic, is diffused into the formed cap layer CP. As described above, the dopant DPa may be an impurity, such as phosphorus.

[0062] As a result, the pillars PL are formed. However, even at this point, the side surfaces and bottom ends of the channel layers CN of the pillars PL are covered with the memory layers ME.

[0063] 4(b), an insulating layer 52 is formed on an insulating layer 51. A slit ST is formed penetrating the insulating layers 52 and 51, the stacked body LMs, and the upper source line DSLt to reach the intermediate layer SCN. The slit ST also extends in the stacked body LMs in the X-direction.

[0064] 4(c), an insulating layer 54s is formed on the side walls of the slit ST facing each other in the Y direction. The insulating layer 54s is, for example, a silicon oxide layer, and serves as a protective layer in a replacement process described later.

[0065] 4(d), a remover such as hot phosphoric acid is poured from above the slit ST to remove the intermediate layer SCN exposed at the bottom of the slit ST. As a result, a gap GPs is formed between the upper source line DSLt and the lower source line DSLb, and the side surface of the memory layer ME at the outermost periphery of the pillar PL is exposed in the gap GPs.

[0066] At this time, the insulating layer 54s on the side wall of the slit ST prevents the remover from flowing into the stacked body LMs, so that the insulating layer NL in the stacked body LMs is not removed.

[0067] As shown in Fig. 4(e), a removal liquid for removing the silicon oxide layer, silicon nitride layer, etc. is poured from the top of the slit ST, and the block insulating layer BK, the charge storage layer CT, and the tunnel insulating layer TN are sequentially removed from the outer periphery of the memory layer ME exposed in the gap GPs. As a result, the side surface of the channel layer CN is exposed in the gap GPs.

[0068] As shown in FIG. 4(f), a source gas for forming polysilicon or the like is injected from above the slit ST to fill the gap GPs with a polysilicon layer or the like to form the intermediate source line BSL.

[0069] As a result, the source lines SL including the lower source line DSLb, the middle source line BSL, and the upper source line DSLt are formed. Also, the channel layer CN of the pillar PL is connected to the source line SL at its side surface.

[0070] As shown in FIG. 4(d) to FIG. 4(f), the process of removing the intermediate layer SCN to form the intermediate source line BSL is also called a replacement process in the source line SL.

[0071] As shown in FIG. 5(a), the insulating layer 54s on the side wall of the slit ST is removed.

[0072] 5(b), a remover such as hot phosphoric acid is poured from above the slit ST to remove the insulating layer NL in the laminate LMs exposed on the side surface of the slit ST, thereby forming a laminate LMg having gaps GPw between multiple insulating layers OL.

[0073] 5(c), a raw material gas serving as a raw material for a conductor or the like is injected from above the slit ST, and the gap GPw is filled with a conductive layer to form the word line WL and the select gate lines SGD, SGS. This forms a stack LM in which multiple word lines WL and select gate lines SGD, SGS are stacked.

[0074] As shown in FIGS. 5(b) to 5(c), the process of removing the insulating layer NL and forming the word lines WL and the like is also called a replacement process in the laminate LM.

[0075] 5(d), an insulating layer 54 is formed on the side wall of the slit ST, and the inside of the insulating layer 54 is filled with a conductive layer 21 to form a plate-like contact LI. However, the inside of the slit ST may be entirely filled with the insulating layer to form a plate-like member that does not function as a source line contact. In this case, the slit ST is formed solely for use in the replacement process of the source line SL and the laminate LM.

[0076] 5(e), in order to form the separation layer SHE, a groove GR is formed which penetrates the insulating layers 52 and 51 and the select gate lines SGD0 and SGD1 and extends in the X direction. In other words, the groove GR is made to penetrate the conductive layers to function as the select gate lines SGD among the conductive layers in the laminate LM, and the conductive layers are separated into a pattern of a plurality of select gate lines SGD.

[0077] As shown in FIG. 5(f), an insulating layer is filled into the trench GR to form a separation layer SHE.

[0078] Thereafter, an insulating layer 53 is formed on the insulating layer 52, and plugs CH that penetrate the insulating layers 53 and 52 and are connected to the cap layers CP of the pillars PL, and bit lines BL that are connected to the plugs CH, etc. are formed.

[0079] In this manner, the semiconductor memory device 1 of the embodiment is manufactured.

[0080] (Overview) In semiconductor memory devices such as 3D non-volatile memories, issues include memory cell malfunctions caused by broadened threshold voltage distributions, and data sensing problems caused by small cell currents. In addition, there are issues with dopants diffused into the cap layer reaching the depth position of the select gate on the source side, for example, deteriorating or varying the off characteristics of the select gate.

[0081] According to the semiconductor memory device 1 of the embodiment, the grain size of the crystals contained in the channel layer CN is larger than the grain size of the crystals contained in the cap layer CP, and the average grain size is, for example, 100 nm or more. This can improve the characteristics of the memory cells MC.

[0082] Specifically, by improving the crystallinity of the channel layer CN, the electrical resistance of the channel layer CN can be reduced and the mobility of electrons, which are carriers, can be improved. In addition, the crystal defects in the channel layer CN can be reduced, making it difficult for scattering and capture of electrons to occur in the channel layer CN.

[0083] By suppressing scattering and trapping of electrons in the channel layer CN, the influence on each other's threshold voltages Vth between adjacent memory cells MC in the same pillar PL is reduced, resulting in a steeper distribution of the threshold voltages Vth and improved write characteristics.

[0084] In addition, the cell current can easily flow through the channel layer CN and is prevented from attenuating in the channel layer CN. As a result, the amount of cell current flowing through the bit line BL increases and is easily sensed, improving the read characteristics of the memory cell MC.

[0085] According to the embodiment of the semiconductor memory device 1, two regions having different crystal grain sizes due to the channel layer CN and the cap layer CP exist in the semiconductor layer, and the region with the larger crystal grain size extends from at least the height position of the topmost select gate line SGD0 into the stack LM.

[0086] Here, the dopant DPa such as arsenic has the property of diffusing along the grain boundaries in the crystal, and therefore the diffusion of the dopant DPa to the channel layer CN side, which has high crystallinity and is less affected by the grain boundaries, is suppressed by the interface segregation between the channel layer CN and the cap layer CP.

[0087] Therefore, the off-characteristics of the select gate STD can be improved and the variation in the off-characteristics can be suppressed. Also, since the select gate STD can be turned on / off more reliably, the reliability of the operation of the semiconductor memory device 1 can be guaranteed even if the number of select gates STD is reduced. Furthermore, it is possible to increase the number of memory cells MC instead of the select gate STD and increase the storage capacity of the semiconductor memory device 1.

[0088] According to the semiconductor memory device 1 of the embodiment, the thickness of the channel layer CN covering the side surface of the core layer CR is, for example, 5 nm or less, which makes it possible to suppress the short channel effect.

[0089] According to the semiconductor memory device 1 of the embodiment, the memory layer ME covers the side and bottom end of the channel layer CN except for the depth position of the intermediate source line BSL in the source line SL, and the channel layer CN is connected to the source line SL at the side. By adopting such a connection method with the source line SL, the channel layer CNa can be crystallized in a state where the side and bottom end of the channel layer CNa are covered with the memory layer ME. This can further improve the crystallinity of the channel layer CN.

[0090] (Modification) Next, a semiconductor memory device 2 according to a modification of the embodiment will be described with reference to Fig. 6. The semiconductor memory device 2 according to the modification differs from the embodiment described above in that a predetermined dopant DPc is diffused in the channel layer CNc.

[0091] Fig. 6 is a cross-sectional view showing an example of the configuration of a semiconductor memory device 2 according to a modified embodiment. Fig. 6 shows a cross section along the Y direction, similar to Fig. 1(a) of the above-mentioned embodiment. Note that in Fig. 6, the same components as those in the semiconductor memory device 1 of the above-mentioned embodiment are denoted by the same reference numerals, and description thereof will be omitted.

[0092] 6, the pillar PLc of the semiconductor memory device 2 includes a channel layer CNc extending in the stacking direction of the layers in the stack LM. A dopant DPc such as carbon is diffused in the crystal of the channel layer CNc. The volume density of the dopant DPc in the crystal of the channel layer CNc is, for example, 3×10 18 atoms / cm 3 5×10 or more 20 atoms / cm 3 The following is the result.

[0093] However, the dopant DPc in the channel layer CNc may be an impurity such as oxygen or nitrogen other than carbon.

[0094] The configuration of the channel layer CNc other than the above and the configuration of the pillar PLc other than the above are similar to the channel layer CN and pillar PL of the above-described embodiment.

[0095] The channel layer CNc containing the above-mentioned dopant DPc can be formed, for example, in the process of Figure 2 (c) of the above-mentioned embodiment, by diffusing the dopant DPc into the channel layer CNa at the timing when the channel layer CNa is formed in the memory hole MH and before the core layer CRs is formed.

[0096] According to the semiconductor memory device 1 of the modified example, the crystal of the channel layer CNc contains at least one dopant DPc selected from carbon, nitrogen, and oxygen, and the volume density of the dopant DPc in the crystal is, for example, 3×10 18 atoms / cm 3 5×10 or more 20 atoms / cm 3 The following is the result.

[0097] The dopant DPc, such as carbon, nitrogen, or oxygen, diffused into the channel layer CNc has the effect of suppressing the dopant DPa, such as arsenic, diffused into the cap layer CP from diffusing into the channel layer CNc, thereby further improving the off-characteristics of the select gate STD and further suppressing the variation in the off-characteristics.

[0098] Furthermore, in the manufacturing process of the semiconductor memory device 2, by diffusing a dopant DPc such as carbon, nitrogen, or oxygen in the channel layer CNa before crystallization, it is possible to expect an effect of promoting the crystallization of the channel layer CNa.

[0099] In addition, the semiconductor memory device 1 of the modified example provides the same effects as the semiconductor memory device 1 of the above-described embodiment.

[0100] (Other variations) In the above-described embodiment and modified example, the semiconductor memory devices 1 and 2 are provided with a stacked body LM including the word lines WL and the select gate lines SGD and SGS, which are metal layers such as tungsten layers, as conductive layers. However, the conductive layer of the stacked body may be a layer including a silicon material such as a polysilicon layer. In this case, a stacked body including layers including a silicon material is formed from the beginning, and the semiconductor memory device is manufactured without a replacement process.

[0101] In the above-described embodiment and modified examples, the semiconductor memory devices 1 and 2 have a one-tier structure including one stacked body LM. However, the semiconductor memory device may have a two-tier or more structure.

[0102] In the above-described embodiment and modified examples, the semiconductor memory devices 1 and 2 include peripheral circuits above or below the stack LM. However, the semiconductor memory device may include peripheral circuits provided in the same layer as the stack.

[0103] When providing a peripheral circuit below the laminate LM, the peripheral circuit including a transistor is formed on a semiconductor substrate such as a silicon substrate, and the source line SL and the laminate LM, etc. are sequentially formed above the peripheral circuit to obtain the semiconductor memory devices 1, 2.

[0104] When a peripheral circuit is provided above the laminate LM, the source line SL and the laminate LM can be formed on a support substrate, and a semiconductor substrate provided with the peripheral circuit can be attached above the laminate LM to obtain the semiconductor memory devices 1 and 2.

[0105] When the stacked body and the peripheral circuit are provided in the same layer, the stacked body can be formed on a semiconductor substrate, and the peripheral circuit can be formed on the outer edge of the stacked body.

[0106] (Additional Note) Preferred aspects of the present invention will be described below.

[0107] (Appendix 1) According to one aspect of the present invention, a laminate in which a plurality of conductive layers and a plurality of insulating layers are alternately laminated; a pillar including a channel layer extending in the stacking direction of the conductive layers in the stacked body, a memory layer provided on a side surface of the channel layer, and a cap layer provided on the channel layer and connected to an upper layer wiring of the stacked body; the channel layer extends into the stack from a height position of at least an uppermost conductive layer among the plurality of conductive layers; the grain size of the crystals contained in the channel layer is larger than the grain size of the crystals contained in the cap layer; A semiconductor memory device is provided.

[0108] (Appendix 2) In the semiconductor memory device according to claim 1, a conductive film extending along the plurality of conductive layers below the stack; The lower ends of the pillars extend to the conductive film.

[0109] (Appendix 3) In the semiconductor memory device of Supplementary Note 2, The channel layer is connected to the conductive film at a side surface.

[0110] (Appendix 4) In the semiconductor memory device of Supplementary Note 3, The memory layer covers a lower end of the channel layer.

[0111] (Appendix 5) In the semiconductor memory device according to claim 3 or 4, The memory layer covers the side surfaces and the bottom end of the channel layer except for a predetermined depth position in the conductive film.

[0112] (Appendix 6) In the semiconductor memory device according to any one of claims 1 to 5, The semiconductor device further includes a separation layer that penetrates at least an uppermost conductive layer of the plurality of conductive layers, extends in a first direction along the plurality of conductive layers, and separates the conductive layers that it penetrates in a second direction intersecting the first direction.

[0113] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0114] 1, 2...semiconductor memory device, BL...bit line, CN, CNc...channel layer, CR...core layer, LM...laminated body, ME...memory layer, OL...insulating layer, PL, PLc...pillar, SGD, SGS...select gate line, SHE...isolation layer, SL...source line, STD, STS...select gate, WL...word line.

Claims

1. a laminate in which a plurality of conductive layers and a plurality of insulating layers are alternately laminated; a pillar including a channel layer extending in the stacking direction of the conductive layers in the stacked body, a memory layer provided on a side surface of the channel layer, and a cap layer provided on the channel layer and connected to an upper layer wiring of the stacked body; the channel layer extends into the stack from a height position of at least an uppermost conductive layer among the plurality of conductive layers; the grain size of the crystals contained in the channel layer is larger than the grain size of the crystals contained in the cap layer; the crystal of the channel layer contains at least one dopant selected from the group consisting of carbon, nitrogen, and oxygen; a volume density of the dopant in the crystal of the channel layer is 3×10 18 atoms / cm 3 or more and 5×10 20 atoms / cm 3 or less; Semiconductor memory device.

2. The average grain size of the crystals in the channel layer is 100 nm or more.

2. The semiconductor memory device according to claim 1.

3. The crystal of the cap layer contains at least one dopant of arsenic and phosphorus.

3. The semiconductor memory device according to claim 1.

4. The pillar includes an insulating core material extending in the stacking direction, the channel layer sandwiched between the memory layer and the core material has a thickness of 5 nm or less; 4. The semiconductor memory device according to claim 1, wherein the first and second memory cells are arranged in a first and second memory cell.

5. The height position of the upper end of the core material is different from the height position of the upper end of the channel layer.

5. The semiconductor memory device according to claim 4.

6. The upper end of the core protrudes into the cap layer.

6. The semiconductor memory device according to claim 4.

7. a laminate in which a plurality of conductive layers and a plurality of insulating layers are alternately laminated; a pillar including a semiconductor layer extending in the stacking direction of the conductive layers in the stacked body, The semiconductor layer is a first region extending from a position higher than an uppermost conductive layer of the plurality of conductive layers to an upper end of the pillar; a second region extending into the stack from at least a height position of the uppermost conductive layer, the second region having a crystal grain size larger than the crystal grain size in the first region; Including, the crystal of the second region contains at least one dopant selected from carbon, nitrogen, and oxygen; a volume density of the dopant in the crystal of the second region is 3×10 18 atoms / cm 3 or more and 5×10 20 atoms / cm 3 or less; Semiconductor memory device.

8. The average grain size of the crystals in the second region is 100 nm or more.

8. The semiconductor memory device according to claim 7.

9. The crystal of the first region contains at least one dopant of arsenic and phosphorus.

9. The semiconductor memory device according to claim 7.

10. The pillar includes an insulating core material extending in the stacking direction, The thickness of the semiconductor layer covering the side surface of the core material is 5 nm or less.

10. The semiconductor memory device according to claim 7.

11. A height position of an upper end portion of the core material is different from a height position of a boundary portion between the first region and the second region. The semiconductor memory device according to claim 10.

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