Semiconductor memory device

Abstract

To provide a semiconductor storage device capable of easily achieving higher integration.SOLUTION: A semiconductor storage device comprises a substrate including a memory region and a hook-up region arranged in a first direction, and a plurality of memory structures arranged in a second direction crossing the first direction. Each of the plurality of memory structures includes a plurality of conductive layers arranged in a third direction crossing a surface of the substrate and extending in the first direction over the memory region and the hook-up region, and a plurality of contact electrodes provided in the hook-up region, extending in the third direction, and including an outer peripheral surface surrounded by a part of the plurality of conductive layers, each of the plurality of contact electrodes being connected to any of the plurality of conductive layers. The hook-up region includes a first region and a second region arranged in the first direction. The first region includes a first contact electrode and a second contact electrode. The second region includes a third contact electrode. A length in the third direction of the third contact electrode is longer than a length in the third direction of the first contact electrode, and shorter than a length in the third direction of the second contact electrode.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor memory device. [Background technology]

[0002] A semiconductor memory device is known that includes a substrate, a plurality of conductive layers stacked in a direction intersecting a surface of the substrate, a semiconductor layer facing the plurality of conductive layers, and a gate insulating layer provided between the conductive layers and the semiconductor layer. The gate insulating layer includes a memory portion capable of storing data, such as an insulating charge storage layer made of silicon nitride (Si3N4) or the like, or a conductive charge storage layer such as a floating gate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-026518 A Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor memory device that can be easily highly integrated is provided. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment includes a substrate having a memory region and a hook-up region aligned in a first direction, and a plurality of memory structures aligned in a second direction intersecting the first direction. Each of the plurality of memory structures includes a plurality of conductive layers aligned in a third direction intersecting the surface of the substrate and extending in the first direction across the memory region and the hook-up region, a semiconductor layer provided in the memory region, extending in the third direction, and facing the plurality of conductive layers, a charge storage film provided between the plurality of conductive layers and the semiconductor layer, and a plurality of contact electrodes provided in the hook-up region, extending in the third direction, having an outer circumferential surface surrounded by a portion of the plurality of conductive layers, and each connected to one of the plurality of conductive layers. The hook-up region includes a first region and a second region aligned in the first direction. The first region includes a first contact electrode and a second contact electrode, and the second region includes a third contact electrode. The length of the third contact electrode in the third direction is longer than the length of the first contact electrode in the third direction and shorter than the length of the second contact electrode in the third direction. [Brief description of the drawings]

[0006] [Figure 1] 2 is a schematic plan view of a memory die MD according to the first embodiment. FIG. [Diagram 2] 2 is a schematic enlarged view of a portion indicated by A and a portion indicated by B in FIG. [Diagram 3] FIG. 3 is a schematic enlarged view of a portion indicated by C in FIG. 2. [Figure 4] 4 is a schematic cross-sectional view of the structure shown in FIG. 3 taken along line DD' and viewed in the direction of the arrow. [Diagram 5] FIG. 5 is a schematic enlarged view of a portion indicated by E in FIG. 4. [Figure 6] 3 is a schematic cross-sectional view of the structure shown in FIG. 2 taken along line FF' and viewed in the direction of the arrow. [Figure 7] 3 is a schematic cross-sectional view of the structure shown in FIG. 2 taken along line GG' and viewed in the direction of the arrow. [Figure 8] FIG. 3 is a schematic enlarged view of the hook-up region shown in FIG. 2. [Figure 9]2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 10] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 11] 1A to 1C are schematic plan views for explaining the manufacturing method. [Figure 12] 3A to 3C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 13] 3A to 3C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 14] 1A to 1C are schematic plan views for explaining the manufacturing method. [Figure 15] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 16] 3A to 3C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 17] 3A to 3C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 18] 3A to 3C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 19] 3A to 3C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 20] 3A to 3C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 21] 3A to 3C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 22] 3A to 3C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 23] 1A to 1C are schematic plan views for explaining the manufacturing method. [Figure 24] 3A to 3C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 25] 3A to 3C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 26] 3A to 3C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 27] 3A to 3C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 28] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 29] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Diagram 30] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Diagram 31] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Diagram 32] 1A to 1C are schematic plan views for explaining the manufacturing method. [Diagram 33] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Diagram 34] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Diagram 35] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Diagram 36] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 37] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 38] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 39] 1A to 1C are schematic plan views for explaining the manufacturing method. [Diagram 40] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Diagram 41] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Diagram 42] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Diagram 43] FIG. 1 is a schematic plan view of a semiconductor memory device according to a comparative example. [Diagram 44] FIG. 44 is a schematic enlarged view of the hook-up region shown in FIG. 43. [Diagram 45] 10A to 10C are schematic cross-sectional views for explaining a manufacturing method of a semiconductor memory device according to a comparative example. [Diagram 46] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 47] FIG. 11 is a schematic plan view showing a configuration of a portion of a semiconductor memory device according to a second embodiment. [Figure 48] 48 is a schematic cross-sectional view of the structure shown in FIG. 47 taken along line HH' and viewed in the direction of the arrows. [Figure 49] 48 is a schematic cross-sectional view of the structure shown in FIG. 47 taken along line II' and viewed in the direction of the arrows. [Figure 50] 48 is a schematic cross-sectional view of the structure shown in FIG. 47 taken along line JJ' and viewed in the direction of the arrows. [Figure 51] FIG. 48 is a schematic enlarged view of the hook-up region shown in FIG. 47. [Figure 52] 10A to 10C are schematic cross-sectional views for illustrating a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 53] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 54] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 55] FIG. 1 is a schematic plan view of a semiconductor memory device according to a comparative example. [Figure 56] FIG. 56 is a schematic enlarged view of the hook-up region shown in FIG. 55. [Figure 57] 10A to 10C are schematic cross-sectional views for explaining a manufacturing method of a semiconductor memory device according to a comparative example. [Figure 58] 10A to 10C are schematic cross-sectional views for explaining a manufacturing method of a semiconductor memory device according to a comparative example. [Figure 59] 10A to 10C are schematic cross-sectional views for explaining a manufacturing method of a semiconductor memory device according to a comparative example. [Figure 60] 13 is a schematic enlarged view of a hook-up region of the semiconductor memory device according to the third embodiment. FIG. [Figure 61] 13 is a schematic enlarged view of a hook-up region of the semiconductor memory device according to the fourth embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiment is merely an example, and is not intended to limit the present invention. Also, the following drawings are schematic, and for the sake of explanation, some configurations may be omitted. Also, parts common to multiple embodiments may be given the same reference numerals, and explanations may be omitted.

[0008] In addition, in this specification, the term "semiconductor memory device" may refer to a memory die, or may refer to a memory system including a controller die, such as a memory chip, a memory card, or an SSD (Solid State Drive). Furthermore, it may refer to a configuration including a host computer, such as a smartphone, a tablet terminal, or a personal computer.

[0009] In addition, in this specification, when it is said that a first configuration is "electrically connected" to a second configuration, the first configuration may be directly connected to the second configuration, or the first configuration may be connected to the second configuration via wiring, a semiconductor member, a transistor, etc. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even if the second transistor is in an OFF state.

[0010] In addition, in this specification, when it is said that a first configuration is "connected between" a second configuration and a third configuration, it may mean that the first configuration, the second configuration, and the third configuration are connected in series, and that the second configuration is connected to the third configuration via the first configuration.

[0011] In this specification, a predetermined direction parallel to the upper surface of the substrate is called the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and a direction perpendicular to the upper surface of the substrate is called the Z direction.

[0012] In this specification, a direction along a predetermined plane may be referred to as a first direction, a direction along this predetermined plane that intersects with the first direction may be referred to as a second direction, and a direction that intersects with this predetermined plane may be referred to as a third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0013] In this specification, expressions such as "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "up," and the direction toward the substrate along the Z direction is called "down." Furthermore, when referring to a certain configuration, the lower surface or lower end refers to the surface or end of the configuration facing the substrate, and when referring to the upper surface or upper end, refers to the surface or end of the configuration facing away from the substrate. Furthermore, surfaces that intersect with the X or Y direction are called side surfaces, etc.

[0014] In addition, in this specification, when referring to a configuration, member, etc., "width," "length," or "thickness" in a specific direction, this may mean the width, length, or thickness in a cross section observed by SEM (Scanning electron microscopy), TEM (Transmission electron microscopy), or the like.

[0015] [First embodiment] [composition] FIG. 1 is a schematic plan view of a memory die MD. FIG. 2 is a schematic enlarged view of the parts indicated by A and B in FIG. 1. FIG. 3 is a schematic enlarged view of the part indicated by C in FIG. 2. FIG. 4 is a schematic cross-sectional view of the structure shown in FIG. 3 cut along the line DD' and viewed in the direction of the arrow. FIG. 5 is a schematic enlarged view of the part indicated by E in FIG. 4. FIG. 6 is a schematic cross-sectional view of the structure shown in FIG. 2 cut along the line FF' and viewed in the direction of the arrow. FIG. 7 is a schematic cross-sectional view of the structure shown in FIG. 2 cut along the line GG' and viewed in the direction of the arrow. FIG. 8 is a schematic enlarged view of the hook-up region shown in FIG. 2.

[0016] 1, the memory die MD includes a semiconductor substrate 100. The semiconductor substrate 100 is a semiconductor substrate made of P-type silicon (Si) containing P-type impurities such as boron (B). On the surface of the semiconductor substrate 100, an N-type well region containing N-type impurities such as phosphorus (P), a P-type well region containing P-type impurities such as boron (B), a semiconductor substrate region in which the N-type well region and the P-type well region are not provided, and an insulating region are provided.

[0017] The memory die MD has four memory cell array regions R arranged in the X and Y directions. MCA The memory cell array region R MCA is two memory hole regions R aligned in the X direction. MH (Memory hole area R MH are sometimes called memory regions.) and these memory hole regions R MH Hook-up area R between HU And, it is equipped with.

[0018] Memory cell array region R MCA is provided with a plurality of memory blocks BLK aligned in the Y direction. Each memory block BLK has two finger structures FS (the finger structures FS are sometimes called memory structures) aligned in the Y direction, as shown in Fig. 2. Each finger structure FS has two string units SU aligned in the Y direction, as shown in Fig. 2.

[0019] An inter-block insulating layer ST such as silicon oxide (SiO2) is provided between two finger structures FS adjacent to each other in the Y direction. In addition, as shown in Figures 2 and 3, for example, an inter-string unit insulating layer SHE such as silicon oxide (SiO2) is provided between two string units SU adjacent to each other in the Y direction.

[0020] Memory hole area R of memory block BLK MHFor example, as shown in FIG. 4 , the semiconductor device includes a plurality of conductive layers 110 aligned in the Z direction, a plurality of semiconductor layers 120 extending in the Z direction, and a plurality of gate insulating films 130 provided between the plurality of conductive layers 110 and the plurality of semiconductor layers 120.

[0021] The conductive layer 110 is a substantially plate-shaped conductive layer extending in the X direction. The conductive layer 110 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The conductive layer 110 may also include polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101 such as silicon oxide (SiO2) is provided between the multiple conductive layers 110 arranged in the Z direction. The conductive layer 110 functions as a gate electrode and a word line of a memory cell, or a gate electrode and a select gate line of a select transistor.

[0022] A semiconductor layer 112 is provided below the conductive layer 110. The semiconductor layer 112 may include polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101 made of silicon oxide (SiO2) or the like is provided between the semiconductor layer 112 and the conductive layer 110. The semiconductor layer 112 functions as a part of the source line.

[0023] The semiconductor layers 120 are arranged in a predetermined pattern in the X and Y directions, for example, as shown in FIG. 3. The semiconductor layers 120 function as channel regions of a plurality of memory cells and select transistors. The semiconductor layers 120 are, for example, semiconductor layers made of polycrystalline silicon (Si). The semiconductor layers 120 have a substantially cylindrical shape, for example, as shown in FIG. 4, and an insulating layer 125 made of silicon oxide or the like is provided in the central portion. The outer peripheral surfaces of the semiconductor layers 120 are surrounded by the conductive layers 110 and face the conductive layers 110.

[0024] An impurity region 121 containing an N-type impurity such as phosphorus (P) is provided at the upper end of the semiconductor layer 120. In the example of Fig. 4, the boundary between the upper end of the semiconductor layer 120 and the lower end of the impurity region 121 is indicated by a dashed line. The impurity region 121 is connected to the bit line BL via a contact Ch and a contact Vy (Fig. 3).

[0025] The lower end of the semiconductor layer 120 is connected to the semiconductor layer 112 .

[0026] The gate insulating film 130 has a substantially cylindrical shape covering the outer peripheral surface of the semiconductor layer 120. The gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a block insulating film 133 stacked between the semiconductor layer 120 and the conductive layer 110, as shown in FIG. 5, for example. The tunnel insulating film 131 and the block insulating film 133 are insulating films such as silicon oxide (SiO2). The charge storage film 132 is a film capable of storing charge such as silicon nitride (Si3N4). The tunnel insulating film 131, the charge storage film 132, and the block insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor layer 120 except for the contact portion between the semiconductor layer 120 and the semiconductor layer 112.

[0027] 5 shows an example in which the gate insulating film 130 includes a charge storage film 132 such as silicon nitride. However, the gate insulating film 130 may include a floating gate such as polycrystalline silicon containing N-type or P-type impurities.

[0028] Hook-up area R of memory block BLK HU For example, as shown in FIG. 2, the contact electrode 112 includes a part of the conductive layer 110 and a plurality of contact electrodes CC arranged in a matrix in the X and Y directions.

[0029] Furthermore, the hook-up area R HU2, the a-th contact electrode CC counting from the +Y direction to the -Y direction (a is an integer equal to or greater than 1) and the b-th contact electrode CC counting from the -X direction to the +X direction (b is an integer equal to or greater than 1) may be referred to as a contact electrode CCab. For example, the second contact electrode CC counting from the +Y direction to the -Y direction and the fourth contact electrode CC counting from the -X direction to the +X direction may be referred to as a contact electrode CC24.

[0030] A row of eight contact electrodes CC arranged in the X direction may be referred to as a contact electrode row CCG. Also, the regions corresponding to the contact electrode rows CCG may be referred to as contact electrode regions. As shown in FIG. 2, the hook-up region R HU In the pixel region 114, contact electrode rows CCG(0) and CCG(1) are alternately arranged in the Y direction.

[0031] 6 and 7, the contact electrodes CC extend in the Z direction and are connected at their lower ends to the conductive layer 110. The contact electrodes CC may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). In addition, an insulating layer 103 such as silicon oxide (SiO2) is provided on the outer circumferential surface of the contact electrodes CC.

[0032] In the following description, the n-th (n is an integer equal to or greater than 1) conductive layer 110 counting from the top may be referred to as conductive layer 110(n-1). Of the multiple contact electrodes CC, one connected to the conductive layer 110(n) may be referred to as contact electrode CC(n). Furthermore, the conductive layer 110(n-1) may be referred to as the n-th conductive layer 110. As shown in FIGS. 4, 6, and 7, the multiple conductive layers 110(n) are arranged at equal intervals in the Z direction. For this reason, the n in the contact electrode CC(n) represents the level of the length (depth) of the contact electrode CC in the Z direction.

[0033] As shown in FIG. 6, the contact electrode row CCG(0) is MHIn order from the closest to the memory hole region R, the contact electrodes CC11(0), CC12(1), CC13(2), CC14(3), CC15(4), CC16(5), CC17(6), and CC18(7) are provided. MH The depth of the contact electrode CC increases stepwise as the distance from the center line increases (that is, the length of the contact electrode CC in the Z direction increases).

[0034] As shown in FIG. 7, the contact electrode row CCG(1) is MH In this manner, the contact electrode row CCG(1) includes contact electrodes CC21(7), CC22(6), CC23(5), CC24(4), CC25(3), CC26(2), CC27(1), and CC28(0) in the order from closest to the memory hole region R MH As the distance from the center line increases, the depth of the contact electrode CC becomes shallower in stages (that is, the length of the contact electrode CC in the Z direction becomes shorter).

[0035] As shown in FIG. 8, the multiple contact electrodes CC11(0), CC12(1), CC13(2), CC14(3), CC15(4), CC16(5), CC17(6), and CC18(7) in the contact electrode column CCG(0) are aligned in the Y direction with the multiple contact electrodes CC21(7), CC22(6), CC23(5), CC24(4), CC25(3), CC26(2), CC27(1), and CC28(0) in the contact electrode column CCG(1).

[0036] In addition, the multiple contact electrodes CC31(0), CC32(1), CC33(2), CC34(3), CC35(4), CC36(5), CC37(6), and CC38(7) in contact electrode row CCG(0) are aligned in the Y direction with the multiple contact electrodes CC41(7), CC42(6), CC43(5), CC44(4), CC45(3), CC46(2), CC47(1), and CC48(0) in contact electrode row CCG(1), respectively.

[0037] An area including a certain number m (m is an integer of 2 or more) of contact electrodes CC may be called a unit area. In the example of FIG. 8, an area of ​​a certain area including two contact electrodes CC arranged in the Y direction is defined as a unit area. HU is virtually divided into a number of unit areas.

[0038] In FIG. 8, the unit area R11 is an area including two contact electrodes CC11(0) and CC21(7). The unit area R12 is an area including two contact electrodes CC12(1) and CC22(6). The unit area R13 is an area including two contact electrodes CC13(2) and CC23(5). The unit area R14 is an area including two contact electrodes CC14(3) and CC24(4). The unit area R15 is an area including two contact electrodes CC15(4) and CC25(3). The unit area R16 is an area including two contact electrodes CC16(5) and CC26(2). The unit area R17 is an area including two contact electrodes CC17(6) and CC27(1). The unit area R18 is an area including two contact electrodes CC18(7) and CC28(0).

[0039] Moreover, the unit area R21 is an area including two contact electrodes CC31(0) and CC41(7). The unit area R22 is an area including two contact electrodes CC32(1) and CC42(6). The unit area R23 is an area including two contact electrodes CC33(2) and CC43(5). The unit area R24 is an area including two contact electrodes CC34(3) and CC44(4). The unit area R25 is an area including two contact electrodes CC35(4) and CC45(3). The unit area R26 is an area including two contact electrodes CC36(5) and CC46(2). The unit area R27 is an area including two contact electrodes CC37(6) and CC47(1). The unit area R28 is an area including two contact electrodes CC38(7) and CC48(0).

[0040] For example, the average value of the depth level "0" of the contact electrode CC11(0) arranged in the unit region R11 and the depth level "7" of the contact electrode CC11(7) is "3.5." Similarly, the average value of the depth level n of each of the two contact electrodes CC arranged in the unit regions R12 to R18 and R21 to R28 is "3.5." In other words, the average value of the length in the Z direction of each of the two contact electrodes CC arranged in each of the unit regions R11 to R18 and R21 to R28 is the same value.

[0041] As shown in FIG. 2, a hook-up region R in which a plurality of contact electrodes CC are arranged HU is the first region R aligned in the X direction. HU1 and the second region R HU2 For example, the first region R HU1 is a region including the contact electrodes CC11 to CC14, CC21 to CC24, . . . , and the second region R HU2 is a region including contact electrodes CC15 to CC18, CC25 to CC28, . . .

[0042] The number of contact electrodes CC included in the multiple unit areas is defined as m (m is an integer equal to or greater than 2). The average value of the Z-direction lengths of the m contact electrodes CC having the first to mth largest Z-direction lengths among the multiple contact electrodes CC is defined as the "first length." The average value of the Z-direction lengths of the m contact electrodes CC having the first to mth smallest Z-direction lengths among the multiple contact electrodes CC is defined as the "second length."

[0043] For example, in the example of FIG. 8, the number m of contact electrodes CC included in the multiple unit regions is "2." The average value of the Z-direction length of the two contact electrodes having the first and second largest Z-direction lengths (e.g., contact electrodes CC18(7), CC17(6)) is "6.5." Therefore, the "first length" is "6.5." The average value of the Z-direction length of the two contact electrodes having the first and second smallest Z-direction lengths (e.g., contact electrodes CC11(0), CC12(1)) is "0.5." Therefore, the "second length" is "0.5."

[0044] As described above, the average value of the lengths in the Z direction of the two contact electrodes CC in each of the unit regions R11-R18, R21-R28 (average value of the depth levels) is 3.5. Therefore, the average value of the lengths in the Z direction of the two contact electrodes CC in each of the unit regions R11-R18, R21-R28 is smaller than the "first length" and larger than the "second length."

[0045] [Manufacturing method] Next, a method for manufacturing a memory die MD will be described with reference to FIGS. 9 to 42. FIGS. 11, 14, 23, 32, and 39 are schematic plan views for explaining the manufacturing method, and show a plan corresponding to FIG. 2. FIGS. 9, 10, 12, 13, 15, 17, 19, 21, 24, 26, 28, 30, 33, 35, 37, and 40 to 42 are schematic cross-sectional views for explaining the manufacturing method, and show a cross-section corresponding to FIG. 6. FIGS. 9, 10, 16, 18, 20, 22, 25, 27, 29, 31, 34, 36, and 38 are schematic cross-sectional views for explaining the manufacturing method, and show a cross-section corresponding to FIG. 7.

[0046] In manufacturing the memory die MD according to this embodiment, a semiconductor layer 112 is formed, for example, as shown in Fig. 9. A plurality of insulating layers 101 and a plurality of sacrificial layers 111 are alternately formed above the semiconductor layer 112. This process is performed by a method such as CVD (Chemical Vapor Deposition).

[0047] Next, as shown in Fig. 10, a plurality of semiconductor layers 120 and the like are formed. In this process, an insulating layer 104 such as silicon oxide (SiO2) is formed on the upper surface of the structure described with reference to Fig. 9 by a method such as CVD. Next, a through hole penetrating the insulating layer 104, the plurality of insulating layers 101, and the plurality of sacrificial layers 111 is formed by a method such as RIE (Reactive Ion Etching). In addition, a gate insulating film 130 (Fig. 5) and a semiconductor layer 120 are formed on the inner circumferential surface of the through hole by a method such as CVD.

[0048] 11 and 12, for example, a plurality of contact holes CH(0) are formed at positions corresponding to the contact electrodes CC. For example, a hard mask 105 is formed on the upper surface of the structure described with reference to Fig. 10. Next, by a method such as RIE, through holes are formed that penetrate the hard mask 105 and the insulating layer 104 and expose the upper surface of the sacrificial layer 111.

[0049] In the following description, the nth (n is an integer equal to or greater than 1) sacrificial layer 111 counting from the top may be referred to as sacrificial layer 111(n-1). Among the multiple contact holes CH, one that exposes the top surface of the sacrificial layer 111(n) and penetrates all the sacrificial layers 111 provided above it may be referred to as contact hole CH(n). Also, the sacrificial layer 111(n-1) may be referred to as the nth sacrificial layer 111. As shown in FIG. 12 and other figures, the multiple sacrificial layers 111(n) are arranged at equal intervals in the Z direction. Therefore, the n in the contact hole CH(n) represents the level of the length (depth) of the contact hole CH in the Z direction.

[0050] Also, hook-up area R HU Of the multiple contact holes CH arranged in, for the multiple contact holes CH shown in FIG. 11, the a-th contact hole CH (a is an integer equal to or greater than 1) counting from the +Y direction to the -Y direction and the b-th contact hole CH (b is an integer equal to or greater than 1) counting from the -X direction to the +X direction may be referred to as contact hole CHab.

[0051] A row of eight contact holes CH aligned in the X direction may be referred to as a contact hole row CHG. As shown in FIG. HU Two contact hole rows CHG(0), CHG(1) are alternately arranged in the Y direction. The contact hole row CHG(0) is formed in the same position as the contact electrode row CCG(0), and the contact hole row CHG(1) is formed in the same position as the contact electrode row CCG(1).

[0052] Next, a resist pattern for processing the contact holes CH is generated using lithography (sometimes called PEP (Photo Engraving Process)).

[0053] For example, as shown in FIG. 13, a resist 151 is applied to the upper surface of the structure described with reference to FIG.

[0054] 12 and 13 show a cross section corresponding to the contact hole row CHG(0). The structure of the cross section corresponding to the contact hole row CHG(1) is similar to the cross section shown in Fig. 12 and 13. For this reason, the cross section corresponding to the contact hole row CHG(1) is omitted from the illustration.

[0055] Next, as shown in Figures 14 to 16, for example, an exposure device (not shown) exposes the positions of contact holes CH12(0), CH14(0), CH16(0), CH18(0), CH21(0), CH23(0), CH25(0), CH27(0), CH32(0), CH34(0), CH36(0), CH38(0), CH41(0), CH43(0), CH45(0), and CH47(0) based on a photomask.

[0056] Then, by developing with a developer appropriate for resist 151, the resist at the positions of contact holes CH12(0), CH14(0), CH16(0), CH18(0), CH21(0), CH23(0), CH25(0), CH27(0), CH32(0), CH34(0), CH36(0), CH38(0), CH41(0), CH43(0), CH45(0), and CH47(0) is removed. This opens these contact holes.

[0057] 17 and 18, the sacrificial layer 111 and the insulating layer 101 are removed one by one from the open contact holes CH12(0), CH14(0), CH16(0), CH18(0), CH21(0), CH23(0), CH25(0), and CH27(0) among the contact holes CH. As a result, the contact holes CH12(1), CH14(1), CH16(1), CH18(1), CH21(1), CH23(1), CH25(1), and CH27(1) that reach the second layer of the sacrificial layer 111(1) are formed. This process is performed by, for example, RIE or the like.

[0058] Incidentally, in CH32(0), CH34(0), CH36(0), CH38(0), CH41(0), CH43(0), CH45(0), and CH47(0), the sacrificial layers 111 and the insulating layers 101 are also removed one by one.

[0059] Then, as shown in FIGS. 19 and 20, the resist 151 is removed.

[0060] Next, as shown in FIGS. 21 and 22, a resist 151 is applied to the upper surface of the structure described with reference to FIGS.

[0061] Next, as shown in Figures 23 to 25, for example, an exposure device (not shown) exposes the positions of contact holes CH13(0), CH14(1), CH17(0), CH18(1), CH21(1), CH22(0), CH25(1), CH26(0), CH33(0), CH34(1), CH37(0), CH38(1), CH41(1), CH42(0), CH45(1), and CH46(0) based on a photomask.

[0062] Then, by developing with a developer appropriate for resist 151, the resist at the positions of contact holes CH13(0), CH14(1), CH17(0), CH18(1), CH21(1), CH22(0), CH25(1), CH26(0), CH33(0), CH34(1), CH37(0), CH38(1), CH41(1), CH42(0), CH45(1), and CH46(0) is removed. This opens these contact holes.

[0063] Next, as shown in Figures 26 and 27, for example, the sacrificial layer 111 and the insulating layer 101 are removed two layers at a time for the open contact holes CH13(0), CH14(1), CH17(0), CH18(1), CH21(1), CH22(0), CH25(1), and CH26(0) among the contact holes CH. As a result, the contact holes CH13(2), CH14(3), CH17(2), CH18(3), CH21(3), CH22(2), CH25(3), and CH26(2) that reach the third and fourth sacrificial layers 111(2) and 111(3) are formed. This process is performed by, for example, RIE or the like.

[0064] In addition, in contact holes CH33(0), CH34(1), CH37(0), CH38(1), CH41(1), CH42(0), CH45(1), and CH26(0), two layers of the sacrificial layer 111 and two layers of the insulating layer 101 are removed.

[0065] Then, as shown in FIGS. 28 and 29, the resist 151 is removed.

[0066] Next, as shown in FIGS. 30 and 31, a resist 151 is applied to the upper surface of the structure described with reference to FIGS.

[0067] Next, as shown in Figures 32 to 34, for example, an exposure device (not shown) exposes the positions of contact holes CH15(0), CH16(1), CH17(2), CH18(3), CH21(3), CH22(2), CH23(1), CH24(0), CH35(0), CH36(1), CH37(2), CH38(3), CH41(3), CH42(2), CH43(1), and CH44(0) based on a photomask.

[0068] Then, by developing with a developer appropriate for resist 151, the resist at the positions of contact holes CH15(0), CH16(1), CH17(2), CH18(3), CH21(3), CH22(2), CH23(1), CH24(0), CH35(0), CH36(1), CH37(2), CH38(3), CH41(3), CH42(2), CH43(1), and CH44(0) is removed. This opens these contact holes.

[0069] Next, as shown in Figures 35 and 36, for example, the sacrificial layer 111 and the insulating layer 101 are removed four layers at a time for the open contact holes CH15(0), CH16(1), CH17(2), CH18(3), CH21(3), CH22(2), CH23(1), and CH24(0) among the contact holes CH. As a result, the contact holes CH15(4), CH16(5), CH17(6), CH18(7), CH21(7), CH22(6), CH23(5), and CH24(4) are formed, which reach the fifth to eighth sacrificial layers 111(4) to 111(7). This process is performed by, for example, RIE or the like.

[0070] In addition, in contact holes CH35(0), CH36(1), CH37(2), CH38(3), CH41(3), CH42(2), CH43(1), and CH44(0), four layers of the sacrificial layer 111 and four layers of the insulating layer 101 are removed.

[0071] 37 and 38, the resist 151 is removed. HU In the memory hole region R, contact hole rows CHG(0) and CHG(1) are arranged alternately in the Y direction. MH The depth of the contact hole CH becomes deeper by one layer as it goes away from the memory hole region R MH The depth of the contact hole CH becomes shallower by one layer as it goes away from the substrate.

[0072] 40, the insulating layer 103 and the sacrificial layer 106 are formed inside the contact holes CH11(0) to CH18(7). This process is performed by, for example, CVD or the like.

[0073] Next, as shown in Fig. 41, for example, a conductive layer 110 is formed. In this step, a groove penetrating the multiple insulating layers 101 and the multiple sacrificial layers 111 is formed at a position corresponding to the inter-block insulating layer ST (Fig. 2) by a method such as RIE. Next, the multiple sacrificial layers 111 are removed by a method such as wet etching via the groove. Next, the multiple conductive layers 110 are formed by a method such as CVD.

[0074] Next, as shown in FIG. 42, for example, contact electrodes CC11(0) to CC18(7) are formed. In this step, for example, the sacrificial layer 106 is removed. Next, a part of the insulating layer 103 is removed by a method such as RIE to expose the upper surfaces of the conductive layers 110(0) to 110(7). Next, contact electrodes CC11(0) to CC18(7) are formed by a method such as CVD.

[0075] Thereafter, bit lines BL and the like are formed, thereby completing the semiconductor memory device described with reference to FIGS.

[0076] The process of forming the contact electrode row CCG(0) from the contact hole row CHG(0) has been described with reference to Figures 40 to 42. However, the process of forming the contact electrode row CCG(1) from the contact hole row CHG(1) is also similar to the contents described with reference to Figures 40 to 42. For this reason, cross-sectional views corresponding to the contact hole row CHG(1) and the contact electrode row CCG(1) and their descriptions are omitted.

[0077] [Comparative Example] [composition] Next, a configuration of a semiconductor memory device according to a comparative example will be described with reference to Fig. 43 and Fig. 44. Fig. 43 is a schematic plan view of the semiconductor memory device according to the comparative example. Fig. 44 is a schematic enlarged view of the hook-up region shown in Fig. 43.

[0078] Furthermore, the hook-up area R HU Of the multiple contact electrodes CC arranged in the multiple contact electrodes CC shown in Figures 43 and 44, the a-th (a is an integer of 1 or more) contact electrode CC counting from the +Y direction to the -Y direction and the b-th (b is an integer of 1 or more) contact electrode CC counting from the -X direction to the +X direction may be referred to as contact electrode CCab.

[0079] In the semiconductor memory device according to the first embodiment, two contact electrode columns CCG(0), CCG(1) are arranged alternately in the Y direction as shown in Fig. 2 and Fig. 8. On the other hand, in the semiconductor memory device according to the comparative example, only the contact electrode column CCG(0) is arranged in the Y direction as shown in Fig. 43 and Fig. 44.

[0080] Each of the contact electrode rows CCG(0) is located in the memory hole region R MH The contact electrodes CC(0), CC(1), CC(2), CC(3), CC(4), CC(5), CC(6), and CC(7) are arranged in the X direction in order from closest to the memory hole region R. That is, the contact electrode rows CCG(0) are all aligned in the X direction from the memory hole region R. MH The depth of the contact hole CH becomes deeper by one layer as it goes away from the substrate.

[0081] In the comparative example, a region including a certain number m (m is an integer of 2 or more) of contact electrodes CC may be called a unit region. In the example of FIG. 44, a region of a certain area including two contact electrodes CC arranged in the Y direction is defined as a unit region. Hook-up region R HU is virtually divided into a number of unit areas.

[0082] In FIG. 44, the unit area R11 is an area including two contact electrodes CC11(0), CC21(0). The unit area R12 is an area including two contact electrodes CC12(1), CC22(1). The unit area R13 is an area including two contact electrodes CC13(2), CC23(2). The unit area R14 is an area including two contact electrodes CC14(3), CC24(3). The unit area R15 is an area including two contact electrodes CC15(4), CC25(4). The unit area R16 is an area including two contact electrodes CC16(5), CC26(5). The unit area R17 is an area including two contact electrodes CC17(6), CC27(6). The unit area R18 is an area including two contact electrodes CC18(7), CC28(7).

[0083] Moreover, the unit area R21 is an area including two contact electrodes CC31(0), CC41(0). The unit area R22 is an area including two contact electrodes CC32(1), CC42(1). The unit area R23 is an area including two contact electrodes CC33(2), CC43(2). The unit area R24 is an area including two contact electrodes CC34(3), CC44(3). The unit area R25 is an area including two contact electrodes CC35(4), CC45(4). The unit area R26 is an area including two contact electrodes CC36(5), CC46(5). The unit area R27 is an area including two contact electrodes CC37(6), CC47(6). The unit area R28 is an area including two contact electrodes CC38(7), CC48(7).

[0084] The average value of the depth level n of two contact electrodes CC arranged in unit areas R11 and R21 is both "0." The average value of the depth level n of two contact electrodes CC arranged in unit areas R12 and R22 is both "1." The average value of the depth level n of two contact electrodes CC arranged in unit areas R13 and R23 is both "2." The average value of the depth level n of two contact electrodes CC arranged in unit areas R14 and R24 is both "3."

[0085] The average value of the depth level n of two contact electrodes CC arranged in unit areas R15 and R25 is both "4." The average value of the depth level n of two contact electrodes CC arranged in unit areas R16 and R26 is both "5." The average value of the depth level n of two contact electrodes CC arranged in unit areas R17 and R27 is both "6." The average value of the depth level n of two contact electrodes CC arranged in unit areas R18 and R28 is both "7."

[0086] In the semiconductor memory device according to the comparative example, as shown in FIG. 44, the number m of contact electrodes CC included in a plurality of unit regions is "2". The average value of the Z-direction length of the two contact electrodes having the first and second largest Z-direction lengths (e.g., contact electrodes CC18(7), CC17(6)) is "6.5". Therefore, the "first length" is "6.5". The average value of the Z-direction length of the two contact electrodes having the first and second smallest Z-direction lengths (e.g., contact electrodes CC11(0), CC12(1)) is "0.5". Therefore, the "second length" is "0.5".

[0087] As described above, the maximum value of each average value of the Z-direction length of two contact electrodes CC in each unit region (each average value of the depth level) is the average value "7" of the Z-direction length of two contact electrodes CC18, CC28, CC38, and CC48 in the unit regions R18 and R28. Therefore, the average value of the Z-direction length of two contact electrodes CC18, CC28, CC38, and CC48 in the unit regions R18 and R28 is greater than "6.5" which is the "first length". In addition, the minimum value of each average value of the Z-direction length of two contact electrodes CC in each unit region is the average value "0" of the Z-direction length of two contact electrodes CC11, CC21, CC31, and CC41 in the unit regions R11 and R21. Therefore, the average value of the Z-direction length of two contact electrodes CC11, CC21, CC31, and CC41 in the unit regions R11 and R21 is less than "0.5" which is the "second length".

[0088] [Manufacturing method] Next, a method for manufacturing a semiconductor memory device according to a comparative example will be described with reference to Figures 45 and 46. Figures 45 and 46 are schematic cross-sectional views for explaining the method for manufacturing a semiconductor memory device according to a comparative example.

[0089] In manufacturing the semiconductor memory device of the comparative example, steps similar to those described with reference to FIG. 9 through to the steps described with reference to FIG. 42 are performed, the steps being the same as the steps of forming the contact hole row CHG(0) and the contact electrode row CCG(0).

[0090] The structures shown in Figures 45 and 46 correspond to the structures described with reference to Figures 30 and 33, respectively. The resist 151 illustrated in Figures 30 and 33 has a hook-up region R HU 45 and 46, the resist 151 has a constant thickness (thickness in the Z direction) and a flat upper surface. HU In this example, there is variation in the film thickness (thickness in the Z direction), and a step d3 occurs on the upper surface.

[0091] Specifically, in the structure shown in FIG. 45 and FIG. 46, the memory hole region R MH The thickness of the resist 151 in the memory hole region R MH The thickness of the resist 151 above the contact hole CH14(3) is d2. The thickness of the resist 151 rapidly increases from above the contact hole CH14(3) to above the contact hole CH15(0). Then, the thickness of the resist 151 again increases from above the memory hole region R MH The difference in thickness of the resist 151 as described above causes a step d3.

[0092] In the semiconductor memory device according to the comparative example, the same contact hole row CHG(0) is arranged in the Y direction. Therefore, the depth of the contact holes CH is uneven. That is, the contact holes CH having a shallow hole depth are arranged in the memory hole region R. MH , and the contact hole CH having a deep hole depth is arranged in a region close to the memory hole region R MH In this case, when the resist 151 is applied, the deeper contact holes CH absorb a larger amount of the resist 151 than the shallower contact holes CH. As a result, the thickness of the resist 151 above the deeper contact holes CH is thinner than the thickness of the resist 151 above the shallower contact holes CH.

[0093] In this way, the unevenness in the depth of the contact holes CH causes variations in the thickness of the resist 151, and the optimal focus of the exposure device is shifted between the thick and thin portions of the resist 151. This reduces the lithography process margin for the focus shift of the exposure device. As a result, the contact holes CH may not be opened, or the uniformity of the dimensions of the contact holes CH may decrease. In addition, the thickness of the resist 151 may be insufficient at the deep contact holes CH. In particular, the greater the number of layers of the conductive layer 110, the deeper the contact holes CH become, and the more likely it is that the thickness of the resist 151 will be insufficient.

[0094] In contrast, the semiconductor memory device according to the first embodiment has a memory hole region R MH A contact hole row CHG(0) in which the depth of the contact hole CH becomes deeper by one layer as it gets farther from the memory hole region R MH A contact hole row CHG(1) in which the depth of the contact hole CH becomes shallower by one layer as it gets farther from the Y direction is alternately arranged in the Y direction. Therefore, there is no deviation in the depth of the contact holes CH per unit area, and the film thickness of the resist 151 is uniform.

[0095] For example, as shown in FIG. 32, the average value of the depth level n of two contact holes CH arranged in all unit regions R11 to R18, R21 to R28 (see FIG. 8) is the same value "1.5". Also, the diameters of all contact holes CH are the same or approximately the same. In this case, the amount of resist 151 absorbed by two contact holes CH arranged in each unit region R11 to R18, R21 to R28 is the same or approximately the same in each unit region R11 to R18, R21 to R28. As a result, the hook-up region R HU In this case, the film thickness of the resist 151 is the same or approximately the same.

[0096] Therefore, it is possible to avoid a decrease in the process margin of lithography. As a result, it is possible to prevent the occurrence of unopened contact holes CH and the decrease in uniformity of the dimensions of the contact holes CH. In addition, it is possible to prevent the film thickness of the resist 151 from becoming insufficient.

[0097] [Second embodiment] [composition] Next, a semiconductor memory device according to the second embodiment will be described with reference to FIGS. 47 to 51. FIG. 47 is a schematic plan view showing a configuration of a part of the semiconductor memory device according to the second embodiment. FIG. 48 is a schematic cross-sectional view of the structure shown in FIG. 47 cut along line HH' and viewed in the direction of the arrows. FIG. 49 is a schematic cross-sectional view of the structure shown in FIG. 47 cut along line II' and viewed in the direction of the arrows. FIG. 50 is a schematic cross-sectional view of the structure shown in FIG. 47 cut along line JJ' and viewed in the direction of the arrows. FIG. 51 is a schematic enlarged view of the hook-up region shown in FIG. 47.

[0098] In the semiconductor memory device according to the first embodiment, one contact electrode row CCG having eight contact electrodes CC is provided between the inter-block insulating layers ST, as described with reference to Figures 2 and 3. In contrast, in the semiconductor memory device according to the second embodiment, three contact electrode rows CCG2 having eight contact electrodes CC are provided between the inter-block insulating layers ST, as shown in Figure 47. Note that the multiple memory blocks BLK aligned in the Y direction are formed as regions between the inter-block insulating layers ST.

[0099] 2, 4, 6, etc., eight conductive layers 110 and insulating layers 101 are formed in the semiconductor memory device according to the first embodiment. In contrast, twenty-four conductive layers 110 and insulating layers 101 are formed in the semiconductor memory device according to the second embodiment, as shown in FIGS. 48 to 50.

[0100] Hook-up area R of memory block BLK HUFor example, as shown in FIG. 47, the contact electrode 111 includes a part of the conductive layer 110 and a plurality of contact electrodes CC arranged in a matrix in the X and Y directions.

[0101] Furthermore, the hook-up area R HU Of the multiple contact electrodes CC arranged in the multiple contact electrodes CC shown in FIG. 47, the a-th (a is an integer of 1 or more) contact electrode CC counting from the +Y direction to the -Y direction and the b-th (b is an integer of 1 or more) contact electrode CC counting from the -X direction to the +X direction may be referred to as contact electrode CCab.

[0102] A row of eight contact electrodes CC arranged in the X direction may be referred to as a contact electrode row CCG2. Also, the regions corresponding to the contact electrode row CCG2 may be referred to as contact electrode regions. As shown in FIG. 47, the hook-up region R HU Between these inter-block insulating layers ST, three contact electrode rows CCG2(0), CCG2(1), and CCG2(2) are arranged in the Y direction.

[0103] As shown in FIG. 48, the contact electrode row CCG2(0) is MH In order from closest to the center, it has contact electrodes CC11(0), CC12(12), CC13(3), CC14(15), CC15(6), CC16(18), CC17(9), and CC18(21).

[0104] As shown in FIG. 49, the contact electrode row CCG2(1) is MH In order from closest to the center, it has contact electrodes CC21(1), CC22(13), CC23(4), CC24(16), CC25(7), CC26(19), CC27(10), and CC28(22).

[0105] As shown in FIG. 50, the contact electrode row CCG2(2) is MHIn order from closest to the center, it has contact electrodes CC31(2), CC32(14), CC33(5), CC34(17), CC35(8), CC36(20), CC37(11), and CC38(23).

[0106] In the example of FIG. 51, a region of a certain area including six contact electrodes CC in three rows and two columns (three in the Y direction and two in the X direction) is defined as a unit region. HU is virtually divided into a number of unit areas.

[0107] In FIG. 51, the unit area S11 is an area including six contact electrodes CC11(0), CC12(12), CC21(1), CC22(13), CC31(2), and CC32(14). The unit area S12 is an area including six contact electrodes CC13(3), CC14(15), CC23(4), CC24(16), CC33(5), and CC34(17). The unit area S13 is an area including six contact electrodes CC15(6), CC16(18), CC25(7), CC26(19), CC35(8), and CC36(20). The unit area S14 is an area including six contact electrodes CC17(9), CC18(21), CC27(10), CC28(22), CC37(11), and CC38(23).

[0108] The average value of the depth level n of the six contact electrodes CC arranged in unit area S11 is "7" (= 42 / 6). The average value of the depth level n of the six contact electrodes CC arranged in unit area S12 is "10" (= 60 / 6). The average value of the depth level n of the six contact electrodes CC arranged in unit area S13 is "13" (= 78 / 6). The average value of the depth level n of the six contact electrodes CC arranged in unit area S14 is "16" (= 96 / 6).

[0109] The minimum average value of the depth level n of the six contact electrodes CC is "7" in the unit area S11, and the maximum average value of the depth level n of the six contact electrodes CC is "16" in the unit area S14.

[0110] As shown in FIG. 51, contact electrode row CCG2(0) including contact electrodes CC41(0), CC42(12), CC43(3), CC44(15), CC45(6), CC46(18), CC47(9), and CC48(21) is a contact electrode row of the same arrangement as contact electrode row CCG2(0) including contact electrodes CC11(0), CC12(12), CC13(3), CC14(15), CC15(6), CC16(18), CC17(9), and CC18(21).

[0111] As shown in FIG. 47, a hook-up region R in which a plurality of contact electrodes CC are arranged HU is the first region R aligned in the X direction. HU1 and the second region R HU2 For example, the first region R HU1 is a region including the contact electrodes CC11 to CC14, CC21 to CC24, . . . , and the second region R HU2 is a region including contact electrodes CC15 to CC18, CC25 to CC28, . . .

[0112] The number of contact electrodes CC included in the multiple unit areas is defined as m (m is an integer equal to or greater than 2). The average value of the Z-direction lengths of the m contact electrodes CC having the first to mth largest Z-direction lengths among the multiple contact electrodes CC is defined as the "third length." The average value of the Z-direction lengths of the m contact electrodes CC having the first to mth smallest Z-direction lengths among the multiple contact electrodes CC is defined as the "fourth length."

[0113] For example, in the example of FIG. 51, the number m of contact electrodes CC included in the multiple unit regions is "6". The average value of the Z-direction lengths of the six contact electrodes whose lengths in the Z direction are the first to sixth largest (e.g., contact electrodes CC38(23), CC28(22), CC18(21), CC36(20), CC26(19), and CC16(18)) is "20.5". Therefore, the "third length" is "20.5". The average value of the Z-direction lengths of the six contact electrodes whose lengths in the Z direction are the first to sixth smallest (e.g., contact electrodes CC11(0), CC21(1), CC31(2), CC13(3), CC23(4), and CC33(5)) is "2.5". Therefore, the "fourth length" is "2.5".

[0114] As described above, the minimum average value of the depth level n of the six contact electrodes CC is "7" in unit area S11, and the maximum average value of the depth level n of the six contact electrodes CC is "16" in unit area S14. Therefore, the average value of the lengths in the Z direction of the six contact electrodes CC in each of unit areas S11 to S14 is smaller than the "third length" and larger than the "fourth length".

[0115] [Manufacturing method] A method for manufacturing the semiconductor memory device according to the second embodiment will now be described with reference to Figures 52 to 54. Figures 52 to 54 are schematic cross-sectional views for explaining the method for manufacturing the semiconductor memory device according to the second embodiment.

[0116] The method for manufacturing the semiconductor memory device according to the second embodiment is substantially similar to the method for manufacturing the semiconductor memory device according to the first embodiment.

[0117] However, in the method for manufacturing the semiconductor memory device according to the second embodiment, 24 sacrificial layers 111 are formed in the step corresponding to FIG.

[0118] In the method for manufacturing a semiconductor memory device according to the first embodiment, contact holes CH(0)-CH(7) reaching the 1st to 8th sacrificial layers 111(0)-111(7) are formed by combining 1st, 2nd, and 4th layer processing (processing of power-of-two layers) for the contact hole CH. In contrast, in the method for manufacturing a semiconductor memory device according to the second embodiment, contact holes CH(0)-CH(23) reaching the 1st to 24th sacrificial layers 111(0)-111(23) are formed by combining 1st, 2nd, 3rd, 6th, and 12th layer processing for the contact hole CH.

[0119] 52 to 54 show a state in which, after the six layers have been processed, the resist 151 corresponding to each layer is removed and the resist 151 is applied again.

[0120] [Comparative Example] [composition] Next, a configuration of a semiconductor memory device according to a comparative example will be described with reference to Fig. 55 and Fig. 56. Fig. 55 is a schematic plan view of the semiconductor memory device according to the comparative example. Fig. 56 is a schematic enlarged view of the hook-up region shown in Fig. 55.

[0121] Hook-up area R of memory block BLK HU For example, as shown in FIG. 55, the contact electrode 111 includes a part of the conductive layer 110 and a plurality of contact electrodes CC arranged in a matrix in the X and Y directions.

[0122] Furthermore, the hook-up area R HU Of the multiple contact electrodes CC arranged in the multiple contact electrodes CC shown in Figures 55 and 56, the a-th (a is an integer equal to or greater than 1) contact electrode CC counting from the +Y direction to the -Y direction and the b-th (b is an integer equal to or greater than 1) contact electrode CC counting from the -X direction to the +X direction may be referred to as contact electrode CCab.

[0123] A row of eight contact electrodes CC arranged in the X direction may be called a contact electrode row CCG2'. As shown in FIG. HUBetween these inter-block insulating layers ST, three contact electrode rows CCG2'(0), CCG2'(1), and CCG2'(2) are arranged in the Y direction.

[0124] As shown in FIGS. 55 and 56, the contact electrode row CCG2′(0) is MH In order from closest to the center, it has contact electrodes CC11(0), CC12(3), CC13(6), CC14(9), CC15(12), CC16(15), CC17(18), and CC18(21).

[0125] In addition, the contact electrode row CCG2'(1) is MH In order from closest to the center, it has contact electrodes CC21(1), CC22(4), CC23(7), CC24(10), CC25(13), CC26(16), CC27(19), and CC28(22).

[0126] In addition, the contact electrode row CCG2'(2) is MH In order from closest to the center, it has contact electrodes CC31(2), CC32(5), CC33(8), CC34(11), CC35(14), CC36(17), CC37(20), and CC38(23).

[0127] In the example of FIG. 56, a region of a certain area including six contact electrodes CC in three rows and two columns (three in the Y direction and two in the X direction) is defined as a unit region. HU is virtually divided into a number of unit areas.

[0128] In FIG. 56, the unit area S11 is an area including six contact electrodes CC11(0), CC12(3), CC21(1), CC22(4), CC31(2), and CC32(5). The unit area S12 is an area including six contact electrodes CC13(6), CC14(9), CC23(7), CC24(10), CC33(8), and CC34(11). The unit area S13 is an area including six contact electrodes CC15(12), CC16(15), CC25(13), CC26(16), CC35(14), and CC36(17). The unit area S14 is an area including six contact electrodes CC17(18), CC18(21), CC27(19), CC28(22), CC37(20), and CC38(23).

[0129] The average value of the depth level n of the six contact electrodes CC arranged in the unit region S11 is "2.5" (=15 / 6). The average value of the depth level n of the six contact electrodes CC arranged in the unit region S12 is "8.5" (=51 / 6). The average value of the depth level n of the six contact electrodes CC arranged in the unit region S13 is "14.5" (=87 / 6). The average value of the depth level n of the six contact electrodes CC arranged in the unit region S14 is "20.5" (=123 / 6).

[0130] The minimum average value of the depth level n of the six contact electrodes CC is "2.5" in the unit area S11, and the maximum average value of the depth level n of the six contact electrodes CC is "20.5" in the unit area S14.

[0131] As shown in FIG. 56, contact electrode row CCG2'(0) including contact electrodes CC41(0), CC42(3), CC43(6), CC44(9), CC45(12), CC46(15), CC47(18), and CC48(21) has the same arrangement as contact electrode row CCG2'(0) including contact electrodes CC11(0), CC12(3), CC13(6), CC14(9), CC15(12), CC16(15), CC17(18), and CC18(21).

[0132] In the semiconductor memory device according to the comparative example, the number m of contact electrodes CC included in a plurality of unit areas is "6" as shown in Fig. 56. Also, the "third length" as described in the second embodiment is "20.5" and the "fourth length" is "2.5".

[0133] As described above, the minimum average value of the depth level n of the six contact electrodes CC is "2.5" in the unit area S11, and the maximum average value of the depth level n of the six contact electrodes CC is "20.5" in the unit area S14. Therefore, the average value of the Z-direction length of the six contact electrodes CC in the unit area S14 is the same as the "third length", and the average value of the Z-direction length of the six contact electrodes CC in the unit area S11 is the same as the "fourth length". In this way, the average value of the Z-direction length of the six contact electrodes CC in each of the unit areas S11 to S14 is not smaller than the "third length". Moreover, the average value of the Z-direction length of the six contact electrodes CC in each of the unit areas S11 to S14 is not larger than the "fourth length".

[0134] [Manufacturing method] A method for manufacturing a semiconductor memory device according to a comparative example will now be described with reference to Figures 57 to 59. Figures 57 to 59 are schematic cross-sectional views for explaining the method for manufacturing a semiconductor memory device according to a comparative example.

[0135] In manufacturing the semiconductor memory device according to the comparative example, steps similar to those described in the second embodiment are performed.

[0136] The structures shown in Figures 57 to 59 correspond to the structures described with reference to Figures 52 to 54, respectively. HU In the embodiment, the film has a constant thickness (thickness in the Z direction) and a flat upper surface.

[0137] On the other hand, the resist 151 illustrated in FIG. 57 to FIG. 59 has a hook-up region R HUIn this example, there is variation in the film thickness (thickness in the Z direction), and a step d3 occurs on the upper surface.

[0138] Specifically, for example, in the structure shown in FIG. 57 to FIG. 59, the memory hole region R MH The thickness of the resist 151 in the memory hole region R MH The thickness of the resist 151 above the contact hole CH14(9) is d2. The thickness of the resist 151 rapidly increases from above the contact hole CH14(9) to above the contact hole CH15(0). Then, the thickness of the resist 151 again increases from above the memory hole region R MH The difference in thickness of the resist 151 as described above causes a step d3.

[0139] In the semiconductor memory device according to the comparative example, the minimum average value of the depth level n of the six contact electrodes CC is "2.5" in the unit area S11, and the maximum average value of the depth level n of the six contact electrodes CC is "20.5" in the unit area S14. In this way, the depth of the contact holes CH per unit area is uneven. In this case, when the resist 151 is applied, the contact holes CH with a deep hole have a larger amount of the resist 151 absorbed than the contact holes CH with a shallow hole. As a result, the film thickness of the resist 151 above the contact holes CH with a deep hole is thinner than the film thickness of the resist 151 above the contact holes CH with a shallow hole.

[0140] In this way, the unevenness in the depth of the contact holes CH causes variations in the thickness of the resist 151, which causes the optimal focus of the exposure tool to shift between thick and thin portions of the resist 151. This reduces the lithography process margin for the focus shift of the exposure tool. As a result, the contact holes CH may not be opened, or the uniformity of the dimensions of the contact holes CH may decrease. Also, the thickness of the resist 151 may be insufficient at the deeper portions of the contact holes CH.

[0141] In contrast, in the semiconductor memory device according to the second embodiment, the minimum average value of the depth level n of the six contact electrodes CC is "7" in the unit area S11, and the maximum average value of the depth level n of the six contact electrodes CC is "16" in the unit area S14. In this manner, the semiconductor memory device according to the second embodiment has a smaller deviation in the depth of the contact holes CH per unit area than the semiconductor memory device according to the comparative example. As a result, the semiconductor memory device according to the second embodiment has a smaller variation in the film thickness of the resist 151 than the semiconductor memory device according to the comparative example.

[0142] Therefore, the process margin of lithography can be secured. As a result, it is possible to prevent the occurrence of unopened contact holes CH and the deterioration of the uniformity of the dimensions of the contact holes CH. In addition, it is possible to prevent the film thickness of the resist 151 from becoming insufficient.

[0143] [Third embodiment] Next, a semiconductor memory device according to a third embodiment will be described with reference to Fig. 60. Fig. 60 is a schematic enlarged view of a hook-up region of the semiconductor memory device according to the third embodiment.

[0144] In the semiconductor memory device according to the third embodiment, three contact electrode columns CCG3 each including eight contact electrodes CC are provided between inter-block insulating layers ST as shown in Fig. 60. Furthermore, in the semiconductor memory device according to the third embodiment, 24 layers of conductive layers 110 and insulating layers 101 are formed.

[0145] A row of eight contact electrodes CC arranged in the X direction may be referred to as a contact electrode row CCG3. Also, the regions corresponding to the contact electrode row CCG3 may be referred to as contact electrode regions. As shown in FIG. 60, the hook-up region R HU Between these inter-block insulating layers ST, three contact electrode columns CCG3(0), CCG3(1), and CCG3(2) are arranged in the Y direction.

[0146] As shown in FIG. 60, the contact electrode row CCG3(0) is MH In order from closest to the center, it has contact electrodes CC11(0), CC12(1), CC13(2), CC14(3), CC15(4), CC16(5), CC17(6), and CC18(7).

[0147] The contact electrode row CCG3(1) is MH In order from closest to the center, it has contact electrodes CC21(8), CC22(9), CC23(10), CC24(11), CC25(12), CC26(13), CC27(14), and CC28(15).

[0148] The contact electrode row CCG3(2) is MH In order from closest to the center, it has contact electrodes CC31 (16), CC32 (17), CC33 (18), CC34 (19), CC35 (20), CC36 (21), CC37 (22), and CC38 (23).

[0149] In the example of FIG. 60, a region of a certain area including three contact electrodes CC arranged in the Y direction is defined as a unit region. HU is virtually divided into a number of unit areas.

[0150] In FIG. 60, the unit area T11 is an area including three contact electrodes CC11(0), CC21(8), and CC31(16). The unit area T12 is an area including three contact electrodes CC12(1), CC22(9), and CC32(17). The unit area T13 is an area including three contact electrodes CC13(2), CC23(10), and CC33(18). The unit area T14 is an area including three contact electrodes CC14(3), CC24(11), and CC34(19). The unit area T15 is an area including three contact electrodes CC15(4), CC25(12), and CC35(20). The unit area T16 is an area including three contact electrodes CC16(5), CC26(13), and CC36(21). The unit region T17 is a region that includes three contact electrodes CC17(6), CC27(14), and CC37(22). The unit region T18 is a region that includes three contact electrodes CC18(7), CC28(15), and CC38(23).

[0151] The average value of the depth level n of the three contact electrodes CC arranged in unit region T11 is "8" (= 24 / 3). The average value of the depth level n of the three contact electrodes CC arranged in unit region T12 is "9" (= 27 / 3). The average value of the depth level n of the three contact electrodes CC arranged in unit region T13 is "10" (= 30 / 3). The average value of the depth level n of the three contact electrodes CC arranged in unit region S14 is "11" (= 33 / 3).

[0152] The average value of the depth level n of the three contact electrodes CC arranged in unit region T15 is "12" (= 36 / 3). The average value of the depth level n of the three contact electrodes CC arranged in unit region T16 is "13" (= 39 / 3). The average value of the depth level n of the three contact electrodes CC arranged in unit region T17 is "14" (= 42 / 3). The average value of the depth level n of the three contact electrodes CC arranged in unit region S18 is "15" (= 45 / 3).

[0153] The minimum average value of the depth level n of the three contact electrodes CC is "8" in the unit area T11, and the maximum average value of the depth level n of the three contact electrodes CC is "15" in the unit area T18.

[0154] In this manner, in each of the unit regions T11 to T18, contact electrodes CC with shallow hole depths and contact electrodes CC with deep hole depths are arranged. Therefore, the difference between the minimum average value of the depth level n of the contact electrodes CC and the maximum average value of the depth level n of the contact electrodes CC is small. Therefore, the process margin of lithography can be secured. As a result, it is possible to prevent the occurrence of unopened contact holes CH and the deterioration of the uniformity of the dimensions of the contact holes CH. In addition, it is possible to prevent the film thickness of the resist 151 from becoming insufficient, and a desired pattern can be formed in the resist 151.

[0155] [Fourth embodiment] Next, a semiconductor memory device according to a fourth embodiment will be described with reference to Fig. 61. Fig. 61 is a schematic enlarged view of a hook-up region of the semiconductor memory device according to the fourth embodiment.

[0156] In the semiconductor memory device according to the fourth embodiment, three contact electrode columns CCG4 each including eight contact electrodes CC are provided between inter-block insulating layers ST as shown in Fig. 61. Also, in the semiconductor memory device according to the fourth embodiment, 24 layers of conductive layers 110 and insulating layers 101 are formed.

[0157] A row of eight contact electrodes CC arranged in the X direction may be referred to as a contact electrode row CCG4. Also, the regions corresponding to the contact electrode row CCG4 may be referred to as contact electrode regions. As shown in FIG. 61, the hook-up region R HU Between these inter-block insulating layers ST, three contact electrode rows CCG4(0), CCG4(1), and CCG4(2) are arranged in the Y direction.

[0158] As shown in FIG. 61, the contact electrode row CCG4(0) is MH In order from closest to the center, it has contact electrodes CC11(0), CC12(1), CC13(2), CC14(3), CC15(4), CC16(5), CC17(6), and CC18(7).

[0159] The contact electrode row CCG4(1) is MH In order from closest to the center, it has contact electrodes CC21 (15), CC22 (14), CC23 (13), CC24 (12), CC25 (11), CC26 (10), CC27 (9), and CC28 (8).

[0160] The contact electrode row CCG4(2) is MH In order from closest to the center, it has contact electrodes CC31 (16), CC32 (17), CC33 (18), CC34 (19), CC35 (20), CC36 (21), CC37 (22), and CC38 (23).

[0161] In the example of FIG. 61, a region of a certain area including three contact electrodes CC arranged in the Y direction is defined as a unit region. HU is virtually divided into a number of unit areas.

[0162] In FIG. 61, the unit area U11 is an area including three contact electrodes CC11(0), CC21(15), and CC31(16). The unit area U12 is an area including three contact electrodes CC12(1), CC22(14), and CC32(17). The unit area U13 is an area including three contact electrodes CC13(2), CC23(13), and CC33(18). The unit area U14 is an area including three contact electrodes CC14(3), CC24(12), and CC34(19). The unit area U15 is an area including three contact electrodes CC15(4), CC25(11), and CC35(20). The unit area U16 is an area including three contact electrodes CC16(5), CC26(10), and CC36(21). The unit area U17 is an area that includes three contact electrodes CC17(6), CC27(9), and CC37(22). The unit area U18 is an area that includes three contact electrodes CC18(7), CC28(8), and CC38(23).

[0163] The average value of the depth level n of the three contact electrodes CC arranged in the unit area U11 is approximately "10.33" (=31 / 3). The average value of the depth level n of the three contact electrodes CC arranged in the unit area U12 is approximately "10.67" (=32 / 3). The average value of the depth level n of the three contact electrodes CC arranged in the unit area U13 is approximately "11" (=33 / 3). The average value of the depth level n of the three contact electrodes CC arranged in the unit area U14 is approximately "11.33" (=34 / 3).

[0164] The average value of the depth level n of the three contact electrodes CC arranged in the unit area U15 is approximately "11.67" (=35 / 3). The average value of the depth level n of the three contact electrodes CC arranged in the unit area U16 is approximately "12" (=36 / 3). The average value of the depth level n of the three contact electrodes CC arranged in the unit area U17 is approximately "12.33" (=37 / 3). The average value of the depth level n of the three contact electrodes CC arranged in the unit area U18 is approximately "12.67" (=38 / 3).

[0165] The minimum average value of the depth level n of the three contact electrodes CC is approximately "10.33" in the unit area U11, and the maximum average value of the depth level n of the three contact electrodes CC is approximately "12.67" in the unit area U18.

[0166] In this manner, in each of the unit regions U11 to U18, contact electrodes CC with shallow holes and contact electrodes CC with deep holes are arranged. Therefore, in the semiconductor memory device according to the fourth embodiment, the difference between the minimum average value of the depth level n of the contact electrodes CC and the maximum average value of the depth level n of the contact electrodes CC is smaller than that in the semiconductor memory device according to the third embodiment. This makes it possible to ensure the process margin of lithography. As a result, it is possible to prevent the occurrence of unopened contact holes CH and the deterioration of the uniformity of the dimensions of the contact holes CH. It is also possible to prevent the film thickness of the resist 151 from becoming insufficient.

[0167] [Other embodiments] The semiconductor memory devices according to the first to fourth embodiments have been described above. However, the configurations and manufacturing methods of the semiconductor memory devices according to the first to fourth embodiments are merely examples, and the specific configurations and manufacturing methods can be appropriately adjusted.

[0168] For example, the hookup area R of the memory block BLK HU In this case, it is sufficient that the difference in the average value of the depth level of the contact holes CH (contact electrodes CC) per unit area is small overall.

[0169] For example, in the first embodiment, the deep contact holes CH (contact electrodes CC) and the shallow contact holes CH (contact electrodes CC) are aligned in the Y direction. However, the deep contact holes CH (contact electrodes CC) and the shallow contact holes CH (contact electrodes CC) may be aligned alternately in the X direction.

[0170] In the first to fourth embodiments, for example, the contact holes CH (the contact electrodes CC) are formed in the hook-up region R HU However, the contact holes CH (contact electrodes CC) may be arranged in various geometric patterns including figures such as triangles and squares.

[0171] Also, for example, in the first embodiment, one contact hole row CHG (contact electrode row CCG) is provided between two inter-block insulating layers ST adjacent in the Y direction, and in the second to fourth embodiments, three contact hole rows CHG (contact electrode rows CCG) are provided between two inter-block insulating layers ST adjacent in the Y direction. However, the number of contact hole rows CHG (contact electrode rows CCG) provided between two inter-block insulating layers ST adjacent in the Y direction is not limited to "1" or "3", and may be "2" or "4 or more".

[0172] Also, for example, in the first to fourth embodiments, the contact hole row CHG (contact electrode row CCG) includes eight contact holes CH (contact electrodes CC). However, the number of contact holes CH (contact electrodes CC) included in the contact hole row CHG (contact electrode row CCG) is not limited to "8" and may be any other number.

[0173] Also, for example, in the first embodiment, the number of layers of the conductive layer 110 is "8", and in the second to fourth embodiments, the number of layers of the conductive layer 110 is "24". However, the number of layers of the conductive layer 110 is not limited to "8" or "24", and may be any other number.

[0174] When applying the resist 151, the amount of the resist 151 applied may be greater when the contact hole CH is deep than when the contact hole CH is shallow. This is because the amount of the resist 151 absorbed by the contact hole CH is greater.

[0175] In the first embodiment, the unit regions R11 to R18 and R21 to 28 are regions including two contact electrodes CC, in the second embodiment, the unit regions S11 to S14 are regions including six contact electrodes CC, and in the third and fourth embodiments, the unit regions T11 to T18 and U11 to U18 are regions including three contact electrodes CC. Any method for setting the unit regions is possible, but at least the number of contact electrodes included in the unit regions (a fixed number) is a number smaller than the number of conductive layers. In general, the smaller the number of contact electrodes included in the unit regions (i.e., the smaller the area of ​​the unit regions), and the smaller the difference in the average values ​​of the depth levels of the contact electrodes in the unit regions, the easier it is to make the film thickness of the resist 151 uniform.

[0176] Furthermore, for example, in the first to fourth embodiments, one end of the semiconductor layer 120 in the Z direction is connected to the semiconductor layer 112. However, one end of the semiconductor layer 120 in the Z direction may be connected to the semiconductor substrate 100. Furthermore, for example, in the first to fourth embodiments, the contact electrode CC is connected to the upper surface of the conductive layer 110. However, the contact electrode CC may be connected to the lower surface of the conductive layer 110.

[0177] 10 and 11, the hard mask 105 is used in the manufacturing methods according to the first to fourth embodiments. However, such methods are merely examples, and the specific methods can be adjusted as appropriate. For example, the semiconductor memory device according to any of the embodiments can be manufactured without using the hard mask 105.

[0178] [others] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0179] 100...semiconductor substrate, 110...conductive layer, 120...semiconductor layer, 130...gate insulating film, CC...contact electrode, CCG...contact electrode row, CH...contact hole, CHC...contact hole row, ST...inter-block insulating layer, R HU …Hookup area, R HU1 …first region, R HU2 ...Second area, R11~R18, R21~R28, S11~S14, T11~T18, U11~U18...unit area.

Claims

1. a substrate having a memory area and a hook-up area aligned in a first direction; a plurality of memory structures aligned in a second direction intersecting the first direction; Equipped with Each of the plurality of memory structures comprises: a plurality of conductive layers aligned in a third direction intersecting a surface of the substrate and extending in the first direction across the memory region and the hook-up region; a semiconductor layer provided in the memory region, extending in the third direction, and facing the plurality of conductive layers; a charge storage film provided between the plurality of conductive layers and the semiconductor layer; a plurality of contact electrodes provided in the hook-up region, extending in the third direction, each having an outer circumferential surface surrounded by a portion of the plurality of conductive layers, each connected to one of the plurality of conductive layers; Equipped with The hook-up region includes a first region and a second region aligned in the first direction, the first region includes a first contact electrode and a second contact electrode; the second region includes a third contact electrode; a length of the third contact electrode in the third direction is longer than a length of the first contact electrode in the third direction and shorter than a length of the second contact electrode in the third direction; the hook-up region includes a first contact electrode region and a second contact electrode region aligned in the second direction, the first contact electrode region and the second contact electrode region each include a predetermined number of the contact electrodes arranged in the first direction; the predetermined number of contact electrodes included in the first contact electrode region have a length in the third direction greater than that of the contact electrodes provided on one side in the first direction; The predetermined number of contact electrodes included in the second contact electrode region have a length in the third direction greater on the other side in the first direction. Semiconductor memory device.

2. each of the plurality of contact electrodes is included in the first region or the second region; The number of the contact electrodes included in the first region is equal to the number of the contact electrodes included in the second region.

2. The semiconductor memory device according to claim 1.

3. The contact electrodes included in the first region are aligned in the first direction with the contact electrodes included in the second region.

3. The semiconductor memory device according to claim 1.

4. a substrate having a memory area and a hook-up area aligned in a first direction; a first memory structure and a second memory structure aligned in a second direction intersecting the first direction; Equipped with The first memory structure and the second memory structure each include: a plurality of conductive layers aligned in a third direction intersecting a surface of the substrate and extending in the first direction across the memory region and the hook-up region; a semiconductor layer provided in the memory region, extending in the third direction, and facing the plurality of conductive layers; a charge storage film provided between the plurality of conductive layers and the semiconductor layer; a plurality of contact electrodes provided in the hook-up region, extending in the third direction, each having an outer circumferential surface surrounded by a portion of the plurality of conductive layers, each connected to one of the plurality of conductive layers; Equipped with the hook-up region includes a plurality of unit regions aligned in the first direction, the plurality of contact electrodes included in the first memory structure and the plurality of contact electrodes included in the second memory structure are each included in any one of the plurality of unit areas; The number of the contact electrodes included in the plurality of unit regions is m (m is an integer of 2 or more), a first length is an average value of lengths in the third direction of m contact electrodes having the first to mth largest lengths in the third direction among the plurality of contact electrodes included in the first memory structure and the second memory structure; When the average value of lengths in the third direction of m contact electrodes having the first to mth smallest lengths in the third direction among the plurality of contact electrodes included in the first memory structure and the second memory structure is defined as a second length, an average value of lengths of the m contact electrodes in each unit region in the third direction is smaller than the first length and larger than the second length, The average values ​​of the lengths of the m contact electrodes in each unit region in the third direction are approximately constant. Semiconductor memory device.

5. A substrate having a memory area and a hook-up area aligned in a first direction; a first memory structure and a second memory structure aligned in a second direction intersecting the first direction; Equipped with The first memory structure and the second memory structure each include: a plurality of conductive layers aligned in a third direction intersecting a surface of the substrate and extending in the first direction across the memory region and the hook-up region; a semiconductor layer provided in the memory region, extending in the third direction, and facing the plurality of conductive layers; a charge storage film provided between the plurality of conductive layers and the semiconductor layer; a plurality of contact electrodes provided in the hook-up region, extending in the third direction, each having an outer circumferential surface surrounded by a portion of the plurality of conductive layers, each connected to one of the plurality of conductive layers; Equipped with the hook-up region includes a plurality of unit regions aligned in the first direction, the plurality of contact electrodes included in the first memory structure and the plurality of contact electrodes included in the second memory structure are each included in any one of the plurality of unit areas; The number of the contact electrodes included in the plurality of unit regions is m (m is an integer of 2 or more), a first length is an average value of lengths in the third direction of m contact electrodes having the first to mth largest lengths in the third direction among the plurality of contact electrodes included in the first memory structure and the second memory structure; When the average value of lengths in the third direction of m contact electrodes having the first to mth smallest lengths in the third direction among the plurality of contact electrodes included in the first memory structure and the second memory structure is defined as a second length, an average value of lengths of the m contact electrodes in each unit region in the third direction is smaller than the first length and larger than the second length, the hook-up region includes a first contact electrode region and a second contact electrode region aligned in the second direction, the first contact electrode region and the second contact electrode region each include a predetermined number of the contact electrodes arranged in the first direction; the predetermined number of contact electrodes included in the first contact electrode region have a length in the third direction greater than that of the contact electrodes provided on one side in the first direction; The predetermined number of contact electrodes included in the second contact electrode region have a length in the third direction greater on the other side in the first direction. Semiconductor memory device.

6. A substrate having a memory area and a hook-up area aligned in a first direction; a first memory structure and a second memory structure aligned in a second direction intersecting the first direction; Equipped with The first memory structure and the second memory structure each include: a plurality of conductive layers aligned in a third direction intersecting a surface of the substrate and extending in the first direction across the memory region and the hook-up region; a semiconductor layer provided in the memory region, extending in the third direction, and facing the plurality of conductive layers; a charge storage film provided between the plurality of conductive layers and the semiconductor layer; a plurality of contact electrodes provided in the hook-up region, extending in the third direction, each having an outer circumferential surface surrounded by a portion of the plurality of conductive layers, each connected to one of the plurality of conductive layers; Equipped with the hook-up region includes a plurality of unit regions aligned in the first direction, the plurality of contact electrodes included in the first memory structure and the plurality of contact electrodes included in the second memory structure are each included in any one of the plurality of unit areas; The number of the contact electrodes included in the plurality of unit regions is m (m is an integer of 2 or more), a first length is an average value of lengths in the third direction of m contact electrodes having the first to mth largest lengths in the third direction among the plurality of contact electrodes included in the first memory structure and the second memory structure; When the average value of lengths in the third direction of m contact electrodes having the first to mth smallest lengths in the third direction among the plurality of contact electrodes included in the first memory structure and the second memory structure is defined as a second length, an average value of lengths of the m contact electrodes in each unit region in the third direction is smaller than the first length and larger than the second length, the hook-up region includes a third contact electrode region; the third contact electrode region includes a fourth contact electrode, a fifth contact electrode, and a sixth contact electrode aligned in the first direction; the fifth contact electrode is provided between the fourth contact electrode and the sixth contact electrode, The length of the fifth contact electrode in the third direction is greater than or smaller than both of the length of the fourth contact electrode in the third direction and the length of the sixth contact electrode in the third direction. Semiconductor memory device.

7. a substrate having a memory area and a hook-up area aligned in a first direction; a plurality of conductive layers aligned in a third direction intersecting a surface of the substrate and extending in the first direction across the memory region and the hook-up region; a semiconductor layer provided in the memory region, extending in the third direction, and facing the plurality of conductive layers; a charge storage film provided between the plurality of conductive layers and the semiconductor layer; a plurality of contact electrodes provided in the hook-up region, extending in the third direction, each having an outer circumferential surface surrounded by a portion of the plurality of conductive layers, each connected to one of the plurality of conductive layers; Equipped with the hook-up region includes a plurality of unit regions aligned in the first direction, the contact electrode is included in any one of the plurality of unit regions, The number of the contact electrodes included in the plurality of unit regions is m (m is an integer of 2 or more), a third length is an average value of lengths in the third direction of m contact electrodes having lengths in the third direction that are the first to mth largest among the plurality of contact electrodes; When the average value of the lengths in the third direction of m contact electrodes having the first to mth smallest lengths in the third direction among the plurality of contact electrodes is defined as a fourth length, an average value of lengths of the m contact electrodes in each unit region in the third direction is smaller than the third length and larger than the fourth length, The average values ​​of the lengths of the m contact electrodes in each unit region in the third direction are approximately constant. Semiconductor memory device.

8. A substrate having a memory area and a hook-up area aligned in a first direction; a plurality of conductive layers aligned in a third direction intersecting a surface of the substrate and extending in the first direction across the memory region and the hook-up region; a semiconductor layer provided in the memory region, extending in the third direction, and facing the plurality of conductive layers; a charge storage film provided between the plurality of conductive layers and the semiconductor layer; a plurality of contact electrodes provided in the hook-up region, extending in the third direction, each having an outer circumferential surface surrounded by a portion of the plurality of conductive layers, each connected to one of the plurality of conductive layers; Equipped with the hook-up region includes a plurality of unit regions aligned in the first direction, the contact electrode is included in any one of the plurality of unit regions, The number of the contact electrodes included in the plurality of unit regions is m (m is an integer of 2 or more), a third length is an average value of lengths in the third direction of m contact electrodes having lengths in the third direction that are the first to mth largest among the plurality of contact electrodes; When the average value of the lengths in the third direction of m contact electrodes having the first to mth smallest lengths in the third direction among the plurality of contact electrodes is defined as a fourth length, an average value of lengths of the m contact electrodes in each unit region in the third direction is smaller than the third length and larger than the fourth length, the hook-up region includes a first contact electrode region and a second contact electrode region aligned in a second direction intersecting the first direction and the third direction, the first contact electrode region and the second contact electrode region each include a predetermined number of the contact electrodes arranged in the first direction; the predetermined number of contact electrodes included in the first contact electrode region have a length in the third direction greater than that of the contact electrodes provided on one side in the first direction; The predetermined number of contact electrodes included in the second contact electrode region have a length in the third direction greater on the other side in the first direction. Semiconductor memory device.

9. A substrate having a memory area and a hook-up area aligned in a first direction; a plurality of conductive layers aligned in a third direction intersecting a surface of the substrate and extending in the first direction across the memory region and the hook-up region; a semiconductor layer provided in the memory region, extending in the third direction, and facing the plurality of conductive layers; a charge storage film provided between the plurality of conductive layers and the semiconductor layer; a plurality of contact electrodes provided in the hook-up region, extending in the third direction, each having an outer circumferential surface surrounded by a portion of the plurality of conductive layers, each connected to one of the plurality of conductive layers; Equipped with the hook-up region includes a plurality of unit regions aligned in the first direction, the contact electrode is included in any one of the plurality of unit regions, The number of the contact electrodes included in the plurality of unit regions is m (m is an integer of 2 or more), a third length is an average value of lengths in the third direction of m contact electrodes having lengths in the third direction that are the first to mth largest among the plurality of contact electrodes; When the average value of the lengths in the third direction of m contact electrodes having the first to mth smallest lengths in the third direction among the plurality of contact electrodes is defined as a fourth length, an average value of lengths of the m contact electrodes in each unit region in the third direction is smaller than the third length and larger than the fourth length, the hook-up region includes a third contact electrode region; the third contact electrode region includes a fourth contact electrode, a fifth contact electrode, and a sixth contact electrode aligned in the first direction; the fifth contact electrode is provided between the fourth contact electrode and the sixth contact electrode, The length of the fifth contact electrode in the third direction is greater than or smaller than both of the length of the fourth contact electrode in the third direction and the length of the sixth contact electrode in the third direction. Semiconductor memory device.

Images