Semiconductor Device

Abstract

To improve the reliability of a semiconductor device.SOLUTION: Some of the multiple through vias TSV formed in the non-transistor region NTR are floating vias FV with floating potential.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and for example, to a technique that is effective when applied to a semiconductor device having a through via. [Background technology]

[0002] Non-Patent Document 1 describes a technique relating to plasma charge-up. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Kobe Steel Technical Report / Vol.52 No.2 (Sep. 2002) Summary of the Invention [Problem to be solved by the invention]

[0004] Semiconductor devices for artificial intelligence and data centers are equipped with neural networks such as large-scale product-sum circuits, and are required to process large amounts of data in real time. In other words, semiconductor devices for artificial intelligence and data centers are required to be equipped with wideband, large-capacity memory devices due to the need to store and update large amounts of image data and to store and update large-capacity neural network weight data at high speed, and are also required to consume less power. For this reason, semiconductor devices in which semiconductor chips such as wideband memories are stacked three-dimensionally via through vias are being considered.

[0005] However, when forming a through via for stacking semiconductor chips in a semiconductor chip, destruction of the through via caused by plasma charge-up has become a problem. If such destruction of the through via occurs, it will cause a defect in the semiconductor chip, leading to a decrease in reliability of the semiconductor device and a decrease in manufacturing yield. Therefore, in order to improve the reliability and manufacturing yield of the semiconductor device, it is desired to suppress destruction of the through via caused by plasma charge-up. [Means for solving the problem]

[0006] In one embodiment, some of the through vias formed in the non-transistor region are through vias at a floating potential. Effect of the Invention

[0007] According to one embodiment, the reliability of the semiconductor device can be improved. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view showing a schematic configuration of a semiconductor device. [Diagram 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Diagram 3] 1A and 1B are diagrams illustrating an example of a mechanism by which a through via is destroyed due to plasma charge-up that occurs when a through hole is formed. [Figure 4] 1 is a photograph showing a through hole in which dielectric breakdown has occurred. [Diagram 5] 1A and 1B are diagrams illustrating a state in which a short circuit defect occurs in a through via; [Figure 6] FIG. 1 is a diagram illustrating a related art. [Figure 7] FIG. 1 is a diagram illustrating an "active via" and a "floating via". [Figure 8] FIG. 13 is a diagram for explaining a qualitative mechanism by which a "floating via" is more susceptible to dielectric breakdown due to plasma charge-up than an "active via." [Figure 9] FIG. 2 is a diagram for explaining locations where spatial non-uniformity of plasma occurs. [Figure 10] 1 is a diagram showing a schematic view of the vicinity of a boundary region between a transistor region and a non-transistor region formed in a base chip; [Figure 11] FIG. 11 is a cross-sectional view taken along line AA in FIG. [Figure 12] 1 is a diagram showing a schematic view of the vicinity of a boundary region between a transistor region and a non-transistor region formed in a base chip; [Figure 13] FIG. 13 is a cross-sectional view taken along line AA in FIG. 12. [Figure 14] 10A and 10B are diagrams for explaining why a floating via arranged in a convex portion of a boundary line is more likely to cause dielectric breakdown; [Figure 15] 3 is a diagram showing a schematic view of the vicinity of a first boundary region between a first transistor region and a non-transistor region and the vicinity of a second boundary region between a second transistor region and a non-transistor region formed in a base chip. FIG. [Figure 16] FIG. 16 is a cross-sectional view taken along line AA in FIG. 15. [Figure 17] FIG. 13 is a diagram for explaining an application example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] In the following embodiments, for convenience, when necessary, the embodiments will be divided into multiple sections or embodiments, but unless otherwise expressly stated, they are not unrelated to each other and one may be a partial or complete variation, detail, supplementary explanation, etc. of the other.

[0010] In addition, in the following embodiments, when referring to the number of elements (including the number, numerical values, quantities, ranges, etc.), unless specifically stated or clearly limited to a specific number in principle, the number is not limited to that specific number and may be more than or less than a specific number.

[0011] Furthermore, in the following embodiments, the components (including element steps, etc.) are not necessarily essential unless specifically stated otherwise or considered to be clearly essential in principle.

[0012] Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of components, etc., it is intended to include those that are substantially similar or similar to those shapes, etc., unless otherwise specified or considered to be obviously different in principle. The same applies to the above numerical values ​​and ranges.

[0013] In addition, in all the drawings for explaining the embodiments, the same members are generally designated by the same reference numerals, and the repeated explanations thereof will be omitted. In addition, hatching may be applied even to plan views in order to make the drawings easier to understand.

[0014] <Configuration of Semiconductor Device> The technical idea of ​​this embodiment is applied to a semiconductor device that includes a central processing unit (CPU) composed of a logic IC and also includes a wideband, large-capacity memory device, such as a semiconductor device for artificial intelligence or data center use.

[0015] FIG. 1 is a plan view showing a schematic configuration of a semiconductor device.

[0016] 1, the semiconductor device 1 has, for example, a rectangular wiring board 10. A semiconductor chip 11 having a central processing unit composed of a logic IC and a stacked chip structure 12 in which a plurality of memory chips are stacked three-dimensionally are mounted on the wiring board 10. The semiconductor device 1 will be put to practical use as a high-performance memory product for next-generation network systems and artificial intelligence / data center accelerators.

[0017] FIG. 2 is a cross-sectional view taken along line AA in FIG.

[0018] In FIG. 2, when attention is paid to the laminated chip structure 12, the laminated chip structure 12 is composed of a base chip 13 arranged in the bottom layer and a plurality of memory chips 14 arranged in a stack on the base chip 13. In this way, the semiconductor device 1 has the laminated chip structure 12 in order to realize a large-capacity memory device. And, each chip constituting the laminated chip structure 12 is electrically connected via a through via TSV. That is, a through via TSV is formed in each chip of the laminated chip structure 12, and the circuits formed in each chip are electrically connected via the through via TSV. As a result, according to the semiconductor device 1, a three-dimensional memory device is realized by the laminated chip structure 12. According to the semiconductor device 1 having such a laminated chip structure 12, the advantage that a large-capacity memory device can be mounted without increasing the planar size of the semiconductor device 1 is obtained.

[0019] In the base chip 13 arranged in the bottom layer of the laminated chip structure 12, not only the integrated circuit formed in the base chip 13 itself, the first power supply wiring for supplying the first power supply potential to the integrated circuit, and the ground wiring for supplying the ground potential, but also the second power supply wiring for supplying the second power supply potential to the integrated circuit formed in the laminated memory chip 14 are formed. This is because the base chip 13 is arranged in the bottom layer of the laminated chip structure 12, and the second power supply potential is supplied to the memory chip 14 arranged above via the base chip 13. That is, the second power supply wiring formed in the base chip 13 is connected to the through via TSV formed in the base chip 13, and the second power supply potential is supplied to the integrated circuit formed in the memory chip 14 through the through via TSV. Furthermore, the memory chip 14 also has a through via TSV formed therein, and the memory chips 14 are electrically connected to each other through the through via TSV. Therefore, the through via TSV is essential for electrically connecting each chip constituting the laminated chip structure 12, and improving the reliability of the through via TSV is very important from the viewpoint of improving the reliability of the semiconductor device 1 including the laminated chip structure 12.

[0020] In particular, from the viewpoint of improving the manufacturing yield of the semiconductor device 1, it is important to improve the reliability of the through-via TSV formed in the base chip 13. This is because, in the semiconductor device 1, a plurality of memory chips 14 are mounted on the base chip 13 to manufacture the stacked chip structure 12. For this reason, if the manufacturing yield of the base chip 13 decreases, a plurality of good memory chips 14 mounted on the defective base chip 13 will also be wasted, resulting in a significant increase in manufacturing costs.

[0021] For this reason, the technical idea regarding the through-via TSV will be described, focusing particularly on the base chip 13. However, the technical idea in this embodiment is not limited to the through-via TSV formed in the base chip 13, and can be widely applied to the through-via TSV formed in the memory chip 14, for example.

[0022] <Room for improvement that impacts through-via reliability> Next, room for improvement that affects the reliability of the through via will be described. In particular, room for improvement that becomes apparent when forming a through hole will be described, focusing on plasma charge-up that occurs when forming a through hole as a phenomenon that affects the reliability of the through via.

[0023] 3 is a diagram for explaining an example of the mechanism by which a through via is destroyed by plasma charge-up that occurs when a through hole is formed. In this specification, the final form in which a conductive material is embedded in a through hole is called a "through via" to be distinguished from a "through hole."

[0024] In Fig. 3, for example, a diffusion layer 101 is formed on the front surface side (lower part in Fig. 3) of a substrate 100 made of silicon, and a silicon oxide film 102 serving as an interlayer insulating layer is also formed. Meanwhile, a silicon nitride film 103 is formed on the back surface side (upper part in Fig. 3) of the substrate 100. A through hole OP is formed in such a substrate 100.

[0025] The through hole OP is formed by using, for example, photolithography and etching techniques. Specifically, a resist film is applied to the back side of the substrate 100, and then the resist film is subjected to exposure and development processing to pattern the resist film. Then, the substrate 100 is etched using the patterned resist film as a mask. This forms the through hole OP in the substrate 100. After that, the patterned resist film is removed. This process of removing the resist film is called an ashing process.

[0026] Here, for example, as shown in FIG. 3, if the aspect ratio of the through hole OP is high, the difference in spatial momentum between electrons and ions (positive ions) makes it easier for electrons to attach to the upper periphery of the through hole OP, and the inflow of electrons into the through hole OP is hindered. Meanwhile, positive ions and radicals are selectively accumulated on the bottom and side surfaces of the through hole OP. In particular, in the ashing process for removing the resist film, the product (polymer) generated by the decomposition of the resist film reattaches to the inner wall, and thus positive ions and radicals are easily captured on the inner wall of the through hole OP. As a result, the equilibrium state of electrons and ions is lost around the through hole OP, inducing plasma charge-up. This phenomenon is called the "electron shading effect."

[0027] When such an "electron shading effect" occurs, a high electric field (see the arrow in FIG. 3) is generated between the positive ions accumulated inside the through hole OP and the electrons attached to the upper periphery of the through hole OP. Then, on the inner wall of the through hole OP, a dielectric breakdown occurs due to the high electric field caused by the plasma charge-up. For example, FIG. 4(a) and FIG. 4(b) are photographs showing a through hole in which a dielectric breakdown has occurred due to the plasma charge-up.

[0028] If a conductive material is filled into the through hole OP where dielectric breakdown has occurred to form a through via, a short circuit defect will occur at the point where dielectric breakdown has occurred.

[0029] Specifically, FIG. 5 is a diagram showing a schematic diagram of a state in which a short circuit defect occurs in a through via.

[0030] FIG. 5 illustrates the power supply wiring VDDM1 and the ground wiring VSS1 formed on the base chip, as well as the power supply wiring VDDM2 and the ground wiring VSS2 formed on the memory chip mounted on the base chip.

[0031] The power supply wiring VDDM1 formed on the base chip is a wiring for supplying a second power supply potential to the circuit formed on the memory chip, and is electrically connected to the power supply wiring VDDM2 formed on the memory chip by a through via TSV1.

[0032] Moreover, a ground wiring VSS1 formed on the base chip is a wiring that supplies a ground potential, and is electrically connected to a ground wiring VSS2 formed on the memory chip by a through via TSV2.

[0033] In addition to the power supply wiring VDDM1 and the ground wiring VSS1, the base chip is formed with a power supply wiring VDDL for supplying a first power supply potential different from the second power supply potential to a circuit formed in the base chip itself.

[0034] 5, for example, it is assumed that a dielectric breakdown due to plasma charge-up occurs in the through via TSV1 connecting the power supply wiring VDDM1 formed in the base chip and the power supply wiring VDDM2 formed in the memory chip. In this case, at the point where the dielectric breakdown occurs, a short circuit occurs between the substrate (ground potential) around the through via TSV1 and the second power supply potential applied to the internal conductor of the through via TSV1. As a result, the circuit formed in the memory chip is destroyed.

[0035] On the other hand, for example, assume that dielectric breakdown due to plasma charge-up occurs in the through via TSV2 connecting the ground wiring VSS1 formed on the base chip and the ground wiring VSS2 formed on the memory chip. In this case, the substrate (ground potential) around the through via TSV2 and the internal conductor of the through via TSV2 become conductive at the point where dielectric breakdown occurs. However, since the potential of the substrate around the through via TSV2 and the potential of the internal conductor of the through via TSV2 are both at ground potential, no short circuit failure occurs.

[0036] Therefore, in the through via TSV2 to which the ground potential is applied, even if a dielectric breakdown occurs when the through hole OP is formed, a short circuit does not occur at the location of the dielectric breakdown. In contrast, in the through via TSV1 to which a potential different from the ground potential is applied, if a dielectric breakdown occurs when the through hole OP is formed, a short circuit occurs between the substrate (ground potential) around the through via TSV2 and the potential applied to the internal conductor of the through via TSV2. This shows that it is necessary to suppress dielectric breakdown, particularly in the through via TSV2 to which a potential different from the ground potential is applied.

[0037] As described above, for example, when plasma charge-up occurs during the formation of a through hole due to the "electron shading effect," dielectric breakdown occurs on the inner wall of the through hole, which may result in a short circuit defect through the through via in which an internal conductor is embedded in the through hole. For this reason, for example, in order to improve the manufacturing yield of the base chip, it is necessary to improve the reliability of the through via, and specifically, it is important to prevent dielectric breakdown of the through via formed in the base chip. In this regard, the following related technology is available to reduce dielectric breakdown of the through via caused by plasma charge-up.

[0038] <Description of Related Art> The term "related art" as used herein refers to art that is not publicly known, but has problems that the inventors have found, and is a prerequisite for the present invention.

[0039] FIG. 6 is a diagram illustrating a related technique.

[0040] 6, a protection circuit PC is provided between the power supply wiring VDDM1 and the ground wiring VSS1 formed on the base chip. This protection circuit PC has a function of leaking the accumulation of electric charge generated when forming the through hole OP. As a result, in the related technology having the protection circuit PC, plasma charge-up in the through hole OP can be suppressed, and therefore, dielectric breakdown in the through hole OP can be prevented. As a result, according to the related technology, short-circuit failure of the through via TSV1 caused by plasma charge-up can be suppressed.

[0041] <Room for improvement in related technologies> However, when the protection circuit PC is mounted on the base chip, the chip area of ​​the base chip increases. In particular, the protection circuit PC mounted on the base chip is a protection circuit for a memory chip dedicated power supply used in a circuit formed on the memory chip. That is, as shown in FIG. 6, the protection circuit PC is provided to prevent a short circuit defect in the through via TSV1 connected to the power supply wiring VDDM1 that supplies the second power supply potential to the memory chip. This means that an extra protection circuit PC that is not originally intended to protect the circuit itself formed on the base chip must be formed on the base chip. That is, according to the related technology, a protection circuit PC that is not directly related to the base chip must be provided, and an increase in the chip area of ​​the base chip becomes apparent. This is a point where there is room for improvement in the related technology.

[0042] On the other hand, if the protection circuit PC is not provided in the base chip, a short circuit defect of the through via TSV1 caused by plasma charge-up will become apparent.

[0043] Therefore, in this embodiment, a measure is taken to prevent a short circuit defect in the through via TSV1 connected to the power supply wiring VDDM1 that supplies the second power supply potential to the memory chip without providing a protection circuit PC. The technical idea of ​​this embodiment with this measure is described below.

[0044] <Basic Concept of the Embodiment> The basic idea of ​​this embodiment is to protect other through vias connected to the circuit from dielectric breakdown by intentionally providing a through via that causes dielectric breakdown due to plasma charge-up. That is, the basic idea of ​​this embodiment is to prevent dielectric breakdown of other through vias connected to the circuit by intentionally providing a through via that does not cause a short circuit failure of the circuit even if dielectric breakdown occurs and causing dielectric breakdown due to plasma charge-up in this through via. According to this basic idea, even if plasma charge-up occurs, dielectric breakdown is suppressed in the through via connected to the circuit, and as a result, short circuit failure in the through via connected to the circuit is prevented. As a result, according to the basic idea, the reliability of the semiconductor device including the through via can be improved.

[0045] Specifically, in the basic concept, in addition to the through via connected to the circuit, a through via that is not connected to the circuit and has a floating potential is intentionally provided, and dielectric breakdown occurs in the through via at the floating potential. As a result, in the basic concept, intentional dielectric breakdown in the through via at the floating potential causes binding of electrons and positive ions. This means that the charge imbalance is eliminated and the high electric field that causes dielectric breakdown is alleviated, and this makes it possible to protect other through vias connected to the circuit from dielectric breakdown. Even if dielectric breakdown occurs in the through via at the floating potential that is not connected to the circuit, a short circuit does not occur in the circuit, and as a result, the circuit formed in the semiconductor device can be protected. For example, even if dielectric breakdown occurs in the through via at the floating potential, the through via at the floating potential is merely electrically connected to the substrate (ground potential) surrounding the through via, so that a short circuit does not occur between a potential different from the ground potential and the ground potential. Therefore, according to the basic concept of this embodiment, even if a protection circuit is not provided as in the related art described above, a short circuit in the circuit formed in the semiconductor device can be effectively suppressed. In other words, this basic concept can be said to be an excellent technical concept in that it can suppress short-circuit defects caused by dielectric breakdown of the through vias without increasing the chip size of the base chip.

[0046] Here, the definition of a through via in this specification will be explained.

[0047] First, the through vias in this specification are classified into "active vias", "ground vias" and "floating vias". "Active vias" refers to through vias that are connected to a circuit in the completed state of the semiconductor device, and is used as a general term including, for example, vias configured to receive a power supply potential and vias configured to receive a ground potential. However, even if the potential is floating in the uncompleted state of the semiconductor device, a through via that will be connected to a circuit in the final completed state of the semiconductor device is included in the "active vias". In particular, the "active vias" that are configured to receive a ground potential are called "ground vias".

[0048] On the other hand, a "floating via" refers to a through via that is not connected to a circuit even in the completed state of the semiconductor device and is configured to have a floating potential. Furthermore, a "floating via" that becomes conductive to the surrounding substrate (ground potential) as a result of dielectric breakdown is called a "damaged via" and is distinguished from a "ground via."

[0049] Based on such a definition, the basic idea of ​​this embodiment can be expressed as an idea of ​​protecting other "active vias" connected to a circuit from dielectric breakdown by providing a "floating via" that intentionally causes dielectric breakdown due to plasma charge-up. In a semiconductor device in which the basic idea of ​​this embodiment is adopted, at least one of "floating vias" and "damage vias" is included among the multiple through vias. That is, in a semiconductor device in which the basic idea is embodied, any of the following is realized: all of the "floating vias" undergo dielectric breakdown and all of the "floating vias" become "damage vias", some of the "floating vias" undergo dielectric breakdown and "floating vias" and "damage vias" coexist, and all of the "floating vias" remain without dielectric breakdown.

[0050] The basic concept of this embodiment will be described below with reference to the drawings.

[0051] FIG. 7 is a diagram showing a schematic diagram of an "active via" and a "floating via".

[0052] In FIG. 7, the power supply wiring VDDM1 formed on the base chip and the power supply wiring VDDM2 formed on the memory chip are connected by the through via TSV1. At this time, the power supply wiring VDDM2 formed on the memory chip has a function of supplying a second power supply potential to an integrated circuit (such as a memory circuit) formed on the memory chip, so the power supply wiring VDDM2 is connected to the circuit. As a result, the through via TSV1 connecting the power supply wiring VDDM1 and the power supply wiring VDDM2 is also connected to the circuit. Therefore, the through via TSV1 connecting the power supply wiring VDDM1 and the power supply wiring VDDM2 becomes an "active via". Similarly, the ground wiring VSS1 formed on the base chip and the ground wiring VSS2 formed on the memory chip are connected by the through via TSV2. And, since the ground wiring VSS1 and the ground wiring VSS2 have a function of supplying a ground potential to the integrated circuit, the through via TSV2 connecting the ground wiring VSS1 and the ground wiring VSS2 is also connected to the circuit. As a result, the through via TSV2 becomes an "active via", and in particular, since the ground potential is applied to the through via TSV2, the through via TSV2 becomes a "ground via" of the "active via".

[0053] 7, the through via TSV3 is not formed in the circuit formed in the base chip or in the memory chip, and is at a floating potential, and is therefore a "floating via." Here, the basic idea of ​​this embodiment is to provide a "floating via" that is intentionally subjected to dielectric breakdown in order to protect the "active via" from dielectric breakdown caused by plasma charge-up, but in order to put this idea into practice, the "floating via" needs to be more susceptible to dielectric breakdown than the "active via."

[0054] In this regard, in order for a "floating via" to be more susceptible to dielectric breakdown than an "active via", it is important that the "floating via" is not connected to a circuit and is at a floating potential not only in the unfinished state of the semiconductor device but also in the finished state of the semiconductor device. In other words, the "floating via" is more susceptible to dielectric breakdown than an "active via" precisely because it is at a floating potential.

[0055] Below, a qualitative mechanism by which a "floating via" is more susceptible to dielectric breakdown due to plasma charge-up than an "active via" will be described.

[0056] FIG. 8 is a diagram for explaining a qualitative mechanism by which a "floating via" is more susceptible to dielectric breakdown due to plasma charge-up than an "active via."

[0057] 8 shows a through hole OP1 of the active via AV and a through hole OP2 of the floating via FV. Since the active via AV is electrically connected to the circuit, it is connected to, for example, a long-extending wiring WL as shown in FIG. 8. On the other hand, the floating via FV is not electrically connected to the circuit, so it is not connected to a long-extending wiring. Due to this difference, the through hole OP2 of the floating via FV is more susceptible to dielectric breakdown than the through hole OP1 of the active via AV.

[0058] For example, as shown in Fig. 8, when forming a through hole OP1 of an active via AV, positive ions accumulate on the inner wall of the through hole OP1 due to the "electron shading effect", but since the through hole OP1 of the active via AV is connected to the long extending wiring WL, the positive ions do not localize on the inner wall of the through hole OP1, but also diffuse to the wiring WL. As a result, the density of positive ions accumulating on the inner wall of the through hole OP1 of the active via AV becomes smaller. This means that a high electric field is unlikely to be generated inside the through hole OP1, so that the through hole OP1 of the active via AV is unlikely to suffer from dielectric breakdown due to plasma charge-up.

[0059] In contrast, positive ions also accumulate on the inner wall of the floating via FV due to the "electron shading effect." Here, the through hole OP2 of the floating via FV is not electrically connected to the circuit. In other words, the through hole OP2 of the floating via FV extends long or is not connected to the wiring. For this reason, the positive ions accumulated on the inner wall of the through hole OP2 of the floating via FV cannot diffuse and remain on the inner wall of the through hole OP2. As a result, the density of positive ions in the through hole OP2 of the floating via FV increases. This means that a high electric field is likely to be generated inside the through hole OP2, so that the through hole OP2 of the floating via FV is more likely to cause dielectric breakdown due to plasma charge-up. Due to the above qualitative mechanism, the through hole OP2 of the floating via FV is more likely to cause dielectric breakdown due to plasma charge-up than the through hole OP1 of the active via AV.

[0060] In this way, according to the basic concept of this embodiment, by providing a "floating via" that intentionally causes dielectric breakdown due to plasma charge-up, other "active vias" connected to the circuit can be protected from dielectric breakdown.

[0061] In particular, the "floating via" provided as a basic concept has two important technical significances. The first technical significance is that, because it is at a floating potential, it is not connected to the wiring for connecting to the circuit, and as a result, the electric field density of positive ions is higher in the "floating via" than in the "active via", making it more susceptible to dielectric breakdown than the "active via". The second technical significance is that even if dielectric breakdown occurs in the "floating via", a short circuit between different potentials does not occur.

[0062] In consideration of these two technical significances of the "floating via", the basic concept is to provide a "floating via" for intentionally causing dielectric breakdown, thereby protecting the "active via" which is at risk of short circuit failure if dielectric breakdown occurs. As a result, according to the basic concept, it is possible to protect the circuit formed in the semiconductor device from short circuit failure caused by plasma charge-up, thereby improving the reliability of the semiconductor device.

[0063] <New findings discovered by the present inventors> Next, the new findings of the present inventors will be described.

[0064] One of the causes of plasma charge-up is the "electron shading effect," but another known cause is the spatial non-uniformity of the plasma. However, at present, no research has been conducted into the locations where the spatial non-uniformity of the plasma becomes apparent. In this regard, the present inventors have conducted extensive research and have found the following new findings regarding the spatial non-uniformity of the plasma, which will be described below.

[0065] FIG. 9 is a diagram for explaining locations where spatial non-uniformity of plasma occurs.

[0066] Fig. 9 shows, for example, a plan view of an enlarged portion of a base chip. In Fig. 9, a transistor region TR is a region in which an integrated circuit including a field effect transistor is formed. Specifically, active diffusion layers that become the source and drain regions of the field effect transistor are formed in the transistor region TR.

[0067] On the other hand, the non-transistor region NTR is a region in which an integrated circuit including, for example, a field effect transistor is not formed. Since no field effect transistor is formed in this non-transistor region NTR, it is not necessary to form an active diffusion layer that serves as a source region or a drain region. However, from the viewpoint of improving the microfabrication accuracy of the entire base chip, a diffusion layer is also formed in this non-transistor region NTR. However, since the diffusion layer formed in the non-transistor region NTR does not function as a source region or a drain region, it is called a non-active diffusion layer. Furthermore, a plurality of through-vias TSV are formed in the non-transistor region NTR.

[0068] The present inventor has newly found that the spatial non-uniformity of plasma becomes apparent in the boundary region BR between the transistor region TR and the non-transistor region NTR as shown in FIG. 9. For example, the density of the active diffusion layer formed in the transistor region TR is different from the density of the non-active diffusion layer formed in the non-transistor region NTR, and the through via TSV is not formed in the transistor region TR. As a result, the density of the diffusion layer and the density of the through via TSV differ in the transistor region TR and the non-transistor region NTR. The present inventor has newly found that the difference between the density of the diffusion layer and the density of the through via TSV causes non-uniformity between the plasma charge density accumulated in the transistor region TR and the plasma charge density accumulated in the non-transistor region NTR. That is, in the boundary region BR between the transistor region TR and the non-transistor region NTR, the spatial non-uniformity of plasma caused by the difference between the density of the diffusion layer and the density of the through via TSV becomes apparent, and as a result, a high electric field based on the spatial non-uniformity of plasma is generated in the boundary region BR. As a result, the through-via TSV located closest to the boundary region BR is more susceptible to dielectric breakdown due to not only the "electron shading effect" but also the spatial non-uniformity of the plasma.

[0069] By combining this knowledge with the basic concept of the present embodiment, the following specific embodiment has been realized, and this specific embodiment will be described below.

[0070] <Specific Example 1> FIG. 10 is a diagram showing the vicinity of the boundary region between the transistor region TR and the non-transistor region NTR formed in the base chip. The base chip is, for example, a semiconductor chip arranged in the lowest layer of the semiconductor chips constituting the stacked structure in a semiconductor device having a stacked structure in which a plurality of semiconductor chips are stacked. In such a base chip, as shown in FIG. 10, there are a transistor region TR in which a field effect transistor is formed and a non-transistor region NTR in which a field effect transistor is not formed. As shown in FIG. 10, no through vias are formed in the transistor region TR, while a plurality of through vias TSV are formed in the non-transistor region NTR. Here, the plurality of through vias TSV formed in the non-transistor region NTR include active vias AV and floating vias FV. At this time, at least some of the through vias among the plurality of through vias TSV arranged in the position closest to the boundary line BL between the transistor region TR and the non-transistor region NTR in a plan view are floating vias FV.

[0071] Next, FIG. 11 is a cross-sectional view taken along line AA in FIG.

[0072] 11, on the front surface side of a semiconductor substrate 200 having a front surface 200a and a back surface 200b, a diffusion layer is formed in both the transistor region TR and the non-transistor region NTR. The diffusion layer formed in the transistor region TR is an active diffusion layer 201 that functions as a source region or a drain region of a field effect transistor. On the other hand, the diffusion layer formed in the non-transistor region NTR is a non-active diffusion layer 202 that does not function as a source region or a drain region. Here, the arrangement density of the active diffusion layer 201 formed in the transistor region TR is higher than the arrangement density of the non-active diffusion layer 202 formed in the non-transistor region NTR.

[0073] The active diffusion layer 201 is connected to the first layer wiring L1 and the second layer wiring L2, and in the transistor region TR, an integrated circuit is formed by the electrical connection of the field effect transistor, the first layer wiring L1, and the second layer 4 wiring L2. That is, an integrated circuit is formed in the transistor region TR. On the other hand, in the non-transistor region NTR, active vias AV and floating vias FV are formed, and the active vias AV are connected to, for example, the first layer wiring L1 and the second layer wiring L2. The active vias AV are electrically connected to the integrated circuit formed in the transistor region TR through the first layer wiring L1 and the second layer wiring L2. In contrast, the floating vias FV are not electrically connected to the first layer wiring L1 and the second layer wiring L2. That is, the floating vias FV are not connected to the circuit and are at a floating potential.

[0074] Although not shown, for example, a memory chip is mounted on the base chip configured in this way. The active via AV shown in Fig. 11 is electrically connected to the memory chip. Specifically, the active via AV functions as a supply path for power supplied to a circuit formed in the memory chip.

[0075] In the base chip of the present embodiment, a protection circuit configured to suppress the destruction of the active via AV caused by plasma charge-up is not formed. This is because, in the present embodiment, a floating via FV having a function of suppressing the destruction of the active via AV caused by plasma charge-up is provided. In particular, the floating via FV is disposed at a position where destruction caused by plasma charge-up is more likely to occur than in the active via AV. Specifically, as shown in FIG. 11, at least one of the multiple floating vias FV is disposed at a position closest to the boundary line BL between the transistor region TR and the non-transistor region NTR in a plan view.

[0076] <<Characteristics of Specific Example 1>> Next, the features of the first specific embodiment will be described.

[0077] A feature of the specific embodiment 1 is that, for example, as shown in FIG. 10 and FIG. 11, at least one of the plurality of through vias TSV arranged at the position closest to the boundary line BL between the transistor region TR and the non-transistor region NTR is a floating via FV. As a result, according to the specific embodiment 1, the active via AV formed in the non-transistor region NTR can be protected from dielectric breakdown caused by plasma charge-up. This is because, in the vicinity of the boundary line BL between the transistor region TR and the non-transistor region NTR, not only the "electron shading effect" but also the spatial non-uniformity of the plasma caused by the difference between the arrangement density of the diffusion layer and the arrangement density of the through via TSV becomes apparent, resulting in the generation of a high electric field caused by plasma charge-up. In other words, by providing a floating via FV that is more likely to cause dielectric breakdown than the active via AV at the position closest to the boundary line BL where such a high electric field occurs, it is possible to intentionally cause dielectric breakdown in the floating via FV, and as a result, it is possible to prevent dielectric breakdown in the other active vias AV. In this case, even if the floating via FV undergoes dielectric breakdown, the floating via FV is not connected to the circuit, so that it does not cause a short circuit failure of the circuit, and therefore the reliability of the semiconductor device can be ensured.

[0078] From the above, according to specific embodiment 1, a floating via FV for intentionally causing dielectric breakdown is provided near the boundary line BL between the transistor region TR and the non-transistor region NTR, where a high electric field is most likely to occur due to the "electron shading effect" and spatial non-uniformity of the plasma, thereby protecting the active via AV, which is likely to cause a short circuit if dielectric breakdown occurs. As a result, according to specific embodiment 1, it is possible to protect the circuit formed in the semiconductor device from a short circuit caused by plasma charge-up by intentional dielectric breakdown in the floating via FV, which is not likely to cause a short circuit even if dielectric breakdown occurs. In other words, according to the specific embodiment, it is possible to improve the reliability of the semiconductor device.

[0079] <Specific Example 2> Next, specific embodiment 2 will be described.

[0080] Fig. 12 is a diagram showing a schematic view of the vicinity of the boundary region between the transistor region TR and the non-transistor region NTR formed in the base chip. Fig. 13 is a cross-sectional view taken along the line AA in Fig. 12. In Fig. 12, the boundary line BL between the transistor region TR and the non-transistor region NTR includes a convex portion 300 that protrudes from the non-transistor region NTR to the transistor region TR in a plan view, and a floating via FV is formed in this convex portion 300.

[0081] As a result, it is possible to intentionally cause dielectric breakdown in the floating via FV according to specific embodiment 2. The reason for this will be explained below.

[0082] FIG. 14 is a diagram for explaining the reason why the floating via FV arranged at the convex portion 300 of the boundary line BL is likely to cause dielectric breakdown. In FIG. 14, a high electric field based on the spatial nonuniformity of plasma is applied to the floating via FV arranged at the convex portion 300 of the boundary line BL from the direction shown by the four arrows in FIG. 14. As a result, the floating via FV arranged at the convex portion 300 of the boundary line BL is more likely to cause dielectric breakdown than the through via TSV arranged at other positions. Therefore, according to the specific embodiment 2, the floating via FV arranged at the convex portion 300 of the boundary line BL is more likely to cause dielectric breakdown, so that the active via AV arranged at other positions can be effectively protected from dielectric breakdown caused by plasma charge-up. In this way, in the specific embodiment 2, by devising the shape of the boundary line BL, a place where a high electric field is effectively generated is created, and by arranging the floating via FV at this place, dielectric breakdown can be caused at the floating via FV with a high probability. As a result, according to the specific embodiment 2, it is possible to protect the circuit formed in the semiconductor device from short-circuit defects caused by plasma charge-up, thereby improving the reliability of the semiconductor device.

[0083] <Specific Example 3> Next, specific embodiment 3 will be described.

[0084] FIG. 15 is a diagram showing the vicinity of a first boundary region between the first transistor region TR1 and the non-transistor region NTR formed in the base chip, and the vicinity of a second boundary region between the second transistor region TR2 and the non-transistor region NTR. FIG. 16 is a cross-sectional view taken along the line AA in FIG. 15. In FIG. 15, the boundary line BL1 between the first transistor region TR1 and the non-transistor region NTR includes a convex portion 300 that protrudes from the non-transistor region NTR to the first transistor region TR1 in a plan view, and a floating via FV is formed in this convex portion 300. On the other hand, the boundary line BL2 between the second transistor region TR2 and the non-transistor region NTR does not have a convex portion. In addition to the floating via FV, an active via AV and an active via AV2 are provided in the non-transistor region NTR. The active AV is a through via that is connected to a circuit but is not electrically connected to a protection circuit that protects the active via AV from plasma charge-up. On the other hand, the active via AV2 is a through via that is electrically connected to a protection circuit that protects the active via AV2 from plasma charge-up. Here, the active via AV2 connected to the protection circuit is disposed at a position closest to at least the boundary line BL2 between the second transistor region TR2 and the non-transistor region NTR. For example, as shown in Fig. 16, the active via AV2 is electrically connected to the protection circuit included in the integrated circuit formed in the first transistor region TR1 through the first layer wiring L1, the second layer wiring L2, and the third layer wiring L3.

[0085] According to the specific embodiment 3 configured as above, the following advantages can be obtained. That is, as shown in FIG. 15, since the floating via FV is formed in the convex portion 300 of the boundary line BL1 where a high electric field caused by plasma charge-up occurs, it is possible to intentionally cause a dielectric breakdown in the floating via FV. This makes it possible to protect the active via AV formed in the non-transistor region NTR from a dielectric breakdown. Furthermore, in the specific embodiment 3, since the active via AV2 connected to the protection circuit is disposed in the vicinity of the boundary line BL2 where a high electric field caused by plasma charge-up occurs, it is possible to prevent a dielectric breakdown in the active via AV2 even if a high electric field caused by plasma charge-up occurs in the vicinity of the boundary line BL2.

[0086] In particular, in the specific embodiment 3, since it is not necessary to provide the through via TSV connected to the protection circuit both near the boundary line BL1 and near the boundary line BL2, the number of protection circuits formed in the base chip can be reduced. Therefore, according to the specific embodiment 3, it is possible to protect the through via TSV from dielectric breakdown caused by plasma charge-up without increasing the chip size of the base chip (first advantage). In addition, in the specific embodiment 3, since it is not necessary to provide the convex portion 300 both near the boundary line BL1 and near the boundary line BL2, it is possible to secure the occupied area of ​​the transistor region (first transistor region TR1 and second transistor region TR2), and it is possible to obtain the advantage that it is not necessary to provide more floating vias FV than necessary to intentionally cause dielectric breakdown (second advantage). Therefore, according to the specific embodiment 3, it is possible to obtain both the first and second advantages described above by using the floating via FV and the active via AV2 connected to the protection circuit.

[0087] <Application Examples> In the embodiment, a floating via FV at a floating potential is provided in order to intentionally cause dielectric breakdown due to plasma charge-up. When dielectric breakdown occurs in this floating via FV, it becomes conductive to the substrate at ground potential through the location where dielectric breakdown occurred, and becomes a "damaged via."

[0088] Here, the "damaged via" itself does not cause short circuit failure in the integrated circuit, so it can be left as it is. However, it is possible that the reliability of the semiconductor device may decrease due to aging caused by temperature changes, for example, starting from this "damaged via". Therefore, in this application example, we will explain a method for reducing the potential for reliability decrease caused by the "damaged via".

[0089] FIG. 17 is a diagram for explaining the ingenuity in the application example.

[0090] In Fig. 17, the damaged via DV formed by dielectric breakdown in the floating via is connected to the rewiring (back surface wiring) RDL to which the ground potential is supplied. As a result, the dielectric breakdown point in the damaged via DV is repaired and covered by the rewiring RDL. As a result, according to the application example, the dielectric breakdown point in the damaged via DV is not exposed, so that the possibility of causing a decrease in the reliability of the semiconductor device can be reduced.

[0091] The invention made by the inventor has been specifically described above based on the embodiment thereof. However, it goes without saying that the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the invention. [Explanation of symbols]

[0092] 1 Semiconductor device 10 Wiring board 11 Semiconductor chips 12. Stacked chip structure 13 Base Chip 14 Memory chips 100 Substrates 101 Diffusion layer 102 Silicon oxide film 103 Silicon nitride film 200 Semiconductor Substrate 200a surface 200b back side 201 Active Diffusion Layer 202 Inactive Diffusion Layer 300 Convex part AV Active Via AV2 Active Via BL boundary line BL1 Border BL2 border BR boundary area DV Damaged Via FV Floating Via L1 1st layer wiring L2 2nd layer wiring L3 3rd layer wiring NTR Non-Transistor Region OP through hole OP1 through hole OP2 through hole PC protection circuit RDL rewiring TR Transistor area TR1 First transistor region TR2 Second transistor region TSV Through Via TSV1 Through Via TSV2 Through Via TSV3 Through Via VDDL Power supply wiring VDDM1 Power supply wiring VDDM2 power wiring VSS1 Ground wiring VSS2 ground wiring WL wiring

Claims

1. a first semiconductor chip having a first transistor region and a non-transistor region; a plurality of through vias formed in the non-transistor region; A semiconductor device comprising: The plurality of through vias include an active via electrically connected to the circuit; A damaged via at ground potential; 13. A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, at least a part of a plurality of through vias arranged at a position closest to a first boundary line between the first transistor region and the non-transistor region in a plan view is the damage via; The damage via is formed on a back surface of the first semiconductor chip, and is connected to a back surface wiring to which a ground potential is supplied.

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