Method and system for operating a bidirectional double-base bipolar junction transistor (B-TRAN)

Abstract

An example is a method of operating a bidirectional double-base bipolar junction transistor (B-TRAN). One example includes conducting a first load current from an upper terminal of a power module to an upper collector-emitter of the transistor, through the transistor, and from a lower collector-emitter of the power module to a lower terminal, and then, in response to assertion of a first shutoff signal, shutting off the first load current from the lower collector-emitter to the lower terminal by opening a lower main FET, thereby commutating a first shutoff current to the lower terminal through the lower base of the transistor and blocking current from the upper terminal to the lower terminal by the transistor.

Description

[Technical field]

[0001] This application claims priority to U.S. Provisional Application No. 63 / 123,704, filed December 10, 2020, which is incorporated herein by reference as if reproduced in full below. [Background technology]

[0002] A bidirectional double-base bipolar junction transistor (hereinafter B-TRAN) is a junction transistor constructed with a base and a collector-emitter on a first side of a bulk region and a separate, isolated base and collector-emitter on a second side of the bulk region opposite the first side. When properly set by an external driver, current can selectively flow through the B-TRAN in either direction, and thus the B-TRAN device is considered a bidirectional device. Based on the bidirectional nature, whether the collector-emitter is considered a collector (e.g., current flows into the B-TRAN) or an emitter (e.g., current flows out of the B-TRAN) depends on the polarity of the applied external voltage, and thus the direction of current through the B-TRAN. As an example, consider a current flowing through the B-TRAN device in a particular direction from the top collector-emitter to the bottom collector-emitter. In such a situation, the top collector-emitter acts as a collector and the bottom collector-emitter acts as an emitter. Summary of the Invention

[0003] At least one example is a method of operating a power module having a bidirectional double base bipolar junction transistor comprising conducting a first load current from an upper terminal of the power module to an upper collector-emitter of the transistor, through the transistor, and from a lower collector-emitter of the power module to a lower terminal, and then, in response to assertion of a first shutoff signal, shutting off the first load current from the lower collector-emitter to the lower terminal by opening a lower main FET, thereby diverting a first shutoff current through the lower base of the transistor to the lower terminal, and blocking current flow from the upper terminal to the lower terminal by the transistor.

[0004] In the example method, interrupting the first load current can further include interrupting the first load current using the lower main FET having a breakdown voltage of 100 volts or less, and blocking current can further include blocking at an applied voltage across the upper and lower terminals of 600 volts or more.

[0005] The example method may include, after blocking current from the upper terminal to the lower terminal, conducting a second load current from the lower terminal of the power module to the lower collector-emitter of the transistor, through the transistor, and from the upper collector-emitter to the upper terminal, and then blocking the second load current from the upper collector-emitter to the upper terminal by opening an upper main FET in response to assertion of a second blocking signal, thereby diverting a second shutoff current through the upper base to the upper terminal, and blocking current from the lower terminal to the upper terminal by the transistor. In the example method, blocking the second load current may further include blocking the second load current using the upper main FET having a breakdown voltage of 100 volts or less, and blocking current from the lower terminal to the upper terminal may further include blocking at an applied voltage across the lower terminal and the upper terminal of 600 volts or more.

[0006] Another example is a switch assembly having an upper terminal, a lower terminal, and an upper control input; a transistor defining an upper base, an upper collector-emitter, a lower base, and a lower collector-emitter; an upper main FET defining a first lead coupled to the upper terminal, a second lead coupled to the upper collector-emitter, and a gate; a lower main FET defining a first lead coupled to the lower collector-emitter, a second lead coupled to the lower terminal, and a gate; and a controller coupled to the upper control input, the gate of the upper main FET, and the gate of the lower main FET. For a first applied voltage across the upper terminal and the lower terminal, the controller may be configured to: assert the gate of the upper main FET to cause the upper main FET to conduct, configure the transistor for conduction from the upper collector-emitter to the lower collector-emitter, and assert the gate of the lower main FET to cause the lower main FET to conduct so that a first load current flows from the upper terminal to the lower terminal; detect a deassertion of the upper control input; and, in response to the deassertion of the upper control input, deassert the gate of the lower main FET to interrupt the first load current, thereby diverting a first shutoff current through the lower base to the lower terminal and configuring the transistor to prevent current flow from the upper terminal to the lower terminal.

[0007] In the example switch assembly, the transistor may have a breakdown voltage of 600 volts or greater, and the lower main FET may have a breakdown voltage of 100 volts or less.

[0008] In this example switch assembly, the breakdown voltage of the transistor may be approximately 1200 volts and the breakdown voltage of the lower main FET may be less than 80 volts.

[0009] The example switch assembly may further include a top base FET having a first lead coupled to the top base, a second lead coupled to the top terminal, and a gate, the top base FET conducting during a period when the first load current flows from the top terminal to the bottom terminal. When the controller configures the transistor to block current flow from the top terminal to the bottom terminal, the controller may be further configured to deassert the gate of the top base FET causing the top base to be electrically floating.

[0010] The example switch assembly may further include a lower control input coupled to the controller. For a second applied voltage across the upper and lower terminals, having an opposite polarity to the first applied voltage, the controller may be configured to: assert the gate of the lower main FET to cause the lower main FET to conduct, configure the transistor for conduction from the upper collector-emitter to the lower collector-emitter, and assert the gate of the upper main FET to cause the upper main FET to conduct so that a second load current flows from the lower terminal to the upper terminal, detect a deassertion of the lower control input, and in response to the deassertion of the lower control input, configure the transistor to deassert the gate of the upper main FET to interrupt the second load current, thereby diverting a second shutoff current through the upper base to the upper terminal and preventing current flow from the lower terminal to the upper terminal. The example switch assembly may further include a lower base FET having a first lead coupled to the lower base, a second lead coupled to the lower terminal, and a gate, the lower base FET conducting during a time period when the second load current flows from the lower terminal to the upper terminal. When the controller configures the transistor to block current flow from the lower collector-emitter to the upper collector-emitter, the controller may be further configured to deassert the gate of the lower base FET causing the lower base to be electrically floating. The breakdown voltage of the transistor may be greater than or equal to 600 volts, and the breakdown voltage of the lower main FET may be less than or equal to 100 volts.

[0011] Another example is a method of operating a bidirectional double-base bipolar junction transistor comprising: making the transistor conductive from the upper collector-emitter to the lower collector-emitter by supplying a current to the upper base of the transistor and electrically floating the lower base of the transistor, and then making the transistor non-conductive by electrically floating the upper base, electrically floating the lower collector-emitter, and directing a shutoff current through the lower base of the transistor.

[0012] In the example method, electrically floating the lower collector-emitter may further include rendering a lower main electrically controlled switch non-conductive, the lower main switch having a first lead coupled to the lower collector-emitter.

[0013] In the example method, making the transistor conductive may further include closing an upper main electrically controlled switch coupled between an upper terminal and the upper collector-emitter and closing a lower main electrically controlled switch coupled between a lower terminal and the lower collector-emitter. Making the transistor non-conductive may further include opening the upper main electrically controlled switch, directing the shut-off current to the upper collector-emitter through a diode associated with the upper main electrically controlled switch, and diverting the shut-off current from the lower collector-emitter to the lower base by opening the lower main electrically controlled switch. The method according to claim 14 .

[0014] In the example method, directing the shutoff current through the lower base can further include directing the current through a diode associated with an electrically controlled switch having a first lead coupled to the lower base.

[0015] In the example method, supplying a current to the upper base may further include at least one selected from the group consisting of: supplying a current to the upper base at a base voltage approximately the same as a collector voltage applied to the upper collector-emitter; and supplying a current to the upper base at the base voltage higher than the collector voltage. [Brief description of the drawings]

[0016] For a detailed description of example embodiments, reference is now made to the accompanying drawings. [Figure 1] 1 illustrates a cross-sectional elevation view of a B-TRAN in accordance with at least some embodiments. [Diagram 2] 1 illustrates an electrical diagram of a switch assembly having a model of a B-TRAN along with a driver circuit, in accordance with at least some embodiments. [Diagram 3] 1 illustrates an example switch assembly in which the B-TRAN is non-conducting, according to an example embodiment. [Figure 4] 1 illustrates an example switch assembly configured for diode conduction in accordance with at least some embodiments. [Diagram 5] 1 illustrates an example switch assembly configured for electrical conduction in accordance with at least some embodiments. [Figure 6] 1 shows an associated switch assembly configured for transistor turn-off. [Figure 7] 1 illustrates an example switch assembly configured for pre-turn-off in accordance with at least some embodiments. [Figure 8] 1 shows a partial electrical schematic, partial block diagram of a switch assembly according to at least some embodiments. [Figure 9] 1 illustrates a partial electrical schematic diagram of a switch assembly according to at least some embodiments. [Figure 10] 1 illustrates a method in accordance with at least some embodiments. [Figure 11]1 illustrates a plot of transient times for transitioning to a non-conducting state in accordance with at least some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] definition Various terms are used to refer to particular system components. Different companies may refer to components by different names, and this document does not intend to distinguish between components that differ in name but not function. In the following description and claims, the terms "including" and "having" are used in an open-ended manner and, therefore, should be interpreted to mean "including, but not limited to." Also, the term "couple" is intended to mean either an indirect connection or a direct connection. Thus, when a first device couples to a second device, the connection may be by a direct connection or by an indirect connection via other devices and connections.

[0018] "About" with reference to a stated parameter means the stated parameter, plus / minus ten percent (+ / - 10%) of the stated parameter.

[0019] "Assert" means to change the state of a Boolean signal. A Boolean signal may be asserted high, i.e., at a higher voltage, or low, i.e., at a lower voltage, at the discretion of the circuit designer. Similarly, "deassert" means to change the state of a Boolean signal to the voltage level opposite to that of the asserted state.

[0020] "Bidirectional double base bipolar junction transistor" means a junction transistor having a base and a collector-emitter on a first face or side of a bulk region and a base and a collector-emitter on a second face or side of the bulk region, the base and collector-emitter on the first side being distinct from the base and collector-emitter on the second side.

[0021] "FET" means a field effect transistor, such as a junction gate FET (JFET) or a metal oxide silicon FET (MOSFET).

[0022] "Closing," with reference to an electrically controlled switch (e.g., a FET), means making the electrically controlled switch conductive. For example, closing a FET used as an electrically controlled switch may mean driving the FET into a fully conductive state.

[0023] "Open," with reference to an electrically controlled switch (eg, a FET), means to render the electrically controlled switch non-conductive.

[0024] "Upper base" means the base of a bidirectional double-base bipolar junction transistor on a first side of the bulk region of the transistor, and should not be read to mean the position of that base relative to gravity.

[0025] "Lower base" means the base of a bidirectional double base bipolar junction transistor on a second side of the bulk region of the transistor opposite the first side, and should not be read to mean the position of that base relative to gravity.

[0026] "Top collector-emitter" means the collector-emitter of a bidirectional double base bipolar junction transistor on a first side of the bulk region of the transistor, and should not be read to mean the position of that collector-emitter relative to gravity.

[0027] "Lower collector-emitter" means the collector-emitter of a bidirectional double base bipolar junction transistor on a second side of the bulk region of the transistor opposite the first side, and should not be read to mean the position of that collector-emitter with respect to gravity.

[0028] "Injecting charge carriers into the [base]" of a transistor or "injecting charge carriers into the [base] (e.g., upper base, lower base)" of a transistor does not include direct coupling to the collector-emitter on the same side of the transistor (e.g., through a transistor).

[0029] "Extracting charge carriers from the [base]" of a transistor or "extracting charge carriers from the [base]" (e.g., upper base, lower base) of a transistor does not include directly coupling the base to the collector-emitter on the same side of the transistor (e.g., through a transistor).

[0030] The terms "input" and "output", when used as nouns, refer to connections (e.g., electrical, software) and should not be read as verbs requiring an action. For example, a timer circuit may define a clock output. The example timer circuit may generate or drive a clock signal on the clock output. In a system implemented directly in hardware (e.g., on a semiconductor substrate), these "inputs" and "outputs" define electrical connections. In a system implemented in software, these "inputs" and "outputs" define parameters that are read or written, respectively, by instructions that perform a function.

[0031] "Controller" means, alone or in combination, a discrete circuit component, an application specific integrated circuit (ASIC), a microcontroller with control software, a reduced instruction set computing (RISC), a digital signal processor (DSP), a processor with control software, a programmable logic device (PLD), or a field programmable gate array (FPGA) configured to read an input and drive an output in response to the input.

[0032] The following description is directed to various embodiments of the present invention. Although one or more of these embodiments may be preferred, the disclosed embodiments should not be interpreted or otherwise used as limiting the scope of the present disclosure, including the claims. Moreover, those skilled in the art will understand that the following description has a wide range of applications, and the description of any embodiment is intended to merely exemplify that embodiment, and is not intended to imply that the scope of the present disclosure, including the claims, is limited to that embodiment.

[0033] Various examples are directed to methods and systems for operating a bidirectional double-base bipolar junction transistor (B-TRAN). In particular, various examples are directed to operating the B-TRAN such that the breakdown voltage drop between the upper collector-emitter and the lower collector-emitter (and vice versa) caused by the beta effect is reduced or eliminated, and the shut-off time is shortened compared to the turn-off of a three-terminal transistor. More specifically, during a transistor-on mode, the B-TRAN conducts a load current, for example from the upper collector-emitter to the lower collector-emitter, and in response to a control signal changing state, the load current is first interrupted by a lower main FET having a breakdown voltage lower than the blocking voltage of the B-TRAN. Interrupting the load current diverts a portion of the load current through the B-TRAN to the lower base (the divert portion is referred to as the shut-off current). The shutoff current reverse-biases the PN junction between the upper collector-emitter and the lower base, thus quickly blocking current flow through the B-TRAN. The applied voltage is then blocked by the B-TRAN. A load current in the reverse direction (e.g., from the lower collector-emitter to the upper collector-emitter) caused by an applied voltage of reverse polarity can similarly be first blocked by the upper main FET and then blocked by the B-TRAN. This specification first refers to an example of a B-TRAN to orient the reader.

[0034] FIG 1 shows an elevational cross-section of an example B-TRAN. In particular, FIG 1 shows a B-TRAN 100 having an upper surface or upper side 102 and a lower surface or lower side 104. The designations "upper" and "lower" are arbitrary and are used merely for convenience of explanation. The upper side 102 points in the opposite direction to the lower side 104. In other words, an outward pointing vector perpendicular to the upper side 102 (this vector is not specifically shown) points in the opposite direction relative to an outward pointing vector perpendicular to the lower side 104 (this vector is not specifically shown).

[0035] The top side 102 includes a plurality of collector-emitter contact regions 106 that form a junction with a drift region or bulk substrate 108. The top side 102 further defines a plurality of base contact regions 110 disposed between the collector-emitter contact regions 106. The collector-emitter contact regions 106 are coupled together to form an upper collector-emitter 112. The base contact regions 110 are coupled together to form an upper base 114. Similarly, the bottom side 104 includes a plurality of collector-emitter contact regions 116 that form a junction with the bulk substrate 108. The bottom side 104 further defines a plurality of base contact regions 118 disposed between the bottom collector-emitter contact regions 106. The collector-emitter contact regions 116 are coupled together to form a lower collector-emitter 120. The lower base contact regions 118 are coupled together to form a lower base 122.

[0036] The B-TRAN 100 in this example is an NPN structure, so that the collector-emitter contact regions 106 and 116 are N-type and the base contact regions 110 and 118 are P-type. In this example system, shallow N+ regions provide ohmic contact from the collector-emitter contact regions 106 and 116 to the respective collector-emitters 112 and 120. Also in this example system, shallow P+ contact doping provides ohmic contact from the base contact regions 110 and 118 to the respective bases 114 and 122. In this example, an optional dielectric-filled trench 124 provides lateral isolation between the base and collector-emitter contact regions. It should be noted that PNP-type B-TRAN devices are also contemplated, but will not be specifically shown to avoid unnecessarily lengthening this description.

[0037] In this example case, the various structures and dopings associated with the top side 102 are mirror images of the various structures and dopings associated with the bottom side 104. However, in some cases, the various structures and dopings associated with the top side 102 are constructed at a different time than the various structures and dopings of the bottom side 104, and therefore there may be slight differences in the structures and dopings between the two sides due to manufacturing tolerances, but such do not adversely affect the operation of the device as a bidirectional double base bipolar junction transistor. To explain the operation of the example B-TRAN device, this specification next refers to a model example B-TRAN device along with a simplified driver circuit.

[0038] FIG. 2 illustrates an electrical diagram of an example switch assembly having a model of a B-TRAN, along with a simplified electrical diagram of a conceptual driver circuit. In particular, FIG. 2 illustrates a model 200 of a B-TRAN, along with a driver portion 202 for the upper side of the B-TRAN and a driver portion 204 for the lower side of the B-TRAN. Referring first to the model 200, the example model 200 defines an upper collector-emitter 112 and an upper base 114 (although in FIG. 2, the upper base 114 is shown on the left). The driver portion 202 is coupled to the upper collector-emitter 112 and the upper base 114. The example model 200 further defines a lower collector-emitter 120 and a lower base 122 (although in FIG. 2, the lower base 122 is shown on the right). The driver portion 204 is coupled to the lower collector-emitter 120 and the lower base 122.

[0039] Internally, the example model 200 includes a first NPN transistor 206 having an emitter E1 coupled to the upper collector-emitter 112, a collector C1 coupled to the lower collector-emitter 120, and a base B1 defining the upper base 114. The example model 200 further includes a second NPN transistor 208 having an emitter E2 coupled to the lower collector-emitter 120, a collector C2 coupled to the upper collector-emitter 112, and a base B2 defining the lower base 122. The bases B1 and B2 are coupled together by series resistors 210 and 212, which represent the drift region of the bulk substrate, and which define a node 214 therebetween. A diode 216 is coupled between the node 214 and the upper collector-emitter 112, which represents a PN junction between the upper collector-emitter 112 and the lower base 122. Similarly, a diode 218 is coupled between node 214 and the lower collector-emitter 120 , and represents a PN junction between the lower collector-emitter 120 and the upper base 114 .

[0040] Outside the model 200, and referring initially to the upper driver portion 202, an electrically controlled switch 222 (hereafter referred to as the upper main switch 222) has a first lead coupled to the upper collector-emitter 112 and a second lead coupled to and defining an upper terminal 224. Although the example upper main switch 222 is shown as a single-pole, single-throw switch in an open or non-conducting configuration, in practice the upper main switch 222 may be a FET. Thus, when the upper main switch 222 is conducting, the upper collector-emitter 112 is coupled to the upper terminal 224. Another electrically controlled switch 226 (hereafter referred to simply as the switch 226) has a first lead coupled to the upper terminal 224 and a second lead coupled to the upper base 114. Although the example switch 226 is shown as a single-pole, single-throw switch in an open or non-conducting configuration, in practice the switch 226 may be a FET. Thus, when the switch 226 is conductive, the top base 114 is coupled to the top terminal 224. The example driver portion 202 further includes a charge carrier source 228, illustrated as a battery. The charge carrier source 228 has a negative lead coupled to the top terminal 224. Another electrically controlled switch 230 (hereafter simply switch 230) has a first lead coupled to the positive terminal of the charge carrier source 228 and a second lead coupled to the top base 114. Although the example switch 230 is illustrated as a single-pole, single-throw switch, in practice the switch 230 may be a FET. Thus, when the switch 230 is conductive, the charge carrier source 228 is coupled between the top terminal 224 and the top base 114.

[0041] Referring now to the lower driver portion 204, an electrically controlled switch 232 (hereinafter, lower main switch 232) has a first lead coupled to the lower collector-emitter 120 and a second lead coupled to and defining a lower terminal 234. Although the example lower main switch 232 is shown as a single-pole, single-throw switch in an open or non-conducting configuration, in practice the lower main switch 232 may be a FET. Thus, when the lower main switch 232 is conducting, the lower collector-emitter 120 is coupled to the lower terminal 234. Another electrically controlled switch 236 (hereinafter, simply switch 236) has a first lead coupled to the lower terminal 234 and a second lead coupled to the lower base 122. Although the example switch 236 is shown as a single-pole, single-throw switch in an open or non-conducting configuration, in practice the switch 236 may be a FET. Thus, when the switch 236 is conducting, the lower base 122 is coupled to the lower terminal 234. The example driver portion 204 further includes a charge carrier source 238, illustrated as a battery. The charge carrier source 238 has a negative lead coupled to the lower terminal 234. Another electrically controlled switch 240 (hereafter simply switch 240) has a first lead coupled to the positive terminal of the charge carrier source 238 and a second lead coupled to the lower base 122. Although the example switch 240 is shown as a single-pole, single-throw switch, in practice the switch 240 may be a FET. Thus, when the switch 240 is conductive, the charge carrier source 238 is coupled between the lower terminal 234 and the lower base 122.

[0042] FIG. 3 illustrates an example switch assembly in a mode in which the B-TRAN is non-conducting and blocking current flow. A non-conducting switch is shown as an open circuit, and a conducting switch is shown as an electrical short. In particular, consider an externally applied voltage across the upper terminal 224 and the lower terminal 234, with the upper terminal 224 at positive polarity. In the configuration illustrated in FIG. 3, the upper main switch 222 is conducting, along with the switch 236 in the lower driver section 204, and all remaining switches are non-conducting. When the upper main switch 222 is conducting, the upper terminal 224 is coupled to the upper collector-emitter 112. When the switch 236 is conducting, the lower base 122 is coupled to the lower terminal 234. In the illustrated configuration, the PN junction, shown as the diode 216 in the model 200, is reverse biased. Also, both the lower collector-emitter 120 and the upper base 114 are left electrically floating. Thus, the B-TRAN is non-conductive for the polarity of the applied voltage, there is no current through the B-TRAN, and therefore the B-TRAN blocks the applied voltage (e.g., 1200V from the upper terminal 224 to the lower terminal 234) by the PN junction formed between the upper collector-emitter 112 and the lower base 122. The configuration of Figure 3 may therefore be referred to as a non-conductive mode or off mode.

[0043] Now consider that the B-TRAN is made conductive. FIG. 4 illustrates an example switch assembly configured in an optional diode-on mode. In particular, from the off mode of FIG. 3, initially, the lower main switch 232 is made conductive, switch 226 is made conductive, and switch 236 is made non-conductive to make the B-TRAN conductive with an externally applied voltage in the polarity shown. The upper main switch 222 may be conductive or non-conductive in the diode-on mode. In the illustrated configuration, the upper PN junction represented by diode 216 is bypassed and the lower PN junction represented by diode 218 is forward biased. Thus, current flows from the upper terminal 224 through the upper base 114 to the lower collector-emitter 120. When used, the diode-on mode may last for a predetermined period of time (e.g., about 1 microsecond (μs) to 5 μs inclusive). In the illustrated configuration, the forward voltage drop is relatively low. In one example, the forward voltage drop is about 200 A / cm 2 At a current density of 1000 Ω, the forward voltage drop is approximately 1.0 V. However, the forward voltage drop can be much lower.

[0044] 5 shows an example switch assembly configured for conduction. When the diode-on mode is used, switch 226 is made non-conductive and switch 230 is made conductive to further reduce the forward voltage drop across the B-TRAN. When the diode-on mode is omitted, from the off mode (FIG. 3), switch 236 is made non-conductive, lower main switch 232 is made conductive, switch 230 is made conductive, and upper main switch 222 remains conductive. In the illustrated configuration, a charge carrier source 228 is coupled between the upper terminal 224 and the upper base 114. As a result, the voltage of the upper base 114 is driven higher than the voltage of the upper collector-emitter 112. Although the lower base 122 is left electrically floating, the lower base 122 is internally connected through the drift region of the B-TRAN, and therefore the lower base 122 can be driven higher than the voltage of the upper collector-emitter 112 (depending on the example voltage of the charge carrier source 228). Thus, both example transistors of the model 200 are partially or fully conducting, a configuration referred to as the conducting mode or transistor-on mode. In this configuration, charge carriers (here holes) are injected into the upper base 114 by the charge carrier source 228. The additional holes in the drift region increase the conductivity of the drift region, which reduces the forward voltage drop across the B-TRAN device. In one example, with an applied voltage of about 0.7V to about 1.0V inclusive between the upper collector-emitter 112 and the upper base 114 (e.g., by the charge carrier source 228), the forward voltage drop can be reduced to between about 0.1V and 0.2V inclusive. Next, related art methods for rendering the B-TRAN non-conductive and potential drawbacks of the related art methods are described.

[0045] FIG. 6 illustrates a related art switch assembly configured for transistor turn-off. In particular, FIG. 6 illustrates the model 200 described above and two external switches 600 and 602. In the related art system, switch 600 selectively couples the upper base 114 directly to the upper collector-emitter 112, which defines the upper terminal. Switch 602 selectively couples the lower base 122 directly to the lower collector-emitter 120, which defines the lower terminal. Thus, for the example applied voltages with the polarities shown, transistor turn-off is achieved by floating the upper base 114 and directly coupling the lower base 122 to the lower collector-emitter 120. Thus, rendering the B-TRAN non-conductive is achieved by draining charge carriers through the lower base 122 and the lower collector-emitter 120 until the upper PN junction, shown as diode 216, becomes reverse biased. Making B-TRAN non-conductive in this manner may be referred to as turning the transistor off.

[0046] Transitioning the B-TRAN to transistor turn-off with the illustrated configuration is a process that may have a long "tail" as the current approaches zero asymptotically, and therefore takes a non-insignificant amount of time. That is, the amount of time it takes for the current through the B-TRAN to reach zero using the techniques of the related art may depend on the amount of load current through the B-TRAN, the magnitude of the applied voltage, and how quickly charge carriers are drained from the drift region by the lower base 122. For example, based on simulations, a transition from fully conducting to non-conducting carrying a current of 100 A may take approximately 6 μs using the configuration shown in FIG. 6. To reduce the transition time, various techniques may be implemented in the related art, such as using a configuration in which both switches 600 and 602 are conducting for a period of time, but while such techniques may reduce the transition time, there is still a current "tail" during the transition.

[0047] Also, implementing a transistor turn-off as shown in FIG. 6 in the related art may reduce the breakdown voltage. In particular, while the example switch 602 is shown as conducting and thus directly coupling the lower base 122 to the lower collector-emitter, in practice the switch 602 may be a transistor, such as a FET. Even a well-designed and constructed FET will have a non-zero voltage drop (e.g., between 0.1V and 0.3V) in the fully conducting state. Furthermore, the electrical connections between the B-TRAN and the external driver circuit, including the switch 602, each have a small but non-zero resistance. As a result, rather than the example lower base 122 and lower collector-emitter 120 having the same potential, the lower base 122 may carry a higher potential than the lower collector-emitter 120. This higher potential on the lower base 122, combined with the beta of the B-TRAN, increases the leakage current and lowers the breakdown voltage of the B-TRAN from the upper collector-emitter 112 to the lower collector-emitter 120. This lower breakdown voltage can become even lower as the temperature of the B-TRAN increases.

[0048] Furthermore, in many cases, the example load current carried from the upper collector-emitter 112 to the lower collector-emitter 120 may be inductive in nature, either because the load itself is inductive (e.g., a motor), or because of the inductive effects of various connections associated with the B-TRAN, or both. Related art switch assemblies such as that shown in FIG. 6 may have difficulty transitioning to non-conducting in the presence of an inductive load. In other words, a non-zero potential difference between the lower base 122 and the lower collector-emitter 120, in combination with an external inductive load, may cause the B-TRAN to transition to non-conducting very slowly, and in some cases at higher inductive currents, may cause the B-TRAN to transition to non-conducting incapable of doing so.

[0049] The above problems are at least partially addressed in the example switch assembly by the use of an upper main switch and a lower main switch. Returning briefly to FIG. 5, FIG. 5 again shows an example switch assembly configured in a transistor-on mode. That is, in an example applied voltage polarity, load current is conducted from the upper terminal 224 through the upper main switch 222 to the upper collector-emitter 112, through the B-TRAN, and from the lower collector-emitter 120 through the lower main switch 232 to the lower terminal 234. In the example system, based on a change in state of an interrupt or control signal (discussed further below), making the B-TRAN non-conductive involves interrupting the current flow by one of the upper or lower main switches. In the example applied voltage polarity of FIG. 5, the current is interrupted by the lower main switch 232.

[0050] Returning to FIG. 3 . According to some examples, transitioning the switch assembly from a conducting or transistor-on mode (as shown in FIG. 5 ) to a non-conducting or off mode of FIG. 3 may involve re-implementing the configuration of FIG. 3 . That is, in some examples, transitioning from a transistor-on mode (as shown in FIG. 5 ) to an off mode may directly involve re-implementing the configuration of FIG. 3 . In particular, making the switch assembly non-conductive may include making switch 230 non-conductive, making lower main switch 232 non-conductive, making switch 236 conductive, and leaving upper main switch 222 conductive. Making switch 230 non-conductive stops the injection of charge carriers through upper base 114. Opening or non-conducting lower main switch 232 blocks the load current from the lower collector-emitter 120 to the lower terminal 234. Furthermore, making lower main switch 232 non-conductive diverts a portion of the load current to flow through lower base 122 and switch 236. The diverted portion of the load current (i.e., the shutoff current) flows for a short period of time until the PN junction shown as diode 216 between the upper collector-emitter 112 and the lower base 122 becomes reverse biased, and the current decreases to substantially zero. When the PN junction shown as diode 216 becomes reverse biased, the example system blocks current flow from the upper terminal 224 to the lower terminal 234 through the B-TRAN. Making the B-TRAN non-conductive in this manner is referred to as diode turn-off, which is significantly faster than transistor turn-off. In other cases, transitioning the switch assembly from conducting to non-conducting may be accomplished through the use of an optional pre-turn-off mode.

[0051] Using a diode turn-off can have several advantages, although not all advantages are present in all cases. In particular, in addition to being faster than a transistor turn-off, the breakdown voltage of a diode turn-off is higher than that of a transistor turn-off. Also, as temperature increases, the breakdown voltage of a diode increases. Furthermore, under inductive loads, a diode turn-off can block higher voltages and currents during turn-off than a transistor turn-off.

[0052] FIG. 7 illustrates an example switch assembly configured in an optional pre-turn-off mode. In some examples, the initial process of making the B-TRAN non-conductive (e.g., about 0.1 μs-5 μs before the full turn-off of a 1200V device) may involve making switches 226 and 236 conductive, making switch 230 non-conductive, and leaving upper main switch 222 and lower main switch 232 conductive. Making switch 230 non-conductive and switch 226 conductive stops the injection of charge carriers from charge carrier source 228. Additionally, making switch 236 conductive causes current drain or outflow from the drift region. These actions consequently reduce and / or remove charge carriers from the drift region, taking the B-TRAN out of saturation and increasing the forward voltage drop. This configuration is referred to as the pre-turn-off mode. In one example, in the pre-turn-off mode, the forward voltage drop from the top collector-emitter 112 to the bottom collector-emitter 120 may rise to between about 0.9V and 3V inclusive. The B-TRAN example may then be made completely non-conductive by again implementing the off mode of Figure 3 for this polarity example. Implementing the pre-turn-off mode even further reduces the amount of time to transition the switch assembly to the off mode (e.g., compared to directly changing the configuration of Figure 5 to the configuration of Figure 3).

[0053] The examples relating to Figures 3-5 and 7 are for a situation where the externally applied voltage has a positive polarity at the top terminal 224. However, this B-TRAN example is a symmetric device, and now that we understand how to control the current through the B-TRAN in the polarity examples shown, controlling the current in the opposite direction follows directly. In such a reverse current situation, charge carrier source 238 and switch 240 would be used rather than charge carrier source 228 and switch 230.

[0054] 8 illustrates a partial block diagram, partially electrical schematic diagram, of an example switch assembly. In particular, the example switch assembly 800 includes a B-TRAN 100 and a driver 802. The B-TRAN 100 is in an NPN configuration, as shown by the example circuit symbol with two emitters and two bases. The circuit symbol shows a top collector-emitter 112, top base 114, bottom collector-emitter 120, and bottom base 122. The top collector-emitter 112 is coupled to a top terminal 224 of the switch assembly 800. The bottom collector-emitter 120 is coupled to a bottom terminal 234 of the switch assembly 800. The driver example 802 defines an upper base terminal 808 coupled to the upper base 114, an upper conduction terminal 810 coupled to the upper collector-emitter 112, a lower base terminal 812 coupled to the lower base 122, and a lower conduction terminal 814 coupled to the lower collector-emitter 120.

[0055] The example driver 802 further includes a controller 816, an electrical isolator 818, and an isolation transformer 820. To place the B-TRAN 100 in various conductive and non-conductive modes, the example driver 802 includes a plurality of electrically controlled switches and charge carrier sources. In particular, the driver 802 includes a switch 226 having a first lead coupled to the upper terminal 224, a second lead coupled to the upper base 114, and a control input coupled to the controller 816. Again, the example switch 226 is shown as a single-pole, single-throw switch, but in practice the switch 226 may be a FET, with the control input being the gate of the FET. Thus, when the switch 226 is made conductive by assertion of its control input, the upper base 114 is coupled to the upper terminal 224.

[0056] The driver 802 further includes a charge carrier source 822, illustrated as a battery. The charge carrier source 822 has a negative lead coupled to the upper terminal 224. Another electrically controlled switch 824 (hereafter simply switch 824) has a first lead coupled to the positive terminal of the charge carrier source 822, a second lead coupled to the upper base 114, and a control input coupled to the controller 816. The example switch 824 is also illustrated as a single-pole, single-throw switch, but in practice the switch 824 may be a FET with the gate of the FET as a control input. Thus, when the switch 824 is conducting, the charge carrier source 822 is coupled between the upper terminal 224 and the upper base 114. The driver 802 further includes a charge carrier source 826, illustrated as a battery. The charge carrier source 826 has a negative lead coupled to the upper terminal 224. Another electrically controlled switch 828 (hereafter simply switch 828) has a first lead coupled to the positive terminal of charge carrier source 826, a second lead coupled to upper base 114, and a control input coupled to controller 816. Although the example switch 828 is also shown as a single-pole, single-throw switch, in practice switch 828 may be a FET with the gate of the FET as the control input. Thus, when switch 828 is conductive, charge carrier source 826 is coupled between upper terminal 224 and upper base 114. Charge carrier sources 822 and 826, either alone or in combination, may be the example charge carrier source 228 of FIG. 2.

[0057] The driver 802 further includes an upper main switch 222 having a first lead coupled to an upper terminal 224, a second lead defining an upper conduction terminal 810 coupled to the upper collector-emitter 112, and a control input coupled to the controller 816. As mentioned above, although the example upper main switch 222 is shown as a single-pole, single-throw switch, in practice the upper main switch 222 may be a FET with the gate of the FET as the control input. Thus, when the upper main switch 222 is made conductive, such as by assertion of its control input, the upper terminal 224 is coupled to the upper collector-emitter 112.

[0058] Referring now to the bottom of the B-TRAN 100, the example driver 802 further includes a switch 236 having a first lead coupled to the bottom terminal 234, a second lead coupled to the bottom base 122, and a control input coupled to the controller 816. Although the example switch 236 is shown as a single-pole, single-throw switch, in practice the switch 236 may be a FET, and the control input is the gate of the FET. Thus, when the switch 236 is made conductive by assertion of its control input, the bottom base 122 is coupled to the bottom terminal 234.

[0059] The driver 802 further includes a charge carrier source 830, illustrated as a battery. The charge carrier source 830 has a negative lead coupled to the lower terminal 234. Another electrically controlled switch 832 (hereafter simply switch 832) has a first lead coupled to the positive terminal of the charge carrier source 830, a second lead coupled to the lower base 122, and a control input coupled to the controller 816. Although the example switch 832 is shown as a single-pole, single-throw switch, in practice the switch 832 may be a FET with the gate of the FET as a control input. Thus, when the switch 832 is conducting, the charge carrier source 830 is coupled between the lower terminal 234 and the lower base 122. The driver 802 further includes a charge carrier source 834, illustrated as a battery. The charge carrier source 834 has a negative lead coupled to the lower terminal 234. Another electrically controlled switch 836 (hereafter simply switch 836) has a first lead coupled to the positive terminal of charge carrier source 834, a second lead coupled to lower base 122, and a control input coupled to controller 816. Although the example switch 836 is shown as a single-pole, single-throw switch, in practice switch 836 may be a FET with the gate of the FET as the control input. Thus, when switch 836 is conductive, charge carrier source 834 is coupled between lower terminal 234 and lower base 122. Charge carrier sources 830 and 834, alone or in combination, may be example charge carrier source 238 of FIG. 2.

[0060] The driver 802 further includes a lower main switch 232 having a first lead coupled to a lower terminal 234, a second lead defining a lower conduction terminal 814 coupled to the lower collector-emitter 120, and a control input coupled to the controller 816. As mentioned above, although the example lower main switch 232 is shown as a single-pole, single-throw switch, in practice the lower main switch 232 may be a FET with the gate of the FET as the control input. Thus, when the lower main switch 232 is conducting, such as by assertion of its control input, the lower terminal 234 is coupled to the lower collector-emitter 120.

[0061] The controller 816 defines control inputs 838 and 840 and control outputs 842, 844, 846, 848, 850, 852, and 854 coupled to the control inputs of the switches 222, 828, 824, 226, 236, 832, 836, and 232, respectively. When the control input 838 is asserted, the controller 816 is designed and constructed to configure the B-TRAN 100 for conduction from the upper terminal 224 to the lower terminal 234 (e.g., FIG. 4 or FIG. 5). Conversely, when the control input 838 is deasserted, the controller 816 is designed and constructed to configure the B-TRAN 100 to prevent current flow from the upper terminal 224 to the lower terminal 234 (e.g., the off mode of FIG. 3). Similarly, when the control input 840 is asserted, the controller 816 is designed and constructed to configure the B-TRAN 100 for conduction from the lower terminal 234 to the upper terminal 224. Conversely, when the control input 840 is deasserted, the controller 816 is designed and constructed to configure the B-TRAN 100 to block current flow from the lower terminal 234 to the upper terminal 224. When the control inputs 838 and 840 are both asserted, the controller 816 configures the B-TRAN 100 for current flow in both directions (e.g., AC breaker service), and when the control inputs 838 and 840 are both deasserted, the controller 816 blocks current flow in both directions.

[0062] In some cases, the configuration in which the B-TRAN 100 is non-conductive depends on the polarity of the applied voltage. Thus, the example controller 816 may further define a polarity input 856 that receives a Boolean indication indicative of the applied polarity. In the example driver 802, a comparator 858 has a first input coupled to the upper terminal 224 (connection shown by bubble "A") and a second input coupled to the lower terminal 234. The comparator 858 defines a comparison output coupled to the polarity input 856. Although FIG. 8 shows the first and second inputs directly coupled to the respective conductive terminals, in practice the voltage across the B-TRAN 100 when non-conductive can be large (e.g., 1200V) and therefore each of the first and second inputs may be coupled to a respective conductive terminal via a respective voltage divider circuit. In still further cases, the applied polarity may be determined by systems and devices external to the switch assembly 800 and a Boolean signal is sent to the control input 856 across the electrical isolator 818.

[0063] Transitioning the B-TRAN 100 from non-conducting to conducting and then back to non-conducting may be a multi-step process. To implement the multi-step process, the controller 816 may be a discrete circuit component, an application specific integrated circuit (ASIC), a microcontroller with control software, a reduced instruction set computing (RISC), a digital signal processor (DSP), a processor with control software, a programmable logic device (PLD), or a field programmable gate array (FPGA), and / or a combination configured to read the control inputs 838 and 840, read the polarity input 856, and drive a control output to effect the mode transition of the B-TRAN 100.

[0064] In the example system, the switch assembly 800 is electrically floating. The example driver 802 implements an electrical isolator 818 to receive control inputs 838 and 840 at the electrical domain of the switch assembly 800. The example electrical isolator 818 may take any suitable form, such as, for example, an optocoupler or a capacitive isolation device. Regardless of the exact nature of the electrical isolator 818, external control signals (e.g., Boolean signals) may be coupled to control inputs 860 and 862 of the electrical isolator 818. The electrical isolator 818 then passes those control signals to the electrical domain of the switch assembly 800. In this example, the external control signals are passed to the control inputs 838 and 840 of the controller 816.

[0065] Reference is now made to the isolation transformer 820. Various devices within the switch assembly 800 may use operating power. For example, the controller 816 may use the bus voltage and power to enable the realization of various operating modes of the B-TRAN. Also, the charge carrier sources within the system may actually be implemented as separate voltage sources in the form of switching power converters or as separate current sources also implemented with switching power converters. The switching power converters implementing the charge carrier sources may use the bus voltage and power. The isolation transformer 820 is provided to provide operating power within the electrical domain of the switch assembly 800. An external system (not specifically shown) may provide an AC signal (e.g., 15V AC) between primary leads 864 and 866 of the isolation transformer 820. The isolation transformer 820 generates an AC voltage on secondary leads 868 and 870. The AC voltage on the secondary side of the isolation transformer 820 is provided to an AC-DC power converter 872, which rectifies the AC voltage and converts it into a bus voltage V to common 874. BUS(e.g., 3.3V, 5V, 12V). The power provided by the AC-DC power converter 872 may be used by various components of the switch assembly 800. In other cases, there may be multiple isolation transformers (e.g., one on each side of the B-TRAN). Even further, a single isolation transformer with multiple secondary windings may be used. Next, example configurations for making the B-TRAN 100 conductive and / or non-conductive in the context of the switch assembly 800 are described.

[0066] As an example, consider a situation where the applied voltage has a positive polarity on the upper terminal 224. Further assume that the control input 860 provided to the galvanic isolator 818 is deasserted, and thus the control signal provided to the control input 838 of the controller 816 is deasserted. Based on the control input 838 being deasserted, the controller 816 is designed and configured to place the B-TRAN 100 in an off mode, taking into account the applied polarity (e.g., as read by the controller 816 through the polarity input 856). Thus, in this configuration example, the upper main switch 222 is conductive and the switch 236 is conductive. In some examples, the switches 222 and 236 are made conductive by the controller 816 asserting the control outputs 842 and 850, respectively. However, in other cases, as will be described in more detail below, the switches 222 and 236 are implemented as FETs with internal body diodes. Thus, the conductivity of upper main switch 222 may be initially based at least on the applied voltage forward biasing the body diode of the FET implementing upper main switch 222. Similarly, the conductivity of switch 236 may initially be based at least on the applied voltage forward biasing the body diode of the FET implementing switch 236. As a result, controller 816 does not necessarily need to take positive action to achieve current blocking for the assumed polarity of the applied voltage. Similar configurations and / or operations may exist for lower main switch 232 and switch 226 when configured to block current of reverse polarity.

[0067] Still considering the example configuration with positive polarity at the upper terminal 224, suppose the control signal provided to the control input 860 of the electrical isolator 818 is then asserted, which in turn asserts the control signal provided to the control input 838 of the controller 816. Based on this assertion, in the example switch assembly 800, the controller 816 may be designed and configured to first place the B-TRAN 100 in an optional diode-on mode by asserting the control output 842 (making the upper main switch 222 conductive), asserting the control output 854 (making the lower main switch 232 conductive), deasserting the control output 850 (making the switch 236 non-conductive), and asserting the control output 848 (making the switch 226 conductive). Making the switch 226 conductive couples the upper terminal 224 to the upper base 114. This configuration causes a current to flow through the B-TRAN 100 with a forward voltage drop corresponding to a diode-on mode. When used, the diode-on mode may last for a predetermined period of time (e.g., about 0.1 μs to 5 μs). The controller 816 may then be designed and configured to place the B-TRAN into a transistor-on mode by injecting charge carriers into the upper base 114. Upon transitioning from the diode-on mode to the transistor-on mode, the controller 816 may be designed and configured to deassert the control output 848 (making the switch 226 non-conductive) and then assert the control output 846 (making the switch 824 conductive) after a sufficient amount of time to ensure that the switch 226 is non-conductive. When not implementing the diode-on mode (i.e., from the off mode of FIG. 3), the controller 816 may be designed and configured to assert control output 842 (making the upper main switch 222 conductive), assert control output 854 (making the lower main switch 232 conductive), deassert control output 850 (making switch 236 non-conductive), and assert control output 846 (making switch 824 conductive). In any event, making switch 824 conductive couples the charge carrier source 822 between the upper collector-emitter 112 and the upper base 114.In some example systems, the charge carrier source 822 generates a controlled voltage of about 1.0 V that is applied across the upper collector-emitter 112 and the upper base 114, which causes a current to flow into the upper base 114. In this configuration, injecting charge carriers into the upper base 114 increases the number of charge carriers in the drift region of the B-TRAN 100, which drives the B-TRAN 100 into saturation.

[0068] The second charge carrier source 826 and associated switch 828 may be used to perform different functions in different switch assemblies 800. For example, the voltage generated by the charge carrier source 826 may be higher than the voltage generated by the charge carrier source 822, and thus, to reduce the switching time from non-conducting to fully conducting, the charge carrier source 826 may be coupled to the upper base 114 for a predetermined period of time, after which the injection of charge carriers may be transferred to the charge carrier source 822 to increase the overall efficiency (e.g., considering the energy used by the switch assembly 800).

[0069] In still further other cases, the voltage generated by the charge carrier source 826 may be lower than the voltage generated by the charge carrier source 822, and in order to reduce switching losses associated with going from conducting to non-conducting, the example switch assembly 800 may transition to injecting charge carriers using the charge carrier source 826 a predetermined time before the next transition, which may increase the forward voltage drop across the B-TRAN 100 but may reduce switching losses at the next transition.

[0070] 8 was for an example of an applied voltage having a positive polarity at the top terminal 224. However, it should be reiterated that the example B-TRAN 100 is a symmetric device, and by now it is straightforward to understand how to configure the B-TRAN 100 into various conducting and non-conducting states, and therefore control of current flow in the opposite direction.

[0071] 8 utilizes separate independent charge carrier sources coupled to each side for the two modes of charge carrier injection. For example, the top side illustratively uses charge carrier source 822 and charge carrier source 826, and the bottom side illustratively uses charge carrier sources 830 and 834. However, in other cases, each side of the B-TRAN 100 may use a single, but variable, charge carrier source, one on each side, to drive the injected carriers.

[0072] FIG. 9 illustrates a partial electrical diagram of an example switch assembly. In particular, FIG. 9 illustrates an example B-TRAN 100 and a portion of an example driver 802. The driver 802 may also include an isolation transformer, an AC-DC power converter, an electrical isolator, a controller, and a comparator, but those components are omitted from the simplified representation of FIG. 9. For purposes of illustration, for the top side 102, FIG. 9 illustrates switches 222, 824, 226, and 828, and example charge carrier sources 822 and 826. For the bottom side 104, FIG. 9 illustrates switches 232, 832, 236, and 836, and example charge carrier sources 830 and 834.

[0073] As alluded to above, many of these switches are implemented as FETs. In the example switch assembly of FIG. 9, the upper main switch 222 is shown as a FET having a source coupled to the upper terminal 224, a drain coupled to the upper collector-emitter 112, a gate defining a control input, and a body diode coupled between the source and drain. When an applied voltage has a positive polarity on the upper terminal 224, the body diode is forward biased, thus making the upper main switch 222 conductive (without any action by the controller 816 (FIG. 8)). During the conductive state of the B-TRAN 100, regardless of the applied polarity, the controller 816 drives the gate to make the FET conductive, lowering the overall voltage drop. In the example case, the FET used to implement the upper main switch 222 can have a breakdown voltage of 100V or less, in some cases about 80V, while the B-TRAN 100 can have a breakdown voltage of 600V or more, in some cases about 1200V.

[0074] The example switch 226 is shown as a pair of back-to-back FETs. In particular, the switch 226 is shown as a first FET with a source coupled to the top terminal 224 and a second FET with a source coupled to the top base 114, with the drains of the FETs tied together. The gates of the FETs may be individually coupled to the controller 816 (FIG. 8) or the gates may be coupled together and driven by the controller 816 as a single unit. The FETs each have a body diode, and in the illustrated configuration, the cathodes of the body diodes are tied together. Having back-to-back FETs allows for bidirectional current blocking and bidirectional current flow, regardless of the presence of the body diodes. For example, the switch 226 can be conductive during an optional diode-on mode (FIG. 4), in which current can flow from the top terminal 224 through the switch 226 to the top base 114 with a positive polarity to the top terminal 224. However, during the transistor on mode, the switch 226 may need to be non-conductive (e.g., to allow other devices to inject charge carriers). Thus, with a positive polarity on the top terminal 224, when the gate is deasserted, the back-to-back FETs block current flow even though the body diode of the first FET is forward biased. Even in situations where a positive polarity is present at the bottom terminal 234, the switch 226 can be conductive upon transition to and during the transistor off mode. For example, the shutoff current in the transition to the transistor off mode may be carried by the switch 226 along with the leakage current in the transistor off mode.

[0075] Similarly, the switch 824 is shown as a pair of back-to-back FETs. In particular, the switch 824 is shown as a FET 900 with a source coupled to the charge carrier source 822 and a FET 902 with a source coupled to the top base 114, with the drains of the FETs 900 and 902 tied together. The gates of the FETs 900 and 902 may be individually coupled to the controller 816 (FIG. 8) or the gates may be tied together and driven by the controller 816 as a single unit. The FETs 900 and 902 each have a body diode, and in the illustrated configuration, the cathodes of the body diodes are tied together. Having back-to-back FETs allows for bidirectional current blocking and bidirectional current flow, regardless of the presence of the body diodes. With positive polarity on the top terminal 224, the transistor on mode may be achieved by the charge carrier source 822 injecting charge carriers through the FETs 900 and 902 into the top base 114. In the other mode, current flow from the charge carrier source 822 to the upper base 114 may be blocked by the FET 902 even though the body diode of the FET 900 may be forward biased by the charge carrier source 822 .

[0076] In the example case, resistors 904 and 906 enable switch 824 to function as both switch 226 and switch 230 (FIG. 2). That is, when charge carrier source 822 is used to inject charge carriers into upper base 114, switch 824 functions as switch 230. However, FET 902 in example switch 824, along with resistors 904 and 906, also enable switch 824 to function as switch 226. For example, when positive polarity is on lower terminal 234 and upper main switch 222 is non-conducting, shutoff current may flow through the body diode of FET 902, through resistor 904 in parallel with FET 900, and through resistor 906 in parallel with charge carrier source 922. Although controller 816 (FIG. 8) may eventually make switch 226 conductive, in this example situation, timing constraints are much more forgiving since the body diode of FET 902 conducts simultaneously with the commutation that creates the shutoff current.

[0077] Still considering the switch 824 and resistors 904 and 906 (and corresponding resistors 908 and 910 for the switch 832 of the lower side 104), a body diode may be used to enable a power-up safe mode. That is, the resistors 904 and 906 ensure that a race condition at power-up of the switch assembly 800 does not cause inadvertent conduction through the B-TRAN 100. In particular, the switch assembly 800 may have the upper terminal 224 and the lower terminal 234 tied together within the overall system. A voltage may appear across the upper terminal 224 and the lower terminal 234, in either polarity, before the AC-DC power converter 872 (FIG. 8) has finished powering up and / or before the controller 816 has had a chance to bootstrap into an operational state. As an example, consider a power-up condition in which a positive polarity appears at the upper terminal 224 before the controller 816 is operational. In such a situation, the body diode of the FET implementing the upper main switch 222 will conduct. Additionally, the body diode of the FET 912 of the switch 832 becomes forward biased, causing shutoff and / or leakage current to flow from the lower base 122 to the lower terminal 234. A similar configuration occurs when a positive polarity appears at the lower terminal 234. Thus, even without control by the controller 816, the B-TRAN 100 enters a non-conduction safe mode regardless of the polarity of the voltage applied between the upper terminal 224 and the lower terminal 234.

[0078] The switch 828 is shown as a single FET having a source coupled to the upper base 114, a drain coupled to the positive lead of the charge carrier source 826, a gate defining a control input, and a body diode coupled between the source and drain. As described above, the charge carrier source 826 may be used for a period of time when the B-TRAN 100 transitions into conduction. A voltage associated with the charge carrier source 826 may keep the body diode of the FET reverse biased when the FET itself is non-conducting, and thus a back-to-back FET may not be required for the switch 828.

[0079] 9 further illustrates the lower main switch 232 as a FET having a source coupled to the lower terminal 234, a drain coupled to the lower collector-emitter 120, a gate defining a control input, and a body diode coupled between the source and drain. When an applied voltage has a positive polarity on the lower terminal 234, the body diode is forward biased, thus making the lower main switch 232 conductive (without any action by the controller 816 (FIG. 8)). During the conductive state of the B-TRAN 100, regardless of the applied polarity, the controller 816 drives the gate to make the FET conductive, lowering the overall voltage drop. In an example case, the FET used to implement the lower main switch 232 can have a breakdown voltage of 100V or less, in some cases about 80V, while the B-TRAN 100 can have a breakdown voltage of 600V or more, in some cases about 1200V.

[0080] Like switch 226, switch 236 may be implemented as a back-to-back FET. Similarly, switch 832 may be implemented as a back-to-back FET. The description of the operation of switches 236 and 832 overlaps with the description of switches 226 and 824, taking into account the polarity of applied voltages, and will not be repeated here again to avoid unnecessarily lengthening the description. Similarly, a charge carrier source 834 is associated with switch 836, which is illustrated as a single FET for the same reasons as described for switch 828.

[0081] When the various switches are implemented as FETs with body diodes as shown in FIG. 9, state transitions can be more easily and quickly implemented by the controller 816 (FIG. 8). As an example, consider the driver 802 has the B-TRAN 100 configured in transistor-on mode with positive polarity on the upper terminal 224. In this situation, the upper main switch 222 is conducting, the switch 824 is conducting, the lower main switch 232 is conducting, and the remaining switches are non-conducting. Now, consider the driver 802 receiving a command to make the B-TRAN 100 non-conducting (e.g., deassertion of the control input 838 (FIG. 8)). When the switches are implemented as FETs as shown, configuring the driver 802 to implement transistor-off mode can involve the controller 816 (FIG. 8) deasserting all gates of all FETs. The upper main switch 222 remains conducting based on the body diodes being forward biased and conducting. The lower main switch 232 blocks the current flow and its body diode is reverse biased. Although the lower main switch 232 is used to block the current flow (e.g., 100A), it is not the primary device that blocks higher voltages; the B-TRAN 100 performs that task. Therefore, it is sufficient for the lower main switch 232 to have a breakdown voltage of 100V or less, in some cases about 80V. The interruption of the current flow diverts the shutoff current to flow through the body diode of the FET 912 of the switch 832 and through the resistors 908 and 910. At some point in the example situation, the controller 816 may turn on the switch 236 to reduce the current through the resistors 908 and 910, but this is not strictly required.

[0082] Consider again the transition from transistor on mode to off mode, again in the example situation of positive polarity at the top terminal 224. When the controller 816 (FIG. 8) transitions the B-TRAN 100 from conducting to non-conducting, the example system of FIG. 9 may extract charge carriers through the top base 114 by a switch exemplified as a FET 914 and a charge carrier source 916. In particular, when the controller 816 transitions from transistor on mode to off mode, the controller 816 may be designed and configured to perform an intermediate step by asserting the gate of the FET 914 to make it conducting, and thus couple the charge carrier source 916 between the top base 114 and the top terminal 224. The charge carrier source 916 of this polarity extracts charge carriers from the drift region through the top base 114, which allows for a faster transition to non-conducting than, for example, performing a pre-turn off mode (FIG. 7) or leaving the top base 114 electrically floating. In terms of forward voltage drop slope, the charge carrier source 916 in this polarity example increases the upward slope of the forward voltage drop, which reduces switching time and therefore reduces switching losses. In the example case, the charge carrier source 916 can be a voltage source (e.g., between 5.0V and 15V, inclusive, illustrated as 12V), and withdrawing the charge carriers can reduce the time to transition from a conducting state to an off mode by between about 0.5μs and 2μs, inclusive. The diode 918 ensures that no current flows in reverse to the upper base 114 of the driver 802 via this path. A similar reduction in transition time can be achieved by the FET 920, the charge carrier source 922, and the diode 924 for the situation where a positive polarity is on the lower terminal 234.

[0083] In still further cases, during a transition from a transistor on mode to an off mode, both FET 914 and FET 920 may be made conductive, and thus both charge carrier sources 916 and 922 draw charge carriers. The period during which both FETs 914 and 920 are conductive may be a relatively short period of time between about 0.5 μs and 2 μs inclusive. Furthermore, only one of FETs 914 and 920 may be made conductive as part of the transition, regardless of the polarity applied across terminals 224 and 234.

[0084] 10 illustrates a method according to at least some embodiments. In particular, the method includes starting (block 1000), conducting a first load current from an upper terminal of a power module to an upper collector-emitter of a transistor, through the transistor, and from a lower collector-emitter of the power module to a lower terminal (block 1002), and then blocking the first load current from the lower collector-emitter to the lower terminal by opening a lower main FET in response to assertion of a first blocking signal, thereby diverting a first shutoff current through a lower base of the transistor to the lower terminal (block 1004), and blocking current from the upper terminal to the lower terminal by the transistor (block 1006). This example may further include conducting a second load current from the lower terminal of the power module to the lower collector-emitter of the transistor, through the transistor, and from the upper collector-emitter to the upper terminal (block 1008), and then, in response to assertion of the second shutoff signal, shutting off the second load current from the upper collector-emitter to the upper terminal by opening the upper main FET, thereby diverting a second shutoff current through the upper base to the upper terminal (block 1010), and blocking current flow from the lower terminal to the upper terminal by the transistor (block 1012). The method then ends (block 1014).

[0085] FIG. 11 shows a plot of the transient time for transitioning the B-TRAN from conducting to non-conducting. In particular, FIG. 11 plots several implementations of the diode turn-off of the example herein together with corresponding related art three terminal or transistor turn-off examples. The vertical axis is the load current through the B-TRAN in amperes, and the horizontal axis is the transient time in microseconds from an arbitrary start time. These various plots were created using a simulation program (e.g., a technology computer-aided design (TCAD) program) with the switch assembly controller current flowing through a resistive load. Example plot 1100 shows the transient time of a diode turn-off without using a pre-turn-off mode, for example, transitioning from a transistor on mode (FIG. 5) directly to an off mode (FIG. 3). Also, in plot 1100, the transition begins at an arbitrary time of 30 μs, and thus the transient time from the example current of 100 A to substantially zero current occurs in approximately 3 μs (i.e., between the 30 μs and 33 μs points). In contrast, plot 1102 shows the transient time for a related art transistor turn-off that does not use a pre-turn-off mode, e.g., transitioning from a conducting to a non-conducting mode (FIG. 6). As previously noted, in plot 1102, the transition begins at an arbitrary time of 30 μs, and thus the transient time from the 100 A example current to substantially zero current occurs in approximately 6 μs, twice as long as in the present example case.

[0086] The transient time for diode turn-off shown by plot 1100 is again without any pre-turn-off. However, the transient time can be further shortened by implementing a pre-turn-off mode (e.g., FIG. 7) between a transistor on mode (e.g., FIG. 5) and an off mode (e.g., FIG. 3). For example, plot 1104 shows the transient time for diode turn-off with a pre-turn-off mode of 5 μs. That is, in the example system, the switch assembly can transition from the transistor on mode (FIG. 5) to the pre-turn-off mode (FIG. 7) for about 5 μs before transitioning to the off mode (FIG. 3). That is, from the transistor on mode (FIG. 5), the switch assembly performs the pre-turn-off mode (FIG. 7) at about the 25 μs point on the horizontal time scale of the horizontal axis of FIG. 11. As mentioned above, the pre-turn-off mode can drain charge carriers from the drift region of the B-TRAN, thus reducing the saturation of the device, but as shown, the amount of current through the B-TRAN is only slightly reduced. At about 30 μs, the example switch assembly transitions to the off mode (FIG. 3), and plot 1104 shows the transient time associated with that transition. Thus, using the pre-turn-off mode (FIG. 7) can reduce the transient time (measured from the off mode implementation of FIG. 3) to less than 1 μs. In contrast, implementing a pre-turn-off with a duration of 5 μs, as shown by plot 1106, can only reduce the transistor turn-off to just under 3 μs.

[0087] Having a shorter transient time may have several advantages, although not all of those advantages need to be present in every implementation. For example, a shorter transient event of a diode turn-off may reduce switching losses compared to a transistor turn-off. Comparing switching losses with a diode turn-off (no pre-turn-off) to a transistor turn-off (no pre-turn-off), switching losses may be cut in half. A shorter transient time also allows for higher frequency operation in situations where increased frequency is desired.

[0088] Each of the upper and lower main switches has a corresponding voltage drop when fully on, but when implemented as a power FET, the forward voltage drop is small (e.g., 0.01V to 0.1V) and negligible in many cases compared to the forward voltage drop of the associated B-TRAN (e.g., 0.2V to 0.6V). It is also noted that the shutoff current through the base opposite the positive polarity during the transition from conducting to non-conducting may have a peak current approximately equal to the load current, but the base region and connections may not be designed to handle the full load current for extended periods of time, and the inventors herein have found through simulations that even a shutoff current having a peak equal to the load current does not adversely affect the operation of the device, given the transient characteristics of the shutoff current (e.g., 1 μs to 3 μs).

[0089] Many of the electrical connections in the drawings are shown as direct couplings with no intervening devices, although not explicitly stated as such in the description above. Nonetheless, this paragraph serves as a predicate for referring to the electrical connections in the claims as "directly coupled" with respect to the electrical connections without intervening devices shown in the drawings. Also, this paragraph does not preclude a base that is electrically connected to a collector-emitter through a transistor may be referred to as "directly coupled."

[0090] The above description is intended to be illustrative of the principles and various embodiments of the present invention. Numerous modifications and variations will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be construed to embrace all such modifications and variations.

Claims

1. 1. A method of operating a power module having a bidirectional double-base bipolar junction transistor, the transistor defining an upper base, an upper collector-emitter, a lower base, and a lower collector-emitter; conducting a first load current from an upper terminal of the power module to the upper collector-emitter of the transistor, through the transistor, and from the lower collector-emitter to a lower terminal of the power module, and then, in response to assertion of a first shutoff signal, interrupting the first load current from the lower collector-emitter to the lower terminal by opening a lower main FET disposed between the lower collector-emitter and the lower terminal, and diverting a first shutoff current through the lower base of the transistor to the lower terminal by closing a lower base FET disposed between the lower base and the lower terminal; and blocking current flow from the upper terminal to the lower terminal by the transistor; How to have that.

2. interrupting the first load current further comprises interrupting the first load current using the lower main FET having a breakdown voltage of 100 volts or less; Blocking the current further comprises blocking an applied voltage across the upper and lower terminals of 600 volts or greater. The method of claim 1.

3. after blocking current from the upper terminal to the lower terminal; conducting a second load current from the lower terminal of the power module to the lower collector-emitter of the transistor, through the transistor, and from the upper collector-emitter to the upper terminal, and then, in response to assertion of a second shutoff signal, interrupting the second load current from the upper collector-emitter to the upper terminal by opening an upper main FET disposed between the upper collector-emitter and the upper terminal, and diverting a second shutoff current through the upper base to the upper terminal by closing an upper base FET disposed between the upper base and the upper terminal; and blocking current flow from the lower terminal to the upper terminal by the transistor; The method of claim 1 further comprising:

4. interrupting the second load current further comprises interrupting the second load current using the upper main FET having a breakdown voltage of 100 volts or less; and blocking current from the lower terminal to the upper terminal further comprises blocking an applied voltage across the lower terminal and the upper terminal of 600 volts or greater. The method according to claim 3.

5. 1. A switch assembly comprising: an upper terminal, a lower terminal, and an upper control input; a transistor defining an upper base, an upper collector-emitter, a lower base, and a lower collector-emitter; an upper main FET defining a first lead coupled to the upper terminal, a second lead coupled to the upper collector-emitter, and a gate; a lower main FET defining a first lead coupled to the lower collector-emitter, a second lead coupled to the lower terminal, and a gate; a top base FET having a first lead coupled to the top base, a second lead coupled to the top terminal, and a gate; a lower base FET having a first lead coupled to the lower base, a second lead coupled to the lower terminal, and a gate; a controller coupled to the upper control input, the gate of the upper main FET, the gate of the lower main FET, the gate of the upper base FET, and the gate of the lower base FET, for a first applied voltage across the upper and lower terminals, the controller: asserting the gate of the upper main FET to cause the upper main FET to conduct, configuring the transistor for conduction from the upper collector-emitter to the lower collector-emitter, and asserting the gate of the lower main FET to cause the lower main FET to conduct, thereby causing a first load current to flow from the upper terminal to the lower terminal; detecting a deassertion of the upper control input; and in response to the deassertion of the upper control input, deasserting the gate of the lower main FET to interrupt the first load current and asserting the gate of the lower base FET to divert a first shutoff current through the lower base to the lower terminal; configuring the transistor to block current flow from the upper terminal to the lower terminal; A controller configured to: A switch assembly having

6. 6. The switch assembly of claim 5, wherein the breakdown voltage of said transistor is greater than or equal to 600 volts and the breakdown voltage of said lower main FET is less than or equal to 100 volts.

7. 6. The switch assembly of claim 5, wherein the breakdown voltage of said transistor is approximately 1200 volts and the breakdown voltage of said lower main FET is less than 80 volts.

8. During a period when the first load current flows from the upper terminal to the lower terminal, the upper base FET is conductive; When the controller configures the transistor to block current flow from the top terminal to the bottom terminal, the controller is further configured to deassert the gate of the top base FET to electrically float the top base.

6. The switch assembly of claim 5.

9. The switch assembly further comprises: a lower control input coupled to the controller; having For a second applied voltage across the upper and lower terminals, the second applied voltage having an opposite polarity to the first applied voltage, the controller: asserting the gate of the lower main FET to cause the lower main FET to conduct, configuring the transistor for conduction from the lower collector-emitter to the upper collector-emitter, and asserting the gate of the upper main FET to cause the upper main FET to conduct, thereby causing a second load current to flow from the lower terminal to the upper terminal; detecting a deassertion of the lower control input; and in response to the deassertion of the lower control input, deasserting the gate of the upper main FET to shut off the second load current and asserting the gate of the upper base FET to divert a second shutoff current through the upper base to the upper terminal; configuring the transistor to block current flow from the lower terminal to the upper terminal; It is configured as follows:

6. The switch assembly of claim 5.

10. The lower base FET is conductive during a period when the second load current flows from the lower terminal to the upper terminal, When the controller configures the transistor to block current flow from the lower collector-emitter to the upper collector-emitter, the controller is further configured to deassert the gate of the lower base FET to cause the lower base to be electrically floating.

10. The switch assembly of claim 9.

11. 10. The switch assembly of claim 9, wherein the breakdown voltage of said transistor is greater than or equal to 600 volts and the breakdown voltage of said lower main FET is less than or equal to 100 volts.

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