Hermetically packaged device and device module

Abstract

In a conventional hermetic package element, a seal portion joining a device wafer and a lid wafer is formed along a crystal orientation of a semiconductor substrate. For this reason, problems of device malfunctions arise due to the device wafer becoming cracked, circuits disposed on the device wafer being broken, and wiring being cut.　A hermetic package element 100 according to the present disclosure is characterized in that: a device wafer 1 includes a projecting region 21 which projects from a lid wafer 2 in a plan view; a seal portion 10 has a polygonal shape in a plan view; and a side 11a of the polygonal shape that faces the projecting region 21 is formed in a different direction to the crystal orientation of the device wafer 1.

Description

[Technical field]

[0001] The present disclosure relates to hermetically packaged devices and device modules. [Background technology]

[0002] Micro Electro Mechanical Systems (MEMS) devices, which are devices in which sensors, actuators, etc. are integrated on a silicon substrate etc. using microfabrication technology, have been put to practical use. Examples of MEMS devices include infrared sensors, gyro sensors, and acceleration sensors.

[0003] Among infrared sensors, uncooled infrared sensors are called thermal sensors because they convert incident infrared rays into heat. Therefore, they are configured to read out temperature changes in an object as changes in an electrical signal, and have a heat-insulating structure in which the sensor (imaging element) is thermally isolated from the base material to increase detection sensitivity. Specifically, the infrared sensor is placed in a sealed vacuum space to improve thermal insulation, that is, inside a vacuum package. In this case, it is known that the lid of the vacuum package is made of low-oxygen silicon or ZnS, which has high infrared transmittance, or an anti-reflection coating (AR coat) is formed.

[0004] On the other hand, as a manufacturing method for vacuum packages, a wafer level package has been proposed in which a device wafer on which MEMS devices are manufactured and a lid wafer facing the device wafer are bonded in a vacuum atmosphere to form multiple vacuum packages (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP2003-531475A (paragraphs 0010-0015, figures 1-4) Summary of the Invention [Problem to be solved by the invention]

[0006] In an airtight package element constructed by a wafer level package, the bonding pads for electrical connection provided on the device wafer are necessarily exposed from the lid wafer, and the bonding part of the device wafer protrudes from the lid wafer. As a result, stress is concentrated at the part where the sealing part on the protruding side of the device wafer contacts the device wafer.

[0007] However, structures such as elements, circuits, and wiring formed on a semiconductor substrate are formed along the crystal orientation of the semiconductor substrate. In a conventional wafer-level hermetic package having such a configuration, the seal portion that bonds the device wafer and the lid wafer is also arranged along the crystal orientation of the device wafer. As a result, the direction of the concentrated stress coincides with the cleavage direction of the device semiconductor substrate, which can cause cracks in the device wafer, destroying the circuits on the device wafer or cutting the wiring, resulting in device malfunctions.

[0008] The present disclosure discloses a technique for solving the above-mentioned problems, and has an object to prevent cracking of the device wafer and obtain a highly reliable hermetically packaged element. [Means for solving the problem]

[0009] The airtight package element according to the present disclosure comprises a device wafer having a mounting surface on which terminals for electrically connecting a semiconductor circuit to the outside are provided, a lid wafer arranged opposite the mounting surface, and a seal portion interposed between the device wafer and the lid wafer and forming an enclosed space of a vacuum atmosphere between the device wafer and the lid wafer in which the semiconductor circuit is housed, wherein the device wafer has a protruding region that protrudes from the lid wafer in a planar view, the terminals are provided in the protruding region, the seal portion is polygonal in a planar view, and the sides of the polygon facing the protruding region are formed in a direction different from the crystal orientation of the device wafer.

[0010] The element module according to the present disclosure is characterized in that it comprises an airtight package element having a device wafer having a mounting surface on which a semiconductor circuit and terminals for electrically connecting the semiconductor circuit to the outside are provided, a lid wafer arranged opposite the mounting surface, and a seal portion interposed between the device wafer and the lid wafer and forming an enclosed space of a vacuum atmosphere between the device wafer and the lid wafer for accommodating the semiconductor circuit, the device wafer having a protruding region protruding from the lid wafer in a planar view, the terminals being provided in the protruding region, the seal portion being polygonal in a planar view, and the sides of the polygon facing the protruding region being formed in a direction different from the crystal orientation of the device wafer, a circuit board, the airtight package element mounted on the circuit board, and an electronic component mounted on the circuit board and electrically connected to the terminals. Effect of the Invention

[0011] According to the present disclosure, it is possible to reduce stress at the site where the seal portion and the device wafer come into contact, thereby preventing cracking of the device wafer and providing a highly reliable hermetically packaged element or element module. [Brief description of the drawings]

[0012] [Figure 1] 2 is a see-through plan view of a lid wafer portion of the hermetic package device according to the first embodiment. FIG. [Diagram 2]2 is a cross-sectional view corresponding to line II-II in FIG. [Diagram 3] FIG. 2 is a partial enlarged view of an area A in FIG. [Figure 4] 11 is a see-through plan view of a lid wafer portion of the hermetic package device according to the second embodiment. FIG. [Diagram 5] 13 is a see-through plan view of a lid wafer portion of the hermetic package device according to a modification of the second embodiment. FIG. [Figure 6] 13 is a see-through plan view of a lid wafer portion of the hermetic package device according to the third embodiment. FIG. [Figure 7] 1 is a diagram showing the relationship between a side 13 and the crystal orientation of the device wafer 1. FIG. [Figure 8] 13 is a see-through plan view of a lid wafer portion of the hermetic package device according to the fourth embodiment. FIG. [Figure 9] FIG. 13 is a plan view of an element module according to a fifth embodiment. [Figure 10] 9A is a cross-sectional view corresponding to line IX-IX in FIG. [Figure 11] FIG. 1 is a transparent plan view of a lid wafer portion of a conventional hermetic package device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, a hermetically packaged device and a device module according to an embodiment of the present disclosure will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted. This applies throughout the entire specification.

[0014] Embodiment 1 The hermetic package element 100 according to the first embodiment will be described with reference to Fig. 1 to Fig. 3. Fig. 1 is a plan view showing a lid wafer portion of the hermetic package element. Fig. 2 is a cross-sectional view corresponding to the line II-II in Fig. 1. Fig. 3 is a partial enlarged view of an area A in Fig. 1.

[0015] First, the basic structure of a hermetically packaged device will be described. Generally, a silicon substrate is processed so that its crystal orientation is in two directions that are parallel and perpendicular to the substrate surface. Both the device wafer 1 and the lid wafer 2 are manufactured by processing a silicon substrate. In Figures 1 to 9 and 11, the device wafer 1 and the lid wafer 2 are arranged so that their crystal orientation is parallel to the X-axis or Y-axis shown in the figures. The outer shapes of the device wafer 1 and the lid wafer 2 are rectangular parallel to the X-axis or Y-axis. As shown in Figures 1 and 2, when viewed in a plan view, i.e., from the Z-axis direction, the device wafer 1 and the lid wafer 2 are arranged with their flat surfaces facing each other in parallel, with a portion of the device wafer 1 extending beyond the lid wafer 2, and are joined by a seal portion 10.

[0016] The seal part 10 is composed of a first underlayer 31 patterned on the mounting surface 1a of the device wafer 1, a second underlayer 32 patterned on the surface of the lid wafer 2 facing the mounting surface 1a, and a sealant layer 33 interposed between the first underlayer 31 and the second underlayer 32 to fill the gap. Both the first underlayer 31 and the second underlayer 32 are patterned continuously without interruption, and are sometimes called sealing rings. The sealant layer 33 is made of a solder material. However, the solder material has low wettability with respect to the surface (mounting surface 1a) of the device wafer 1 and the surface of the lid wafer 2, and it is difficult to bond the device wafer 1 and the lid wafer 2 as is. Therefore, the first underlayer 31 and the second underlayer 32 are made of a material that has good wettability with the solder material and good adhesion to each wafer so as to function as an intermediate layer for bonding each wafer and the sealant layer 33. For example, the sealing material layer 33 is lead-free solder, and the first underlayer 31 and the second underlayer 32 are made of nickel, but the materials are not limited to these and any material can be selected. However, since high-temperature solder and AuSn solder are expensive and have a high environmental impact, lead-free solder is preferable.

[0017] With the seal part 10 configured in this manner, the sealed space 22 surrounded by the device wafer 1, the lid wafer 2, and the seal part 10 is maintained in a vacuum atmosphere. In order to ensure this vacuum volume, the seal part 10 is formed to a thickness of 50 to 150 μm, and has a thickness of 100 μm in this embodiment. Although the inside of the sealed space 22 is called a vacuum atmosphere, this does not mean a complete vacuum, and it is sufficient to have a vacuum degree necessary to maintain thermal insulation.

[0018] An infrared imaging element 3, a scanning circuit 4, and a readout circuit 5 are arranged in an area 20 inside the seal portion 10 on the mounting surface 1a of the device wafer 1. The MEMS and semiconductor elements arranged in the area 20, including the imaging element 3, the scanning circuit 4, and the readout circuit 5, are referred to as a semiconductor circuit 7. The semiconductor circuit 7 is arranged inside an enclosed space 22 maintained in a vacuum atmosphere with excellent thermal insulation properties, which enhances its reliability as an infrared sensor. A gas adsorbent (not shown) called a getter for maintaining the degree of vacuum is formed on the lid wafer 2 in a portion surrounded by the second base layer 32. Also, a recess may be formed to increase the vacuum volume. Furthermore, an anti-reflection film called an AR coat for improving the transmittance of infrared rays may be formed on the outer surface of the lid wafer 2.

[0019] In a plan view, i.e., when viewed from the Z-axis direction, the device wafer 1 has an area that protrudes from the lid wafer 2, and this protruding area is referred to as the protruding area 21. A plurality of terminals 8 (bonding pads) for electrically connecting the semiconductor circuit 7 to the outside are provided on the mounting surface 1a of the protruding area 21. The terminals 8 and the semiconductor circuit 7 are electrically connected via wiring (not shown) provided on the mounting surface 1a. The terminal 8 thus configured is electrically connected by wires or the like to a circuit board or the like (not shown), and functions as an element module 200 (FIGS. 9 and 10) which will be described later.

[0020] Based on the above-mentioned configuration, a characteristic configuration of the hermetic package element 100 of the present disclosure will be described. As shown in FIG. 1, in a plan view, i.e., when viewed from the Z-axis direction, the shape of the seal portion 10 is a polygon consisting of sides 11a, 11b, 11c, and 11d. As described above, the crystal orientations of the device wafer 1 and the lid wafer 2 are parallel to the X-axis or Y-axis. In contrast, none of the sides of the seal portion 10 are parallel to the X-axis or Y-axis, and are formed in a direction different from the crystal orientations of the device wafer 1 and the lid wafer 2. 3 is a straight line parallel to the Y-axis. An angle θ is formed between the side 11a facing the protruding region 21 and the auxiliary line yy. Here, the angle θ is neither zero degrees nor 90 degrees.

[0021] Next, effects of the hermetically packaged sensor according to the first embodiment of the present disclosure will be described. Point D in FIG. 2 is a contact point between the device wafer 1 and the seal portion 10 on the side where the device wafer 1 protrudes from the lid wafer 2. The hermetically sealed package element 100 is heated to a high temperature in a vacuum atmosphere to melt the solder material of the sealing material layer 33, and then cooled to form a solder paste between the device wafer 1 and the lid wafer 2. A sealed space 22 is formed. The linear expansion coefficient of the solder used in the sealing material layer 33 is greater than the linear expansion coefficient of the silicon used in the device wafer 1 and the lid wafer 2. For this reason, in a normal use state, residual stress acts at point D in the direction from point D to the lid wafer (+Z direction) and in the direction from point D to the semiconductor circuit (-X direction).

[0022] 11 is a plan view showing a lid wafer portion of a conventional hermetic package device 900. In a conventional hermetic package device, structures such as elements, circuits, and wiring formed on a semiconductor substrate are formed along the crystal orientation of the semiconductor substrate. In addition, a seal portion 10 that bonds the device wafer and the lid wafer is also arranged along the crystal orientation of the device wafer. The following description will be given with reference to FIG. 2 as a cross-sectional view corresponding to line II-II in FIG. 11. Residual stress acts on the entire end 16f on the right side of side 16a in the figure, similar to the residual stress acting on point D. In other words, the residual stress acting on side 16a acts in a concentrated manner along end 16f. End 16f is parallel to the Y axis in the figure, and coincides with the cleavage direction of the device wafer, i.e., the crystal orientation. This causes problems such as cracks in the device wafer, destruction of circuits arranged on the device wafer, or disconnection of wiring, resulting in malfunction of the device.

[0023] In contrast, in the hermetic package element 100 according to the first embodiment of the present disclosure, the side 11a is arranged so as to be inclined at an angle θ with respect to the crystal orientation of the device wafer 1. In other words, the direction in which the concentrated stress acts is shifted from the crystal orientation by the angle θ, and the stress concentration is alleviated. This makes it possible to prevent cracking of the device wafer 1, destruction of the circuits arranged on the device wafer 1, or malfunction of the device due to disconnection of the wiring. This makes it possible to obtain a hermetic package element with high reliability.

[0024] When the angle θ is 0 as in the conventional airtight package, that is, when the side 11a of the seal portion 10 is parallel to the crystal orientation of the device wafer 1, in our reliability tests, a crack occurred at point D, which is the contact point between the device wafer 1 and the seal portion 10, resulting in the airtightness of the sealed space 22 being broken and causing a malfunction in the airtight packaged element 100. However, when the angle θ was increased from 0, no malfunction occurred in the reliability tests.

[0025] On the other hand, because the external shapes of the semiconductor circuit 7, terminals 8, etc. are arranged parallel to the crystal direction, as the angle θ is set larger, the area for installing the seal portion 10 in the hermetic package element becomes larger, resulting in a problem of an increase in device size. The larger the area of ​​the semiconductor circuit 7, the greater the effect of the angle θ, so it is necessary to select the angle θ so that it falls within the allowable range of the size of the hermetic package element. For this reason, the angle θ is preferably greater than 0 degrees and less than or equal to 5 degrees, and more preferably greater than or equal to 1 degree and less than or equal to 3 degrees.

[0026] In this embodiment, the sealing rings of the device wafer and the lid wafer are formed by electrolytic nickel plating. The width of the sealing rings formed by electrolytic nickel plating is determined by using existing photolithography technology, and it is possible to form any angle θ by using a photomask pattern.

[0027] As described above, the airtight package element 100 of embodiment 1 comprises a device wafer 1 having a mounting surface 1a on which a semiconductor circuit 7 and terminals 8 for electrically connecting the semiconductor circuit 7 to the outside are provided, a lid wafer 2 arranged opposite the mounting surface 1a, and a seal portion 10 interposed between the device wafer 1 and the lid wafer 2 and forming an airtight space 22 of a vacuum atmosphere between the device wafer 1 and the lid wafer 2 to accommodate the semiconductor circuit 7. Here, the device wafer 1 has a protruding region 21 that protrudes from the lid wafer 2 in a plan view. The terminals 8 are provided in the protruding region 21. The sealing portion 10 is polygonal in a plan view, and a side 11a facing the protruding region 21 is formed in a direction different from the crystal orientation of the device wafer 1. Furthermore, the angle θ between the side 11a facing the protruding region 21 and the crystal orientation of the device wafer 1 is preferably greater than 0 degrees and equal to or less than 5 degrees, and more preferably equal to or greater than 1 degree and equal to or less than 3 degrees.

[0028] According to this configuration, the side 11a is arranged so as to be inclined at an angle θ with respect to the crystal orientation of the device wafer 1, so the direction in which the concentrated stress acts is shifted from the crystal orientation by the angle θ. This reduces the stress concentration, and thus makes it possible to prevent cracking of the device wafer 1, destruction of the circuits arranged on the device wafer 1, or malfunction of the device due to disconnection of the wiring, thereby providing the effect of obtaining a highly reliable hermetic package element.

[0029] Embodiment 2 A hermetically packaged element 110 according to embodiment 2 will be described. In embodiment 1, all sides of the seal portion 10 are configured so as not to be parallel to the crystal orientation of the device wafer 1. In embodiment 2, side 11a of the seal portion 10 facing the protruding region 21 is configured so as not to be parallel to the crystal orientation, and the other sides are configured so as to be parallel to the crystal orientation.

[0030] FIG. 4 is a see-through plan view of a lid wafer portion of the hermetic package device 110 according to the second embodiment. The seal portion 10 of the hermetic package element 110 according to the second embodiment has sides 11a, 12b, 12c, and 12d. The material, cross-sectional structure, etc. of the sides 12b, 12c, and 12d are the same as those of the sides 11a, 11b, 11c, and 11d. The sides 12b, 12c, and 12d correspond to the sides 11b, 11c, and 11d in the first embodiment, respectively, but are arranged parallel to the X-axis or Y-axis like the conventional hermetic package element. That is, the sides 12b, 12c, and 12d are arranged parallel to the crystal orientation of the device wafer 1. In the portion where the sides 12b, 12c, and 12d face, the device wafer 1 does not protrude from the lid wafer 2, and the sides 12b, 12c, and 12d do not face the protruding region. The wiring that electrically connects the semiconductor circuit 7 on the device wafer 1 to the outside is arranged so as not to intersect with the seal portion 10 in any portion other than the side 11a facing the protruding region 21.

[0031] In other words, in embodiment 2, edges 12b, 12c, and 12d of sealing portion 10 that do not face protruding region 21 are formed in the same direction as the crystal orientation of device wafer 1, as in conventional airtight packages, so there is no risk of stress concentration, cracking of device wafer 1, destruction of circuits arranged on device wafer 1, or device malfunction due to broken wiring. The other parts are the same as those in the first embodiment, and the description thereof will be omitted.

[0032] The second embodiment also provides the effect of stress relaxation, similar to the first embodiment. Moreover, the second embodiment can reduce the size of the hermetically packaged element 110 compared to the first embodiment. This is effective in cases where the size of the hermetically packaged element 110 cannot be increased by tilting all the sides of the sealing ring due to device layout restrictions.

[0033] The side of the seal portion 10 facing the protruding region 21 does not have to be a single side that is not parallel to the crystal orientation. 5 is a transparent plan view of a lid wafer portion of an airtight packaged element 111 according to a modification of the second embodiment. Unlike the airtight packaged element 110, the sides of the seal portion 10 facing the protruding region 21 in the airtight packaged element 111 are made up of a side 11a that is not parallel to the crystal orientation, and sides 12e and 12f that are continuous with the side 11a and are parallel to the crystal orientation. Here, the length of the side 11a is longer than the lengths of the sides 12e and 12f. It should be noted that, even if some parts of the edge of the seal portion 10 facing the protruding region 21 are parallel to the crystal orientation, if the majority of the edge is not parallel to the crystal orientation, this will have a certain effect in alleviating stress concentration.

[0034] Embodiment 3 A hermetic package device 120 according to a third embodiment will be described with reference to FIGS. In the first embodiment, the side of the seal portion 10 facing the protruding region 21 is a single side 11a. In contrast, in the third embodiment, the seal portion 10 facing the protruding region 21 has a plurality of sides, which are arranged in a zigzag pattern.

[0035] 6 is a plan view showing a lid wafer portion of the hermetic package element 120 according to the third embodiment. The seal portion 10 of the hermetic package element 120 according to the third embodiment has sides 12b, 12c, and 12d and a side 13 facing the protruding region 21. The side 13 is continuous and consists of a plurality of sides 13a, 13b, and 13c arranged in a zigzag pattern. The sides 12b, 12c, and 12d and the side 13 are made of the same material and have the same cross-sectional structure. Like the side 11a, the side 13 is a side of the seal portion 10 facing the protruding region 21, and both sides are arranged not parallel to the crystal orientations (X and Y directions on the paper), and are continuous sides not parallel to the crystal orientations having a bending point.

[0036] Fig. 7 is a diagram showing the relationship between the side 13 and the crystal orientation of the device wafer 1. Parts other than those necessary for explanation are omitted from Fig. 7. The two auxiliary lines yy shown in Fig. 7 are straight lines parallel to the Y axis, that is, the auxiliary lines yy indicate the same direction as the crystal orientation. Sides 13a, 13b, and 13c are arranged so as not to be parallel to the crystal orientation (X and Y directions on the paper). The angles between sides 11a, 11b, and 11c and auxiliary line yy are θ1, θ2, and θ3, respectively. The absolute values ​​of θ1, θ2, and θ3 may be the same or different from each other. θ1 and θ3 are measured in a clockwise direction from auxiliary line yy, while θ2 is measured in a counterclockwise direction from auxiliary line yy, i.e., θ1, θ3 and θ2 have opposite signs, or are said to be zigzag with respect to auxiliary line yy (crystal orientation).

[0037] 7 is the width that side 13 occupies in the X-axis direction. For example, consider a case where the lengths of sides 13a, 13b, and 13c in embodiment 3 are each set to 1 / 3 of the length of side 11a in embodiment 1, and the angle θ in embodiment 1 is set to the same as the angles θ1, θ2, and θ3 in embodiment 3. Then, W can be set to 1 / 3 of the width that side 11a occupies in the X-axis direction in embodiment 1. That is, as shown in the third embodiment, by forming the sides of the seal portion 10 facing the protruding region 21 into a plurality of sides arranged in a zigzag pattern, it is possible to suppress an increase in the size of the hermetically packaged element. The other parts will not be described.

[0038] As described above, the airtight package element 120 of embodiment 3 comprises a device wafer 1 having a semiconductor circuit 7 and terminals 8 for electrically connecting the semiconductor circuit 7 to the outside on its mounting surface 1a, a lid wafer 2 arranged opposite the mounting surface 1a, and a seal portion 10 interposed between the device wafer 1 and the lid wafer 2 and forming an airtight space 22 of a vacuum atmosphere between the device wafer 1 and the lid wafer 2 to accommodate the semiconductor circuit 7. Here, the device wafer 1 has a protruding region 21 that protrudes from the lid wafer 2 in a plan view. The terminals 8 are provided in the protruding region 21. The sealing portion 10 is polygonal in a plan view, and has a side 13a that faces the protruding region 21 that is formed in a direction different from the crystal orientation of the device wafer 1. Here, in the third embodiment, the side 13 is sides 13a, 13b, and 13c that are arranged in a zigzag pattern.

[0039] This configuration provides the same effect as the hermetic packaged element 100 shown in embodiment 1. In addition to the above, the hermetic packaged element 120 according to embodiment 3 provides an effect of suppressing an increase in the size of the hermetic packaged element by forming the sides of the seal portion 10 facing the protruding region 21 into a plurality of sides arranged in a zigzag pattern.

[0040] In the third embodiment, the side of the seal portion 10 facing the protruding region 21 is divided into three parts and arranged in a zigzag shape, but it may be divided into two parts and arranged in a V shape. The number of divisions may be four or more, and the divided lengths do not have to be equal. Even if a side that is arranged parallel to the crystal orientation is included in addition to the multiple sides arranged in a zigzag or V shape, an increase in the size of the hermetically packaged element can be suppressed.

[0041] Embodiment 4 An airtight packaged element 130 according to a fourth embodiment will be described with reference to Fig. 8. In the first to third embodiments, the case where the protruding region 21 is on one side of the airtight packaged element will be described, whereas in the fourth embodiment, the case where the protruding region is on two sides of the airtight packaged element will be described.

[0042] FIG. 8 is a see-through plan view of a lid wafer portion of the hermetic package device 130 according to the fourth embodiment. In the fourth embodiment, the device wafer 1 has two protruding portions that protrude from the lid wafer 2. One of them is the protruding region 21, as in the first embodiment, and the other is the protruding region 21a. The second protruding region, 21a, is disposed on the opposite side of the first protruding region, 21, across the sealed space 22. A plurality of terminals 8 (bonding pads) are also disposed on the mounting surface 1a of the protruding region 21a, and are electrically connected to the imaging element 3, the scanning circuit 4, and the readout circuit 5 via wiring (not shown).

[0043] The shape of the seal portion 10 in the fourth embodiment is a polygon made up of sides 11a, 12b, 14c, and 12d. Side 11a faces the protruding region 21 and is formed in a direction different from the crystal orientation. Sides 12b and 12d are formed in the same direction as the crystal orientation. Side 14c faces protruding region 21a and is formed in a direction different from the crystal orientation of device wafer 1. The material, cross-sectional structure, etc. of side 14c are the same as sides 11a, 12b, and 12d. Description of other parts will be omitted.

[0044] The hermetically packaged device 130 according to the fourth embodiment configured as above also exhibits the effect of reducing stress, similar to that of the first embodiment. Although the first protruding region 21 and the second protruding region 21a are disposed on opposite sides of the sealed space 22, they may be disposed adjacent to each other, for example, on the sides of sides 11a and 12b. Also, the protruding regions may be disposed on three or more sides.

[0045] Embodiment 5. In the fifth embodiment, an element module will be described in which the hermetically packaged element described in the first to fourth embodiments is mounted on a circuit board together with other electronic components. Figures 9 and 10 are provided to explain the configuration of the element module according to the fifth embodiment. Figure 9 is a plan view of the element module according to the fifth embodiment, and Figure 10 is a cross-sectional view corresponding to the line XX in Figure 9. The configuration of the airtight packaged element portion will be described using the airtight packaged element 100, which is similar to any of the first to fourth embodiments and may be replaced with any of the airtight packaged elements 110, 111, 120, or 130. Further, a description of similar portions will be omitted, and Figs. 1 to 8 will be used.

[0046] As shown in Figures 9 and 10, the element module 200 of embodiment 5 has an airtight package element 100, components 204 such as resistors and capacitors, and electronic components 206 including semiconductor devices 205, mounted on a mounting surface 203 of a circuit board 202. The mounted electronic components are then electrically connected to the terminals 8 of the airtight packaged element 100 by wire bonds or the like (not shown) to form an element module 200. In this fifth embodiment, the airtight packaged element 100 and the electronic components 206 are fixed to the circuit board 202 by using a thermosetting conductive adhesive 208. Although not shown, other components, covers, etc. necessary for configuring the element module 200 are also provided.

[0047] The element module 200 according to the fifth embodiment includes the hermetically packaged element described in any one of the first to fourth embodiments, and is robust against vibration and impact. For example, when the hermetically packaged element 100 that functions as an infrared sensor is used, it is robust against vibration and impact, and cracking of the device wafer can be prevented, resulting in a highly reliable infrared sensor.

[0048] The present disclosure is not limited to the above-described embodiment, and includes various modified examples. For example, the above-described embodiment has been described in detail to clearly explain the present disclosure, and the present disclosure is not necessarily limited to those having all of the configurations described. In addition, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. Also, it is possible to add, delete, or replace a part of the configuration of each embodiment with the configuration of another embodiment. [Explanation of symbols]

[0049] 1 device wafer, 1a mounting surface, 2 lid wafer, 3 imaging element, 4 scanning circuit, 5 read circuit, 7 semiconductor circuit, 8 terminal (bonding pad), 10 sealing portion, 11a, 11b, 11c, 11d, 12b, 12c, 12d, 12e, 12f, 13, 13a, 13b, 13c sides, 21, 21a protruding area, 22 enclosed space, 31 first undercoat layer, 32 second undercoat layer, 33 sealant layer, 100,110,11,120,130 Hermetically packaged element, 200 element module, 202 circuit board, 206 electronic component, θ, θ1, θ2, θ3 angles

Claims

1. a device wafer having a mounting surface provided with a semiconductor circuit and a terminal for electrically connecting the semiconductor circuit to an external device; a lid wafer disposed opposite the mounting surface; a seal portion interposed between the device wafer and the lid wafer and forming a sealed space of a vacuum atmosphere between the device wafer and the lid wafer for accommodating the semiconductor circuit, the device wafer has a protruding region protruding from the lid wafer in a plan view, The terminal is provided in the protruding region, The sealing portion is polygonal in plan view, and a side of the polygon facing the protruding region is formed in a direction different from the crystal orientation of the device wafer. A hermetically packaged device comprising:

2. 2. The hermetically packaged element according to claim 1, wherein the sides of the polygon not facing the protruding region are formed in the same direction as the crystal orientation of the device wafer.

3. The angle between the side facing the protruding region and the crystal orientation of the device wafer is greater than 0 degrees and is equal to or smaller than 5 degrees.

3. A hermetically packaged element according to claim 1 or 2.

4. The angle between the side facing the protruding region and the crystal orientation of the device wafer is 1 degree or more and 3 degrees or less.

3. A hermetically packaged element according to claim 1 or 2.

5. The side facing the protruding region includes a side arranged in a V-shape or a zigzag pattern.

5. The hermetically packaged element according to claim 1, wherein

6. The hermetic package element according to any one of claims 1 to 5, characterized in that the sealing portion is formed of a first base layer patterned on the mounting surface, a second base layer patterned on the surface of the lid wafer opposite the mounting surface, and a sealing material layer filling the space between the first base layer and the second base layer, wherein lead-free solder is used for the sealing material layer and nickel is used for the first base layer and the second base layer.

7. 7. An element module comprising: a circuit board; the hermetically sealed package element according to claim 1 mounted on the circuit board; and an electronic component mounted on the circuit board and electrically connected to the terminal.

Images