Semiconductor memory device

Abstract

Transistors (N1, N5) that correspond to a drive transistor (PD1) are respectively formed at a cell upper part and a cell lower part. Transistors (N2, N6) that correspond to a drive transistor (PD2) are respectively formed at the cell upper part and the cell lower part. A transistor (P1) that corresponds to a load transistor (PU2) is formed at the cell lower part. A transistor (P2) that corresponds to a load transistor (PU1) is formed at the cell upper part.

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor memory device including a three-dimensional transistor, and more particularly to a layout structure of a two-port static random access memory (SRAM) cell using a three-dimensional transistor. [Background technology]

[0002] SRAMs are widely used in semiconductor integrated circuits. A known type of SRAM is a two-port SRAM that has two ports for reading and writing data (see, for example, Patent Document 1).

[0003] Furthermore, transistors, which are the basic building blocks of LSIs, have achieved increased integration density, reduced operating voltages, and improved operating speeds through the reduction of gate lengths (scaling). In recent years, however, excessive scaling has caused problems with off-state current and the resulting dramatic increase in power consumption. To solve this problem, there has been active research into three-dimensional transistors, which change the transistor structure from the conventional planar type to a three-dimensional type.

[0004] Non-Patent Documents 1 and 2 disclose, as new devices, a three-dimensional structure device in which a three-dimensional P-type FET and an N-type FET are stacked vertically to a substrate, and an SRAM cell (hereinafter simply referred to as a cell) using this device. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent No. 9,362,292 (Figure 1) [Non-patent literature]

[0006] [Non-Patent Document 1] Ryckaert J. et al., "The Complementary FET (CFET) for CMOS scaling beyond N3", 2018 Symposium on VLSI Technology Digest of Technical Papers [Non-Patent Document 2] A. Mocuta et al., "Enabling CMOS Scaling Towards 3nm and Beyond", 2018 Symposium on VLSI Technology Digest of Technical Papers Summary of the Invention [Problem to be solved by the invention]

[0007] In this specification, a three-dimensional device in which three-dimensional P-type FETs and N-type FETs are stacked vertically to a substrate is called a CFET (Complementary FET) following the description in Non-Patent Document 1. The direction perpendicular to the substrate is called the depth direction.

[0008] However, no concrete study has been done on the layout of a two-port SRAM cell using CFETs.

[0009] The present disclosure aims to provide a layout structure of a two-port SRAM cell using CFETs. [Means for solving the problem]

[0010] In a first aspect of the present disclosure, there is provided a semiconductor memory device including a two-port SRAM cell, the two-port SRAM cell including a first transistor having one node connected to a first power supply that supplies a first voltage, the other node connected to the first node, and a gate connected to a second node; a second transistor having one node connected to the first power supply, the other node connected to the second node, and a gate connected to the first node; a third transistor having one node connected to the first node, the other node connected to a second power supply that supplies a second voltage different from the first voltage, and a gate connected to the second node; The transistor includes a fourth transistor, a fifth transistor having one node connected to a first bit line, the other node connected to the first node, and a gate connected to a first word line, a sixth transistor having one node connected to a second bit line forming a first complementary bit line pair with the first bit line, the other node connected to the second node, and a gate connected to the first word line, a seventh transistor having one node connected to a third bit line, the other node connected to the first node, and a gate connected to the second word line, and an eighth transistor having one node connected to a fourth bit line forming a second complementary bit line pair with the third bit line, the other node connected to the second node, and a gate connected to the second word line. The third and fourth transistors are respectively a first three-dimensional structure transistor which is a three-dimensional structure transistor of a first conductivity type formed in a first layer, and a second three-dimensional structure transistor which is a three-dimensional structure transistor of the first conductivity type formed in a second layer different from the first layer. The first transistor is a three-dimensional transistor of a second conductivity type different from the first conductivity type formed in the second layer. The second transistor is a three-dimensional transistor of the second conductivity type formed in the first layer. Each of the fifth to eighth transistors includes a three-dimensional transistor of the first conductivity type formed in at least one of the first and second layers.

[0011] According to the present disclosure, the first to eighth transistors constitute a two-port SRAM circuit. The third and fourth transistors each include a first-conductivity-type three-dimensional structure transistor formed in the first layer and a first-conductivity-type three-dimensional structure transistor formed in the second layer. The first transistor includes a second-conductivity-type three-dimensional structure transistor formed in the second layer. The second transistor includes a second-conductivity-type three-dimensional structure transistor formed in the first layer. The fifth to eighth transistors each include a first-conductivity-type three-dimensional structure transistor formed in at least one of the first and second layers. That is, the first to eighth transistors constituting the two-port SRAM circuit each include a three-dimensional structure transistor. This makes it possible to realize a two-port SRAM cell using CFETs.

[0012] In a second aspect of the present disclosure, there is provided a semiconductor memory device including a two-port SRAM cell, the two-port SRAM cell including a first transistor having one node connected to a first power supply that supplies a first voltage, the other node connected to the first node, and a gate connected to a second node; a second transistor having one node connected to the first power supply, the other node connected to the second node, and a gate connected to the first node; a third transistor having one node connected to the first node, the other node connected to a second power supply that supplies a second voltage different from the first voltage, and a gate connected to the second node; The transistor includes a fourth transistor, a fifth transistor having one node connected to a first bit line, the other node connected to the first node, and a gate connected to a first word line, a sixth transistor having one node connected to a second bit line forming a first complementary bit line pair with the first bit line, the other node connected to the second node, and a gate connected to the first word line, a seventh transistor having one node connected to a third bit line, the other node connected to the first node, and a gate connected to the second word line, and an eighth transistor having one node connected to a fourth bit line forming a second complementary bit line pair with the third bit line, the other node connected to the second node, and a gate connected to the second word line. The third and fourth transistors are respectively a first three-dimensional structure transistor which is a three-dimensional structure transistor of a first conductivity type formed in a first layer, and a second three-dimensional structure transistor which is a three-dimensional structure transistor of the first conductivity type formed in a second layer different from the first layer. The first and second transistors each include a three-dimensional transistor of a second conductivity type different from the first conductivity type formed in the second layer, and the fifth to eighth transistors each include a three-dimensional transistor of the first conductivity type formed in at least one of the first and second layers.

[0013] According to the present disclosure, the first to eighth transistors constitute a two-port SRAM circuit. The third and fourth transistors each consist of a three-dimensional structure transistor of a first conductivity type formed in the first layer and a three-dimensional structure transistor of a first conductivity type formed in the second layer. The first and second transistors each consist of a three-dimensional structure transistor of a second conductivity type formed in the second layer. The fifth to eighth transistors each include a three-dimensional structure transistor of a first conductivity type formed in at least one of the first and second layers. That is, the first to eighth transistors constituting the two-port SRAM circuit each consist of a three-dimensional structure transistor. This makes it possible to realize a two-port SRAM cell using a CFET.

[0014] In a third aspect of the present disclosure, there is provided a semiconductor memory device including a two-port SRAM cell, the two-port SRAM cell including a first transistor having one node connected to a first power supply that supplies a first voltage, the other node connected to the first node, and a gate connected to a second node; a second transistor having one node connected to the first power supply, the other node connected to the second node, and a gate connected to the first node; a third transistor having one node connected to the first node, the other node connected to a second power supply that supplies a second voltage different from the first voltage, and a gate connected to the second node; The transistor includes a fourth transistor, a fifth transistor having one node connected to a first bit line, the other node connected to the first node, and a gate connected to a first word line, a sixth transistor having one node connected to a second bit line forming a first complementary bit line pair with the first bit line, the other node connected to the second node, and a gate connected to the first word line, a seventh transistor having one node connected to a third bit line, the other node connected to the first node, and a gate connected to the second word line, and an eighth transistor having one node connected to a fourth bit line forming a second complementary bit line pair with the third bit line, the other node connected to the second node, and a gate connected to the second word line. The third and fourth transistors are each composed of a plurality of first three-dimensional structure transistors that are a plurality of first conductive type three-dimensional structure transistors formed in a first layer. The plurality of first three-dimensional structure transistors are formed side by side in a second direction perpendicular to a first direction in which the channels of the first to eighth transistors extend. The first and second transistors each include a three-dimensional transistor of a second conductivity type different from the first conductivity type formed in a second layer different from the first layer, and at least a portion of each of the fifth to eighth transistors overlaps with the third and fourth transistors in a plan view. Each of the fifth to eighth transistors includes a three-dimensional transistor of the first conductivity type formed in at least one of the first and second layers.

[0015] According to the present disclosure, the first to eighth transistors constitute a two-port SRAM circuit. The third and fourth transistors are each formed in a first layer and are composed of a plurality of first-conductivity-type three-dimensional structure transistors arranged in a second direction. The first and second transistors are each composed of a second-conductivity-type three-dimensional structure transistor formed in a second layer. The fifth to eighth transistors each include a first-conductivity-type three-dimensional structure transistor formed in at least one of the first and second layers. That is, the first to eighth transistors constituting the two-port SRAM circuit are each composed of a three-dimensional structure transistor. This makes it possible to realize a two-port SRAM cell using a CFET.

[0016] In addition, the first and second transistors at least partially overlap with the third and fourth transistors in a plan view. That is, the first and second transistors are stacked with the third and fourth transistors, respectively. This makes it possible to reduce the area of ​​the 2-port SRAM cell.

[0017] Therefore, a two-port SRAM cell using CFETs can be realized, and the area of ​​the two-port SRAM cell can be reduced.

[0018] In a fourth aspect of the present disclosure, there is provided a semiconductor memory device including first and second two-port SRAM cells, each of which includes a first transistor having one node connected to a first power supply that supplies a first voltage, the other node connected to the first node, and a gate connected to a second node; a second transistor having one node connected to the first power supply, the other node connected to the second node, and a gate connected to the first node; a third transistor having one node connected to the first node, the other node connected to a second power supply that supplies a second voltage different from the first voltage, and a gate connected to the second node; a fourth transistor connected to the first bit line, a fifth transistor having one node connected to the first node and a gate connected to the first word line, a sixth transistor having one node connected to a second bit line forming a first complementary bit line pair with the first bit line, a sixth transistor having one node connected to the second node and a gate connected to the first word line, a seventh transistor having one node connected to the third bit line, a seventh transistor having one node connected to the first node and a gate connected to the second word line, and an eighth transistor having one node connected to a fourth bit line forming a second complementary bit line pair with the third bit line, a second node connected to the second node and a gate connected to the second word line. The first and second two-port SRAM cells are arranged adjacent to each other in a second direction perpendicular to a first direction in which channels of the first to eighth transistors extend. In the first and second two-port SRAM cells, the third and fourth transistors each include a three-dimensional structure transistor of a first conductivity type formed in a first layer, the first transistor each includes a three-dimensional structure transistor of a second conductivity type different from the first conductivity type formed in a second layer different from the first layer, the second transistor each includes a three-dimensional structure transistor of the second conductivity type formed in at least one of the first and second layers, and the fifth to eighth transistors each include a three-dimensional structure transistor of the first conductivity type formed in at least one of the first and second layers.The fifth and seventh transistors in the first two-port SRAM cell at least partially overlap with the sixth and eighth transistors in the second two-port SRAM cell, respectively, in a plan view.

[0019] According to the present disclosure, the first and second two-port SRAM cells are each configured with a two-port SRAM circuit by the first to eighth transistors provided in the first and second two-port SRAM cells, respectively. The third and fourth transistors each include a three-dimensional structure transistor of a first conductivity type formed in a first layer. The first transistors each include a three-dimensional structure transistor of a second conductivity type formed in a second layer. The second transistors each include a three-dimensional structure transistor of a second conductivity type formed in at least one of the first and second layers. The fifth to eighth transistors each include a three-dimensional structure transistor of a first conductivity type formed in at least one of the first and second layers. That is, the first to eighth transistors constituting the two-port SRAM circuit are each configured with a three-dimensional structure transistor. This makes it possible to realize a two-port SRAM cell using a CFET.

[0020] The first and second two-port SRAM cells are disposed adjacent to each other in the second direction, and the fifth and seventh transistors in the first two-port SRAM cell at least partially overlap with the sixth and eighth transistors in the second two-port SRAM cell in a plan view. That is, the fifth and seventh transistors in the first two-port SRAM cell are stacked with the sixth and eighth transistors in the second two-port SRAM cell. This makes it possible to reduce the area of ​​the two-port SRAM cells.

[0021] Therefore, a two-port SRAM cell using CFETs can be realized, and the area of ​​the two-port SRAM cell can be reduced. Effect of the Invention

[0022] According to the present disclosure, a two-port SRAM cell using CFETs can be realized. [Brief description of the drawings]

[0023] [Figure 1] FIG. 2 is a plan view showing an example of a layout structure of a 2-port SRAM cell according to the first embodiment. [Diagram 2] 1 is a cross-sectional view showing an example of a layout structure of a 2-port SRAM cell according to the first embodiment. [Diagram 3] 1 is a circuit diagram showing a configuration of a 2-port SRAM cell according to a first embodiment. [Figure 4] FIG. 4 is a plan view showing another example of the layout structure of the two-port SRAM cell according to the first embodiment. [Diagram 5] FIG. 4 is a plan view showing another example of the layout structure of the two-port SRAM cell according to the first embodiment. [Figure 6] FIG. 4 is a plan view showing another example of the layout structure of the two-port SRAM cell according to the first embodiment. [Figure 7] FIG. 4 is a plan view showing another example of the layout structure of the two-port SRAM cell according to the first embodiment. [Figure 8] FIG. 11 is a plan view showing an example of a layout structure of a 2-port SRAM cell according to a second embodiment. [Figure 9] FIG. 11 is a plan view showing another example of the layout structure of the 2-port SRAM cell according to the second embodiment. [Figure 10] FIG. 11 is a plan view showing another example of the layout structure of the 2-port SRAM cell according to the second embodiment. [Figure 11] FIG. 11 is a plan view showing another example of the layout structure of the 2-port SRAM cell according to the second embodiment. [Figure 12] FIG. 11 is a plan view showing another example of the layout structure of the 2-port SRAM cell according to the second embodiment. [Figure 13] FIG. 11 is a plan view showing another example of the layout structure of the 2-port SRAM cell according to the second embodiment. [Figure 14] FIG. 11 is a plan view showing another example of the layout structure of the 2-port SRAM cell according to the second embodiment. [Figure 15] FIG. 11 is a plan view showing another example of the layout structure of the 2-port SRAM cell according to the second embodiment. [Figure 16] FIG. 11 is a plan view showing another example of the layout structure of the 2-port SRAM cell according to the second embodiment. [Figure 17] 1 is a cross-sectional view showing a structure of a semiconductor device including a CFET. [Figure 18] 1 is a cross-sectional view showing a structure of a semiconductor device including a CFET. [Figure 19] 1 is a cross-sectional view showing a structure of a semiconductor device including a CFET. [Figure 20] 1 is a cross-sectional view showing a structure of a semiconductor device including a CFET. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] Hereinafter, the embodiments will be described with reference to the drawings. In the following embodiments, a semiconductor memory device includes a plurality of SRAM cells (in this specification, simply referred to as cells as appropriate), and at least some of the plurality of SRAM cells include CFETs, i.e., three-dimensional devices in which a three-dimensional P-type FET and an N-type FET are stacked vertically to a substrate.

[0025] First, the basic structure of a CFET will be described. Figures 17 to 20 are diagrams showing the structure of a semiconductor device equipped with a CFET, with Figure 17 being a cross-sectional view in the X direction, Figure 18 being a cross-sectional view of the gate portion in the Y direction, Figure 19 being a cross-sectional view of the source-drain portion in the Y direction, and Figure 20 being a plan view. Note that the X direction is the direction in which the nanowire extends, the Y direction is the direction in which the gate extends, and the Z direction is the direction perpendicular to the substrate surface. Also, Figures 17 to 20 are schematic diagrams, and the dimensions and positions of each part are not necessarily consistent.

[0026] In this semiconductor device, an element isolation region 302 is formed on the surface of a semiconductor substrate 301 such as a silicon (Si) substrate, and an element active region 30a is defined by the element isolation region 302. In the element active region 30a, an N-type FET is formed on a P-type FET.

[0027] In the element active region 30a, a stacked transistor structure 390a is formed on a semiconductor substrate 301. The stacked transistor structure 390a includes a gate structure 391 formed on the semiconductor substrate 301. The gate structure 391 includes a gate electrode 356, a plurality of nanowires 358, a gate insulating film 355, and an insulating film 357. The gate electrode 356 extends in the Y direction and rises in the Z direction. The nanowires 358 penetrate the gate electrode 356 in the X direction and are arranged in the Y direction and the Z direction. The gate insulating film 355 is formed between the gate electrode 356 and the nanowires 358. The gate electrode 356 and the gate insulating film 355 are formed at positions set back from both ends of the nanowires 358 in the X direction, and an insulating film 357 is formed in the setback portion. An insulating film 316 is formed on both sides of the insulating film 357 on the semiconductor substrate 301. 321 and 322 are interlayer insulating films.

[0028] As shown in FIG. 18, the gate electrode 356 is connected to an upper layer wiring by a via 385 provided in the opening 375.

[0029] For example, the gate electrode 356 can be made of titanium, titanium nitride, polycrystalline silicon, or the like. For example, the gate insulating film 355 can be made of a high dielectric constant material such as hafnium oxide, aluminum oxide, or oxides of hafnium and aluminum. For example, the nanowire 358 can be made of silicon, or the like. For example, the insulating film 316 and the insulating film 357 can be made of silicon oxide, silicon nitride, or the like.

[0030] In this semiconductor device, the number of nanowires 358 arranged in the Z direction is four, and in the element active region 30a, a P-type semiconductor layer 331p is formed at each end of two nanowires 358 on the semiconductor substrate 301 side. Two local wirings 386 in contact with the P-type semiconductor layer 331p are formed to sandwich a gate structure 391 in the X direction. Also, an N-type semiconductor layer 341n is formed at each end of two nanowires 358 on the side away from the semiconductor substrate 101. Two local wirings 388 in contact with the N-type semiconductor layer 341n are formed to sandwich a gate structure 391 in the X direction. An insulating film 332 is formed between the local wirings 386 and the local wirings 388. An insulating film 389 is formed on the local wirings 388. For example, the P-type semiconductor layer 331p is a P-type SiGe layer, and the N-type semiconductor layer 341n is an n-type Si layer. For example, silicon oxide, silicon nitride, or the like can be used for the insulating film 332.

[0031] 19, the local wiring 388 is connected to the embedded wiring 3101 through a via 3071. The local wiring 386 is connected to the embedded wiring 3102 through a via 3072.

[0032] Thus, the stacked transistor structure 390a has a P-type FET including the gate electrode 356, the nanowire 358, the gate insulating film 355, and the P-type semiconductor layer 331p. In this P-type FET, one P-type semiconductor layer 331p functions as a source region, the other P-type semiconductor layer 331p functions as a drain region, and the nanowire 358 functions as a channel. The stacked transistor structure 390a also has an N-type FET including the gate electrode 356, the nanowire 358, the gate insulating film 355, and the N-type semiconductor layer 341n. In this N-type FET, one N-type semiconductor layer 341n functions as a source region, the other N-type semiconductor layer 341n functions as a drain region, and the nanowire 358 functions as a channel.

[0033] In addition, in the layers above the stacked transistor structure, wiring between transistors is performed using vias and metal wiring, and this can be realized by a known wiring process.

[0034] In this embodiment, the number of nanowires in the P-type FET and the N-type FET is four in the Y direction and two in the Z direction, totaling eight, but the number of nanowires is not limited to this. Also, the number of nanowires in the P-type FET and the N-type FET may be different.

[0035] In this specification, the semiconductor layer portions formed on both ends of the nanowire and constituting the terminals that become the source or drain of the transistor are referred to as “pads.” In the above-mentioned basic structure example of the CFET, the P-type semiconductor layer 331p and the N-type semiconductor layer 341n correspond to the pads.

[0036] In addition, in the plan views and cross-sectional views of the following embodiments, the illustration of each insulating film may be omitted. In addition, in the plan views and cross-sectional views of the following embodiments, the nanowire and the pads on both sides thereof may be illustrated in a simplified linear shape. In this specification, expressions such as "same size" that mean that the size is the same, include the range of manufacturing variations.

[0037] In addition, in this specification, the source and drain of a transistor are appropriately referred to as a "node" of the transistor. In other words, one node of a transistor refers to the source or drain of the transistor, and both nodes of a transistor refer to the source and drain of the transistor.

[0038] In addition, in this specification, it is based on the stacking of P-type FETs and N-type FETs, but in some cases, a P-type FET or an N-type FET is formed only in the upper layer (or lower layer). As a method of formation, for example, after forming a device in the upper layer (or lower layer), the device in the upper layer (or lower layer) is partially removed (for example, by removing a pad portion, or removing a gate wiring and a pad portion), so that a P-type FET or an N-type FET can be formed only in the upper layer (or lower layer). Also, when forming the pad portion of the device in the upper layer (or lower layer) by epitaxial growth, a P-type FET or an N-type FET can be formed only in the upper layer (or lower layer) by partially not forming the upper layer (or lower layer).

[0039] In addition, in this specification, it is based on the stacking of P-type FETs and N-type FETs, but in some cases, FETs of the same conductivity type (P-type FETs or N-type FETs) are stacked in the upper and lower layers. That is, FETs of different conductivity types may be formed in at least one of the upper and lower layers. As a method of formation, for example, when an N-type FET (or P-type FET) is formed in a part of the upper layer (or lower layer), the part where the N-type FET (or P-type FET) is formed is masked, and the other parts are doped to the P conductivity type (or N conductivity type). Then, the parts other than the part where the N-type FET is formed are masked, and doped to the N conductivity type (or P conductivity type). This allows FETs of different conductivity types to be formed in at least one of the upper and lower layers, so that FETs of the same conductivity type can be reliably stacked.

[0040] In the following embodiments, "VDD" and "VSS" are used to indicate the voltage or power supply itself.

[0041] In addition, in the following embodiments and their modified examples, the same components and the like are denoted by the same reference numerals and descriptions thereof may be omitted.

[0042] (First embodiment) 1 and 2 are diagrams showing an example of the layout structure of a two-port SRAM cell according to the first embodiment, in which Figs. 1(a), (b), and (c) are plan views, and Figs. 2(a), (b), and (c) are cross-sectional views in the horizontal direction in plan view. Specifically, Fig. 1(a) shows the lower part, i.e., a part including a three-dimensional transistor formed on the side closer to the substrate, Fig. 1(b) shows the upper part, i.e., a part including a three-dimensional transistor formed on the side farther from the substrate, and Fig. 1(c) shows the M1 and M2 layers, which are metal wiring layers. Fig. 2(a) is a cross section taken along X1-X1', Fig. 2(b) is a cross section taken along X2-X2', and Fig. 2(c) is a cross section taken along X3-X3'.

[0043] Fig. 3 is a circuit diagram showing the configuration of a two-port SRAM cell according to the first embodiment. As shown in Fig. 3, the two-port SRAM cell according to this embodiment has a two-port SRAM circuit including load transistors PU1 and PU2, drive transistors PD1 and PD2, and access transistors PG1 to PG4. The load transistors PU1 and PU2 are P-type FETs, and the drive transistors PD1 and PD2 and the access transistors PG1 to PG4 are N-type FETs.

[0044] The load transistor PU1 is provided between a power supply VDD and a first node NA, and the drive transistor PD1 is provided between the first node NA and a power supply VSS. The load transistor PU1 and the drive transistor PD1 have gates connected to a second node NB, and constitute an inverter INV1. The load transistor PU2 is provided between a power supply VDD and a second node NB, and the drive transistor PD2 is provided between the second node NB and a power supply VSS. The load transistor PU2 and the drive transistor PD2 have gates connected to the first node NA, and constitute an inverter INV2. That is, the output of one inverter is connected to the input of the other inverter, thereby forming a latch.

[0045] The access transistor PG1 is provided between the first bit line BLA and the first node NA, and its gate is connected to the first word line WLA. The access transistor PG2 is provided between the second bit line BLAX and the second node NB, and its gate is connected to the first word line WLA. The access transistor PG3 is provided between the third bit line BLB and the first node NA, and its gate is connected to the second word line WLB. The access transistor PG4 is provided between the fourth bit line BLBX and the second node NB, and its gate is connected to the second word line WLB. The first and second bit lines BLA and BLAX form a first complementary bit line pair, and the third and fourth bit lines BLB and BLBX form a second complementary bit line pair.

[0046] In a two-port SRAM cell circuit, when the first and second bit lines BLA, BLAX constituting a first complementary bit line pair are driven to a high level and a low level, respectively, and the first word line WLA is driven to a high level, a high level is written to the first node NA and a low level is written to the second node NB. On the other hand, when the first and second bit lines BLA, BLAX are driven to a low level and a high level, respectively, and the first word line WLA is driven to a high level, a low level is written to the first node NA and a high level is written to the second node NB. Then, when the first word line WLA is driven to a low level while data is written to the first and second nodes NA, NB, a latch state is established and the data written to the first and second nodes NA, NB is held.

[0047] Also, when the first and second bit lines BLA, BLAX are precharged to a high level and the first word line WLA is driven to a high level, the states of the first and second bit lines BLA, BLAX are determined according to the data written to the first and second nodes NA, NB, so that data can be read from the SRAM cell. Specifically, when the first node NA is at a high level and the second node NB is at a low level, the first bit line BLA is held at a high level and the second bit line BLAX is discharged to a low level. On the other hand, when the first node NA is at a low level and the second node NB is at a high level, the first bit line BLA is discharged to a low level and the second bit line BLAX is held at a high level.

[0048] Furthermore, when the third and fourth bit lines BLB, BLBX constituting the second complementary bit line pair are driven to a high level and a low level, respectively, and the second word line WLB is driven to a high level, a high level is written to the first node NA and a low level is written to the second node NB. On the other hand, when the third and fourth bit lines BLB, BLBX are driven to a low level and a high level, respectively, and the second word line WLB is driven to a high level, a low level is written to the first node NA and a high level is written to the second node NB. Then, when the second word line WLB is driven to a low level while data is written to the first and second nodes NA, NB, the latch state is determined and the data written to the first and second nodes NA, NB is held.

[0049] Also, when the third and fourth bit lines BLB, BLBX are precharged to a high level in advance and the second word line WLB is driven to a high level, the states of the third and fourth bit lines BLB, BLBX are determined according to the data written to the first and second nodes NA, NB, so that data can be read from the SRAM cell. Specifically, when the first node NA is at a high level and the second node NB is at a low level, the third bit line BLB is held at a high level and the fourth bit line BLBX is discharged to a low level. On the other hand, when the first node NA is at a low level and the second node NB is at a high level, the third bit line BLB is discharged to a low level and the fourth bit line BLBX is held at a high level.

[0050] As described above, the 2-port SRAM cell has the functions of writing data to the SRAM cell, holding data, and reading data from the SRAM cell by controlling the first and second bit lines BLA, BLAX, and the first word line WLA. Also, the 2-port SRAM cell has the functions of writing data to the SRAM cell, holding data, and reading data from the SRAM cell by controlling the third and fourth bit lines BLB, BLBX, and the second word line WLB.

[0051] In the following description, in plan views such as FIG. 1, the horizontal direction of the drawing is the X direction, the vertical direction of the drawing is the Y direction, and the direction perpendicular to the substrate surface is the Z direction. The solid lines running vertically and horizontally in plan views such as FIG. 1 and the solid lines running vertically in cross-sectional views such as FIG. 2 indicate grids used for component placement during design. The grids are arranged at equal intervals in the X direction and at equal intervals in the Y direction. The grid intervals may be the same or different in the X and Y directions. The grid intervals may be different for each layer. Furthermore, each component does not necessarily need to be arranged on a grid. However, from the viewpoint of suppressing manufacturing variations, it is preferable to arrange the components on the grid.

[0052] In addition, the dotted lines surrounding the cells in the plan views of Figure 1 and the like indicate the cell frame of the 2-port SRAM cell (the outer edge of the 2-port SRAM cell). The 2-port SRAM cell is arranged so that the cell frame is in contact with the cell frame of the adjacent cell in the X or Y direction.

[0053] As shown in FIG. 1(a), power supply wirings 11 and 12 extending in the Y direction are provided below the cell. Both power supply wirings 11 and 12 are buried power supply wirings (BPR: Buried Power Rail) formed in a buried wiring layer. The power supply wirings 11 and 12 each supply a voltage VSS. In FIG. 1, transistors P1 and P2 correspond to load transistors PU2 and PU1, respectively. Transistors N1 and N5 correspond to drive transistor PD1. Transistors N2 and N6 correspond to drive transistor PD2. Transistors N3, N4, N7, and N8 correspond to access transistors PG1 to PG4, respectively.

[0054] Nanowires 21a to 21c and 26a to 26d extending in the Y direction are formed in the lower part of the cell, and nanowires 21d to 21j extending in the Y direction are formed in the upper part of the cell.

[0055] Nanowires 21a, 26a, and 26c are formed side by side in the X direction. Nanowires 21b, 21c, 26b, and 26d are formed side by side in the X direction. Nanowires 21d, 21f, 21g, and 21i are formed side by side in the X direction. Nanowires 21e, 21h, and 21j are formed side by side in the X direction.

[0056] Moreover, the nanowires 21d, 21i, 26a, and 26c are formed side by side with the nanowires 21e, 21j, 26b, and 26d in the Y direction, respectively. Moreover, the nanowires 21b and 21g are formed at the same position in the X direction in a plan view.

[0057] Moreover, the nanowires 21a, 21c, and 26a to 26d overlap with the nanowires 21f, 21h, 21d, 21e, 21i, and 21j, respectively, in a plan view.

[0058] Gate wirings (Gate) 31-36 extend in the Z direction from the bottom to the top of the cell, and also extend in the X direction. Gate wirings 31-33 are formed side by side in the X direction, and gate wirings 34-36 are formed side by side in the X direction. Gate wiring 31 serves as the gate of transistor N3 and dummy transistor N21. Gate wiring 32 serves as the gate of transistors N1, N5, and P2. Gate wiring 33 serves as the gate of transistor N7 and dummy transistor N23. Gate wiring 34 serves as the gate of transistor N4 and dummy transistor N22. Gate wiring 35 serves as the gate of transistors N2, N6, and P1. Gate wiring 36 serves as the gate of transistor N8 and dummy transistor N24.

[0059] Pads 22a to 22n doped with an N-type semiconductor are formed at the top end of nanowire 21a, the bottom end of nanowire 21a, the top end of nanowire 21c, the bottom end of nanowire 21c, the top end of nanowire 21d, between nanowires 21d and 21e, the bottom end of nanowire 21e, the top end of nanowire 21f, the bottom end of nanowire 21f, the top end of nanowire 21h, the bottom end of nanowire 21h, the top end of nanowire 21i, between nanowires 21i and 21j, and the bottom end of nanowire 21j. Nanowires 21a, 21c, 21d to 21f, and 21h to 21j form channel portions of transistors N1 to N8, respectively. Pads 22a and 22b form nodes of transistor N1. Pads 22c and 22d form nodes of transistor N2. Pads 22e and 22f form a node of transistor N3. Pads 22f and 22g form a node of transistor N4. Pads 22h and 22i form a node of transistor N5. Pads 22j and 22k form a node of transistor N6. Pads 22l and 22m form a node of transistor N7. Pads 22m and 22n form a node of transistor N8.

[0060] That is, the nanowire 21a, the gate wiring 32, and the pads 22a and 22b constitute a transistor N1. The nanowire 21c, the gate wiring 35, and the pads 22c and 22d constitute a transistor N2. The nanowire 21d, the gate wiring 31, and the pads 22e and 22f constitute a transistor N3. The nanowire 21e, the gate wiring 34, and the pads 22f and 22g constitute a transistor N4. The nanowire 21f, the gate wiring 32, and the pads 22h and 22i constitute a transistor N5. The nanowire 21h, the gate wiring 35, and the pads 22j and 22k constitute a transistor N6. The nanowire 21i, the gate wiring 33, and the pads 22l and 22m constitute a transistor N7. The nanowire 21j, the gate wiring 36, and the pads 22m and 22n constitute a transistor N8.

[0061] Pads 22o to 22r doped with a P-type semiconductor are formed at the upper end of nanowire 21b in the drawing, the lower end of nanowire 21b in the drawing, the upper end of nanowire 21g in the drawing, and the lower end of nanowire 21g in the drawing, respectively. Nanowires 21b and 21g form channel portions of transistors P1 and P2, respectively. Pads 22o and 22p form the node of transistor P1. Pads 22q and 22r form the node of transistor P2.

[0062] That is, the nanowire 21b, the gate wiring 35, and the pads 22o and 22p form a transistor P1. The nanowire 21g, the gate wiring 32, and the pads 22q and 22r form a transistor P2.

[0063] Dummy pads 27a to 27f doped with an N-type semiconductor are formed at the top of the nanowire 26a in the drawing, between the nanowires 26a and 26b, at the bottom of the nanowire 26b in the drawing, at the top of the nanowire 26c in the drawing, between the nanowires 26c and 26d, and at the bottom of the nanowire 26d in the drawing. The dummy pads 27a and 27b form the node of the dummy transistor N21. The dummy pads 27b and 27c form the node of the dummy transistor N22. The dummy pads 27d and 27e form the node of the dummy transistor N23. The dummy pads 27e and 27f form the node of the dummy transistor N24. The nanowires 26a to 26d correspond to the channel portions of the dummy transistors N21 to N24.

[0064] The dummy transistors N21 to N24 are transistors that do not have a logical function. The dummy transistors N21 to N24 are omitted in the circuit diagram of Fig. 3. Some of the two-port SRAM cells in the embodiments and their modifications described below include dummy transistors, but the dummy transistors do not affect the logical function of the two-port SRAM cell, so they are not shown in the circuit diagram.

[0065] Therefore, in the two-port SRAM cell according to this embodiment, the transistors N3 to N8 overlap with the dummy transistors N21 and N22, the transistors N1 and N2, and the dummy transistors N23 and N24, respectively, in a plan view.

[0066] Moreover, the transistor N1 and the dummy transistors N21 and N23 are formed side by side in the X direction. The transistors N2 and P1 and the dummy transistors N22 and N24 are formed side by side in the X direction. The transistors N3, N5, N7 and P2 are formed side by side in the X direction. The transistors N4, N6 and N8 are formed side by side in the X direction.

[0067] Moreover, the transistors N3, N7 and the dummy transistors N21, N23 are formed side by side in the Y direction with the transistors N4, N8 and the dummy transistors N22, N24, respectively. Moreover, the transistors P1, P2 are formed at the same position in the X direction in a plan view.

[0068] Local interconnects (LI) 41a to 41e extending in the X-direction are formed at the bottom of the cell. The local interconnect 41a is connected to the pad 22a. The local interconnect 41b is connected to the pad 22b. The local interconnect 41c is connected to the pads 22c and 22o. The local interconnect 41d is connected to the pad 22p. The local interconnect 41e is connected to the pad 22d.

[0069] Local wirings 41f to 41n extending in the X direction are formed on the upper part of the cell. The local wiring 41f is connected to the pad 22e. The local wiring 41g is connected to the pad 22h. The local wiring 41h is connected to the pad 22q. The local wiring 41i is connected to the pad 22l. The local wiring 41j is connected to the pads 22f, 22i, and 22r. The local wiring 41k is connected to the pads 22j and 22m. The local wiring 41l is connected to the pad 22g. The local wiring 41m is connected to the pad 22k. The local wiring 41n is connected to the pad 22n.

[0070] The local wiring 41a is connected to the power supply wiring 11 via a contact (via) 51a, and is connected to the local wiring 41g via a contact 51b. The local wiring 41b is connected to the local wiring 41j via a contact 51c. The local wiring 41c is connected to the local wiring 41k via a contact 51d. The local wiring 41e is connected to the power supply wiring 12 via a contact 51e, and is connected to the local wiring 41m via a contact 51f. The local wiring 41j is connected to the gate wiring 35 via a shared contact 61a. The local wiring 41k is connected to the gate wiring 32 via a shared contact 61b.

[0071] That is, the pads of the transistors N1 and N5 are connected to each other by local wiring and contacts, and they share a gate wiring. The pads of the transistors N2 and N6 are connected to each other by local wiring and contacts, and they share a gate wiring. The transistors N1 and N5 correspond to the drive transistor PD1, and the transistors N2 and N6 correspond to the drive transistor PD2. Therefore, in the 2-port SRAM cell according to this embodiment, the drive transistors PD1 and PD2 are each composed of two N-type FETs connected in parallel.

[0072] The local wirings 41b and 41j, the contact 51c, the shared contact 61a and the gate wiring 35 correspond to a first node NA, and the local wirings 41c and 41k, the contact 51d, the shared contact 61b and the gate wiring 32 correspond to a second node NB.

[0073] As shown in FIG. 1(c), wires 71-75 extending in the Y direction from the top to the bottom of the cell are formed in the M1 wiring layer, which is a metal wiring layer. Wires 76-79 are also formed. Wire 71 supplies a voltage VDD. Wires 72-75 correspond to the first bit line BLA, the third bit line BLB, the second bit line BLAX, and the fourth bit line BLBX, respectively.

[0074] Wires 81 and 82 extending in the X direction from the left to right ends of the cell are formed in the M2 wiring layer, which is an upper layer of the M1 wiring layer. The wires 81 and 82 are arranged side by side in the Y direction. The wires 81 and 82 correspond to the first word line WLA and the second word line WLB, respectively.

[0075] The wiring 71 is connected to the local wiring 41h via a contact 91a, and is connected to the local wiring 41d via a contact 91b. The wiring 72 is connected to the local wiring 41f via a contact 91c. The wiring 73 is connected to the local wiring 41l via a contact 91d. The wiring 74 is connected to the local wiring 41i via a contact 91e. The wiring 75 is connected to the local wiring 41n via a contact 91f.

[0076] Moreover, the wiring 76 is connected to the gate wiring 31 through the contact (gate-contact) 61c, and is connected to the wiring 81 through the contact 91g. The wiring 77 is connected to the gate wiring 33 through the contact 61d, and is connected to the wiring 81 through the contact 91h. The wiring 78 is connected to the gate wiring 34 through the contact 61e, and is connected to the wiring 82 through the contact 91i. The wiring 79 is connected to the gate wiring 36 through the contact 61f, and is connected to the wiring 82 through the contact 91j. That is, the wiring 81 is connected to the gate wiring 31 through the contact 91g, the wiring 76, and the contact 61c, and is connected to the gate wiring 33 through the contact 91h, the wiring 77, and the contact 61d. The wiring 82 is connected to the gate wiring 34 through the contact 91i, the wiring 78, and the contact 61e, and is connected to the gate wiring 36 through the contact 91j, the wiring 79, and the contact 61f.

[0077] With the above configuration, the transistor P2 (load transistor PU1) has a pad 22q connected to the wiring 71 that supplies a voltage VDD, a pad 22r connected to the local wiring 41j (first node NA), and a gate wiring 32 connected to the shared contact 61b (second node NB). The transistor P1 (load transistor PU2) has a pad 22p connected to the wiring 71 that supplies a voltage VDD, a pad 22o connected to the local wiring 41c (second node NB), and a gate wiring 35 connected to the shared contact 61a (first node NA). The transistors N1 and N5 (drive transistors PD1) have pads 22b and 22i connected to the local wirings 41b and 41j (first node NA), pads 22a and 22h connected to the power supply wiring 11 that supplies a voltage VSS, and a gate wiring 32 connected to the shared contact 61b (second node NB). In the transistors N2 and N6 (drive transistor PD2), the pads 22c and 22j are connected to the local wirings 41c and 41k (second node NB), the pads 22d and 22k are connected to the power supply wiring 12 that supplies the voltage VSS, and the gate wiring 35 is connected to the shared contact 61a (first node NA). In the transistor N3 (access transistor PG1), the pad 22e is connected to the wiring 72 (first bit line BLA), the pad 22f is connected to the local wiring 41j (first node NA), and the gate wiring 31 is connected to the wiring 81 (first word line WLA). In the transistor N7 (access transistor PG2), the pad 22l is connected to the wiring 74 (second bit line BLAX), the pad 22m is connected to the local wiring 41k (second node NB), and the gate wiring 33 is connected to the wiring 81 (first word line WLA). In the transistor N4 (access transistor PG3), the pad 22g is connected to the wiring 73 (third bit line BLB), the pad 22f is connected to the local wiring 41j (first node NA), and the gate wiring 34 is connected to the wiring 82 (second word line WLB). In the transistor N8 (access transistor PG4), the pad 22n is connected to the wiring 75 (fourth bit line BLBX), the pad 22m is connected to the local wiring 41k (second node NB), and the gate wiring 36 is connected to the wiring 82 (second word line WLB).That is, a two-port SRAM circuit is configured by the transistors N1 to N8, P1, and P2. The transistors N1, N2, and P1 are formed in the lower part of the cell, and the transistors N3 to N8 and P2 are formed in the upper part of the cell. The transistors N1 to N8, P1, and P2 are each a three-dimensional structure transistor. This makes it possible to realize a two-port SRAM cell using a CFET.

[0078] Moreover, the transistors P1 and P2 are formed at the same position in the X direction in a plan view, which makes it possible to reduce the area of ​​the 2-port SRAM cell.

[0079] Moreover, the drive transistor PD1 is composed of transistors N1 and N5 connected in parallel, and the drive transistor PD2 is composed of transistors N2 and N6 connected in parallel. Moreover, the transistors N1 and N2 overlap with the transistors N5 and N6, respectively, in a plan view. This makes it possible to reduce the area while improving the driving capability of the 2-port SRAM cell.

[0080] When 2-port SRAM cells are arranged adjacent to each other in the X direction, they may be arranged inverted in the X direction or may not be arranged inverted in the X direction. When 2-port SRAM cells are arranged adjacent to each other in the Y direction, they are arranged inverted in the Y direction.

[0081] Furthermore, no local wiring is connected to each node of the dummy transistors N21 to N24. Therefore, the dummy transistors N21 to N24 do not affect the logical function of the two-port SRAM cell. Although the dummy transistors N21 to N24 do not necessarily have to be formed, forming the dummy transistors N21 to N24 can suppress manufacturing variations in the semiconductor memory device, improve yields, and improve reliability.

[0082] In addition, the shared contact 61a connecting the local wiring 41j and the gate wiring 35, and the shared contact 61b connecting the local wiring 41k and the gate wiring 32 may be formed in the same process step as the contacts 61c to 61f connecting the wiring arranged in the M1 wiring layer and the gate wiring, or may be formed in a different process step.

[0083] In addition, although the wiring 71 for supplying the voltage VDD is provided in the M1 wiring layer, the wiring for supplying the voltage VDD may be provided in the buried wiring layer. Also, the wiring for supplying the voltage VDD may be provided in both the M1 wiring layer and the buried wiring layer. In this case, the power supply for supplying the voltage VDD is strengthened, so that the power supply can be stabilized.

[0084] Although the transistors N3, N4, N7, and N8 are formed in the upper part of the cell, they may be formed in the lower part of the cell. In this case, the transistors N3, N4, N7, and N8 are formed in the lower part of the cell instead of the dummy transistors N21 to N24. Then, local wiring and contacts are formed in the two-port SRAM cell so that the above-mentioned two-port SRAM circuit is configured.

[0085] (Variation 1) Fig. 4 is a plan view showing another example of the layout structure of the 2-port SRAM cell according to the first embodiment. Specifically, Fig. 4(a) shows the lower part of the cell, Fig. 4(b) shows the upper part of the cell, and Fig. 4(c) shows the M1 and M2 wiring layers. In Fig. 4, in comparison with Fig. 1, in addition to the transistors N1, N2, and P1, transistors N11 to N14, N17, and N18 are formed in the lower part of the cell, and dummy transistors N21 to N24 are omitted. Also, in addition to the transistors N3 to N8, and P2, transistors N15 and N16 are formed in the upper part of the cell.

[0086] Specifically, nanowires 23a, 23c, 23d, 23e, 23i, and 23j extending in the Y direction are formed in the lower part of the cell, and nanowires 23f and 23h extending in the Y direction are formed in the upper part of the cell.

[0087] Nanowires 23a, 23d, and 23i are formed side by side with nanowire 21a in the X-direction. Nanowires 23c, 23e, and 23j are formed side by side with nanowires 21b and 21c in the X-direction. Nanowire 23f is formed side by side with nanowires 21d, 21f, 21g, and 21i in the X-direction. Nanowire 23h is formed side by side with nanowires 21e, 21h, and 21j in the X-direction.

[0088] Moreover, the nanowires 23d and 23i are formed side by side with the nanowires 23e and 23j, respectively, in the Y direction.

[0089] Furthermore, the nanowires 23a, 23c, 23d, 23e, 23i, and 23j overlap with the nanowires 23f, 23h, 21d, 21e, 21i, and 21j, respectively, in a plan view.

[0090] The gate wiring 31 serves as the gate of the transistor N13. The gate wiring 32 serves as the gates of the transistors N11 and N15. The gate wiring 33 serves as the gate of the transistor N17. The gate wiring 34 serves as the gate of the transistor N14. The gate wiring 35 serves as the gates of the transistors N12 and N16. The gate wiring 36 serves as the gate of the transistor N18.

[0091] Pads 24a to 24n doped with an N-type semiconductor are formed at the top end of the nanowire 23a, the bottom end of the nanowire 23a, the top end of the nanowire 23c, the bottom end of the nanowire 23c, the top end of the nanowire 23d, between the nanowires 23d and 23e, the bottom end of the nanowire 23e, the top end of the nanowire 23f, the bottom end of the nanowire 23f, the top end of the nanowire 23h, the bottom end of the nanowire 23h, the top end of the nanowire 23i, between the nanowires 23i and 23j, and the bottom end of the nanowire 23j. The nanowires 23a, 23c, 23d, 23e, 23f, 23h, 23i, and 23j form the channels of the transistors N11 to N18. The pads 24a and 24b form the nodes of the transistor N11. Pads 24c and 24d form the node of transistor N12. Pads 24e and 24f form the node of transistor N13. Pads 24f and 24g form the node of transistor N14. Pads 24h and 24i form the node of transistor N15. Pads 24j and 24k form the node of transistor N16. Pads 24l and 24m form the node of transistor N17. Pads 24m and 24n form the node of transistor N18.

[0092] That is, the nanowire 23a, the gate wiring 32, and the pads 24a and 24b constitute the transistor N11. The nanowire 23c, the gate wiring 35, and the pads 24c and 24d constitute the transistor N12. The nanowire 23d, the gate wiring 31, and the pads 24e and 24f constitute the transistor N13. The nanowire 23e, the gate wiring 34, and the pads 24f and 24g constitute the transistor N14. The nanowire 23f, the gate wiring 32, and the pads 24h and 24i constitute the transistor N15. The nanowire 23h, the gate wiring 35, and the pads 24j and 24k constitute the transistor N16. The nanowire 23i, the gate wiring 33, and the pads 24l and 24m constitute the transistor N17. The nanowire 23j, the gate wiring 36, and the pads 24m and 24n constitute the transistor N18.

[0093] Therefore, the transistors N11 to N14, N17, and N18 overlap with the transistors N15, N16, N3, N4, N7, and N8, respectively, in a plan view.

[0094] In addition, the transistors N11, N13, and N17 are formed side by side with the transistor N1 in the X direction. The transistors N12, N14, and N18 are formed side by side with the transistors N2 and P1 in the X direction. The transistor N15 is formed side by side with the transistors N3, N5, N7, and P2 in the X direction. The transistor N16 is formed side by side with the transistors N4, N6, and N8 in the X direction.

[0095] Moreover, the transistors N13 and N17 are formed side by side with the transistors N14 and N18, respectively, in the Y direction.

[0096] Local wirings 42a to 42d extending in the X direction are formed at the bottom of the cell. Local wiring 42a is connected to pad 24e. Local wiring 42b is connected to pad 24l. Local wiring 42c is connected to pad 24g. Local wiring 42d is connected to pad 24n.

[0097] In the lower part of the cell, the local wiring 41a is connected to the pads 22a and 24a. The local wiring 41b is connected to the pads 22b, 24b, and 24f. The local wiring 41c is connected to the pads 22c, 22o, 24c, and 24m. The local wiring 41e is connected to the pads 22d and 24d.

[0098] In the upper part of the cell, local wiring 41g is connected to pads 22h and 24h. Local wiring 41j is connected to pads 22f, 22i, and 24i. Local wiring 41k is connected to pads 22j, 22m, 22r, and 24j. Local wiring 41m is connected to pads 22k and 24k.

[0099] Local wiring 42a is connected to local wiring 41f via contact 52a. Local wiring 42b is connected to local wiring 41i via contact 52b. Local wiring 42c is connected to local wiring 41l via contact 52c. Local wiring 42d is connected to local wiring 41n via contact 52d.

[0100] That is, the pads of the transistors N1, N5, N11, and N15 are connected to each other by local wiring and contacts, and they share a gate wiring. The pads of the transistors N2, N6, N12, and N16 are connected to each other by local wiring and contacts, and they share a gate wiring. The pads of the transistors N3 and N13 are connected to each other by local wiring and contacts, and they share a gate wiring. The pads of the transistors N4 and N14 are connected to each other by local wiring and contacts, and they share a gate wiring. The pads of the transistors N7 and N17 are connected to each other by local wiring and contacts, and they share a gate wiring. The pads of the transistors N8 and N18 are connected to each other by local wiring and contacts, and they share a gate wiring. In this modified example, transistors N1, N5, N11, and N15 correspond to drive transistor PD1, transistors N2, N6, N12, and N16 correspond to drive transistor PD2, transistors N3 and N13 correspond to access transistor PG1, transistors N7 and N17 correspond to access transistor PG2, transistors N4 and N14 correspond to access transistor PG3, and transistors N8 and N18 correspond to access transistor PG4.

[0101] Therefore, in this modification, the drive transistors PD1, PD2 are each composed of four N-type FETs connected in parallel, and the access transistors PG1 to PG4 are each composed of two N-type FETs connected in parallel. Also, the transistors corresponding to the drive transistors PD1, PD2 and the transistors corresponding to the access transistors PG1 to PG4 are stacked. Thus, this modification can provide the same effects as the 2-port SRAM cell according to the first embodiment.

[0102] Moreover, the drive transistor PD1 is composed of transistors N1, N5, N11, and N15 connected in parallel, the drive transistor PD2 is composed of transistors N2, N6, N12, and N16 connected in parallel, the access transistor PG1 is composed of transistors N3 and N13 connected in parallel, the access transistor PG2 is composed of transistors N7 and N17 connected in parallel, the access transistor PG3 is composed of transistors N4 and N14 connected in parallel, and the access transistor PG4 is composed of transistors N8 and N18 connected in parallel. Moreover, the transistors N11 to N14, N17, and N18 overlap with the transistors N15, N16, N3, N4, N7, and N8, respectively, in a plan view. This makes it possible to improve the driving capability of the 2-port SRAM cell while reducing the area.

[0103] (Variation 2) 5 is a plan view showing another example of the layout structure of the 2-port SRAM cell according to the first embodiment. Specifically, FIG. 5(a) shows the lower part of the cell, FIG. 5(b) shows the upper part of the cell, and FIG. 5(c) shows the M1 and M2 wiring layers. In FIG. 5, in comparison with FIG. 1, the transistor P1 is formed in the upper part of the cell. Also, dummy transistors N25 and N26 are formed in the lower part of the cell.

[0104] Specifically, nanowire 21b is formed in the upper part of the cell, and nanowires 28a and 28b extending in the Y direction are formed in the lower part of the cell.

[0105] Nanowire 21b is formed side by side with nanowires 21e, 21h, and 21j in the X direction. Nanowire 28a is formed side by side with nanowires 21a, 26a, and 26c in the X direction. Nanowire 28b is formed side by side with nanowires 21c, 26b, and 26d in the X direction.

[0106] Moreover, the nanowires 21g and 21b overlap with the nanowires 28a and 28b, respectively, in a plan view.

[0107] Dummy pads 29a to 29d doped with an N-type semiconductor are formed at the upper end of nanowire 28a in the drawing, the lower end of nanowire 28a in the drawing, the upper end of nanowire 28b in the drawing, and the lower end of nanowire 28b in the drawing. Nanowires 28a and 28b form channels of dummy transistors N25 and N26, respectively. Dummy pads 29a and 29b form a node of dummy transistor N25, and dummy pads 29c and 29d form a node of dummy transistor N26. Dummy transistors N25 and N26 are transistors that do not have a logic function.

[0108] Therefore, the transistors P2 and P1 overlap with the dummy transistors N25 and N26, respectively, in a plan view.

[0109] The transistor P1 is arranged in the X-direction with the transistors N4, N6, and N8. The dummy transistor N25 is arranged in the X-direction with the transistor N1 and the dummy transistors N21 and N23. The dummy transistor N26 is arranged in the X-direction with the transistor N2 and the dummy transistors N22 and N24.

[0110] At the bottom of the cell, the local wiring 41c is connected to the pad 22c. At the top of the cell, the local wiring 41k is connected to the pads 22o, 22j, and 22m.

[0111] In this modification, each transistor including the dummy transistor is stacked. Also, the transistor including the dummy transistor formed in the lower part of the cell is only an N-type FET. Thus, this modification can obtain the same effect as the 2-port SRAM cell according to the first embodiment.

[0112] In addition, the transistors N3 to N8, P2, and P1 overlap with the dummy transistors N21 and N22, the transistors N1 and N2, and the dummy transistors N23 to N26, respectively, in a plan view. That is, each transistor including the dummy transistors is stacked with other transistors. This eliminates the need to remove some of the transistors, and thus makes it possible to suppress the complication of the manufacturing process.

[0113] In addition, transistors N1, N2 and dummy transistors N21 to N26 are formed in the lower part of the cell, and transistors P1, P2, N3 to N8 are formed in the upper part of the cell. That is, only N-type FETs are arranged in the lower part of the cell, and the above configuration can be realized by replacing some of the transistors arranged in the upper part of the cell with N-type FETs. This makes it possible to suppress the complication of the manufacturing process.

[0114] (Variation 3) 6 is a plan view showing another example of the layout structure of the 2-port SRAM cell according to the first embodiment. Specifically, FIG. 6(a) shows the lower part of the cell, FIG. 6(b) shows the upper part of the cell, and FIG. 6(c) shows the M1 and M2 wiring layers. In FIG. 6, in comparison with FIG. 1, in addition to the transistors N1 and N2, the transistors N11 to N14, N17, and N18 and the dummy transistors N25 and N26 are formed in the lower part of the cell, and the dummy transistors N21 to N24 are omitted. Also, in addition to the transistors N3 to N8 and P2, the transistors N15, N16, and P1 are formed in the upper part of the cell.

[0115] Local wirings 42a to 42d are formed in the lower part of the cell. In the upper part of the cell, local wiring 41j is connected to pads 22f, 22i, 22r, and 24i. Local wiring 41k is connected to pads 22j, 22m, 22o, and 24j.

[0116] In this modified example, transistors N1, N5, N11, and N15 correspond to drive transistor PD1, transistors N2, N6, N12, and N16 correspond to drive transistor PD2, transistors N3 and N13 correspond to access transistor PG1, transistors N7 and N17 correspond to access transistor PG2, transistors N4 and N14 correspond to access transistor PG3, and transistors N8 and N18 correspond to access transistor PG4.

[0117] Therefore, in this modification, the drive transistors PD1 and PD2 are each composed of four N-type FETs connected in parallel, and the access transistors PG1 to PG4 are each composed of two N-type FETs connected in parallel. Moreover, each transistor including the dummy transistor is stacked. Moreover, the transistors including the dummy transistors formed in the lower part of the cell are only N-type FETs. Thus, with this modification, it is possible to obtain the same effects as the 2-port SRAM cell according to the first embodiment.

[0118] Moreover, the drive transistor PD1 is composed of transistors N1, N5, N11, and N15 connected in parallel, the drive transistor PD2 is composed of transistors N2, N6, N12, and N16 connected in parallel, the access transistor PG1 is composed of transistors N3 and N13 connected in parallel, the access transistor PG2 is composed of transistors N7 and N17 connected in parallel, the access transistor PG3 is composed of transistors N4 and N14 connected in parallel, and the access transistor PG4 is composed of transistors N8 and N18 connected in parallel. Moreover, the transistors N11 to N14, N17, and N18 overlap with the transistors N15, N16, N3, N4, N7, and N8, respectively, in a plan view. This makes it possible to improve the driving capability of the 2-port SRAM cell while reducing the area.

[0119] In addition, the transistors N3 to N8, N15, N16, P1, and P2 overlap with the transistors N13, N14, N1, N2, N17, N18, N11, and N12 and the dummy transistors N26 and N25 in plan view. That is, each transistor including the dummy transistor is stacked with other transistors. This eliminates the need to remove some of the transistors, and thus makes it possible to suppress the complication of the manufacturing process.

[0120] In addition, transistors N1, N2, N11 to N14, N17, and N18 and dummy transistors N25 and N26 are formed in the lower part of the cell, and transistors N3 to N8, N15, N16, P1, and P2 are formed in the upper part of the cell. That is, only N-type FETs are arranged in the lower part of the cell, and the above configuration can be realized by replacing some of the transistors arranged in the upper part of the cell with N-type FETs. This makes it possible to suppress the complication of the manufacturing process.

[0121] (Variation 4) 7 is a plan view showing another example of the layout structure of the 2-port SRAM cell according to the first embodiment. Specifically, FIG. 7(a) shows the lower part of the cell, FIG. 7(b) shows the upper part of the cell, and FIG. 7(c) shows the M1 and M2 wiring layers. In FIG. 7, in comparison with FIG. 1, in addition to the transistors N1 and N2 and the dummy transistors N21 to N24, transistors N5 and N6 are formed in the lower part of the cell. Also, in addition to the transistors N3, N4, N7, N8, and P2, transistor P1 and dummy transistors P21 and P22 are formed in the upper part of the cell.

[0122] Specifically, nanowires 21f and 21h are formed in the lower part of the cell, and nanowire 21b and nanowires 28c and 28d extending in the Y direction are formed in the upper part of the cell.

[0123] Nanowire 21f is formed side by side with nanowires 21a, 26a, and 26c in the X direction. Nanowire 21h is formed side by side with nanowires 21c, 26b, and 26d in the X direction. Nanowire 28c is formed side by side with nanowires 21d, 21g, and 21i in the X direction. Nanowires 21b and 28d are formed side by side with nanowires 21e and 21j in the X direction.

[0124] Moreover, the nanowires 21a, 21f, 21c, and 21h overlap with the nanowires 21g, 28c, 28d, and 21b, respectively, in a plan view.

[0125] Dummy pads 29e to 29h doped with a P-type semiconductor are formed at the upper end of nanowire 28c in the drawing, the lower end of nanowire 28c in the drawing, the upper end of nanowire 28d in the drawing, and the lower end of nanowire 28d in the drawing. Nanowires 28c and 28d form channels of dummy transistors P21 and P22, respectively. Dummy pads 29e and 29f form the node of dummy transistor P21, and dummy pads 29g and 29h form the node of dummy transistor P22. Note that dummy transistors P21 and P22 are transistors that do not have a logic function.

[0126] Therefore, the transistors P1, P2 and the dummy transistors P21, P22 overlap with the transistors N6, N1, N5, N2, respectively, in a plan view.

[0127] Moreover, the transistors N5 and N6 are formed side by side with the transistors N1 and N2, respectively, in the X direction.

[0128] As shown in Fig. 7(c), wirings 71a and 71b extending in the X direction are formed in the M1 wiring layer. The wirings 71a and 71b each supply a voltage VDD. The wiring 71a is connected to the local wiring 41h via a contact 91a. The wiring 71b is connected to the local wiring 41d via a contact 91b.

[0129] In this modification, transistors corresponding to the drive transistors PD1 and PD2 are formed side by side in the X direction at the bottom of the cell. Also, transistors corresponding to the load transistors PU1 and PU2 are formed at the top of the cell and are stacked with the transistors corresponding to the drive transistors PD1 and PD2. This modification provides the same effects as the 2-port SRAM cell according to the first embodiment.

[0130] In addition, the transistors N1, N2, N5, and N6 and the dummy transistors N21 to N24 overlap the transistor P2, the dummy transistors P22 and P21, and the transistors P1, N3, N4, N7, and N8, respectively, in a plan view. That is, each transistor including the dummy transistors is stacked with other transistors. This makes it unnecessary to remove some of the transistors, and thus makes it possible to suppress the complication of the manufacturing process.

[0131] In addition, transistors N1, N2, N5, and N6 and dummy transistors N21 to N24 are formed in the lower part of the cell, and transistors N3, N4, N7, N8, P1, and P2 and dummy transistors P21 and P22 are formed in the upper part of the cell. That is, only N-type FETs are arranged in the lower part of the cell, and the above configuration can be realized by replacing some of the transistors arranged in the upper part of the cell with N-type FETs. This makes it possible to suppress the complication of the manufacturing process.

[0132] Second embodiment FIG. 8 is a diagram showing an example of a layout structure of a two-port SRAM cell according to the second embodiment. Specifically, FIG. 8(a) shows the lower part of the cell, FIG. 8(b) shows the upper part of the cell, and FIG. 8(c) shows the M1 and M2 wiring layers. In FIG. 8, transistors N1, N2, N7, N8, N47, N48, and P1 are formed in the lower part of the cell, and transistors N3 to N6, N43, N44, and P2 are formed in the upper part of the cell. In FIG. 8, another two-port SRAM cell is arranged adjacent to the two-port SRAM cell according to this embodiment in the X direction. Specifically, transistors N43 and N44 are transistors included in the two-port SRAM cell arranged on the right side of the two-port SRAM cell according to this embodiment. Also, transistors N47 and N48 are transistors included in the two-port SRAM cell arranged on the left side of the two-port SRAM cell according to this embodiment.

[0133] More specifically, nanowires 21i and 21j are formed in the lower part of the cell. Nanowires 121i and 121j extending in the Y direction are formed in the lower part of the cell at the left end in the drawing, and nanowires 121d and 121e extending in the Y direction are formed in the upper part of the cell at the right end in the drawing.

[0134] Nanowire 121d is formed side by side with nanowires 21d, 21f, and 21g in the X direction. Nanowire 121e is formed side by side with nanowires 21e and 21h in the X direction. Nanowire 121i is formed side by side with nanowires 21a and 21i in the X direction. Nanowire 121j is formed side by side with nanowires 21b, 21c, and 21j in the X direction.

[0135] Moreover, the nanowires 121d and 121e are formed side by side in the Y direction. The nanowires 121i and 121j are formed side by side in the Y direction.

[0136] Moreover, the nanowires 121d, 121e, 121i, and 121j overlap with the nanowires 21i, 21j, 21d, and 21e, respectively, in a plan view.

[0137] The gate wiring 33 serves as the gate of the transistor N43. The gate wiring 36 serves as the gate of the transistor N44. The gate wiring 31 serves as the gate of the transistor N47. The gate wiring 34 serves as the gate of the transistor N48.

[0138] That is, the transistors N43 and N44 overlap with the transistors N7 and N8, respectively, in a plan view. The transistors N47 and N48 overlap with the transistors N3 and N4, respectively, in a plan view.

[0139] In addition, the transistor N43 is formed side by side with the transistors N3, N5, and P2 in the X direction. The transistor N44 is formed side by side with the transistors N4 and N6 in the X direction. The transistor N47 is formed side by side with the transistors N1 and N7 in the X direction. The transistor N48 is formed side by side with the transistors N2, N8, and P1 in the X direction.

[0140] Moreover, the transistors N43 and N44 are formed side by side in the Y direction. The transistors N47 and N48 are formed side by side in the Y direction.

[0141] At the bottom of the cell, the local wiring 41c is connected to the pads 22c, 22m, and 22o, and at the top of the cell, the local wiring 41k is connected to the pad 22j.

[0142] With the above configuration, a two-port SRAM circuit is formed by the transistors N1 to N8, P1, and P2. The transistors N1, N2, N7, N8, and P1 are formed in the lower part of the cell, and the transistors N3 to N6 and P2 are formed in the upper part of the cell. The transistors N1 to N8, P1, and P2 are each a three-dimensional structure transistor. This makes it possible to realize a two-port SRAM cell using a CFET.

[0143] Moreover, the transistors P1 and P2 are formed at the same position in the X direction in a plan view, which makes it possible to reduce the area of ​​the 2-port SRAM cell.

[0144] Moreover, the drive transistor PD1 is composed of transistors N1 and N5 connected in parallel, and the drive transistor PD2 is composed of transistors N2 and N6 connected in parallel. Moreover, the transistors N1 and N2 overlap with the transistors N5 and N6, respectively, in a plan view. This makes it possible to reduce the area while improving the driving capability of the 2-port SRAM cell.

[0145] Moreover, the transistors N43 and N44 correspond to the transistors N3 and N4 in the two-port SRAM cell arranged on the right side of the drawing of the two-port SRAM cell according to this embodiment. Moreover, the transistors N47 and N48 correspond to the transistors N7 and N8 in the two-port SRAM cell arranged on the left side of the drawing of the two-port SRAM cell according to this embodiment. Moreover, the transistors N43 and N44 overlap with the transistors N7 and N8 in a plan view, respectively, and the transistors N47 and N48 overlap with the transistors N3 and N4 in a plan view, respectively. That is, the transistor N3 corresponding to the access transistor PG1 is stacked with the transistor N47 corresponding to the access transistor PG2 of the two-port SRAM cell adjacent to the left side of the drawing. The transistor N7 corresponding to the access transistor PG2 is stacked with the transistor N43 corresponding to the access transistor PG1 of the two-port SRAM cell adjacent to the right side of the drawing. The transistor N4 corresponding to the access transistor PG3 is stacked with the transistor N48 corresponding to the access transistor PG4 of the two-port SRAM cell adjacent to the left side of the drawing. The transistor N8 corresponding to the access transistor PG4 is stacked with the transistor N44 corresponding to the access transistor PG3 of the adjacent 2-port SRAM cell on the right side of the drawing, thereby making it possible to reduce the area of ​​the 2-port SRAM cell.

[0146] In this embodiment, two-port SRAM cells adjacent to each other in the X direction are arranged without being inverted in the X direction, while two-port SRAM cells adjacent to each other in the Y direction are arranged with being inverted in the Y direction.

[0147] Alternatively, the transistors N3, N4, N43, and N44 may be formed in the lower part of the cell, and the transistors N7, N8, N47, and N48 may be formed in the upper part of the cell. In this case, local wiring and contacts are formed so that a 2-port SRAM cell circuit is formed in the 2-port SRAM cell according to this embodiment.

[0148] (Variation 1) 9 is a diagram showing another example of the layout structure of the 2-port SRAM cell according to the second embodiment. Specifically, FIG. 9(a) shows the lower part of the cell, FIG. 9(b) shows the upper part of the cell, and FIG. 9(c) shows the M1 and M2 wiring layers. In FIG. 9, in comparison with FIG. 8, the transistor P1 is formed in the upper part of the cell. Also, dummy transistors N25 and N26 are formed in the lower part of the cell.

[0149] Specifically, nanowire 21b is formed in the upper part of the cell, and nanowires 28a and 28b are formed in the lower part of the cell.

[0150] Nanowire 21b is formed side by side with nanowires 21e, 21h, and 121e in the X direction. Nanowire 28a is formed side by side with nanowires 21a, 21i, and 121i in the X direction. Nanowire 28b is formed side by side with nanowires 21c, 21j, and 121j in the X direction.

[0151] Moreover, the nanowires 21g and 21b overlap with the nanowires 28a and 28b, respectively, in a plan view.

[0152] That is, the transistors P2 and P1 overlap with the dummy transistors N25 and N26, respectively, in a plan view.

[0153] The transistor P1 is arranged in the X direction with the transistors N4, N6, and N44. The dummy transistor N25 is arranged in the X direction with the transistors N1, N7, and N47. The dummy transistor N26 is arranged in the X direction with the transistors N2, N8, and N48.

[0154] At the bottom of the cell, the local wiring 41c is connected to the pads 22c and 22m, and at the top of the cell, the local wiring 41k is connected to the pads 22j and 22o.

[0155] In this modification, each transistor including the dummy transistor is stacked. Also, the transistor including the dummy transistor formed in the lower part of the cell is only an N-type FET. And, in this modification, the same effect as that of the SRAM cell according to the second embodiment can be obtained.

[0156] In addition, the transistors N1, N2, N7, N8, N47, and N48 and the dummy transistors N25 and N26 overlap with the transistors N5, N6, N43, N44, N3, N4, P2, and P1, respectively, in a plan view. That is, each transistor including the dummy transistors is stacked with other transistors. This eliminates the need to remove some of the transistors, thereby making it possible to suppress the complication of the manufacturing process.

[0157] In addition, transistors N1, N2, N7, N8, N47, N48 and dummy transistors N25, N26 are formed in the lower part of the cell, and transistors N3 to N6, N43, N44, P1, P2 are formed in the upper part of the cell. That is, only N-type FETs are arranged in the lower part of the cell, and the above configuration can be realized by replacing some of the transistors arranged in the upper part of the cell with N-type FETs. This makes it possible to suppress the complication of the manufacturing process.

[0158] (Variation 2) 10 is a diagram showing another example of the layout structure of the 2-port SRAM cell according to the second embodiment. Specifically, FIG. 10(a) shows the lower part of the cell, FIG. 10(b) shows the upper part of the cell, and FIG. 10(c) shows the M1 and M2 wiring layers. In FIG. 10, in comparison with FIG. 8, in addition to the transistors N1, N2, N7, N8, N47, and N48, transistors N5 and N6 are formed in the lower part of the cell. Also, in addition to the transistors N3, N4, N43, N44, and P2, transistor P1 and dummy transistors P21 and P22 are formed in the upper part of the cell.

[0159] Specifically, nanowires 21f and 21h are formed in the lower part of the cell, and nanowires 21b, 28c and 28d are formed in the upper part of the cell.

[0160] Nanowire 21f is formed side by side with nanowires 21a, 21i, and 121i in the X direction. Nanowire 21h is formed side by side with nanowires 21c, 21j, and 121j in the X direction. Nanowire 28c is formed side by side with nanowires 21d, 21g, and 121d in the X direction. Nanowires 21b and 28d are formed side by side with nanowires 21e and 121e in the X direction.

[0161] Moreover, the nanowires 21a, 21f, 21c, and 21h overlap with the nanowires 21g, 28c, 28d, and 21b, respectively, in a plan view.

[0162] That is, the transistors P1, P2 and the dummy transistors P21, P22 overlap with the transistors N6, N1, N5, N2, respectively, in a plan view.

[0163] The transistor N5 is formed side by side with the transistors N1, N7, and N47 in the X direction. The transistor N6 is formed side by side with the transistors N2, N6, N8, and N48 in the X direction.

[0164] In addition, at the bottom of the cell, local wiring 41a is connected to pads 22a and 22h. Local wiring 41b is connected to pads 22b and 22i. Local wiring 41c is connected to pads 22c, 22j, and 22m. Local wiring 41e is connected to pads 22d and 22k. At the top of the cell, local wiring 41k is connected to pad 22o.

[0165] In this modification, transistors corresponding to the drive transistors PD1 and PD2 are formed side by side in the X direction at the bottom of the cell. Also, transistors corresponding to the load transistors PU1 and PU2 are formed at the top of the cell and are stacked with the transistors corresponding to the drive transistors PD1 and PD2. This modification provides the same effects as the 2-port SRAM cell according to the second embodiment.

[0166] In addition, the transistors N1, N2, N5 to N8, N47, and N48 overlap the transistor P2, the dummy transistors P22 and P21, and the transistors P1, N43, N44, N3, and N4, respectively, in a plan view. That is, each transistor including the dummy transistor is stacked with other transistors. This makes it unnecessary to remove some of the transistors, and thus makes it possible to suppress the complication of the manufacturing process.

[0167] In addition, transistors N1, N2, N5 to N8, N47, and N48 are formed in the lower part of the cell, and transistors N3, N4, N43, N44, P1, and P2 and dummy transistors P21 and P22 are formed in the upper part of the cell. That is, only N-type FETs are arranged in the lower part of the cell, and the above configuration can be realized by replacing some of the transistors arranged in the upper part of the cell with N-type FETs. This makes it possible to suppress the complication of the manufacturing process.

[0168] (Variation 3) Figures 11 and 12 are diagrams showing another example of the layout structure of the 2-port SRAM cell according to the second embodiment. Specifically, Figures 11(a) and 12(a) show the lower part of the cell, Figures 11(b) and 12(b) show the upper part of the cell, and Figures 11(c) and 12(c) show the M1 and M2 wiring layers.

[0169] In FIG. 11, in comparison with FIG. 8, in addition to the transistors N1, N2, N47, N48, and P1, transistors N43 and N44 are formed in the lower part of the cell. Also, in addition to the transistors N3 to N6, and P2, transistors N7 and N8 are formed in the upper part of the cell. In FIG. 12, in comparison with FIG. 8, in addition to the transistors N1, N2, N7, N8, and P1, transistors N3 and N4 are formed in the lower part of the cell. Also, in addition to the transistors N5, N6, N43, N44, and P2, transistors N47 and N48 are formed in the upper part of the cell.

[0170] In this modification, the two-port SRAM cells shown in Fig. 11 and Fig. 12 are alternately arranged adjacent to each other in the X direction. Specifically, in Fig. 11, the transistors N43 and N44 are transistors included in the two-port SRAM cell shown in Fig. 12 arranged on the right side of the drawing, and the transistors N47 and N48 are transistors included in the two-port SRAM cell shown in Fig. 12 arranged on the left side of the drawing. Also, in Fig. 12, the transistors N43 and N44 are transistors included in the two-port SRAM cell shown in Fig. 11 arranged on the right side of the drawing, and the transistors N47 and N48 are transistors included in the two-port SRAM cell shown in Fig. 11 arranged on the left side of the drawing.

[0171] 11 and 12, the nanowires 21d, 21e, 21i, and 21j overlap with the nanowires 121i, 121j, 121d, and 121e, respectively, in a planar view. That is, the transistors N3, N4, N7, and N8 overlap with the transistors N47, N48, N43, and N44, respectively, in a planar view.

[0172] 11, nanowires 121d, 121e, 121i, and 121j are formed in the lower part of the cell, and nanowires 21d, 21e, 21i, and 21j are formed in the upper part of the cell. Nanowires 21a, 121d, and 121i are formed side by side in the X direction. Nanowires 21b, 21c, 121e, and 121j are formed side by side in the X direction. Nanowires 21d, 21f, 21g, and 21i are formed side by side in the X direction. Nanowires 21e, 21h, and 21j are formed side by side in the X direction.

[0173] 11, transistors N43, N44, N47, and N48 are formed in the lower part of the cell, and transistors N3, N4, N7, and N8 are formed in the upper part of the cell. Transistors N1, N43, and N47 are formed side by side in the X direction. Transistors N2, N44, N48, and P1 are formed side by side in the X direction. Transistors N3, N5, N7, and P2 are formed side by side in the X direction. Transistors N4, N6, and N8 are formed side by side in the X direction.

[0174] In Fig. 12, nanowires 21d, 21e, 21i, and 21j are formed in the lower part of the cell, and nanowires 121d, 121e, 121i, and 121j are formed in the upper part of the cell. Nanowires 21a, 21d, and 21i are formed side by side in the X direction. Nanowires 21b, 21c, 21e, and 21j are formed side by side in the X direction. Nanowires 21f, 21g, 121d, and 121i are formed side by side in the X direction. Nanowires 21h, 121e, and 121j are formed side by side in the X direction.

[0175] 12, transistors N3, N4, N7, and N8 are formed in the lower part of the cell, and transistors N43, N44, N47, and N48 are formed in the upper part of the cell. Transistors N1, N3, and N7 are formed side by side in the X direction. Transistors N2, N4, N8, and P1 are formed side by side in the X direction. Transistors N5, N43, N47, and P2 are formed side by side in the X direction. Transistors N6, N44, and N48 are formed side by side in the X direction.

[0176] In this modification, transistors corresponding to the access transistors PG1 to PG4 are formed only in either the upper or lower part of the cell. Transistors corresponding to the load transistors are formed at the same positions in the X direction. Transistors corresponding to the drive transistors PD1 and PD2 are stacked. This modification can provide the same effects as the 2-port SRAM cell according to the second embodiment.

[0177] Also, in FIG. 11, transistors N3, N4, N7, and N8 are formed in the upper part of the cell. In FIG. 12, transistors N3, N4, N7, and N8 are formed in the lower part of the cell. That is, in FIG. 11 and FIG. 12, transistors corresponding to the access transistors PG1 to PG4 are formed only in either the upper part or the lower part of the cell. That is, even if the device characteristics of the transistors formed in the upper part of the cell and the lower part of the cell are different, since the transistors corresponding to the access transistors PG1 to PG4 are formed in the same layer (either the upper part of the cell or the lower part of the cell), there is no deviation in characteristics between the first and second complementary bit line pairs (between the first and second bit lines BLA, BLAX, and between the third and fourth bit lines BLB, BLBX). This makes it possible to suppress variations in transistor performance between the first and second complementary bit line pairs. Therefore, the operating margin is increased and the operation is stabilized in the semiconductor memory device.

[0178] 11 and 12, the transistors P1 and P2 are formed at the same position in the X direction in a plan view, which makes it possible to reduce the area of ​​the 2-port SRAM cell.

[0179] 11 and 12, the drive transistor PD1 is composed of transistors N1 and N5 connected in parallel, and the drive transistor PD2 is composed of transistors N2 and N6 connected in parallel. The transistors N1 and N2 overlap with the transistors N5 and N6, respectively, in a plan view. This makes it possible to reduce the area of ​​the 2-port SRAM cell while improving the driving capability.

[0180] 11 and 12, the 2-port SRAM cell shown in FIG. 12 is arranged adjacent to the 2-port SRAM cell shown in FIG. 11 without being inverted in the X direction, but the 2-port SRAM cell shown in FIG. 12 may be arranged adjacent to the 2-port SRAM cell shown in FIG. 12 by inverting it in the X direction. In this case, for example, in FIG. 11, the transistors N43 and N44 correspond to the transistors N7 and N8, respectively, in the 2-port SRAM cell shown in FIG. 12 arranged on the right side of the drawing. Also, the transistors N47 and N48 correspond to the transistors N3 and N4, respectively, in the 2-port SRAM cell shown in FIG. 12 arranged on the left side of the drawing.

[0181] (Variation 4) Figures 13 and 14 are diagrams showing another example of the layout structure of the 2-port SRAM cell according to the second embodiment. Specifically, Figures 13(a) and 14(a) show the lower part of the cell, Figures 13(b) and 14(b) show the upper part of the cell, and Figures 13(c) and 14(c) show the M1 and M2 wiring layers.

[0182] In FIG. 13, in contrast to FIG. 8, in addition to the transistors N1, N2, N47, and N48, transistors N43, N44, and dummy transistors N25, N26 are formed in the lower part of the cell. Also, in addition to the transistors N3 to N6, and P2, transistors N7, N8, and P1 are formed in the upper part of the cell. In FIG. 14, in contrast to FIG. 8, in addition to the transistors N1, N2, N7, and N8, transistors N3, N4, and dummy transistors N25, N26 are formed in the lower part of the cell. Also, in addition to the transistors N5, N6, N43, N44, and P2, transistors N47, N48, and P1 are formed in the upper part of the cell.

[0183] In this modification, the two-port SRAM cells shown in Fig. 13 and Fig. 14 are alternately arranged adjacent to each other in the X direction. Specifically, in Fig. 13, the transistors N43 and N44 are transistors included in the two-port SRAM cell shown in Fig. 14 arranged on the right side of the drawing, and the transistors N47 and N48 are transistors included in the two-port SRAM cell shown in Fig. 14 arranged on the left side of the drawing. Also, in Fig. 14, the transistors N43 and N44 are transistors included in the two-port SRAM cell shown in Fig. 13 arranged on the right side of the drawing, and the transistors N47 and N48 are transistors included in the two-port SRAM cell shown in Fig. 13 arranged on the left side of the drawing.

[0184] 13 and 14, the nanowires 21d, 21e, 21i, and 21j overlap with the nanowires 121i, 121j, 121d, and 121e, respectively, in a planar view. That is, the transistors N3, N4, N7, and N8 overlap with the transistors N47, N48, N43, and N44, respectively, in a planar view.

[0185] 13 and 14, the nanowire 21b is formed in the upper part of the cell, and the nanowires 28a and 28b are formed in the lower part of the cell. The nanowires 21g and 21b overlap the nanowires 28a and 28b, respectively, in a planar view. That is, the transistors P2 and P1 overlap the dummy transistors N25 and N26, respectively, in a planar view.

[0186] In Fig. 13, nanowires 121d, 121e, 121i, and 121j are formed in the lower part of the cell, and nanowires 21d, 21e, 21i, and 21j are formed in the upper part of the cell. Nanowires 21a, 28a, 121d, and 121i are formed side by side in the X direction. Nanowires 21c, 28b, 121e, and 121j are formed side by side in the X direction. Nanowires 21d, 21f, 21g, and 21i are formed side by side in the X direction. Nanowires 21b, 21e, 21h, and 21j are formed side by side in the X direction.

[0187] 13, transistors N1, N43, N47 and dummy transistor N25 are formed side by side in the X direction. Transistors N2, N44, N48 and dummy transistor N26 are formed side by side in the X direction. Transistors N3, N5, N7, P2 are formed side by side in the X direction. Transistors N4, N6, N8, P1 are formed side by side in the X direction.

[0188] In Fig. 14, nanowires 21d, 21e, 21i, and 21j are formed in the lower part of the cell, and nanowires 121d, 121e, 121i, and 121j are formed in the upper part of the cell. Nanowires 21a, 21d, 21i, and 28a are formed side by side in the X direction. Nanowires 21c, 21e, 21j, and 28b are formed side by side in the X direction. Nanowires 21f, 21g, 121d, and 121i are formed side by side in the X direction. Nanowires 21b, 21h, 121e, and 121j are formed side by side in the X direction.

[0189] 14, transistors N1, N3, N7 and dummy transistor N25 are formed side by side in the X direction. Transistors N2, N4, N8 and dummy transistor N26 are formed side by side in the X direction. Transistors N5, N43, N47, P2 are formed side by side in the X direction. Transistors N6, N44, N48, P1 are formed side by side in the X direction.

[0190] In this modification, transistors corresponding to the access transistors PG1 to PG4 are formed only in either the upper or lower part of the cell. Moreover, each transistor including the dummy transistor is stacked. Moreover, the transistors including the dummy transistor formed in the lower part of the cell are only N-type FETs. Thus, this modification can obtain the same effects as the 2-port SRAM cell according to the second embodiment.

[0191] Also, in FIG. 13, transistors N3, N4, N7, and N8 are formed in the upper part of the cell. In FIG. 14, transistors N3, N4, N7, and N8 are formed in the lower part of the cell. That is, in FIG. 13 and FIG. 14, transistors corresponding to the access transistors PG1 to PG4 are formed only in either the upper part or the lower part of the cell. That is, even if the device characteristics of the transistors formed in the upper part of the cell and the lower part of the cell are different, since the transistors corresponding to the access transistors PG1 to PG4 are formed in the same layer (either the upper part or the lower part of the cell), there is no deviation in characteristics between the first and second complementary bit line pairs (between the first and second bit lines BLA, BLAX, and between the third and fourth bit lines BLB, BLBX). This makes it possible to suppress variations in transistor performance between the first and second complementary bit line pairs. Therefore, the operating margin is increased and the operation is stabilized in the semiconductor memory device.

[0192] 13 and 14, the transistors N1, N2, N43, N44, N47, and N48 and the dummy transistors N25 and N26 overlap with the transistors N5 to N8, N3, N4, P2, and P1, respectively, in a plan view. That is, in FIG. 13 and FIG. 14, each transistor including the dummy transistor is stacked with other transistors. This makes it unnecessary to remove some of the transistors, and thus makes it possible to suppress the complication of the manufacturing process.

[0193] In addition, in FIG. 13, the transistors N1, N2, N43, N44, N47, and N48 and the dummy transistors N25 and N26 are formed in the lower part of the cell, and the transistors N3 to N8, P1, and P2 are formed in the upper part of the cell. In FIG. 14, the transistors N1 to N4, N7, and N8 and the dummy transistors N25 and N26 are formed in the lower part of the cell, and the transistors N5, N6, N43, N44, N47, N48, P1, and P2 are formed in the upper part of the cell. That is, in FIG. 13 and FIG. 14, only N-type FETs are arranged in the lower part of the cell, and the above configuration can be realized by replacing some of the transistors arranged in the upper part of the cell with N-type FETs. This makes it possible to suppress the complication of the manufacturing process.

[0194] 13 and 14, the 2-port SRAM cell shown in FIG. 14 is arranged adjacent to the 2-port SRAM cell shown in FIG. 13 without being inverted in the X direction, but the 2-port SRAM cell shown in FIG. 14 may be arranged adjacent to the 2-port SRAM cell shown in FIG. 14 by inverting it in the X direction. In this case, for example, in FIG. 13, the transistors N43 and N44 correspond to the transistors N7 and N8, respectively, in the 2-port SRAM cell shown in FIG. 14 arranged on the right side of the drawing. Also, the transistors N47 and N48 correspond to the transistors N3 and N4, respectively, in the 2-port SRAM cell shown in FIG. 14 arranged on the left side of the drawing.

[0195] (Variation 5) Figures 15 and 16 are diagrams showing another example of the layout structure of the 2-port SRAM cell according to the second embodiment. Specifically, Figures 15(a) and 16(a) show the lower part of the cell, Figures 15(b) and 16(b) show the upper part of the cell, and Figures 15(c) and 16(c) show the M1 and M2 wiring layers.

[0196] In FIG. 15, in contrast to FIG. 8, in addition to the transistors N1, N2, N47, and N48, transistors N5, N6, N43, and N44 are formed in the lower part of the cell. Also, in addition to the transistors N3, N4, and P2, transistors N7, N8, and P1 and dummy transistors P21 and P22 are formed in the upper part of the cell. In FIG. 16, in contrast to FIG. 8, in addition to the transistors N1, N2, N7, and N8, transistors N3 to N6 are formed in the lower part of the cell. Also, in addition to the transistors N43, N44, and P2, transistors N47, N48, P1 and dummy transistors P21 and P22 are formed in the upper part of the cell.

[0197] In this modification, the two-port SRAM cells shown in Fig. 15 and Fig. 16 are alternately arranged adjacent to each other in the X direction. Specifically, in Fig. 15, the transistors N43 and N44 are transistors included in the two-port SRAM cell shown in Fig. 16 arranged on the right side of the drawing, and the transistors N47 and N48 are transistors included in the two-port SRAM cell shown in Fig. 16 arranged on the left side of the drawing. Also, in Fig. 16, the transistors N43 and N44 are transistors included in the two-port SRAM cell shown in Fig. 15 arranged on the right side of the drawing, and the transistors N47 and N48 are transistors included in the two-port SRAM cell shown in Fig. 15 arranged on the left side of the drawing.

[0198] 15 and 16, the nanowires 21d, 21e, 21i, and 21j overlap with the nanowires 121i, 121j, 121d, and 121e, respectively, in a planar view. That is, the transistors N3, N4, N7, and N8 overlap with the transistors N47, N48, N44, and N47, respectively, in a planar view.

[0199] 15 and 16, nanowires 21f and 21h are formed in the lower part of the cell, and nanowires 28c and 28d are formed in the upper part of the cell. Nanowires 21a, 21f, 21c, and 21h overlap with nanowires 21g, 28c, 28d, and 21b, respectively, in plan view. That is, transistors P1 and P2 and dummy transistors P21 and P22 overlap with transistors N6, N1, N5, and N2, respectively, in plan view.

[0200] In Fig. 15, nanowires 121d, 121e, 121i, and 121j are formed in the lower part of the cell, and nanowires 21d, 21e, 21i, and 21j are formed in the upper part of the cell. Nanowires 21a, 21f, 121d, and 121i are formed side by side in the X direction. Nanowires 21c, 21h, 121e, and 121j are formed side by side in the X direction. Nanowires 21d, 21g, 21i, and 28c are formed side by side in the X direction. Nanowires 21b, 21e, 21j, and 28d are formed side by side in the X direction.

[0201] 15, transistors N1, N5, N43, and N47 are formed side by side in the X direction. Transistors N2, N6, N44, and N48 are formed side by side in the X direction. Transistors N3, N7, and P2 and a dummy transistor P21 are formed side by side in the X direction. Transistors N4, N8, and P1 and a dummy transistor P22 are formed side by side in the X direction.

[0202] In Fig. 16, nanowires 21d, 21e, 21i, and 21j are formed in the lower part of the cell, and nanowires 121d, 121e, 121i, and 121j are formed in the upper part of the cell. Nanowires 21a, 21d, 21f, and 21i are formed side by side in the X direction. Nanowires 21c, 21e, 21h, and 21j are formed side by side in the X direction. Nanowires 21g, 28c, 121d, and 121i are formed side by side in the X direction. Nanowires 21b, 28d, 121e, and 121j are formed side by side in the X direction.

[0203] 16, transistors N1, N3, N5, and N7 are formed side by side in the X direction. Transistors N2, N4, N6, and N8 are formed side by side in the X direction. Transistors N43, N47, and P2, and a dummy transistor P21 are formed side by side in the X direction. Transistors N44, N48, and P1, and a dummy transistor P22 are formed side by side in the X direction.

[0204] In this modification, transistors corresponding to the access transistors PG1 to PG4 are formed only in either the upper or lower part of the cell. In addition, transistors corresponding to the drive transistors PD1 and PD2 are formed side by side in the X direction in the lower part of the cell. In addition, transistors corresponding to the load transistors PU1 and PU2 are formed in the upper part of the cell, and are stacked with the transistors corresponding to the drive transistors PD1 and PD2. Thus, with this modification, it is possible to obtain the same effect as the 2-port SRAM cell according to the second embodiment.

[0205] Also, in FIG. 15, transistors N3, N4, N7, and N8 are formed in the upper part of the cell. In FIG. 16, transistors N3, N4, N7, and N8 are formed in the lower part of the cell. That is, in FIG. 15 and FIG. 16, transistors corresponding to the access transistors PG1 to PG4 are formed only in either the upper part or the lower part of the cell. That is, even if the device characteristics of the transistors formed in the upper part of the cell and the lower part of the cell are different, since the transistors corresponding to the access transistors PG1 to PG4 are formed in the same layer (either the upper part or the lower part of the cell), there is no deviation in characteristics between the first and second complementary bit line pairs (between the first and second bit lines BLA, BLAX, and between the third and fourth bit lines BLB, BLBX). This makes it possible to suppress variations in transistor performance between the first and second complementary bit line pairs. Therefore, the operating margin is increased and the operation is stabilized in the semiconductor memory device.

[0206] 15 and 16, the transistors N1, N2, N5, N6, N43, N44, N47, and N48 overlap the transistor P2, the dummy transistors P22 and P21, and the transistors P1, N7, N8, N3, and N4, respectively, in a plan view. That is, in FIG. 15 and 16, each transistor including the dummy transistor is stacked with other transistors. This makes it unnecessary to remove some of the transistors, and thus makes it possible to suppress the complication of the manufacturing process.

[0207] In addition, in FIG. 15, transistors N1, N2, N5, N6, N43, N44, N47, and N48 are formed in the lower part of the cell, and transistors N3, N4, N7, N8, P1, and P2 and dummy transistors P21 and P22 are formed in the upper part of the cell. In FIG. 16, transistors N1 to N8 are arranged in the lower part of the cell, and transistors N43, N44, N47, N48, P1, and P2 and dummy transistors P21 and P22 are formed in the upper part of the cell. That is, in FIG. 15 and FIG. 16, only N-type FETs are arranged in the lower part of the cell, and the above configuration can be realized by replacing some of the transistors arranged in the upper part of the cell with N-type FETs. This makes it possible to suppress the complication of the manufacturing process.

[0208] 15 and 16, the 2-port SRAM cell shown in FIG. 16 is arranged adjacent to the 2-port SRAM cell shown in FIG. 15 without being inverted in the X direction, but the 2-port SRAM cell shown in FIG. 15 may be arranged adjacent to the 2-port SRAM cell by inverting it in the X direction. In this case, for example, in FIG. 15, the transistors N43 and N44 correspond to the transistors N7 and N8, respectively, in the 2-port SRAM cell shown in FIG. 16 arranged on the right side of the drawing. Also, the transistors N47 and N48 correspond to the transistors N3 and N4 in the 2-port SRAM cell shown in FIG. 16 arranged on the left side of the drawing.

[0209] In the above-described embodiments and modifications, each transistor has one nanowire, but some or all of the transistors may have multiple nanowires. In this case, multiple nanowires may be provided in the X direction in a plan view, or multiple nanowires may be provided in the Z direction. Also, multiple nanowires may be provided in both the X direction and the Z direction. Also, the number of nanowires provided in the transistors at the upper and lower parts of the cell may be different.

[0210] In each of the above-described embodiments, each transistor may be configured with a plurality of transistors connected in parallel.

[0211] In addition, in each of the above-described embodiments, the cross-sectional shape of the nanowire is substantially square, but this is not limited thereto, and may be, for example, circular or rectangular.

[0212] In addition, in the above-described embodiments, a nanowire FET is used as an example of a three-dimensional transistor, but the present invention is not limited to this. For example, the transistor formed in the lower part of the cell may be a fin transistor. [Industrial Applicability]

[0213] The present disclosure can be applied to a semiconductor memory device having an SRAM cell using a CFET, making it possible to realize a two-port SRAM cell using a CFET and reduce the area of ​​the two-port SRAM cell. [Explanation of symbols]

[0214] 11,12 Power wiring 21a-21j, 23a, 23c-23f, 23h-23j Nanowires 22a~22n,24a~24n Pads N1 to N8, N11 to N18, N43, N44, N47, N48, P1, P2 transistors 71~75,81,82 Wiring PU1, PU2 load transistor PD1, PD2 drive transistor PG1~PG4 Access transistors WLA 1st Word Line WLB Second word line BLA 1st bit line BLAX 2nd bit line BLB 3rd bit line BLBX 4th bit line

Claims

1. A semiconductor memory device including a two-port SRAM cell, The two-port SRAM cell comprises: a first transistor having one node connected to a first power supply supplying a first voltage, another node connected to the first node, and a gate connected to a second node; a second transistor having one node connected to the first power supply, another node connected to the second node, and a gate connected to the first node; a third transistor having one node connected to the first node, another node connected to a second power supply that supplies a second voltage different from the first voltage, and a gate connected to the second node; a fourth transistor having one node connected to the second node, another node connected to the second power supply, and a gate connected to the first node; a fifth transistor having one node connected to the first bit line, another node connected to the first node, and a gate connected to the first word line; a sixth transistor having one node connected to a second bit line forming a first complementary bit line pair with the first bit line, another node connected to the second node, and a gate connected to the first word line; a seventh transistor having one node connected to the third bit line, another node connected to the first node, and a gate connected to the second word line; an eighth transistor having one node connected to a fourth bit line forming a second complementary bit line pair with the third bit line, another node connected to the second node, and a gate connected to the second word line; Equipped with The third and fourth transistors each include a first three-dimensional structure transistor which is a three-dimensional structure transistor of a first conductivity type formed in a first layer; a second three-dimensional structure transistor which is a three-dimensional structure transistor of the first conductivity type formed in a second layer different from the first layer; the first transistor is a three-dimensional transistor of a second conductivity type different from the first conductivity type formed in the second layer, the second transistor is a three-dimensional transistor of the second conductivity type formed in the first layer, Each of the fifth to eighth transistors includes a three-dimensional transistor of the first conductivity type formed in at least one of the first and second layers. A semiconductor memory device comprising:

2. 2. The semiconductor memory device according to claim 1, The semiconductor memory device is characterized in that the first and second transistors are formed at the same position in a second direction perpendicular to a first direction in which channels of the first to eighth transistors extend when viewed in a plan view.

3. 2. The semiconductor memory device according to claim 1, The semiconductor memory device according to claim 1, wherein the second three-dimensional transistor at least partially overlaps with the first three-dimensional transistor in a plan view.

4. 2. The semiconductor memory device according to claim 1, The first three-dimensional structure transistor includes a plurality of first three-dimensional structure transistors, The second three-dimensional structure transistor includes a plurality of second three-dimensional structure transistors, the plurality of first three-dimensional structure transistors are formed side by side in a second direction perpendicular to a first direction in which channels of the first to eighth transistors extend, The plurality of second three-dimensional structure transistors are formed side by side in the second direction. A semiconductor memory device comprising:

5. 2. The semiconductor memory device according to claim 1, The fifth to eighth transistors each include a third three-dimensional structure transistor formed in the first layer; a fourth three-dimensional structure transistor formed in the second layer so as to overlap at least a portion of the fourth three-dimensional structure transistor in a plan view; 1. A semiconductor memory device comprising:

6. A semiconductor memory device including first and second two-port SRAM cells, The first and second two-port SRAM cells each include a first transistor having one node connected to a first power supply supplying a first voltage, another node connected to the first node, and a gate connected to a second node; a second transistor having one node connected to the first power supply, another node connected to the second node, and a gate connected to the first node; a third transistor having one node connected to the first node, another node connected to a second power supply that supplies a second voltage different from the first voltage, and a gate connected to the second node; a fourth transistor having one node connected to the second node, another node connected to the second power supply, and a gate connected to the first node; a fifth transistor having one node connected to the first bit line, another node connected to the first node, and a gate connected to the first word line; a sixth transistor having one node connected to a second bit line forming a first complementary bit line pair with the first bit line, another node connected to the second node, and a gate connected to the first word line; a seventh transistor having one node connected to the third bit line, another node connected to the first node, and a gate connected to the second word line; an eighth transistor having one node connected to a fourth bit line forming a second complementary bit line pair with the third bit line, another node connected to the second node, and a gate connected to the second word line; Equipped with the first and second two-port SRAM cells are arranged adjacent to each other in a second direction perpendicular to a first direction in which channels of the first to eighth transistors extend; In each of the first and second two-port SRAM cells, each of the third and fourth transistors includes a three-dimensional structure transistor of a first conductivity type formed in a first layer; the first transistor includes a three-dimensional structure transistor of a second conductivity type different from the first conductivity type formed in a second layer different from the first layer, the second transistor includes a three-dimensional structure transistor of the second conductivity type formed in at least one of the first and second layers, each of the fifth to eighth transistors includes a three-dimensional structure transistor of the first conductivity type formed in at least one of the first and second layers; the fifth and seventh transistors in the first two-port SRAM cell at least partially overlap with the sixth and eighth transistors in the second two-port SRAM cell, respectively, in a plan view; the fifth and seventh transistors of the first two-port SRAM cell and the fifth and seventh transistors of the second two-port SRAM cell are formed in one of the first and second layers; the sixth and eighth transistors of the first two-port SRAM cell and the sixth and eighth transistors of the second two-port SRAM cell are formed in the other of the first and second layers; the second transistor is formed in the first layer, the first and second transistors are formed at the same position in the second direction in a plan view, The third and fourth transistors each include a first three-dimensional structure transistor formed in the first layer; a second three-dimensional transistor formed in the second layer so as to overlap at least a portion of the first three-dimensional transistor in a plan view. A semiconductor memory device comprising:

7. A semiconductor memory device including first and second two-port SRAM cells, The first and second two-port SRAM cells each include a first transistor having one node connected to a first power supply supplying a first voltage, another node connected to the first node, and a gate connected to a second node; a second transistor having one node connected to the first power supply, another node connected to the second node, and a gate connected to the first node; a third transistor having one node connected to the first node, another node connected to a second power supply that supplies a second voltage different from the first voltage, and a gate connected to the second node; a fourth transistor having one node connected to the second node, another node connected to the second power supply, and a gate connected to the first node; a fifth transistor having one node connected to the first bit line, another node connected to the first node, and a gate connected to the first word line; a sixth transistor having one node connected to a second bit line forming a first complementary bit line pair with the first bit line, another node connected to the second node, and a gate connected to the first word line; a seventh transistor having one node connected to the third bit line, another node connected to the first node, and a gate connected to the second word line; an eighth transistor having one node connected to a fourth bit line forming a second complementary bit line pair with the third bit line, another node connected to the second node, and a gate connected to the second word line; Equipped with the first and second two-port SRAM cells are arranged adjacent to each other in a second direction perpendicular to a first direction in which channels of the first to eighth transistors extend; In each of the first and second two-port SRAM cells, each of the third and fourth transistors includes a three-dimensional structure transistor of a first conductivity type formed in a first layer; the first transistor includes a three-dimensional structure transistor of a second conductivity type different from the first conductivity type formed in a second layer different from the first layer, the second transistor includes a three-dimensional structure transistor of the second conductivity type formed in at least one of the first and second layers, each of the fifth to eighth transistors includes a three-dimensional structure transistor of the first conductivity type formed in at least one of the first and second layers; the fifth and seventh transistors in the first two-port SRAM cell at least partially overlap with the sixth and eighth transistors in the second two-port SRAM cell, respectively, in a plan view; the fifth and seventh transistors of the first two-port SRAM cell and the fifth and seventh transistors of the second two-port SRAM cell are formed in one of the first and second layers; the sixth and eighth transistors of the first two-port SRAM cell and the sixth and eighth transistors of the second two-port SRAM cell are formed in the other of the first and second layers; the second transistor is formed in the second layer, The third and fourth transistors each include a first three-dimensional structure transistor formed in the first layer; a second three-dimensional transistor formed in the second layer so as to overlap at least a portion of the first three-dimensional transistor in a plan view. A semiconductor memory device comprising:

8. 8. The semiconductor memory device according to claim 6, the fifth to eighth transistors of the first two-port SRAM cell are formed in one of the first and second layers, and the fifth to eighth transistors of the second two-port SRAM cell are formed in the other of the first and second layers.

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