Stacked CMOS image sensor

Abstract

To increase performance of a pixel sensor even at a small size.SOLUTION: An image sensor 102 is a stacked complementary metal-oxide semiconductor (CMOS) image sensor in which a pixel sensor spans multiple integrated circuits (IC) and has only one first gate dielectric thickness T1 at a first IC chip 104a at which a photodetector 106 of the pixel sensor is arranged. The pixel sensor has only one or more second gate dielectric thicknesses T2 at a second IC chip 104b that is stacked with the first IC chip. The one or more second gate dielectric thicknesses are less than or equal to the first gate dielectric thickness. The first and second gate dielectric thicknesses correspond to transistors of the pixel sensor which form a pixel circuit 112 of the pixel sensor configured to facilitate readout of the photodetector.SELECTED DRAWING: Figure 3A

Description

[Background technology]

[0001] Integrated circuits (ICs) with image sensors are used in a wide range of modern electronic devices, such as cameras, mobile phones, etc. Types of image sensors include, for example, complementary metal-oxide semiconductor (CMOS) image sensors and charge-coupled device (CCD) image sensors. Compared with CCD image sensors, CMOS image sensors are increasingly favored due to their low power consumption, small size, fast data processing, direct output of data, and low manufacturing costs. Summary of the Invention [Problem to be solved by the invention]

[0002] The semiconductor manufacturing industry continues to pursue miniaturization of image sensors to achieve lower manufacturing costs, higher device integration density, faster speeds, better performance, etc. However, it is not easy to miniaturize transistors in pixel circuits. For example, transistors in pixel circuits have different gate dielectric thicknesses, which increases the complexity of forming the transistors and thus the difficulty of miniaturizing the transistors. Since it is not easy to miniaturize transistors in pixel circuits, the photodetector elements may be miniaturized instead, which may result in a decrease in the performance of the pixel sensor. [Means for solving the problem]

[0003] The present disclosure provides an image sensor, which includes a first integrated circuit (IC) chip, a second IC chip stacked with the first IC chip, and a pixel sensor spanning the first and second IC chips. The pixel sensor includes a first transistor and a photodetector element in the first IC chip, and further includes a plurality of second transistors in the second IC chip. The first transistor includes a gate dielectric layer of a first thickness, and the plurality of second transistors include individual gate dielectric layers of a second thickness that is less than or equal to the first thickness.

[0004] The present disclosure provides an image sensor including a first semiconductor substrate, a photodetector element and a first transistor adjacent to each other on the first semiconductor substrate, a second semiconductor substrate, a plurality of second transistors on the second semiconductor substrate, a third semiconductor substrate stacked on the first and second semiconductor substrates, and a plurality of third transistors on the third semiconductor substrate, the second semiconductor substrate being between and spaced apart from the first and third semiconductor substrates, the photodetector element and the first and second transistors forming a pixel sensor, and a gate dielectric thickness of each of the plurality of second transistors being between, inclusive, a gate dielectric thickness of the first transistor and a maximum gate dielectric thickness in the third transistor.

[0005] The present disclosure provides a method of forming an image sensor, the method including forming a first IC chip including forming a photodetector element on a first substrate, forming a first transistor on the first substrate adjacent to the photodetector element, where the photodetector element and the first transistor form a first pixel sensor portion, and forming a first interconnect structure over the first transistor and the photodetector element and further electrically coupled to the first transistor, forming a second IC chip including forming a plurality of second transistors on a second substrate, where the plurality of second transistors form the second pixel sensor portion, and forming a second interconnect structure over the second transistor and electrically coupled to the second transistor, and bonding the first IC chip and the second IC chip together such that the first pixel sensor portion and the second pixel sensor portion are stacked and electrically coupled together to form a pixel sensor, where the first transistor includes a gate dielectric layer of a first thickness and the plurality of second transistors include individual gate dielectric layers of a second thickness less than or equal to the first thickness. Effect of the Invention

[0006] Since the photodetector element is relatively large and is present in the first IC chip but not in the second IC chip, the pixel sensor portion in the first IC chip limits the miniaturization of the pixel sensor. Thus, the pixel sensor portion in the second IC chip can have unused space. This unused space can be used for additional functions. In addition, miniaturization of the pixel sensor in the first IC chip has the effect of miniaturizing the entire pixel sensor. Therefore, the pixel sensor can be miniaturized without miniaturizing the photodetector element, and the performance of the pixel sensor can be improved even in a small size. [Brief description of the drawings]

[0007] Aspects of the present disclosure are best understood by reading the following detailed description in conjunction with the accompanying drawings, in which: It should be noted that, in accordance with standard practice in the industry, various features have not been drawn to scale, and in fact the sizes of various features may be arbitrarily increased or reduced for clarity of illustration.

[0008] [Figure 1] FIG. 1 illustrates circuit diagrams of several embodiments of stacked complementary metal-oxide semiconductor (CMOS) image sensors in which pixel sensors span multiple integrated circuit (IC) chips. [Diagram 2] FIG. 2 depicts schematic cross-sectional views of some embodiments of the image sensor of FIG. [Diagram 3] 3A-3C depict circuit diagrams of several other embodiments of the image sensor of FIG. 1 in which the gate dielectric thickness is varied. [Figure 4] FIG. 4 illustrates a circuit diagram of some other embodiments of the image sensor of FIG. 1 in which the pixel sensor includes multiple sub-pixels. [Diagram 5] FIG. 5 illustrates circuit diagrams of some other embodiments of the image sensor of FIG. 1 in which the reset transistor is on the same IC chip as the photodetector element. [Figure 6] FIG. 6 illustrates circuit diagrams of some other embodiments of the image sensor of FIG. 1 in which the pixel sensor includes auxiliary pixel circuitry. [Figure 7]FIG. 7 illustrates a circuit diagram of some other embodiments of the image sensor of FIG. 1, in which the image sensor further includes a third IC chip. [Figure 8] FIG. 8 depicts schematic cross-sectional views of some embodiments of the image sensor of FIG. [Figure 9] 9A-9D show circuit diagrams of several alternative embodiments of the image sensor of FIG. [Figure 10] FIG. 10 depicts a schematic cross-sectional view of several embodiments of image sensors, each including a plurality of pixel sensors such as that of FIG. [Figure 11] FIG. 11 illustrates a plan view layout diagram of some embodiments of the image sensor of FIG. [Figure 12] FIG. 12 depicts schematic cross-sectional views of several embodiments of image sensors, each including multiple pixel sensors such as FIG. 9D. [Figure 13] FIG. 13 depicts a schematic cross-sectional view of some embodiments of the image sensor of FIG. 1 in which the first transistor has a gate dielectric layer formed by a protective layer covering the photodetector element. [Figure 14] 14A-14D depict schematic cross-sectional views of several alternative embodiments of the image sensor of FIG. [Figure 15] FIG. 15 illustrates cross-sectional views of some embodiments of the image sensor of FIG. [Figure 16] 16A-16C depict cross-sectional views of several alternative embodiments of the image sensor of FIG. [Figure 17] FIG. 17 illustrates cross-sectional views of several embodiments of image sensors, each including multiple pixel sensors such as those of FIG. [Figure 18] 18, 19A, 19B, 20, 21, 22A, 22B, 23A, 23B, 24-26, 27A, 27B, 28A, 28B, and 29 depict a series of diagrams of several embodiments of methods for forming a stacked CMOS sensor in which pixel sensors span multiple IC chips. [Figure 19]18, 19A, 19B, 20, 21, 22A, 22B, 23A, 23B, 24-26, 27A, 27B, 28A, 28B, and 29 depict a series of diagrams of several embodiments of methods for forming a stacked CMOS sensor in which pixel sensors span multiple IC chips. [Figure 20] 18, 19A, 19B, 20, 21, 22A, 22B, 23A, 23B, 24-26, 27A, 27B, 28A, 28B, and 29 depict a series of diagrams of several embodiments of methods for forming a stacked CMOS sensor in which pixel sensors span multiple IC chips. [Figure 21] 18, 19A, 19B, 20, 21, 22A, 22B, 23A, 23B, 24-26, 27A, 27B, 28A, 28B, and 29 depict a series of diagrams of several embodiments of methods for forming a stacked CMOS sensor in which pixel sensors span multiple IC chips. [Figure 22] 18, 19A, 19B, 20, 21, 22A, 22B, 23A, 23B, 24-26, 27A, 27B, 28A, 28B, and 29 depict a series of diagrams of several embodiments of methods for forming a stacked CMOS sensor in which pixel sensors span multiple IC chips. [Figure 23] 18, 19A, 19B, 20, 21, 22A, 22B, 23A, 23B, 24-26, 27A, 27B, 28A, 28B, and 29 depict a series of diagrams of several embodiments of methods for forming a stacked CMOS sensor in which pixel sensors span multiple IC chips. [Figure 24] 18, 19A, 19B, 20, 21, 22A, 22B, 23A, 23B, 24-26, 27A, 27B, 28A, 28B, and 29 depict a series of diagrams of several embodiments of methods for forming a stacked CMOS sensor in which pixel sensors span multiple IC chips. [Diagram 25] 18, 19A, 19B, 20, 21, 22A, 22B, 23A, 23B, 24-26, 27A, 27B, 28A, 28B, and 29 depict a series of diagrams of several embodiments of methods for forming a stacked CMOS sensor in which pixel sensors span multiple IC chips. [Figure 26]18, 19A, 19B, 20, 21, 22A, 22B, 23A, 23B, 24-26, 27A, 27B, 28A, 28B, and 29 depict a series of diagrams of several embodiments of methods for forming a stacked CMOS sensor in which pixel sensors span multiple IC chips. [Figure 27] 18, 19A, 19B, 20, 21, 22A, 22B, 23A, 23B, 24-26, 27A, 27B, 28A, 28B, and 29 depict a series of diagrams of several embodiments of methods for forming a stacked CMOS sensor in which pixel sensors span multiple IC chips. [Figure 28] 18, 19A, 19B, 20, 21, 22A, 22B, 23A, 23B, 24-26, 27A, 27B, 28A, 28B, and 29 depict a series of diagrams of several embodiments of methods for forming a stacked CMOS sensor in which pixel sensors span multiple IC chips. [Figure 29] 18, 19A, 19B, 20, 21, 22A, 22B, 23A, 23B, 24-26, 27A, 27B, 28A, 28B, and 29 depict a series of diagrams of several embodiments of methods for forming a stacked CMOS sensor in which pixel sensors span multiple IC chips. [Diagram 30] FIG. 30 illustrates a block diagram of some embodiments of the methods of FIGS. 18, 19A, 19B, 20, 21, 22A, 22B, 23A, 23B, 24-26, 27A, 27B, 28A, 28B, and 29. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The present disclosure provides many different embodiments or examples for implementing different features of the present disclosure. To simplify the present disclosure, specific examples of components and arrangements are described below. Of course, these are illustrative and not intended to be limiting. For example, a configuration of a first feature above or on a second feature in the following description may include an embodiment in which the first and second features are formed in direct contact, and may also be an embodiment in which an additional feature is formed between the first and second features such that the first and second features are not in direct contact. In addition, the present disclosure may repeat symbols in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself dictate a relationship between the various embodiments and / or configurations referred to.

[0010] Additionally, spatially relative terms such as "left," "right," "side," "rear," "behind," "rear," "front," "below," "lower," "upper," "above," and the like may be used to facilitate the description to explain the relationship of one element or feature depicted in the figures to another element or feature. The spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted. The device may be otherwise oriented (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0011] A stacked complementary metal oxide semiconductor (CMOS) image sensor may include a first integrated circuit (IC) chip and a second IC chip stacked together. The first IC chip houses pixel sensors repeated in a grid pattern, and the second IC chip houses an application specific integrated circuit (ASIC) electrically coupled to the pixel sensors and each repetition of the pixel sensors. The pixel sensors include a photodetector element and a pixel circuit localized on the first IC chip. The photodetector element is configured to accumulate charge in response to incident radiation. The pixel circuit is configured to enable readout of the accumulated charge and includes a plurality of transistors.

[0012] The semiconductor manufacturing industry continues to pursue miniaturization of image sensors to achieve lower manufacturing costs, higher device integration density, faster speeds, better performance, etc. However, it is not easy to miniaturize transistors in pixel circuits. For example, transistors in pixel circuits have different gate dielectric thicknesses, which increases the complexity of forming the transistors and thus the difficulty of miniaturizing the transistors. Since it is not easy to miniaturize transistors in pixel circuits, the photodetector elements may be miniaturized instead, which may result in a decrease in the performance of the pixel sensor.

[0013] Various embodiments of the present disclosure are directed to a stacked CMOS image sensor in which a pixel sensor spans multiple IC chips and has only one first gate dielectric thickness in a first IC chip on which a photodetecting element of the pixel sensor is located. Additionally, the pixel sensor has only one or more second gate dielectric thicknesses in a second IC chip stacked with the first IC chip, the one or more second gate dielectric thicknesses being less than or equal to the first gate dielectric thickness. The first gate dielectric thickness and the second gate dielectric thickness correspond to transistors of the pixel sensor that form a pixel circuit of the pixel sensor configured to facilitate readout of the photodetecting element.

[0014] Because the pixel sensor is spread across the first and second IC chips, the pixel sensor has fewer transistors on the first IC chip than would otherwise be the case, and this allows the pixel sensor to be scaled on the first IC chip without scaling the photodetector element. Furthermore, because the pixel sensor has only one gate dielectric thickness on the first IC chip, this reduces the complexity of forming the first transistor of the pixel sensor on the first IC chip than would otherwise be the case. Thus, the first transistor of the pixel sensor is easier to scale, and this further allows the pixel sensor to be scaled on the first IC chip without scaling the photodetector element.

[0015] Since the photodetector element is relatively large and is present in the first IC chip but not in the second IC chip, the pixel sensor portion in the first IC chip limits the miniaturization of the pixel sensor. Thus, the pixel sensor portion in the second IC chip can have unused space. This unused space can be used for additional functions. In addition, miniaturization of the pixel sensor in the first IC chip has the effect of miniaturizing the entire pixel sensor. As described above, the pixel sensor can be miniaturized without miniaturizing the photodetector element, so the performance of the pixel sensor can be improved even in a small size.

[0016] 1, a circuit diagram 100 of some embodiments of a stacked CMOS image sensor including a pixel sensor 102 is provided. The pixel sensor 102 spans a first IC chip 104a and a second IC chip 104b that are stacked together. The first and second IC chips 104a, 104b are shown stacked horizontally, but may alternatively be stacked vertically. The pixel sensor 102 may be, for example, a four-transistor (4T) CMOS active pixel sensor (APS), and / or may be known as, for example, a pixel.

[0017] The pixel sensor 102 has only one gate dielectric thickness, i.e., the first gate dielectric thickness T1, on the first IC chip 104a that houses the photodetecting element 106 of the pixel sensor 102. Furthermore, the pixel sensor 102 has only one gate dielectric thickness, i.e., the first gate dielectric thickness T1, on the second IC chip 104a. Thus, the only gate dielectric thickness on the second IC chip 104b is equal to the only gate dielectric thickness on the first IC chip 104a. In other embodiments, the only gate dielectric thickness on the second IC chip 104b is less than the only gate dielectric thickness on the first IC chip 104a. In other embodiments, the pixel sensor 102 has only two gate dielectric thicknesses or any other suitable number of gate dielectric thicknesses on the second IC chip 104b, each of which is less than or equal to the only gate dielectric thickness on the first IC chip 104a.

[0018] The first transistor 108 is in the first IC chip 104a and has a first gate dielectric thickness T1. Additionally, a plurality of second transistors 110 are in the second IC chip 104b, each second transistor 110 having an individual first gate dielectric thickness T1. The first and second transistors 108, 110 form a pixel circuit 112 that spans the first and second IC chips 104a, 104b and are configured to enable readout of the photodetector element 106.

[0019] Because the pixel sensor 102 is spread across the first and second IC chips 104a, 104b, the pixel sensor 102 has fewer transistors on the first IC chip 104a than it would otherwise be. For example, instead of having four transistors on the first IC chip 104a, the pixel sensor 102 may have only one transistor on the first IC chip 104a. This allows the pixel sensor 102 to be scaled on the first IC chip 104a without scaling the photodetector element 106. Furthermore, because the pixel sensor 102 has only one gate dielectric thickness (e.g., the first gate dielectric thickness T1) on the first IC chip 104a, the complexity of forming the first transistor 108 is reduced compared to otherwise. Thus, the first transistor 108 is easier to scale. This allows the pixel sensor 102 to be scaled on the first IC chip 104a without scaling the photodetector element 106.

[0020] Since the light detection element 106 is relatively large and is present in the first IC chip 104a but not in the second IC chip 104b, the portion of the pixel sensor 102 in the first IC chip 104a limits the miniaturization of the pixel sensor 102. Therefore, miniaturization of the pixel sensor 102 in the first IC chip 104a can have the effect of miniaturizing the entire pixel sensor 102. As described above, since the pixel sensor 102 can be miniaturized without miniaturizing the light detection element 106, the performance of the pixel sensor 102 can be improved even in a small size.

[0021] 1, the photodetector element 106 is a photodiode and is electrically coupled from ground 114 to the first transistor 108. The anode of the photodetector element 106 is electrically coupled to ground 114 and the cathode of the photodetector element 106 is electrically coupled to the first transistor 108. In other embodiments, the photodetector element 106 may be a type of photodetector element other than a photodiode. The first transistor 108 is more specifically a transfer transistor 116 gated by a transmit signal TX and configured to selectively transfer charge accumulating in the photodetector element 106 to a floating diffusion node FD.

[0022] The second transistor 110 includes a reset transistor 118, a source follower transistor 120, and a select transistor 122. The reset transistor 118 is gated by a reset signal RST and is electrically coupled from a reset voltage Vrst to the floating diffusion node FD. The reset transistor 118 is further configured to clear any accumulated charge at the floating diffusion node FD by electrically coupling the floating diffusion node FD to the reset voltage Vrst. This electrical coupling by the reset transistor 118 may also clear any accumulated charge at the photodetector element 106 when the transfer transistor 116 is ON.

[0023] The source follower transistor 120 is gated by the charge at the floating diffusion node FD. For example, the gate of the source follower transistor 120 may be electrically shorted to the floating diffusion node FD and / or the source / drain region of the transfer transistor 116. Furthermore, the select transistor 122 is gated by a select signal SEL. The source follower transistor 120 and the select transistor 122 are electrically coupled in series from a power supply voltage VDD to an output OUT of the pixel sensor 102. The source follower transistor 120 is configured to buffer and amplify the voltage at the floating diffusion node FD for non-destructive readout of the voltage. The select transistor 122 is configured to selectively pass the buffered and amplified voltage from the source follower transistor 120 to the output OUT.

[0024] In some embodiments, the image sensor has only one gate dielectric thickness on the first IC chip 104a and / or only one or two gate dielectric thicknesses on the second IC chip 104b. For example, all transistors on the first IC chip 104a individually have a first gate dielectric thickness T1, and / or all transistors on the second IC chip 104b individually have a first gate dielectric thickness T1. Furthermore, in some embodiments, each gate dielectric thickness on the second IC chip 104b is equal to or less than each gate dielectric thickness on the first IC chip 104a. For example, all transistors on the first IC chip 104a individually may have a first gate dielectric thickness T1, and all transistors on the second IC chip 104b may each have a gate dielectric thickness equal to or less than the first gate dielectric thickness T1.

[0025] In at least some embodiments, the gate dielectric thickness, as used above and below, refers to the separation between the gate electrode of the corresponding transistor and the semiconductor channel of the corresponding transistor. Such separation is achieved by the gate dielectric layer of the corresponding transistor, and thus the gate dielectric thickness also refers to the thickness of the gate dielectric layer. The corresponding transistor may correspond to, for example, either the first and second transistors 108, 110. In some embodiments, the first and second transistors 108, 110 are metal oxide semiconductor field effect transistors (MOSFETs), fin field effect transistors (FinFETs), gate-all-around field effect transistors (GAA FETs), nanosheet field effect transistors, or the like, or any combination of the foregoing.

[0026] 2, a schematic cross-sectional view 200 of some embodiments of the image sensor of FIG. 1 is provided in which the first and second IC chips 104a and 104b are stacked vertically. The first IC chip 104a overlies the second IC chip 104b, and the image sensor is configured to receive radiation 202 from the top of the image sensor.

[0027] 3A-3C, circuit diagrams 300A-300C are provided of several other embodiments of the image sensor of FIG. 1 in which the gate dielectric thicknesses of the plurality of second transistors 110 are varied.

[0028] In Fig. 3A, the pixel sensor 102 has only one gate dielectric thickness on the second IC chip 104b, as in Fig. 1. However, unlike Fig. 1, this gate dielectric thickness is a second gate dielectric thickness T2 that is less than or equal to the first gate dielectric thickness T1 that the pixel sensor 102 has on the first IC chip 104a. Thus, each second transistor 110 has an individual second gate dielectric thickness T2.

[0029] In Fig. 3B, the pixel sensor 102 has only two gate dielectric thicknesses on the second IC chip 104b, one less than the first gate dielectric thickness T1 that the pixel sensor 102 has on the first IC chip 104a, and one equal to the first gate dielectric thickness T1. The two gate dielectric thicknesses include the first gate dielectric thickness T1 described with reference to Fig. 1 and the second gate dielectric thickness T2 described with reference to Fig. 3A. The reset transistor 118 and the select transistor 122 have the first gate dielectric thickness T1, and the source follower transistor 120 has the second gate dielectric thickness T2.

[0030] In another embodiment, the reset transistor 118 and the source follower transistor 120 have a first gate dielectric thickness T1, and the select transistor 122 has a second gate dielectric thickness T2. Additionally, in another embodiment, the source follower transistor 120 and the select transistor 122 have a first gate dielectric thickness T1, and the reset transistor 118 has a second gate dielectric thickness T2.

[0031] In Figure 3C, the pixel sensor 102 has only two gate dielectric thicknesses, each of which is less than the first gate dielectric thickness T1 that the pixel sensor 102 has on the first IC chip 104a. The only two gate dielectric thicknesses include the second gate dielectric thickness T2 described with respect to Figure 3A, and also include a third gate dielectric thickness T3 that is less than the second gate dielectric thickness T2. The reset transistor 118 and the select transistor 122 have the second gate dielectric thickness T2, and the source follower transistor 120 has the third gate dielectric thickness T3.

[0032] In another embodiment, the reset transistor 118 and the source follower transistor 120 have a second gate dielectric thickness T2, and the select transistor 122 has a third gate dielectric thickness T3. Additionally, in another embodiment, the source follower transistor 120 and the select transistor 122 have a second gate dielectric thickness T2, and the reset transistor 118 has a third gate dielectric thickness T3.

[0033] As seen in FIGS. 3A-3C, the source follower transistor 120 has a thinner gate dielectric thickness than that of FIG. 1. Reducing the gate dielectric thickness of the source follower transistor 120 can provide better anti-noise performance and / or loop gain to the image sensor. Thus, the image sensor of FIGS. 3A-3C can have better anti-noise performance and / or loop gain than the image sensor of FIG. 1. Furthermore, as seen in FIGS. 1 and 3A-3C, the pixel sensor 102 does not have more than two gate dielectric thicknesses on the second IC chip 104b. While it is possible to implement more than two gate dielectric thicknesses, more than two gate dielectric thicknesses increase the complexity of forming the pixel sensor 102. Furthermore, the increased complexity reduces the yield and / or limits the scaling of the pixel sensor 102.

[0034] 4, a circuit diagram 400 of some other embodiments of the image sensor described in FIG. 1 is provided in which the pixel sensor 102 includes a plurality of sub-pixels 102s on the first IC chip 104a. More specifically, the pixel sensor 102 includes a plurality of photo-detecting elements 106 and a plurality of first transistors 108 on the first IC chip 104a. The photo-detecting elements 106 are paired with the first transistors 108 in a one-to-one correspondence, and each photo-detecting element-transistor pair forms a sub-pixel 102s.

[0035] Each photodetector element 106 is a photodiode and is electrically coupled from ground 114 to a respective first transistor 108. For example, an anode of each photodetector element 106 is electrically coupled to ground 114, and a cathode of each photodetector element 106 is electrically coupled to a respective first transistor 108. In other embodiments, the photodetector elements 106 are types of photodetector elements other than photodiodes. The first transistor 108 is a transfer transistor gated by respective transfer signals TX1, TX2, TX3, TX4 and configured to selectively transfer charge accumulated in the photodetector elements 106 to a floating diffusion node FD common to the subpixels 102s. The second transistor 110 is as in FIG. 1 and is shared by the subpixels 102s.

[0036] 1, the pixel sensor 102 has only one gate dielectric thickness, namely, the first gate dielectric thickness T1, on the first IC chip 104a. Thus, each first transistor 108 has the first gate dielectric thickness T1. This simplifies the manufacture of the pixel sensor 102 and allows the pixel sensor 102 to be miniaturized without compromising performance.

[0037] 5, a circuit diagram 500 of some other embodiments of the image sensor of FIG. 1 is provided in which the reset transistor 118 is in the first IC chip 104a. Furthermore, the reset transistor 118 has the same gate dielectric thickness as the transfer transistor 116, i.e., the first gate dielectric thickness T1. Thus, the pixel sensor 102 also has only one gate dielectric thickness in the first IC chip 104a, which is equal to or greater than each gate dielectric thickness in the second IC chip 104b.

[0038] As seen above (e.g., in FIGS. 1, 3A-3C, 4, 5), each transistor in the first IC chip 104a of the pixel sensor 102 has a gate dielectric thickness that is equal to or greater than the maximum gate dielectric thickness among all transistors in the second IC chip 104b of the pixel sensor 102. Furthermore, in some embodiments, each transistor in the first IC chip 104a has a gate dielectric thickness that is equal to or greater than the maximum gate dielectric thickness among all transistors in the second IC chip 104b.

[0039] 6, there is provided a circuit diagram 600 of some other embodiments of the image sensor of FIG. 1, in which the pixel sensor 102 includes an auxiliary pixel circuit 602. The auxiliary pixel circuit 602 is electrically coupled between the selection transistor 122 and the output OUT of the pixel sensor 102, and is formed by a second transistor 110. Note that ellipses in the auxiliary pixel circuit 602 are used to represent zero or more additional transistors. Furthermore, the auxiliary pixel circuit 602 is configured to perform additional processing on the signal from the selection transistor 122 before passing it to the output OUT. For example, noise filtering, etc. may be performed.

[0040] Because the photodetector element 106 is relatively large and is present on the first IC chip 104a but not on the second IC chip 104b, the portion of the pixel sensor 102 on the first IC chip 104a limits the miniaturization of the pixel sensor 102. Therefore, the portion of the pixel sensor 102 on the second IC chip 104b may have unused space that allows for integration of auxiliary pixel circuitry 602 into the pixel sensor 102 without enlarging the pixel sensor 102.

[0041] 7, a circuit diagram 700 of some other embodiments of the image sensor of FIG. 1 is provided, in which the image sensor further includes a third IC chip 104c. The third IC chip 104c houses an ASIC 702 electrically coupled to the pixel sensor 102 and other pixel sensors (not shown) of the image sensor. The ASIC 702 may be configured to perform, for example, analog-to-digital conversion (ADC), buffering, image processing, etc., or any combination of the foregoing. In some embodiments, the ASIC 702 performs buffering and ADC on the output OUT of the pixel sensor 102 and the outputs of the other pixel sensors of the image sensor to generate digital data representing an image, and then performs image processing on the image formed by the digital data.

[0042] The ASIC 702 has only two gate dielectric thicknesses, a first gate dielectric thickness T1 and a second gate dielectric thickness T2. Furthermore, each of the only two gate dielectric thicknesses of the ASIC 702 is equal to or less than each gate dielectric thickness of the pixel sensor 102 in the second IC chip 104b. In other words, each of the only two gate dielectric thicknesses of the ASIC 702 is equal to or less than the minimum gate dielectric thickness of the pixel sensor 102 in the second IC chip 104b. The first gate dielectric thickness T1 is equal to each gate dielectric thickness of the pixel sensor 102 in the second IC chip 104b, and the second gate dielectric thickness T2 is less than each gate dielectric thickness of the pixel sensor 102 in the second IC chip 104b.

[0043] In another embodiment, the ASIC 702 has only one gate dielectric thickness that is less than or equal to each gate dielectric thickness that the pixel sensor 102 has on the second IC chip 104b. In yet another embodiment, the ASIC 702 has only three or more gate dielectric thicknesses that are less than or equal to each gate dielectric thickness that the pixel sensor 102 has on the second IC chip 104b.

[0044] The third IC chip 104c includes a plurality of third transistors 704 electrically interconnected to form an ASIC 702, each of which has only two gate dielectric thicknesses of the ASIC 702. Further, the plurality of third transistors 704 includes at least one n-type transistor 704n and at least one p-type transistor 704p. Note that ellipses in the ASIC 702 are used to represent zero or more additional third transistors. The n-type and p-type transistors 704n, 704p each have a first gate dielectric thickness T1 or a second gate dielectric thickness T2. The plurality of third transistors 704 may be, for example, MOSFETs, FinFETs, GAA FETs, nanosheet field effect transistors, other suitable types of transistors, or any combination of the foregoing.

[0045] In some embodiments, each gate dielectric thickness in the third IC chip 104c is equal to or less than each gate dielectric thickness in the second IC chip 104b which is less than each gate dielectric thickness in the first IC chip 104a. For example, all transistors in the third IC chip 104c have a gate dielectric thickness equal to or less than the minimum gate dielectric thickness among all transistors in the second IC chip 104b and / or all transistors in the second IC chip 104b have a gate dielectric thickness equal to or less than the minimum gate dielectric thickness among all transistors in the first IC chip 104a.

[0046] In some embodiments, the pixel sensor 102 has only one gate dielectric thickness on the first IC chip 104a, the pixel sensor 102 has only one or two gate dielectric thicknesses on the second IC chip 104b, and the ASIC 702 has only two or more gate dielectric thicknesses on the third IC chip 104c. The only one gate dielectric thickness on the first IC chip 104a is equal to or greater than the maximum gate dielectric thickness of the only one or two gate dielectric thicknesses on the second IC chip 104b. Furthermore, the minimum gate dielectric thickness of the only one or two gate dielectric thicknesses on the second IC chip 104b is equal to or greater than the maximum gate dielectric thickness of the only two or more gate dielectric thicknesses on the third IC chip 104c.

[0047] In some embodiments, the first IC chip 104a has only one gate dielectric thickness, the second IC chip 104b has only one or two gate dielectric thicknesses, and the third IC chip 104c has only two or more gate dielectric thicknesses. The only one gate dielectric thickness on the first IC chip 104a is equal to or greater than the maximum gate dielectric thickness of the only one or two gate dielectric thicknesses on the second IC chip 104b. Furthermore, the minimum gate dielectric thickness of the only one or two gate dielectric thicknesses on the second IC chip 104b is equal to or greater than the maximum gate dielectric thickness of the only two or more gate dielectric thicknesses on the third IC chip 104c.

[0048] As described above, the ASIC 702 may have only one, two, or more gate dielectric thicknesses, each of which is less than or equal to the minimum gate dielectric thickness that the pixel sensor 102 has on the second IC chip 104b. Additionally, the pixel sensor 102 may have only one, two, or more gate dielectric thicknesses, each of which is less than or equal to the only gate dielectric thickness that the pixel sensor 102 has on the first IC chip 104a. Thus, each gate dielectric thickness that the pixel sensor 102 has on the second IC chip 104b can be said to be collectively between the only gate dielectric thickness that the pixel sensor 102 has on the first IC chip 104a and the maximum gate dielectric thickness that the ASIC 702 has on the third IC chip 104c. Further, in some embodiments, the first IC chip 104a may have only one gate dielectric thickness, and each gate dielectric thickness in the second IC chip 104b can be said to be between the only gate dielectric thickness and the maximum gate dielectric thickness in the third IC chip 104c, inclusive.

[0049] 8, a schematic cross-sectional view 800 is provided of some embodiments of the image sensor of FIG. 7 in which the first, second, and third IC chips 104a-104c are stacked vertically. The first IC chip 104a is at the top of the image sensor and the second IC chip 104b is between the first IC chip 104a and the third IC chip 104c. Further, the image sensor is configured to receive radiation 802 from the top of the image sensor.

[0050] 9A-9D, circuit diagrams 900A-900D of several alternative embodiments of the image sensor of FIG. 7 are provided.

[0051] In Fig. 9A, the pixel sensor 102 has only two gate dielectric thicknesses in the second IC chip 104b, one of which is less than and the other of which is equal to the only gate dielectric thickness that the pixel sensor 102 has in the first IC chip 104a. Furthermore, the only two gate dielectric thicknesses in the second IC chip 104b include a first gate dielectric thickness T1 and a second gate dielectric thickness T2. The source follower transistor 120 has the second gate dielectric thickness T2, and the reset transistor 118 and the select transistor 122 have the first gate dielectric thickness T1.

[0052] In addition, the ASIC 702 has only two gate dielectric thicknesses in the third IC chip 104c, one of which is less than and the other of which is equal to the minimum gate dielectric thickness that the pixel sensor 102 has in the second IC chip 104b. Furthermore, the only two gate dielectric thicknesses in the third IC chip 104c include a second gate dielectric thickness T2 in the n-type transistor 704n and a third gate dielectric thickness T3 in the p-type transistor 704p in the ASIC 702.

[0053] 9B provides a variation of FIG. 9A in which the ASIC 702 has only two gate dielectric thicknesses in the third IC chip 104c that are each less than the minimum gate dielectric thickness that the pixel sensor 102 has in the second IC chip 104b. Additionally, the only two gate dielectric thicknesses in the third IC chip 104c include a fourth gate dielectric thickness T4 in the n-type transistor 704n and a third gate dielectric thickness T3 in the p-type transistor 704p in the ASIC 702.

[0054] 9C, the pixel sensor 102 has only one gate dielectric thickness on the second IC chip 104b, which is less than the only gate dielectric thickness that the pixel sensor 102 has on the first IC chip 104a. Further, the only gate dielectric thickness on the second IC chip 104b includes a second gate dielectric thickness T2, and each of the source follower transistor 120, the reset transistor 118, and the select transistor 122 has the second gate dielectric thickness T2.

[0055] In addition, the ASIC 702 has only two gate dielectric thicknesses in the third IC chip 104c, and these two gate dielectric thicknesses are each less than the maximum gate dielectric thickness that the pixel sensor 102 has in the second IC chip 104b. Furthermore, the only two gate dielectric thicknesses in the third IC chip 104c include a fourth gate dielectric thickness T4 in the n-type transistor 704n and a third gate dielectric thickness T3 in the p-type transistor 704p in the ASIC 702.

[0056] In Figure 9D, the pixel sensor 102 includes an auxiliary pixel circuit 602 as described with respect to Figure 6. The auxiliary pixel circuit 602 is electrically coupled between the select transistor 122 and the output OUT of the pixel sensor 102, and is formed by a second transistor 110. Note that an ellipsis is used in the auxiliary pixel circuit 602 to represent zero or more additional second transistors.

[0057] 7 and 9A-9D depict particular embodiments of the first and second IC chips 104a, 104b, the first and second IC chips 104a, 104b of Figures 7 and 9A-9D may alternatively be as in any of Figures 1, 3A-3C, 4-6. Additionally, while ASIC 702 is illustrated as having only two gate dielectric thicknesses in third IC chip 104c, ASIC 702 may alternatively have three or more gate dielectric thicknesses.

[0058] Referring to FIG. 10, a schematic cross-sectional view 1000 is provided of several embodiments of an image sensor including multiple pixel sensors 102, each as in FIG. 1. In other words, the pixel sensor 102 of FIG. 1 is repeated, and there are multiple instances or repetitions of the pixel sensor of FIG. 1. In other embodiments, the pixel sensor 102 is as in any of FIGS. 3A-3D, 4-6, respectively. Furthermore, the first and second IC chips 104a, 104b are stacked vertically. The first IC chip 104a overlies the second IC chip 104b, and the image sensor is configured to receive radiation 202 from the top of the image sensor.

[0059] 11, a plan view layout diagram 1100 of some embodiments of the image sensor of FIG. 10 is provided, in which multiple pixel sensors 102 are in multiple columns and multiple rows. The schematic cross-sectional diagram 1000 of FIG. 10 may be taken, for example, along line A-A' of FIG.

[0060] The columns are R1, R2, R3, and R M and several columns are C1, C2, C3, and C N The subscripts of the column labels correspond to the column numbers, where M is an integer greater than 3. Similarly, the subscripts of the column labels correspond to the column numbers, where N is an integer greater than 3. Furthermore, the multiple columns and columns form a two-dimensional array in which the pixel sensors 102 are in a periodic grid pattern. Other suitable patterns are possible in other embodiments.

[0061] Referring to FIG. 12, a schematic cross-sectional view 1200 of some embodiments of an image sensor including a plurality of pixel sensors 102, each of which is as in FIG. 9D, is provided. In other words, the pixel sensor 102 of FIG. 9D is repeated, and there are multiple instances or repetitions of the pixel sensor of FIG. 9D. In other embodiments, each of the plurality of pixel sensors 102 may be as in any of FIGS. 7, 9A-9D. Furthermore, the ASIC 702 is shared by the plurality of pixel sensors 102. For example, there may be a many-to-one correspondence between the pixel sensors 102 and the ASIC 702. Furthermore, the first, second, and third IC chips 104a, 104b, 104c are stacked vertically. The second IC chip 104b is between the first IC chip 104a and the third IC chip 104c, and the image sensor is configured to receive radiation 802 from the top of the image sensor.

[0062] It should be understood that while Figure 11 is described with respect to the image sensor of Figure 10, Figure 11 is also applicable to the image sensor of Figure 12. For example, the schematic cross-sectional view 1200 of Figure 12 may be taken along line A-A' of Figure 11.

[0063] 13, a schematic cross-sectional view 1300 of some embodiments of the image sensor of FIG. 1 is provided in which the first transistor 108 has a first gate dielectric layer 1302 formed by a protective layer 1304 that covers and protects the photodetector element 106. The protective layer 1304 covers the photodetector element 106 on a front side 1306fs of a first semiconductor substrate 1306 that contains the photodetector element 106. The protective layer 1304 may be or include, for example, silicon oxide, silicon nitride, a high-k material, other suitable dielectrics, or any combination of the foregoing. The first semiconductor substrate 1306 may be, for example, a bulk substrate such as single crystal silicon, silicon germanium, or other suitable type of semiconductor substrate.

[0064] The photodetector element 106 is in the first semiconductor substrate 1306 and includes a collector region 1308. The collector region 1308 corresponds to a doped region of the first semiconductor substrate 1306 and has an opposite doping type to the immediately surrounding region of the first semiconductor substrate 1306. For example, the collector region 1308 may have an n-type doping type and the immediately surrounding region of the first semiconductor substrate 1306 may have a p-type doping type, or vice versa. Thus, the boundary of the collector region 1308 may be defined by, for example, a PN junction. During operation, the photodetector element 106 receives radiation from the backside 1306bs of the first semiconductor substrate 1306, which results in the accumulation of charge in the collector region 1308.

[0065] The first transistor 108 is on and partially defined by the front side 1306fs of the first semiconductor substrate 1306. Furthermore, the first transistor 108 includes a first gate electrode 1310, a first gate dielectric layer 1302, and a pair of first source / drain regions 1312. The first gate dielectric layer 1302 has only one gate dielectric thickness that the pixel sensor 102 has in the first IC chip 104a. Thus, the first gate dielectric layer 1302 has a first gate dielectric thickness T1. Furthermore, as described above, the first gate dielectric layer 1302 is formed by the protective layer 1304. The first gate dielectric layer 1302 may be or include, for example, silicon oxide and / or other suitable dielectrics.

[0066] The first gate electrode 1310 is stacked with the first gate dielectric layer 1302 and is separated from the first semiconductor substrate 1306 by the first gate dielectric layer 1302. Furthermore, the first gate electrode 1310 has a planar shape. In other embodiments, the first gate electrode 1310 may have other suitable shapes, examples of which are provided below. The first gate electrode 1310 may be or include, for example, doped polysilicon, a metal, other suitable conductive material, or any combination of the foregoing.

[0067] The first source / drain regions 1312 are in the first semiconductor substrate 1306 and are separated from each other by a first channel region 1314 under the first gate electrode 1310. Furthermore, the first source / drain regions 1312 correspond to doped regions of the first semiconductor substrate 1306 that share a common doping type. One side of the first source / drain regions 1312 is formed by the collector region 1308 and the other side of the first source / drain regions 1312 is formed by the floating diffusion node FD.

[0068] In operation, the first gate electrode 1310 may be biased so that the first channel region 1314 is conductive. This results in the transfer of stored charge in the collector region 1308 to the floating diffusion node FD. Thus, as described above, the first gate electrode 1310 is more specifically the transfer transistor 116 in this embodiment.

[0069] 14A-14D, schematic cross-sectional views 1400A-1400D of several other embodiments of the image sensor of FIG. 13 are provided.

[0070] 14A, the first gate dielectric layer 1302 further includes a dielectric layer 1402 covering and including a portion of the protective layer 1304 under the first gate electrode 1310. Furthermore, the protective layer 1304 has a thickness less than the only gate dielectric thickness that the pixel sensor 102 has on the first IC chip 104a. For example, the protective layer 1304 has a thickness less than the first gate dielectric thickness T1.

[0071] 14B, the protective layer 1304 is omitted. Instead, the first gate dielectric layer 1302 is present only on the first transistor 108. In other embodiments, the protective layer 1304 still covers and protects the photodetector element 106, but is instead spaced apart from the first gate dielectric layer 1302.

[0072] 14C, the portion of the protective layer 1304 covered by the first gate electrode 1310 has a greater thickness than the portion of the protective layer 1304 not covered by the first gate electrode 1310. The greater thickness corresponds to the first gate dielectric thickness T1, since the portion of the protective layer 1304 covered by the first gate electrode 1310 forms the first gate dielectric layer 1302.

[0073] In FIG. 14D, the collector region 1308 is buried in the first semiconductor substrate 1306. Additionally, the first gate electrode 1310 has a bottom protrusion, which causes the first gate electrode 1310 to have a vertically elongated shape. In some embodiments, the first gate electrode 1310 is also known as a vertical transfer gate. The bottom protrusion protrudes from a bottom of the first gate electrode 1310 into the front side 1306fs of the first semiconductor substrate 1306 due to its proximity to the collector region 1308. Additionally, the bottom protrusion is separated from the first semiconductor substrate 1306 by the first gate dielectric layer 1302.

[0074] The portions of the protective layer 1304 covered by the first gate electrode 1310 have the same thickness as the portions of the protective layer 1304 not covered by the first gate electrode 1310, although variations are possible in other embodiments. For example, as shown in Figure 14C, the portions of the protective layer 1304 not covered by the first gate electrode 1310 may have a thinner thickness than the portions of the protective layer 1304 covered by the first gate electrode 1310. As another example, as shown in Figure 14B, the portions of the protective layer 1304 not covered by the first gate electrode 1310 may be omitted.

[0075] It should be understood that although the image sensors of Figures 13, 14A-14D are depicted using an embodiment of second transistor 110 as in Figure 1, in other embodiments, an embodiment of second transistor such as in any of Figures 3A-3C, 4-6 is possible. Additionally, although the image sensors of Figures 13, 14A-14D are depicted without third IC chip 104c in Figures 7, 9A-9D, in other embodiments, the image sensors may further include third IC chip 104c as in any of Figures 7, 9A-9D.

[0076] Referring to FIG. 15, a cross-sectional view 1500 of some embodiments of the image sensor of FIG. 1 is provided. The first IC chip 104a covers the second IC chip 104b and includes a first semiconductor substrate 1306 housing the photodetector element 106. In addition, the first IC chip 104a further includes a first transistor 108 and a first interconnect structure 1502 on the front side of and underlying the first semiconductor substrate 1306. The first transistor 108 and the photodetector element 106 may be, for example, as described with respect to FIG. 13. Alternatively, the first transistor 108 and the photodetector element 106 may be as in any of FIGS. 14A-14D.

[0077] The first interconnect structure 1502 underlies and is electrically coupled to the first transistor 108 and includes a plurality of first conductive lines 1504 and a plurality of first conductive vias 1506 in a first interconnect dielectric layer 1508. The first conductive lines 1504 and the first conductive vias 1506 are grouped into a plurality of first wire levels and a plurality of first via levels, respectively, that are alternately stacked to form conductive paths leading from the first transistor 108. It should be noted that the via level closest to the first semiconductor substrate 1306 is also referred to as the contact via level, and thus the first conductive vias 1506 at this via level may also be referred to as contacts or contact vias.

[0078] Second IC chip 104b is similar to first IC chip 104a and includes a second semiconductor substrate 1510, a plurality of second transistors 110, and a second interconnect structure 1512. Note that only one second transistor 110, reset transistor 118, is shown. The other second transistors are outside of cross-sectional view 1500. Additionally, second transistors 110 and second interconnect structure 1512 overlie second semiconductor substrate 1510 on the front side of second semiconductor substrate 1510.

[0079] The plurality of second transistors 110 include individual second gate electrodes 1514, individual second gate dielectric layers 1516, and individual pairs of second source / drain regions 1518. The second gate electrodes 1514 are each stacked with the second gate dielectric layer 1516 separating the second gate electrodes 1514 from the second semiconductor substrate 1510. The pairs of second source / drain regions 1518 are in the second semiconductor substrate 1510, and each second gate electrode 1514 is between the second source / drain regions of a respective pair of second source / drain regions 1518.

[0080] The second interconnect structure 1512 overlies and is electrically coupled to the second transistor 110 and includes a plurality of second conductive lines 1520 and a plurality of second conductive vias 1522 in a second interconnect dielectric layer 1524. The second conductive lines 1520 and the second conductive vias 1522 are grouped into a plurality of second wire levels and a plurality of second via levels, respectively, that are alternately stacked to form conductive paths leading from the second transistor 110.

[0081] As described above, the pixel sensor 102 has only one gate dielectric thickness, i.e., the first gate dielectric thickness T1, in the first IC chip 104a. Furthermore, the pixel sensor 102 has only one gate dielectric thickness, i.e., the first gate dielectric thickness T1, in the second IC chip 104b. In other words, all the transistors in the pixel sensor 102 have the same gate dielectric thickness in the first and second IC chips 104a, 104b. This allows the pixel sensor 102 to be miniaturized without compromising the sensitivity of the photodetecting element 106.

[0082] In another embodiment, only one gate dielectric thickness on the second IC chip 104b is less than only one gate dielectric thickness on the first IC chip 104a. In another embodiment, the pixel sensor 102 has only two or more gate dielectric thicknesses on the second IC chip 104b, and each of these only two or more gate dielectric thicknesses is less than or equal to only one gate dielectric thickness on the first IC chip 104a.

[0083] 15, a first bonding structure 1526 is between the first and second IC chips 104a and 104b to facilitate bonding the first and second IC chips 104a and 104b at a first bonding interface 1528. Such bonding may include, for example, a combination of a metal-to-metal bond and a dielectric-to-dielectric bond at the bonding interface.

[0084] The first and second IC chips 104a and 104b include respective first bonding dielectric layers 1530 bonded together in direct contact at a first bonding interface 1528, and further include respective first bonding pads 1532 bonded together in direct contact at the first bonding interface 1528. The first bonding pads 1532 are respectively recessed in the first bonding dielectric layer 1530 and electrically coupled to the first and second interconnect structures 1502 and 1512, respectively, by first bonding vias 1534 in the first bonding dielectric layer 1530.

[0085] A backside passivation layer 1536, a color filter 1538, and a microlens 1540 are stacked on the backside of the first semiconductor substrate 1306 over the first IC chip 104a. The backside passivation layer 1536 is dielectric and is transparent to radiation. The color filter 1538 is between the backside passivation layer 1536 and the microlens 1540. Furthermore, the color filter 1538 is configured to transmit a first color wavelength (e.g., red wavelength, etc.) while blocking a second color wavelength. The microlens 1540 is configured to focus the incident radiation onto the photodetector elements 106 to increase quantum efficiency.

[0086] 16A-16C, cross-sectional views 1600A-1600C of several other embodiments of the image sensor of FIG. 15 are provided.

[0087] In Figure 16A, the respective second dielectric layer 1516 of the reset transistor 118 has a second gate dielectric thickness T2 that is less than the only gate dielectric thickness (e.g., the first gate dielectric thickness T1) that the pixel sensor 102 has on the first IC chip 104a. Furthermore, in some embodiments, the image sensor corresponds to the circuit diagram 300A of Figure 3A or the circuit diagram 300C of Figure 3C.

[0088] In Figure 16B, the image sensor is front-side illuminated rather than back-side illuminated. Furthermore, in some embodiments, the image sensor corresponds to circuit diagram 300A of Figure 3A or circuit diagram 300C of Figure 3C.

[0089] The first semiconductor substrate 1306 and the first interconnect structure 1502 are vertically flipped, with the first interconnect structure 1502 disposed above the first semiconductor substrate 1306. Additionally, the backside passivation layer 1536 is omitted, a frontside passivation layer 1602 separates the color filters 1538 from the first interconnect structure 1502, and through-substrate vias (TSVs) 1604 extend through the first semiconductor substrate 1306. The TSVs 1604 extend from the first interconnect structure 1502 to the first junction structure 1526 to provide electrical coupling between the first interconnect structure 1502 and the first junction structure 1526. Additionally, the TSVs 1604 are separated from the first semiconductor substrate 1306 by a TSV dielectric layer 1606.

[0090] 16C, the image sensor further includes a third IC chip 104c that underlies and is bonded to the second IC chip 104b. Additionally, in some embodiments, the image sensor corresponds to circuit diagram 700 of FIG.

[0091] The third IC chip 104c is similar to the second IC chip 104b and includes a third semiconductor substrate 1608, a plurality of third transistors 704, and a third interconnect structure 1610. Note that only one third transistor 704 is shown. The other third transistors are outside of the cross-sectional view 1600C of FIG. 16C. Additionally, the third transistors 704 and the third interconnect structure 1610 overlie the third semiconductor substrate 1608 on the front side of the third semiconductor substrate 1608.

[0092] The third transistors 704 form the ASIC 702 and include respective third gate electrodes 1612, respective third gate dielectric layers 1614, and respective pairs of third source / drain regions 1616. The third gate electrodes 1612 are each stacked with the third gate dielectric layer 1614 that separates the third gate electrodes 1612 from the third semiconductor substrate 1608. The pairs of third source / drain regions 1616 are in the third semiconductor substrate 1608, with each third gate electrode 1612 between the third source / drain regions of a respective pair of third source / drain regions 1616.

[0093] The third interconnect structure 1610 overlies and is electrically coupled to the third transistor 704 and further includes a plurality of third conductive lines 1618 and a plurality of third conductive vias 1620 in a third interconnect dielectric layer 1622. The third conductive lines 1618 and the third conductive vias 1620 are grouped into a plurality of third wire levels and a plurality of third via levels, respectively, that are alternately stacked to define conductive paths leading from the third transistor 704.

[0094] As described above, the ASIC 702 has only two or more gate dielectric thicknesses in the third IC chip 104c, including the first gate dielectric thickness T1 and at least one other gate dielectric thickness outside of the cross-sectional view 1600C of FIG. 16C. Furthermore, each of the only two or more gate dielectric thicknesses is less than or equal to the minimum gate dielectric thickness that the pixel sensor 102 has in the first and second IC chips 104a and 104b.

[0095] A second bonding structure 1624 is between the second IC chip 104b and the third IC chip 104c and enables bonding of the second and third IC chips 104b and 104c at a second bonding interface 1626. Such bonding may include, for example, a combination of metal-to-metal and dielectric-to-dielectric bonding at the bonding interface. The second and third IC chips 104b and 104c include respective second bonding dielectric layers 1628 that are bonded together in direct contact at the second bonding interface 1626. Additionally, the second and third IC chips 104b and 104c include respective second bonding pads 1630 that are bonded together in direct contact at the second bonding interface 1626. The second bonding pads 1630 are respectively recessed in the second bonding dielectric layer 1628 and electrically coupled to the second and third interconnect structures 1512 and 1610, respectively, by second bonding vias 1632 in the second bonding dielectric layer 1628.

[0096] The second bonding vias 1632 in the third IC chip 104c extend to the third interconnect structure 1610, and the second bonding vias 1632 in the second IC chip 104b extend to the TSVs 1634. The TSVs 1634 extend from the second interconnect structure 1512 through the second semiconductor substrate 1510 and are separated from the second semiconductor substrate 1510 by a TSV dielectric layer 1636.

[0097] 17, a cross-sectional view 1700 of some embodiments of an image sensor each including a plurality of pixel sensors 102 as in FIG. 15 is provided. Additionally, in the first IC chip 104a, trench isolation structures 1702 extend into the front side of the first semiconductor substrate 1306 to isolate the pixel sensors 102 from one another. The trench isolation structures 1702 include a dielectric material and may be, for example, shallow trench isolation (STI) structures and / or deep trench isolation (DTI) structures.

[0098] Although the image sensor of Figure 17 is shown and described using the embodiment of pixel sensor 102 in Figure 15, in other embodiments, the image sensor may use the embodiment of pixel sensor 102 in any of Figures 16A-16C. Additionally, although the image sensor of Figure 17 is shown and described without the third IC chip 104c of Figure 16C, in other embodiments, the image sensor may include the third IC chip 104c.

[0099] 18, 19A, 19B, 20, 21, 22A, 22B, 23A, 23B, 24-26, 27A, 27B, 28A, 28B, and 29, a series of diagrams of several embodiments of methods of forming a stacked CMOS image sensor in which pixel sensors span multiple IC chips are provided. The stacked CMOS image sensor may correspond, for example, to the stacked CMOS image sensor of FIG. 16C or other suitable image sensor.

[0100] As shown in Figures 18, 19A, 19B, and 20, a first IC chip 104a is formed that includes a first portion 102a of a pixel sensor. The first portion 102a of the pixel sensor has only one gate dielectric thickness, i.e., a first gate dielectric thickness T1, on the first IC chip 104a. Furthermore, the first portion 102a of the pixel sensor has a total number of transistors that is less than the total number of transistors that the pixel sensor has. For example, the first portion 102a of the pixel sensor may have only one transistor.

[0101] As depicted in cross-sectional view 1800 of Figure 18, photodetector element 106 and floating diffusion node FD are formed in a first semiconductor substrate 1306. Photodetector element 106 and floating diffusion node FD are laterally separated from one another, and photodetector element 106 includes a collector region 1308. Collector region 1308 and floating diffusion node FD correspond to doped regions of first semiconductor substrate 1306 and share a common doping type that is opposite to the doping type of the immediately surrounding region of first semiconductor substrate 1306. As such, the boundary between collector region 1308 and floating diffusion node FD is defined by a PN junction.

[0102] 18, a protective layer 1304 and a first gate electrode layer 1802 are deposited over the front side 1306fs of the first semiconductor substrate 1306. The protective layer 1304 is a dielectric and separates the first gate electrode layer 1802 from the first semiconductor substrate 1306. The protective layer 1304 may be or include, for example, silicon oxide, other suitable oxides, high-k dielectrics, other suitable dielectrics, or any combination of the foregoing. The first gate electrode layer 1802 is conductive and may be or include, for example, doped polysilicon, metal, other suitable conductive material, or any combination of the foregoing.

[0103] As shown in cross-sectional view 1900A of Figure 19A and circuit diagram 1900B of Figure 19B, the first gate electrode layer 1802 is patterned to form a first gate electrode 1310. The first gate electrode 1310 is laterally between the collector region 1308 and the floating diffusion node FD. Further, the first gate electrode 1310 is separated from a first semiconductor substrate 1306 by a portion of a protective layer 1304, also referred to as a first gate dielectric layer 1302, having a first gate dielectric thickness T1.

[0104] The first gate electrode 1310 and the first gate dielectric layer 1302, together with the collector region 1308 and the floating diffusion node FD, form the first transistor 108. The collector region 1308 and the floating diffusion node FD serve as a pair of a first source / drain region 1312 for the first transistor 108. Thus, during use of the first transistor 108, a conductive channel is formed from the collector region 1308 to the floating diffusion node FD, depending on whether the gate-source voltage of the first transistor 108 is above or below a threshold voltage. The conductive channel may be used, for example, to transfer charge stored in the collector region 1308 to the floating diffusion node FD. Thus, the first transistor 108 is also referred to as a transfer transistor 116.

[0105] Patterning of the first gate electrode layer 1802 may be performed, for example, by a photolithography / etching process or other suitable patterning process. The photolithography / etching process may include, for example, forming a mask on the first gate electrode layer 1802 and performing an etch on the first gate electrode layer 1802 with the mask in place. The etch is shown stopped before etching into the protective layer 1304. However, the etch may alternatively etch partially or completely through the thickness of the protective layer 1304.

[0106] 20, a first interconnect structure 1502 is formed above and electrically coupled to the first transistor 108 and the floating diffusion node FD. The first interconnect structure 1502 includes a plurality of first conductive lines 1504 and a plurality of first conductive vias 1506 in a first interconnect dielectric layer 1508. The first conductive lines 1504 and the first conductive vias 1506 are grouped into a plurality of first wire levels and a plurality of first via levels, respectively, that are alternately stacked to define a conductive path.

[0107] 20, a first bonding portion structure 1526a is formed on the first interconnect structure 1502. The first bonding portion structure 1526a includes a first bonding pad 1532 and a first bonding via 1534 in a first bonding dielectric layer 1530. The first bonding pad 1532 and the first bonding dielectric layer 1530 form a common bonding surface, and the first bonding via 1534 extends from the first bonding pad 1532 to the first interconnect structure 1502.

[0108] As shown in Figures 21, 22A, and 22B, a second IC chip 104b is formed that includes a second portion 102b of the pixel sensor. The second portion 102b of the pixel sensor has only one, two, or more gate dielectric thicknesses, each of which is less than or equal to the only first gate dielectric thickness of the first portion 102a of the pixel sensor. For example, the second portion 102b of the pixel sensor has only one or two gate dielectric thicknesses, including the first gate dielectric thickness T1, in the second IC chip 104b. Furthermore, the second portion 102b of the pixel sensor has a total number of transistors that is less than the total number of transistors of the pixel sensor 102, which in some embodiments is more than the total number of transistors of the first portion 102a of the pixel sensor. For example, the first portion 102a of the pixel sensor may have only one transistor, and the second portion 102b of the pixel sensor may have only three or more transistors.

[0109] As shown in the cross-sectional view 2100 of FIG. 21, a plurality of second transistors 110 are formed on the front side 1510fs of the second semiconductor substrate 1510. Note that only one second transistor 110, the reset transistor 118, is shown. However, additional second transistors (e.g., a select transistor and a source follower transistor) are shown hereafter in FIG. 22B. The second transistor 110 includes a respective second gate electrode 1514, a respective second gate dielectric layer 1516, and a pair of respective second source / drain regions 1518. The second gate electrodes 1514 are stacked with the second gate dielectric layer 1516 that separates the second gate electrodes 1514 from the second semiconductor substrate 1510. Furthermore, the second gate dielectric layers 1516 each have a thickness equal to or less than the only gate dielectric thickness of the first portion 102a of the pixel sensor. For example, the second gate dielectric layer 1516 of the reset transistor 118 may have a first gate dielectric thickness T1. Pairs of second source / drain regions 1518 are in the second semiconductor substrate 1510 , and each second gate electrode 1514 is between the second source / drain regions of a respective pair of second source / drain regions 1518 .

[0110] As shown in the cross-sectional view 2200A of FIG. 22A and the circuit diagram 2200B of FIG. 22B, a second interconnect structure 1512 and a second junction structure 1526b are formed stacked above and electrically coupled to the second transistor 110. The second interconnect structure 1512 includes a plurality of second conductive lines 1520 and a plurality of second conductive vias 1522 in a second interconnect dielectric layer 1524. The second conductive lines 1520 and the second conductive vias 1522 are grouped into a plurality of second wire levels and a plurality of second via levels, respectively, that are alternately stacked to define a conductive path. The second junction structure 1526b is electrically coupled to the second interconnect structure 1512 over the second interconnect structure 1512. Furthermore, the second interface structure 1526 b has been described as like the first interface structure 1526 a , except that the first interface via 1534 extends from the first interface pad 1532 to the second interconnect structure 1512 .

[0111] 22B, the plurality of second transistors 110 includes a reset transistor 118, a source follower transistor 120, and a select transistor 122 electrically interconnected by a second interconnect structure 1512 (see FIG. 22A). The source follower transistor 120 and the select transistor 122 are electrically coupled in series. Additionally, the reset transistor 118 has a source / drain region electrically coupled (e.g., electrically shorted) to the gate electrode of the source follower transistor 120.

[0112] As depicted in cross-sectional view 2300A of Figure 23A and circuit diagram 2300B of Figure 23B, the first IC chip 104a of Figure 20 is flipped vertically and bonded to the second IC chip 104b of Figures 22A and 22B at a first bonding interface 1528. The bond forms a pixel sensor 102 from a first portion 102a of the pixel sensor 102 in Figure 20 and a second portion 102b of the pixel sensor 102 in Figures 22A and 22B.

[0113] Because the pixel sensor 102 spans the first and second IC chips 104a and 104b, the pixel sensor 102 has fewer transistors in the first IC chip 104a than it would otherwise. For example, instead of having four transistors in the first IC chip 104a, the pixel sensor 102 may have only one transistor in the first IC chip 104a. This allows the pixel sensor 102 to be scaled in the first IC chip 104a without scaling the photodetecting element 106. Furthermore, because the pixel sensor 102 has only one gate dielectric thickness (e.g., the first gate dielectric thickness T1) in the first IC chip 104a, the complexity of forming the first transistor 108 is reduced compared to otherwise. In this way, the first transistor 108 can be scaled more easily. This further allows the pixel sensor 102 to be scaled in the first IC chip 104a without scaling the photodetecting element 106.

[0114] Since the light detection element 106 is relatively large and is present in the first IC chip 104a but not in the second IC chip 104b, the portion of the pixel sensor 102 in the first IC chip 104a limits the miniaturization of the pixel sensor 102. Therefore, miniaturization of the pixel sensor 102 in the first IC chip 104a can have the effect of miniaturizing the entire pixel sensor 102. As described above, the pixel sensor 102 can be miniaturized without miniaturizing the light detection element 106, so the performance of the pixel sensor 102 can be improved even in a small size.

[0115] 24, the structure of Figures 23A and 23B is flipped vertically and the second semiconductor substrate 1510 is thinned from the backside 1510bs of the second semiconductor substrate 1510. The thinning may be performed, for example, by chemical mechanical polishing (CMP), or the like.

[0116] 24, a TSV 1634 is formed that extends through the second semiconductor substrate 1510 from the backside 1510bs of the second semiconductor substrate 1510 to the second interconnect structure 1512. Further, the TSV 1634 is formed separated from the second semiconductor substrate 1510 and the second interconnect dielectric layer 1524 by a TSV dielectric layer 1636.

[0117] 25, a third bond portion structure 1624a is formed on the backside 1510bs of the second semiconductor substrate 1510. The third bond portion structure 1624a includes a second bond pad 1630 and a second bond via 1632 in a second bond dielectric layer 1628. The second bond pad 1630 and the second bond dielectric layer 1628 form a common bond surface, and the second bond via 1632 extends from the second bond pad 1630 to the TSV 1634.

[0118] 26, 27A, and 27B, a third IC chip 104c is formed that includes an ASIC 702. The ASIC 702 has only one, two, or more gate dielectric thicknesses that are less than or equal to a minimum gate dielectric thickness of the only one, two, or more gate dielectric thicknesses that the pixel sensors 102 have on the second IC chip 104b, respectively. For example, the ASIC 702 has only two or more gate dielectric thicknesses on the third IC chip 104c, including a first gate dielectric thickness T1.

[0119] As shown in the cross-sectional view 2600 of FIG. 26, a plurality of third transistors 704 are formed on the front side 1608fs of the third semiconductor substrate 1608. Note that only one third transistor 704 is shown. However, additional third transistors are shown in FIG. 27B. The third transistor 704 includes a respective third gate electrode 1612, a respective third gate dielectric layer 1614, and a pair of respective third source / drain regions 1616. The third gate electrodes 1612 are respectively stacked with the third gate dielectric layer 1614 that separates the third gate electrodes 1612 from the third semiconductor substrate 1608. Furthermore, the third gate dielectric layer 1614 each has a thickness equal to or less than the minimum gate dielectric thickness that the pixel sensor 102 has in the second IC chip 104b. For example, the third gate dielectric layer 1614 of the illustrated third transistor 704 may have a first gate dielectric thickness T1. A pair of third source / drain regions 1616 are in the third semiconductor substrate 1608 , and each third gate electrode 1612 is between the third source / drain regions of a respective pair of third source / drain regions 1616 .

[0120] As shown in the cross-sectional view 2700A of FIG. 27A and the circuit diagram 2700B of FIG. 27B, a third interconnect structure 1610 and a fourth junction structure 1624b are formed stacked on and electrically coupled to the third transistor 704. The third interconnect structure 1610 includes a plurality of third conductive lines 1618 and a plurality of third conductive vias 1620 in a third interconnect dielectric layer 1622. The third conductive lines 1618 and the third conductive vias 1620 are grouped into a plurality of third wire levels and third via levels, respectively, that are alternately stacked to define a conductive path. The fourth junction structure 1624b is illustrated as the third junction structure 1624a overlying the third semiconductor substrate 1619, except that a second junction via 1632 extends from the second bond pad 1630 to the third interconnect structure 1610.

[0121] 27B, the plurality of third transistors 704 includes at least one n-type transistor 704n and at least one p-type transistor 704p. Note that ellipses are used in the ASIC 702 to represent zero or more additional third transistors. Further, the n-type transistor 704n has a second gate dielectric thickness T2, and the p-type transistor 704p has a first gate dielectric thickness T1.

[0122] As shown in cross-section 2800A of Figure 28A and circuit diagram 2800B of Figure 28B, the structure of Figure 25 is flipped vertically and bonded to the third IC chip 104c of Figures 27A and 27B at the second bonding interface 1626. The bond electrically couples the pixel sensor 102 to the ASIC 702.

[0123] 29, the first semiconductor substrate 1306 is thinned from the backside 1306bs of the first semiconductor substrate 1306. The thinning may be performed by, for example, CMP or the like.

[0124] 29, a backside passivation layer 1536, a color filter 1538, and a microlens 1540 are formed on the backside 1306bs of the first semiconductor substrate 1306 and stacked above the first IC chip 104a. The backside passivation layer 1536 is a dielectric and is transparent to radiation. The color filter 1538 is between the backside passivation layer 1536 and the microlens 1540. Further, the color filter 1538 is configured to transmit the first color wavelength while blocking the second color wavelength. The microlens 1540 is configured to focus the incident radiation onto the photodetector element 106 to increase quantum efficiency.

[0125] Although Figures 18, 19A, 19B, 20, 21, 22A, 22B, 23A, 23B, 24-26, 27A, 27B, 28A, 28B, and 29 have been described with reference to a method, it should be understood that the structures illustrated in these figures are not limited to the method and can be separate and independent of the method. Although Figures 18, 19A, 19B, 20, 21, 22A, 22B, 23A, 23B, 24-26, 27A, 27B, 28A, 28B, and 29 have been described as a sequence of acts, it should be understood that in other embodiments, the order of acts may be changed. 18, 19A, 19B, 20, 21, 22A, 22B, 23A, 23B, 24-26, 27A, 27B, 28A, 28B, and 29 illustrate and describe a particular set of acts, in other embodiments some of the acts illustrated and / or described may be omitted, and further, in other embodiments acts not illustrated and / or described may be included.

[0126] 18, 19A, 19B, 20, 21, 22A, 22B, 23A, 23B, 24-26, 27A, 27B, 28A, 28B, and 29 depict the formation of image sensors having particular gate dielectric thicknesses, other gate dielectric thicknesses are possible. For example, the gate dielectric thicknesses of the first, second, and third IC chips 104a-104c may alternatively be formed according to any of the embodiments described above, such as the embodiments described with respect to FIGS. 1, 2, 3A-3C, 4-8, 9A-9D, 10-13, 14A-14D, 15, 16A-16C, and 17. Additionally, while Figures 18, 19A, 19B, 20, 21, 22A, 22B, 23A, 23B, 24-26, 27A, 27B, 28A, 28B, and 29 depict the formation of a single pixel sensor 102 in an image sensor, it should be understood that multiple instances of pixel sensor 102 may be formed simultaneously. These multiple instances may be formed, for example, in the grid pattern seen in Figures 10-12.

[0127] Referring to FIG. 30, a block diagram 3000 of some embodiments of the methods of FIGS. 18, 19A, 19B, 20, 21, 22A, 22B, 23A, 23B, 24-26, 27A, 27B, 28A, 28B, and 29 is provided.

[0128] At 3002, a first IC chip is formed including a first portion of a pixel sensor, the first portion of the pixel sensor having only one gate dielectric thickness. See, e.g., Figures 18, 19A, 19B, 20. Such formation may include, for example, 1) forming a photodetecting element in a first semiconductor substrate at 3002a (see, e.g., Figure 18), 2) depositing a protective layer and a first gate electrode layer over a front side of the first semiconductor substrate at 3002b (see, e.g., Figure 18), 3) patterning the first gate electrode layer to form a first transistor adjacent to the photodetecting element and having only one gate dielectric thickness at 3002c (see, e.g., Figures 19A and 19B), and 4) forming a first interconnect structure over and electrically coupled to the first transistor at 3002d (see, e.g., Figure 20).

[0129] At 3004, a second IC chip is formed that includes a second portion of the pixel sensor, the second portion of the pixel sensor including a plurality of second transistors, each having only one, two, or more gate dielectric thicknesses that are less than or equal to the only gate dielectric thickness of the first portion of the pixel sensor (see, e.g., Figures 21, 22A, and 22B).

[0130] At 3006, the first IC chip and the second IC chip are bonded together at a first bonding interface, see, for example, Figures 23A and 23B.

[0131] At 3008, a TSV is formed that passes through the second semiconductor substrate of the second IC chip and extends to a second interconnect structure of the second IC chip on the front side of the second semiconductor substrate. See, for example, FIG.

[0132] At 3010, junction structures are formed over and electrically coupled to the TSVs on the backside of the second semiconductor substrate, see, for example, FIG.

[0133] At 3012, a third IC chip is formed that includes an ASIC, the ASIC including a plurality of third transistors, each having only one, two, or more gate dielectric thicknesses that are less than or equal to the only one, two, or more gate dielectric thicknesses of the second portion of the pixel sensor (see, e.g., Figures 26, 27A, and 27B).

[0134] At 3014, the second IC chip and the third IC chip are bonded together at a second bonding interface. See, for example, Figures 28A and 28B.

[0135] At 3016, the first semiconductor substrate is thinned from a backside of the first semiconductor substrate. See, for example, FIG.

[0136] At 3018, a backside passivation layer, a color filter, and a microlens are formed that are stacked above the first IC chip on the backside of the first semiconductor substrate. See, for example, FIG.

[0137] 30 block diagram 3000 illustrates and describes a sequence of acts or events, it should be understood that the illustrated order of such acts or events is not to be construed as limiting. For example, some acts may occur in different orders and / or concurrently with other acts or events than those illustrated and / or described herein. Furthermore, not all acts are required to implement one or more aspects or embodiments of the description herein, and one or more acts illustrated herein may take place in one or more other acts and / or phases.

[0138] In some embodiments, the present disclosure provides an image sensor having a first IC chip, a second IC chip stacked on the first IC chip, and a pixel sensor spanning the first and second IC chips, the pixel sensor including a first transistor and a photodetector element in the first IC chip, and further including a plurality of second transistors in the second IC chip, the first transistor including a gate dielectric layer having a first thickness, and the plurality of second transistors including individual gate dielectric layers having a second thickness less than or equal to the first thickness. In some embodiments, the pixel sensor is a 4T type APS. In some embodiments, the pixel sensor includes only one transistor in the first IC chip and only three or more transistors in the second IC chip. In some embodiments, each second thickness is less than the first thickness. In some embodiments, the plurality of second transistors includes a reset transistor, a source follower transistor, and a select transistor, the source follower transistor and the select transistor are electrically coupled in series, and the gate electrode of the source follower transistor is electrically shorted to the source / drain region of the reset transistor and the source / drain region of the first transistor. In some embodiments, the pixel sensor is repeated in multiple columns and multiple rows, and the repetitions of the pixel sensor do not overlap. In some embodiments, the pixel sensor has only one photodetector element. In some embodiments, the pixel sensor has a plurality of photodetector elements including the photodetector element and a plurality of first transistors including the first transistor, the plurality of first transistors corresponding to the plurality of photodetector elements in a one-to-one correspondence and electrically coupled to a common node.

[0139] In some embodiments, the present disclosure provides another image sensor including a first semiconductor substrate, adjacent photodetector elements and a first transistor on the first semiconductor substrate, a second semiconductor substrate, a plurality of second transistors on the second semiconductor substrate, a third semiconductor substrate stacked with the first and second semiconductor substrates such that the second semiconductor substrate is between the first and third semiconductor substrates, and a plurality of third transistors on the third semiconductor substrate, the photodetector elements and the first and second transistors forming a pixel sensor, and each gate dielectric thickness of the second transistors is between, inclusively, the gate dielectric thickness of the first transistor and a maximum gate dielectric thickness in the third transistor. In some embodiments, the third transistor forms an ASIC electrically coupled to the pixel sensor. In some embodiments, each gate dielectric thickness of the plurality of second transistors is less than the gate dielectric thickness of the first transistor. In some embodiments, the maximum gate dielectric thickness in the plurality of third transistors is less than each gate dielectric thickness of the second transistor. In some embodiments, the pixel sensor has only two different gate dielectric thicknesses in the second semiconductor substrate. In some embodiments, the plurality of second transistors include source follower transistors, a gate electrode of the source follower transistor being electrically shorted with a source / drain region of the first transistor, and a gate dielectric thickness of the source follower transistor being less than a gate dielectric thickness of the first transistor.

[0140] In some embodiments, the present disclosure provides a method of forming an image sensor, the method including forming a first IC chip including forming a photodetector element in a first substrate, forming a first transistor on the first substrate adjacent to the photodetector element, where the photodetector element and the first transistor form a first pixel sensor portion, forming a first interconnect structure overlying the first transistor and the photodetector element and further electrically coupled to the first transistor, forming a second IC chip including forming a plurality of second transistors on a second substrate, where the second transistor forms a second pixel sensor portion, and forming a second interconnect structure overlying the second transistor and electrically coupled to the second transistor, and bonding the first and second IC chips together such that the first and second pixel sensor portions are stacked and electrically coupled together to form a pixel sensor, where the first transistor includes a gate dielectric layer of a first thickness and the second transistor includes a gate dielectric layer of a second thickness less than or equal to the first thickness. In some embodiments, forming the first transistor includes depositing a dielectric passivation layer covering the photodetector element and having a first thickness, depositing a gate electrode layer covering the dielectric passivation layer, and patterning the gate electrode layer to form a gate electrode separated from the first substrate by the dielectric passivation layer, which continues to cover the photodetector element after bonding. In some embodiments, the bonding is performed by bonding in which metal pads of each of the first and second IC chips are bonded together at an interface and dielectric layers of each of the first and second IC chips are bonded together at the interface. In some embodiments, the method further includes forming a third IC chip including forming a plurality of third transistors on a third substrate, the third transistors including respective gate dielectric layers having a third thickness less than or equal to each of the first and second thicknesses, and forming a third interconnect structure covering the third transistors, the third transistors and the third interconnect structure forming an ASIC, and bonding the second IC chip and the third IC chip together such that the second IC chip is between the first IC chip and the third IC chip, and the ASIC is electrically coupled to the pixel sensor.In some embodiments, forming the first IC chip includes forming a plurality of instances of a first pixel sensor portion arranged in a grid pattern, and forming the second IC chip includes forming a plurality of instances of a second pixel sensor portion arranged in a grid pattern, the plurality of instances of the second pixel sensor portion corresponding to the plurality of instances of the first pixel sensor portion in a one-to-one correspondence.

[0141] The foregoing outlines features of some embodiments so that those skilled in the art may more easily understand aspects of the present disclosure. Those skilled in the art should appreciate that this disclosure may be readily used as a basis for designing or modifying other processes and structures to carry out the same purposes and / or achieve the same advantages as the embodiments presented herein. Those skilled in the art should also appreciate that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various modifications, substitutions, and alterations may be made without departing from the spirit and scope of the present disclosure. [Industrial Applicability]

[0142] The disclosed image sensor and method for forming the image sensor may be used in applications where there is a high requirement for high performance of the pixel sensor even in small size. [Explanation of symbols]

[0143] 100, 300A, 300B, 300C, 400, 500, 600, 700, 900A~900D, 1900B, 2200B, 2300B, 2700B, 2800B: Circuit diagram 102: Pixel sensor 104a: First IC chip 104b: Second IC chip 104c: 3rd IC chip 106: Photodetector element 108: First transistor 110: second transistor 112: Pixel circuit 114: Grand 116: Transfer transistor 118: Reset transistor 120: Source follower transistor 122: Selection transistor 200, 800, 1000, 1200, 1300, 1400A~1400D, 1500, 1600A~1600C, 1700, 1800, 1900A, 2000, 2100, 2200A, 2300A, 2400, 2500, 2600, 2700A, 2800A, 2900: Cross-section 202, 802: Radiation 602: Auxiliary pixel circuit 702: ASIC 704: 3rd transistor 704p: p-type transistor 704n: n-type transistor 1100: Plan view layout diagram 1302: first gate dielectric layer 1304: Protective layer 1306: First semiconductor substrate 1306bs: Backside of first semiconductor substrate 1306fs: Front side of first semiconductor substrate 1308: Collector area 1310: First gate electrode 1312: first source / drain region pair 1314: First channel region 1402: Dielectric layer 1502: First interconnect structure 1504: First conductive wire 1506: First conductive via 1508: First interconnect dielectric layer 1510: second semiconductor substrate 1510bs: Backside of second semiconductor substrate 1510fs: Front side of second semiconductor substrate 1512: second interconnect structure 1514: Second gate electrode 1516: second gate dielectric layer 1518: second source / drain region pair 1520: Second conductive wire 1522: Second conductive via 1524: second interconnect dielectric layer 1526: 1st joint structure 1526a: 1st joint structure 1526b:Second joint structure 1528: 1st bonding interface 1530: First bonding dielectric layer 1532: First bonding pad 1534: First junction via 1536: Backside passivation layer 1538: Color filter 1540: Microlens 1602: Front side passivation layer 1604, 1634: Through-substrate vias (TSV) 1606, 1636: TSV dielectric layers 1608: Third semiconductor substrate 1608fs: Front side of the third semiconductor substrate 1610: Third interconnect structure 1612: Third gate electrode 1614: Third gate dielectric layer 1616: Third source / drain region pair 1618: Third conductive wire 1620: 3rd conductive via 1622: Third interconnect dielectric layer 1624:Second joint structure 1624a: Third joint structure 1624b: 4th joint structure 1626:Second bonding interface 1628: Second bonding dielectric layer 1630: 2nd bond pad 1632: Second junction via 1702: Trench isolation structure 1802: First gate electrode layer 3000: Block diagram 3002, 3002a, 3002b, 3002c, 3002d, 3004, 3006, 3008, 3010, 3012, 3014, 3016, 3018: Act A-A': Line C1, C2, C3, CN : column FD: Floating Diffusion Node OUT: Output R1, R2, R3, R M :column SEL: Selection signal T1: first gate dielectric thickness T2: second gate dielectric thickness T3: third gate dielectric thickness T4: fourth gate dielectric thickness TX: Transmit signal VDD: Power supply voltage Vrst: Reset voltage

Claims

1. a first integrated circuit (IC) chip; a second IC chip stacked on the first IC chip; a third IC chip stacked on the second IC chip; a pixel sensor spanning the first IC chip, the second IC chip, and the third IC chip; Including, the pixel sensor includes a first transistor and a photodetector element in the first IC chip, a plurality of second transistors in the second IC chip, and a plurality of third transistors in the third IC chip; the first transistor includes a gate dielectric layer of a first thickness, and the plurality of second transistors include respective gate dielectric layers of a second thickness that is less than or equal to the first thickness; the second IC chip has a front side on which the plurality of second transistors are arranged, and is stacked such that the front side faces the first IC chip; the second thickness being greater than or equal to a maximum third thickness of a gate dielectric layer in the third transistor; Image sensor.

2. The image sensor of claim 1 , wherein each said second thickness is less than said first thickness.

3. the plurality of second transistors include a reset transistor, a source follower transistor, and a selection transistor; the source follower transistor and the select transistor are electrically coupled in series; a gate electrode of the source follower transistor is electrically shorted to a source / drain region of the reset transistor and a source / drain region of the first transistor; 2. The image sensor of claim 1.

4. 2. The image sensor of claim 1, wherein the pixel sensors are repeated in multiple rows and multiple columns, and the repetitions of the pixel sensors do not overlap.

5. A first semiconductor substrate; a photodetector element and a first transistor adjacent to each other on the first semiconductor substrate; A second semiconductor substrate; a plurality of second transistors on the second semiconductor substrate; a third semiconductor substrate stacked on the first semiconductor substrate and the second semiconductor substrate; a plurality of third transistors on the third semiconductor substrate; Including, the second semiconductor substrate is between the first semiconductor substrate and the third semiconductor substrate and is spaced apart from the first semiconductor substrate and the third semiconductor substrate; the photodetector element, the first transistor, and the plurality of second transistors form a pixel sensor; a gate dielectric thickness of each of the plurality of second transistors is equal to or less than a gate dielectric thickness of the first transistor and is equal to or greater than a maximum gate dielectric thickness among the plurality of third transistors; Image sensor.

6. The image sensor of claim 5 , wherein a gate dielectric thickness of each of the plurality of second transistors is less than a gate dielectric thickness of the first transistor.

7. 1. A method of forming an image sensor, comprising: forming a photodetector element in a first substrate; forming a first transistor on the first substrate adjacent to the photodetector element, the photodetector element and the first transistor forming a first pixel sensor portion; forming a first interconnect structure overlying the first transistor and the photodetector element and electrically coupled to the first transistor; Including, forming a first integrated circuit (IC) chip; forming a plurality of second transistors on a second substrate, the second transistors forming second pixel sensor portions; forming a second interconnect structure overlying and electrically coupled to the second transistor, the first transistor including a gate dielectric layer having a first thickness and the second transistor including a separate gate dielectric layer having a second thickness less than or equal to the first thickness; Including, forming a second IC chip; forming a plurality of third transistors on a third substrate, the third transistors including respective gate dielectric thicknesses of a third thickness less than each of the first thickness and the second thickness; Including, forming a third IC chip; bonding the first IC chip and the second IC chip together with the second interconnect structure of the second IC chip facing the first IC chip such that the first pixel sensor portion and the second pixel sensor portion are stacked and electrically coupled together to form a pixel sensor; Including, method.

8. forming the first transistor; depositing a dielectric protection layer covering the photodetector elements and having the first thickness; depositing a gate electrode layer overlying the dielectric protection layer; patterning the gate electrode layer to form a gate electrode separated from the first substrate by the dielectric passivation layer; Including, the dielectric protection layer continues to cover the photodetector element after bonding; The method of claim 7.

9. 8. The method of claim 7, wherein the bonding is performed by bonding in which metal pads of the first IC chip and the second IC chip are bonded together at an interface and dielectric layers of the first IC chip and the second IC chip are bonded together at the interface.

10. forming a plurality of third transistors on a third substrate; forming the third IC chip forming a third interconnect structure overlying the third transistor, the third transistor and the third interconnect structure forming an application specific integrated circuit (ASIC); Further comprising: The method comprises: bonding the second IC chip and the third IC chip together such that the second IC chip is between the first IC chip and the third IC chip, and the ASIC is electrically coupled to the pixel sensor. Further comprising: The method according to claim 7.

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