PACKAGE STRUCTURE FOR ENABLED CHIP INTERCONNECTION AND METHOD FOR MANUFACTURING SAME - Patent application

Abstract

To provide a package structure capable of improving the product integration degree to reduce a manufacturing cost and achieve chip interconnection.SOLUTION: Provided are a package structure for achieving chip interconnection and a method of manufacturing the same. The structure includes a core layer 100, a connection bridge layer 200, a first dielectric layer 300, a second dielectric layer 400, a first pad layer 500, and a second pad layer 600. The first dielectric layer is installed on a first surface of the core layer. The second dielectric layer is installed on a second surface opposed to the first surface, of the core layer. The first dielectric layer is installed between the core layer and the first pad layer. The second dielectric layer is installed between the second pad layer and the core layer. The first pad layer and the core layer are connected with each other by a first guide hole 700. The second pad layer and the core layer are connected with each other by a second guide hole 800. The connection bridge layer buried in the first dielectric layer is electrically insulated from the core layer. The connection bridge layer and the first pad layer are connected with each other by a third guide hole 900.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present application relates to the field of integrated circuit technology, and more particularly to a package structure and method for fabricating the same for implementing chip interconnection, and a semiconductor device. [Background technology]

[0002] With the daily development of electronic technology, the performance requirements of electronic products are becoming higher and higher, which leads to more complex electronic components and wiring board circuits, and also to the demand for smaller and thinner electronic products. Therefore, the trend toward higher density integration, smaller size, and multi-function of electronic component packaging substrates such as chips is inevitable. Driven by the demand for smaller and lighter electronic products, the semiconductor packaging industry has higher and higher requirements for chip functions, which leads to more requirements for the number of I / O ports on chips, and the requirements for the size and spacing of I / O ports are becoming finer and finer. When the function of a single chip cannot meet the performance demand of a product, it is necessary to adopt multiple chips to perform interconnection to meet the demand. In the past, it was necessary to manufacture a TSV (Through Silicon Via) / TGV (Through Glass Via) interposer separately for chip interconnection, which is relatively expensive, the thickness of the TSV / TGV interposer is relatively thick, the volume of the package module increases, and the package module cannot be truly made short, light, and thin. In addition, the TSV / TGV interposer realizes multi-chip interconnection, and the design freedom is relatively low. The 2.5D package structure chip is mounted on the surface of the TSV / TGV interposer, and the welding of the interposer and the package carrier plate realizes the interconnection, and the integration degree is relatively low. Therefore, a new package structure to realize chip interconnection is required. Summary of the Invention [Problem to be solved by the invention]

[0003] SUMMARY OF THE PRESENT APPLICATION It is an object of the present application to solve, at least to some extent, one of the problems existing in the prior art.

[0004] Therefore, an object of the present invention is to provide a package structure for realizing chip interconnection, a method for fabricating the same, and a semiconductor device, which can improve the product integration degree and reduce the fabrication cost. [Means for solving the problem]

[0005] In order to achieve the above objective, the technical solutions according to the embodiments of the present application are as follows: A package structure for realizing chip interconnection, used for connection with a PCB, the package structure for realizing chip interconnection includes a core layer, a connection bridge layer, a first dielectric layer, a second dielectric layer, a first guide hole, a second guide hole, a third guide hole, a first pad layer, and a second pad layer, in which the first dielectric layer is disposed on a first surface of the core layer, the second dielectric layer is disposed on a second surface of the core layer opposite to the first surface, the first dielectric layer is disposed between the core layer and the first pad layer, and the second dielectric layer is disposed on the second pad layer. and the core layer, the first pad layer and the core layer are connected by the first guide hole, the second pad layer and the core layer are connected by the second guide hole, the connection bridge layer is embedded in the first dielectric layer, the connection bridge layer is electrically insulated from the core layer, the connection bridge layer and the first pad layer are connected by the third guide hole, the first pad layer is used for connection with the chip, the second pad layer is used for connection with the PCB, and the connection bridge layer is used for interconnecting two chips.

[0006] In addition, based on the package structure for realizing the chip interconnection of the above embodiment of the present invention, the present invention may further have the following additional technical features.

[0007] Furthermore, in an embodiment of the present application, the core layer includes a base material, a first sub-wiring layer, a second sub-wiring layer, a third sub-wiring layer, a fourth sub-wiring layer, a fourth guide hole, a fifth guide hole, a sixth guide hole, a third dielectric layer, and a fourth dielectric layer, wherein the first sub-wiring layer is disposed on a first surface of the base material, the second sub-wiring layer is disposed on a second surface of the base material opposite to the first surface, and the first sub-wiring layer and the second sub-wiring layer are connected to each other by the fourth guide hole. the fourth guide hole is provided on the base material, the third dielectric layer is provided between the third sub-wiring layer and the first sub-wiring layer, the third sub-wiring layer and the first sub-wiring layer are connected by the fifth guide hole provided in the third dielectric layer, the fourth dielectric layer is provided between the fourth sub-wiring layer and the second sub-wiring layer, and the fourth sub-wiring layer and the second sub-wiring layer are connected by the sixth guide hole provided in the fourth dielectric layer.

[0008] Furthermore, in an embodiment of the present application, the connecting bridge layer includes one or more connecting bridges.

[0009] Furthermore, in an embodiment of the present application, the connection bridge layer includes at least one or a combination of a film wiring layer, a silicon interposer, a glass interposer, or a chip.

[0010] Furthermore, in an embodiment of the present application, the first dielectric layer includes at least one of a viscous medium material, a thermosetting medium material, or a photosensitive medium material.

[0011] On the other hand, an embodiment of the present application further provides a method for fabricating a package structure realizing chip interconnection according to any one of the above claims, the method comprising: forming the core layer; applying the first dielectric layer to the first surface of the core layer and the second dielectric layer to the second surface of the core layer; In the process of applying the first dielectric layer, the connecting bridge layer is embedded in the first dielectric layer; forming, in the first dielectric layer, the first guide hole disposed between the core layer and the first pad layer, and the third guide hole disposed between the connection bridge layer and the first pad layer, and forming, in the second dielectric layer, the second guide hole; forming the first pad layer on the first guide hole and the third guide hole, and forming the second pad layer on the second guide hole.

[0012] Furthermore, the embodiment of the present application further includes the steps of mounting a chip on the first pad layer and welding a PCB on the second pad layer.

[0013] Further, in an embodiment of the present application, the step of forming a core layer comprises: forming a first sub-wiring layer on a first surface of a base material, forming a second sub-wiring layer on an opposing second surface of the base material, and forming a fourth guide hole in the base material; applying a third dielectric layer on the first sub-wiring layer, applying a fourth dielectric layer on the second sub-wiring layer, and opening windows in the third dielectric layer and the fourth dielectric layer; forming a fifth guide hole and a third sub-wiring layer on the third dielectric layer, and forming a sixth guide hole and a fourth sub-wiring layer in the fourth dielectric layer. Effect of the Invention

[0014] The advantages and beneficial effects of the present application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present application.

[0015] The present application provides an improved method for manufacturing a semiconductor device, comprising: providing a connection bridge layer embedded in a first dielectric layer and a third guide hole, which enables two or more chips to be interconnected; providing a first pad layer and a first guide hole to realize a connection between a core layer of a package structure and a chip; and providing a second pad layer and a second guide hole to realize an interconnection between a core layer of a package structure and a PCB, thereby finally realizing high-density integration of interconnections between the package structure, the PCB and the chip, and interconnections between multiple chips, and reducing manufacturing costs. [Brief description of the drawings]

[0016] [Figure 1] FIG. 2 is a structural schematic diagram of a package structure for realizing chip interconnection in a specific embodiment of the present invention; [Diagram 2] FIG. 2 is a structural schematic diagram of a core layer of a packaging structure realizing chip interconnection in a specific embodiment of the present invention; [Diagram 3] 2A to 2C are schematic diagrams illustrating steps of a method for fabricating a packaging structure for achieving chip interconnection in a specific embodiment of the present invention. [Figure 4] 4 is a schematic diagram showing a step of forming a core layer in a method for fabricating a package structure for realizing chip interconnection in a specific embodiment of the present invention; FIG. [Diagram 5] 1 is a schematic diagram of a structural change of a core layer formation in a method for fabricating a package structure to realize chip interconnection in a specific embodiment of the present invention; [Figure 6] 1 is a schematic diagram of structural changes during fabrication of a package structure for achieving chip interconnection in a specific embodiment of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] The following describes in detail the embodiments of the present invention with reference to the accompanying drawings, and the principles and processes of the package structure realizing chip interconnection in the embodiments of the present invention and the manufacturing method of the package structure realizing chip interconnection are described below.

[0018] Referring to FIG. 1, the package structure realizing the chip interconnection of the present invention can be connected to a PCB to realize its circuit function, and the package structure includes a core layer 100, a connection bridge layer 200, a first dielectric layer 300, a second dielectric layer 400, a first pad layer 500, a second pad layer 600, a first guide hole 700, a second guide hole 800, and a third guide hole 900, where the first dielectric layer 300 can be disposed on a first surface of the core layer 100, and the second dielectric layer 400 can be disposed on a second surface of the core layer 100 opposite to the first surface, and the thicknesses of the first dielectric layer and the second dielectric layer can be the same or different.

[0019] The first dielectric layer 300 may be disposed between the core layer 100 and the first pad layer 500, the second dielectric layer 400 may be disposed between the second pad layer 600 and the core layer 100, the first pad layer 500 and the core layer 100 may be connected by a first guide hole 700, the first guide hole may be disposed inside the first dielectric layer, the second pad layer 600 and the core layer 100 may be connected by a second guide hole 800, the connecting bridge layer 200 may be embedded in the first dielectric layer 300, the connecting bridge layer 200 and the first pad layer 500 may be connected by a third guide hole 900, which is similar to the first guide hole 700, and the third guide hole 900 may be disposed inside the first dielectric layer, and the connecting bridge layer 200 may be electrically insulated from the core layer 100 when disposed. The first pad layer 500 can be used for connection with pins or connection balls of the chip, the second pad layer 600 can be used for connection with the PCB, and the connection bridge layer 200 can be used for interconnection between two chips. Note that the first pad layer 500 can connect the core layer 100 and the connection bridge layer 200, and since the electrical requirements of the two layers may be different, each sub-pad of the first pad layer 500 may be placed in a different volume.

[0020] Furthermore, in some embodiments of the present application, referring to FIG. 2 , the core layer 100 may include a substrate 1001, a first sub-wiring layer 1002, a second sub-wiring layer 1003, a third sub-wiring layer 1004, a fourth sub-wiring layer 1005, a third dielectric layer 1006, a fourth dielectric layer 1007, a fourth guide hole 1008, a fifth guide hole 1009, and a sixth guide hole 1010.

[0021] Here, the first sub-wiring layer 1002 is disposed on a first surface of the base material 1001, the second sub-wiring layer 1003 is disposed on a second surface of the base material 1001 opposite to the first surface, the first sub-wiring layer 1002 and the second sub-wiring layer 1003 are connected by a fourth guide hole 1008, the fourth guide hole 1008 is disposed on the base material 1001, and the third dielectric layer 1006 is disposed between the third sub-wiring layer 1004 and the first sub-wiring layer 1005. 1002, the third sub-wiring layer 1004 and the first sub-wiring layer 1002 are connected by a fifth guide hole 1009 provided in the third dielectric layer 1006, and the fourth dielectric layer 1007 is provided between the fourth sub-wiring layer 1005 and the second sub-wiring layer 1003, and the fourth sub-wiring layer 1005 and the second sub-wiring layer 1003 are connected by a sixth guide hole 1010 provided in the fourth dielectric layer 1007. Note that in some embodiments of the present application, the material of the third dielectric layer may be the same as the material of the fourth dielectric layer.

[0022] Further, in some embodiments of the present application, the connection bridge layer includes one or more connection bridges. Specifically, the present application can realize the interconnection of two or more chips, so that one or more connection bridge layers can be set accordingly, and when the number of chips to be interconnected is two, one connection bridge can be set in the connection bridge layer, and when the number of chips to be interconnected is N, N-1 connection bridges can be set in the connection bridge layer. In addition, when the electrical requirements of the chips to be interconnected are different, the parameters such as the length, width, and thickness of each connection bridge can be set to be the same, or some parameters or all parameters can be set to be different according to actual needs.

[0023] Furthermore, in some embodiments of the present application, the connection bridge layer may be a structure capable of realizing interconnection between multiple chips and capable of realizing electrical interconnection with high precision, so the connection bridge layer may include a film wiring layer, a silicon interposer, a glass interposer or a chip, a combination of one or two of them, or other combinations.

[0024] Furthermore, in some embodiments of the present application, the first dielectric layer may include at least one of a viscous medium material, a thermosetting medium material, or a photosensitive medium material. Or, it may be a combination of two of the viscous medium material, the thermosetting medium material, or the photosensitive medium material. A specific combination form may be to divide the first dielectric layer into two sub-dielectric layers, a first sub-dielectric layer and a second sub-dielectric layer, and the two sub-dielectric layers may be applied on the core layer as different materials. For example, the first sub-dielectric layer of the viscous medium material may be applied first, and the second sub-dielectric layer made of the thermosetting medium material may be applied on the basis of the sub-dielectric layer of the viscous medium material. Or, the first dielectric layer may be a first dielectric layer in which the first sub-dielectric layer, the second sub-dielectric layer, and the third sub-dielectric layer made of the three materials are mixed after being laminated. Specifically, the present application first applies a first sub-dielectric layer made of a viscous medium material, and places a connecting bridge layer on the surface of the first sub-dielectric layer made of the viscous medium material. The viscous medium material can fix the connecting bridge well and facilitates the subsequent processes, and the connecting bridge layer is embedded in the first dielectric layer composed of two or more sub-dielectric layers of different materials by applying the second sub-dielectric layer composed of a thermosetting medium material on the basis of the first sub-dielectric layer composed of the viscous medium material.

[0025] Furthermore, in some embodiments of the present application, the substrate may be made of an organic polymer material or a glass material, which are chemically stable, resistant to high temperatures, resistant to corrosion, and have good insulating properties, and can maintain good stability in the process of semiconductor manufacturing, so that the semiconductor manufacturing can be performed normally.

[0026] In addition, referring to Figure 3, which corresponds to the packaging structure realizing chip interconnection in Figure 1, an embodiment of the present application further provides a manufacturing method for a packaging structure realizing chip interconnection for manufacturing a packaging structure realizing chip interconnection in any one of the above embodiments, and the manufacturing method may include the following steps.

[0027] S1: Forms the core layer. In the embodiment of the present application, the core layer may be divided into a substrate, a single or multiple wiring layers, and a dielectric layer. The wiring layer is a circuit layer capable of realizing a specific circuit function, and when the circuit is relatively simple, the wiring layer may be a single layer. When a single circuit is not sufficient to realize the function of the entire module, the core layer may include a double or multiple wiring layers. When the circuit includes a mixed circuit, the core layer may also include a double or multiple wiring layers. For example, a high-speed circuit with a digital logic circuit frequency reaching or exceeding 45MHz-50MHz and a low-speed circuit with a digital logic circuit frequency lower than 45MHz-50MHz require a certain signal separation, and the corresponding circuits need to be installed on different layers, and correspondingly, different wiring layers need to be installed on two opposite surfaces of the substrate at this time. Specifically, the present application divides the core layer into different layers, such as a substrate, a first sub-wiring layer, a second sub-wiring layer, a third sub-wiring layer, a fourth sub-wiring layer, a third dielectric layer and a fourth dielectric layer, based on considerations of circuit integration and circuit function realization.

[0028] S2: Applying a first dielectric layer to a first surface of the core layer and applying a second dielectric layer to a second surface of the core layer. Specifically, in the manufacturing process, a first dielectric layer may be applied on a first surface, and after the application of the first dielectric layer, a second dielectric layer may be applied on another opposing surface. When the first dielectric layer is applied on the first surface, since the first dielectric layer is formed by laminating a plurality of different materials, in the process of applying the first dielectric layer, a first sub-dielectric layer made of a viscous medium material may be applied first, and a second sub-dielectric layer made of a thermosetting material or a photosensitive material may be applied on the basis of the first sub-dielectric layer. The first sub-dielectric layer and the second sub-dielectric layer collectively constitute the first dielectric layer.

[0029] S3: In the process of applying the first dielectric layer, embed a connecting bridge layer into the first dielectric layer. Specifically, in the manufacturing process, a first sub-dielectric layer may be provided on the first dielectric layer, and a connecting bridge layer may be provided on one side of the first sub-dielectric layer facing the core layer. When the number of connecting bridges in the connecting bridge layer is two or less, they may be provided at any positions with intervals. When the number of connecting bridges is more than one, the connecting bridges may be provided at equal intervals or may not be provided at equal intervals. After providing the connecting bridges, a second sub-dielectric layer is provided on each connecting bridge and the first sub-dielectric layer. The two sub-dielectric layers may be made of one of a viscous medium material, a thermosetting medium material, and a photosensitive medium material. The two sub-dielectric layers may be made of the same material or different materials. Specifically, in order to well fix the connecting bridges in the manufacturing process, the first sub-dielectric layer may be made of a viscous medium material, and the second sub-dielectric layer may be made of a thermosetting material.

[0030] S4: Form a first guide hole in the first dielectric layer, the first guide hole being located between the core layer and the first pad layer, and a third guide hole being located between the connection bridge layer and the first pad layer, and form a second guide hole in the second dielectric layer. Specifically, in some embodiments of the present application, when the first guide hole is manufactured, the area covering each connection bridge layer may be first windowed to form the window of the first guide hole, and then the other area of ​​the first dielectric layer may be windowed to form the window of the third guide hole. The depth of the window of the third guide hole may be greater than the depth of the window of the first guide hole, and the windowing method may be selected as laser windowing. Similarly, the second guide hole may be simultaneously windowed by selecting the laser windowing method. After the windowing is completed, the area where the windowing is performed is metallized to finally form the first guide hole, the second guide hole, and the third guide hole that can realize electrical conduction.

[0031] S5: A first pad layer is formed on the first guide hole and the third guide hole, and a second pad layer is formed on the second guide hole. Specifically, in some embodiments of the present application, the first pad layer and the second pad layer may adopt a plating method, and a first pad layer having the same or different volumes may be plated on the first guide hole and the third guide hole, and a second pad layer having the same or different volumes may be plated on the second guide hole. In addition, when plating, the surfaces on one side of the first guide hole and the third guide hole and the surface on the other side where the second guide hole is located may be plated simultaneously to form the first pad layer and the second pad layer at the same time. Alternatively, the first guide hole and the third guide hole may be plated first to form the first pad layer, and the second guide hole may be plated further to form the second pad layer.

[0032] Furthermore, in some embodiments of the present application, the method for fabricating a packaging structure for realizing chip interconnection may further include the following steps. S6: Mount a chip on the first pad layer, and weld a PCB on the second pad layer. Specifically, the first pad layer can be used to connect the chip and the core layer, and can also realize the interconnection between multiple chips, and the second pad layer can connect the core layer and the PCB, so that the circuit of the core layer can realize its specific function in the package structure realizing the chip interconnection. Therefore, in some embodiments, the package structure realizing the chip interconnection of the present application may mount the chip on the first pad layer and weld the PCB on the second pad layer.

[0033] Further, referring to FIG. 4, in some embodiments of the present application, the above step S1 may include the following steps:

[0034] S11: A first sub-wiring layer is formed on a first surface of a base material, a second sub-wiring layer is formed on an opposing second surface, and a fourth guide hole is formed in the base material. Specifically, the step may include forming a fourth guide hole by drilling the substrate and performing via hole metallization on the hole, which may adopt a copperization or metal sputtering process, and performing hole filling plating on the fourth guide hole to form the first sub-wiring layer and the second sub-wiring layer.

[0035] S12: A third dielectric layer is applied on the first sub-wiring layer, a fourth dielectric layer is applied on the second sub-wiring layer, and windows are formed in the third dielectric layer and the fourth dielectric layer. Specifically, the third dielectric layer may be a thermosetting insulating material or a photosensitive insulating material, and the fourth dielectric layer may be a thermosetting insulating material or a photosensitive insulating material. In the process, the third dielectric layer needs to completely cover the entire first sub-wiring layer, and the fourth dielectric layer needs to completely cover the second sub-wiring layer, thereby ensuring that the first sub-wiring layer and the second sub-wiring layer are insulated from some areas of other subsequent wiring layers. After the third dielectric layer and the fourth dielectric layer are applied, the third dielectric layer can be windowed. The windowing method can be selected according to the dielectric layer material, for example, the dielectric layer made of a photosensitive insulating material may adopt the exposure and development method to perform windowing, or may adopt a laser windowing process, and for the dielectric layer made of a thermosetting material, a laser windowing process may be adopted.

[0036] S13: A fifth guide hole and a third sub-wiring layer are formed on the third dielectric layer, and a sixth guide hole and a fourth sub-wiring layer are formed on the fourth dielectric layer. Specifically, a metal seed layer is fabricated on the surface of the third dielectric layer and the fourth dielectric layer, and a copperization or metal sputtering process may be adopted to fabricate the metal seed layer. After the metal seed layer is fabricated, a mask is applied to the dielectric layer, and a wiring pattern layer is further fabricated by exposure and development technology. After the wiring pattern is fabricated, a plurality of windows formed by window opening are further plated in step S12, and guide holes are finally formed. After plating is completed, the mask is peeled off. Finally, the metal seed layer is etched to finally form a fifth guide hole, a sixth guide hole, a third sub-wiring layer, and a fourth sub-wiring layer. Dry etching or wet etching may be adopted for the etching.

[0037] In the following, a manufacturing flow of a package structure realizing chip interconnection according to an embodiment of the present application will be described by taking a package structure realizing chip interconnection composed of two connection bridges as an example.

[0038] First, the core layer is produced.

[0039] The first step of the core layer fabrication is shown in FIG. 5A, in which a via hole is drilled on the substrate 1001, a metallization is performed on the via hole, a guide hole is formed to connect the opposing surfaces of the substrate, and finally, the guide hole is filled with plating to form a fourth guide hole 1008, a first sub-wiring layer 1002, and a second sub-wiring layer 1003 in the figure. The substrate 1001 may be an organic polymer, a glass material, or the like. The second step is shown in FIG. 5B, in which a third dielectric layer 1006 and a fourth dielectric layer 1007 are applied on the first wiring layer and the second wiring layer of the core layer, respectively, and windows are opened thereon to form a plurality of windows, which can be used to fabricate subsequent guide holes. The final step, referring to Fig. 5c, is to fabricate a metal seed layer on the surface of the third dielectric layer 1006 and the fourth dielectric layer 1007, and after the metal seed layer is fabricated, a mask is applied to the dielectric layer, and then a wiring pattern layer is fabricated by exposure and development technology, and after the wiring pattern is fabricated, the window formed by the window opening on the dielectric layer is plated, and after the plating is completed, the mask is peeled off, and finally the metal seed layer is etched, so as to finally form the fifth guide hole 1009, the sixth guide hole 1010, the third sub-wiring layer 1004 and the fourth sub-wiring layer 1005. Dry etching may be adopted for the etching.

[0040] Next, the remaining portions of the interconnect package structure are fabricated.

[0041] 6, first, the first and second dielectric layers are applied on the surfaces of both sides of the core layer in the above step. Referring to Fig. 6a and 6b, when applying the first dielectric layer 300, it is necessary to apply a first sub-dielectric layer 300a made of a viscous material first, so that the first sub-dielectric layer 300a completely covers one side of the core layer, and two connecting bridge layers 200 are arranged on the surface of the first sub-dielectric layer 300a at a distance from each other, and since the first sub-dielectric layer 300a is made of a viscous material, the viscous dielectric layer can help fix the two connecting bridges, and can prevent the connecting bridge layer 200 from shifting in the subsequent process. After applying the first sub-dielectric layer 300a, the second sub-dielectric layer 300b needs to be applied on the first sub-dielectric layer 300a and the connecting bridge layer 200, and the second sub-dielectric layer 300b needs to completely cover the first sub-dielectric layer 300a and the two connecting bridge layers 200, and finally complete the process of applying the first dielectric layer 300. Regarding the process of applying the second dielectric layer 400, in this embodiment, the material of the second dielectric layer 400 is only a thermosetting material, so the second dielectric layer 400 can be directly applied on the surface of one side of the core layer facing the first dielectric layer 300. It should be noted that the second dielectric layer 400 needs to completely cover the core layer. After applying the first dielectric layer 300 and the second dielectric layer 400, the first dielectric layer and the second dielectric layer 400 need to be windowed. 6c, when the dielectric layer is windowed, the first dielectric layer 300 above the connecting bridge layer 200 may be windowed first by exposure and development process to form a plurality of third window openings 900a, and then the remaining portion of the first dielectric layer may be windowed to form a plurality of first window openings 700a. Similarly, the second dielectric layer 400 may be windowed by laser windowing process to form a plurality of second window openings 800a in the second dielectric layer 400. After the windowing is completed, it is necessary to fabricate the first guide hole, the second guide hole, the third guide hole, the first pad layer and the second pad layer on both sides.Referring to FIG. 6d, a first guide hole 700, a second guide hole 800 and a third guide hole 900 are formed by hole filling plating, and a metal seed layer fabrication, circuit pattern fabrication, plating, film stripping and metal seed layer etching processes are carried out on the first dielectric layer 300 and the second dielectric layer 400, so that a first pad layer 500 is finally formed on the first guide hole 700 and the third guide hole 900, and a second pad layer 600 is formed on the second guide hole 800. Finally, the first pad layer 500 can realize interconnection between multiple chips, and the direct connection between the chip and the core layer can be realized, and the second pad layer 600 can realize the connection between the core layer and the PCB. Finally, referring to FIG. 6e, after completing the fabrication of the first pad layer and the second pad layer, multiple chips 1000 may be welded onto the pads of the first pad layer to realize chip interconnection, and a PCB 1100 may be welded onto the second pad layer to realize chip-to-PCB integration.

[0042] In some alternative embodiments, the functions / operations noted in the block diagrams may not occur in the order noted in the operational diagrams. For example, two blocks shown in succession may be executed substantially simultaneously, or the aforementioned blocks may be executed in reverse order, depending on the functions / operations involved. It should be noted that the embodiments shown and described in the flowcharts of this application are provided as examples to provide a more complete understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is changed and sub-operations described as part of a larger operation are executed independently.

[0043] In the above description of this specification, a statement referring to terms such as "one embodiment / example," "another embodiment / example," or "some embodiments / examples" means that the specific features, structures, materials, or characteristics described in connection with an embodiment or example are included in at least one embodiment or example of this application. In this specification, generalized expressions of such terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0044] Although embodiments of the present application have been shown and described, it should be understood that those skilled in the art can make various changes, modifications, substitutions, and variations to these embodiments without departing from the principles and spirit of the present application, and the scope of the present application is limited by the claims and their equivalents.

[0045] Although the above describes the preferred embodiments of the present application in detail, the present application is not limited to the above-described embodiments. Those skilled in the art may make various equivalent modifications or substitutions without departing from the spirit of the present application, and these equivalent modifications or substitutions are included within the scope limited by the claims of the present application.

Claims

1. A package structure for use in connection with a PCB and for realizing chip interconnection, comprising: a core layer, a connection bridge layer, a first dielectric layer, a second dielectric layer, a first guide hole, a second guide hole, a third guide hole, a first pad layer, and a second pad layer; wherein the first dielectric layer is disposed on a first surface of the core layer, and the second dielectric layer is disposed on a second surface of the core layer opposite to the first surface; the first dielectric layer is disposed between the core layer and the first pad layer, the second dielectric layer is disposed between the second pad layer and the core layer, the first pad layer and the core layer are connected by the first guide hole, the second pad layer and the core layer are connected by the second guide hole, the connection bridge layer is embedded in the first dielectric layer, the connection bridge layer is electrically insulated from the core layer, and the connection bridge layer and the first pad layer are connected by the third guide hole; the first pad layer is used for connection with the chip, the second pad layer is used for connection with the PCB, and the connection bridge layer is used for interconnecting two chips; the first dielectric layer includes a first sub-dielectric layer made of a viscous medium material and a second sub-dielectric layer made of a thermosetting medium material; the first sub-dielectric layer is formed on the first surface of the core layer so as to completely cover the first surface; the connecting bridge layer is disposed on a surface of the first sub-dielectric layer; the second sub-dielectric layer is formed on the first sub-dielectric layer and the connecting bridge layer so as to completely cover the first sub-dielectric layer and the connecting bridge layer; A package structure for achieving chip interconnection, comprising:

2. The core layer is the substrate, a first sub-wiring layer, a second sub-wiring layer, a third sub-wiring layer, a fourth sub-wiring layer, a fourth guide hole, a fifth guide hole, a sixth guide hole, a third dielectric layer, and a fourth dielectric layer; wherein the first sub-wiring layer is disposed on a first surface of the base material, the second sub-wiring layer is disposed on a second surface of the base material opposite to the first surface, the first sub-wiring layer and the second sub-wiring layer are connected by the fourth guide hole, and the fourth guide hole is disposed on the base material; the third dielectric layer is disposed between the third sub-wiring layer and the first sub-wiring layer, and the third sub-wiring layer and the first sub-wiring layer are connected by the fifth guide hole disposed in the third dielectric layer; the fourth dielectric layer is disposed between the fourth sub-wiring layer and the second sub-wiring layer, and the fourth sub-wiring layer and the second sub-wiring layer are connected by the sixth guide hole disposed in the fourth dielectric layer; 2. The package structure for realizing chip interconnection according to claim 1.

3. the connecting bridge layer includes one or more connecting bridges; 2. The package structure for realizing chip interconnection according to claim 1.

4. The connection bridge layer includes at least one or more combinations of a film wiring layer, a silicon interposer, a glass interposer, or a chip; 2. The package structure for realizing chip interconnection according to claim 1.

5. The substrate comprises an organic polymer material or a glass material; 3. The package structure for realizing chip interconnection according to claim 2.

6. A method for fabricating a package structure implementing the chip interconnection according to any one of claims 1 to 5, comprising the steps of: forming the core layer; applying the first dielectric layer to the first surface of the core layer and the second dielectric layer to the second surface of the core layer; In the process of applying the first dielectric layer, the connecting bridge layer is embedded in the first dielectric layer; forming, in the first dielectric layer, the first guide hole disposed between the core layer and the first pad layer, and the third guide hole disposed between the connection bridge layer and the first pad layer, and forming, in the second dielectric layer, the second guide hole; forming the first pad layer on the first guide hole and the third guide hole, and forming the second pad layer on the second guide hole; In the process of applying the first dielectric layer, the step of embedding a connecting bridge layer in the first dielectric layer includes: applying a first sub-dielectric layer composed of a viscous material over the first surface of the core layer so as to completely cover the first surface; disposing the connecting bridge layer over the first sub-dielectric layer; applying a second sub-dielectric layer composed of a thermosetting medium material over the first sub-dielectric layer and the connecting bridge layer so as to completely cover the first sub-dielectric layer and the connecting bridge layer; 23. A method for fabricating a package structure for achieving chip interconnection comprising:

7. The method further includes the steps of mounting a chip on the first pad layer and welding a PCB on the second pad layer.

7. The method for fabricating a package structure for realizing chip interconnection according to claim 6.

8. The step of forming the core layer comprises: forming a first sub-wiring layer on a first surface of a substrate, forming a second sub-wiring layer on an opposing second surface, and forming a fourth guide hole in the substrate; applying a third dielectric layer on the first sub-wiring layer, applying a fourth dielectric layer on the second sub-wiring layer, and opening windows in the third dielectric layer and the fourth dielectric layer; forming a fifth guide hole and a third sub-wiring layer on the third dielectric layer, and forming a sixth guide hole and a fourth sub-wiring layer on the fourth dielectric layer.

7. The method for fabricating a package structure for realizing chip interconnection according to claim 6.

9. At least one package structure implementing the chip interconnection according to any one of claims 1 to 5, A semiconductor device comprising:

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