Solid-state imaging element and imaging device

Abstract

a first substrate having a photoelectric conversion unit and a transfer transistor electrically connected to the photoelectric conversion unit; a second substrate having an output transistor disposed opposite the first substrate and including a gate electrode, a channel region of a first conductivity type disposed opposite the gate electrode, and a source / drain region of the first conductivity type adjacent to the channel region; and a drive circuit that outputs signal charges generated in the photoelectric conversion unit via the transfer transistor and the output transistor.

Description

[Technical field]

[0001] The present technology relates to a solid-state imaging element and an imaging device having a photoelectric conversion unit. [Background technology]

[0002] In recent years, in addition to being used for image capture, image sensors are also used for surveillance, automatic driving of automobiles, etc. For such image sensors, solid-state imaging elements such as CCDs (Charge Coupled Devices) and CMOSs ​​(Complementary Metal Oxide Semiconductors) are used.

[0003] A solid-state imaging device includes, for example, a photoelectric conversion unit provided for each pixel, and an output transistor that outputs a signal charge generated in the photoelectric conversion unit to a drive circuit (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2012-54876 A Summary of the Invention

[0005] In such a solid-state imaging device, it is desirable to suppress noise.

[0006] Therefore, it is desirable to provide a solid-state imaging element capable of suppressing noise, and an imaging apparatus including the same.

[0007] The solid-state imaging device (1) according to an embodiment of the present disclosure includes a photoelectric conversion unit 、 A transfer transistor electrically connected to the photoelectric conversion unit A charge storage section to which the signal charge generated in the photoelectric conversion section is transferred from the transfer transistor a first substrate having the above structure, a gate electrode provided opposite the first substrate, and a first conductivity type channel region disposed opposite the gate electrode; First conductivity typea second substrate having an output transistor including a first conductive type source-drain region adjacent to a channel region; and a drive circuit in which a signal charge generated in the photoelectric conversion unit is output via a transfer transistor and an output transistor. the first substrate includes a semiconductor substrate having a first surface serving as a light incidence side and a second surface opposed to the first surface, the semiconductor substrate has a well region of a second conductivity type different from the first conductivity type, the photoelectric conversion unit is formed by being embedded in the well region of the second conductivity type, the charge accumulation unit is composed of an impurity diffusion region of the first conductivity type provided in the well region of the second conductivity type near the first surface of the semiconductor substrate, and the transfer transistor has a channel region of the second conductivity type between the photoelectric conversion unit and the charge accumulation unit. .

[0008] An imaging device (1) according to an embodiment of the present disclosure includes the solid-state imaging element (1) according to the embodiment of the present disclosure.

[0009] The solid-state imaging element (2) according to one embodiment of the present disclosure includes: a semiconductor substrate having a first surface serving as a light incident side and a second surface opposed to the first surface; a photoelectric conversion unit; and a transfer transistor electrically connected to the photoelectric conversion unit; a charge accumulation section to which signal charges generated in the photoelectric conversion section are transferred from a transfer transistor; a channel region of a first conductivity type electrically connected to the transfer transistor; First conductivity type a gate electrode having a plurality of surfaces overlying the channel region; First conductivity type an output transistor including a first conductive type source-drain region adjacent to a channel region; and a drive circuit in which a signal charge generated in the photoelectric conversion unit is output via a transfer transistor and the output transistor. the semiconductor substrate has a well region of a second conductivity type different from the first conductivity type, the photoelectric conversion unit is formed by embedding the well region of the second conductivity type, the charge accumulation unit is composed of an impurity diffusion region of the first conductivity type provided in the well region of the second conductivity type near the first surface of the semiconductor substrate, and the transfer transistor has a channel region of the second conductivity type between the photoelectric conversion unit and the charge accumulation unit. .

[0010] An imaging device (2) according to an embodiment of the present disclosure includes the solid-state imaging element (2) according to the embodiment of the present disclosure.

[0011] In the solid-state imaging element (1)(2) and the imaging device (1)(2) according to an embodiment of the present disclosure, the output transistor has a channel region of the same conductivity type (first conductivity type) as that of the source / drain region, and therefore the current path of the channel region is formed away from the interface on the gate electrode side, which makes it difficult for carriers flowing through the channel region to be captured (trapped) by the interface on the gate electrode side.

[0012] Note that the effects described below are not necessarily limited to those described below, and may be any of the effects described in this disclosure. [Brief description of the drawings]

[0013] [Figure 1] 1 is a block diagram illustrating an example of a functional configuration of an imaging element according to a first embodiment of the present disclosure. [Diagram 2] 2 is a diagram illustrating an example of a circuit configuration of the pixel illustrated in FIG. 1. [Diagram 3] 2 is a schematic plan view illustrating an example of the configuration of a pixel illustrated in FIG. 1. [Figure 4A] 4 is a schematic diagram showing a cross-sectional configuration taken along line AA' shown in FIG. [Figure 4B] 4 is a schematic diagram showing a cross section taken along line BB' shown in FIG. [Diagram 5] 4C is a schematic cross-sectional view illustrating another example of the configuration of the gate electrode shown in FIG. 4B. [Figure 6A] 4B is a schematic cross-sectional view of an amplifying transistor according to a comparative example, which corresponds to FIG. 4A. [Figure 6B] 4B is a schematic cross-sectional view of an amplifying transistor according to a comparative example, the diagram corresponding to FIG. 4B. [Figure 7] 4C is a schematic cross-sectional view illustrating a current path flowing through the amplifying transistor illustrated in FIG. 4B. [Figure 8] 1 is a schematic cross-sectional view illustrating a configuration of an imaging element according to Modification 1. FIG. [Figure 9] 11 is a cross-sectional view illustrating a configuration of an imaging element according to Modification 2. FIG. [Figure 10] FIG. 11 is a diagram illustrating an example of a circuit configuration of a pixel of an image sensor according to Modification 3. [Figure 11] 11 is a schematic diagram illustrating an example of a planar configuration of the imaging element illustrated in FIG. 10. [Figure 12] 11 is a schematic diagram illustrating a schematic configuration of a main part of an imaging element according to a second embodiment of the present disclosure. FIG. [Figure 13] 13 is a diagram illustrating an example of the pixel and a readout circuit of FIG. 12. [Figure 14] 13 is a diagram illustrating an example of the pixel and a readout circuit of FIG. 12. [Figure 15] 13 is a diagram illustrating an example of the pixel and a readout circuit of FIG. 12. [Figure 16] 13 is a diagram illustrating an example of the pixel and a readout circuit of FIG. 12. [Figure 17] 1 is a diagram illustrating an example of a connection mode between a plurality of readout circuits and a plurality of vertical signal lines. [Figure 18] 13 is a diagram illustrating an example of a cross-sectional configuration of the image sensor in FIG. 12 in the vertical direction. [Figure 19] 13 is a schematic plan view illustrating a configuration of a main part of an image sensor according to Modification 4. FIG. [Figure 20A] 20 is a schematic diagram illustrating a cross-sectional configuration taken along line AA' shown in FIG. 19. [Figure 20B] 20 is a schematic diagram illustrating a cross-sectional configuration taken along line BB' shown in FIG. 19. [Figure 21A] 20B is a schematic cross-sectional view illustrating a step in the method for manufacturing the image sensor illustrated in FIG. 20A etc. [Figure 21B] FIG. 21B is a schematic cross-sectional view showing a step subsequent to FIG. 21A. [Figure 21C] FIG. 21C is a schematic cross-sectional view showing a step subsequent to FIG. 21B. [Figure 22A] FIG. 21D is a schematic cross-sectional view illustrating another example of the step subsequent to FIG. 21C. [Figure 22B] FIG. 22B is a schematic cross-sectional view showing a step subsequent to FIG. 22A. [Figure 22C] FIG. 22C is a schematic cross-sectional view showing a step subsequent to FIG. 22B. [Figure 22D] FIG. 22D is a schematic cross-sectional view showing a step following FIG. 22C. [Figure 22E] FIG. 22E is a schematic cross-sectional view showing a step following FIG. 22D. [Figure 22F] FIG. 22B is a schematic cross-sectional view showing the step following FIG. 22E. [Figure 22G] FIG. 22C is a schematic cross-sectional view showing the step following FIG. 22F. [Fig. 22H] FIG. 22C is a schematic cross-sectional view showing the step following FIG. 22G. [Diagram 23] 13 is a schematic cross-sectional view illustrating a configuration of a main part of an image sensor according to Modification 5. FIG. [Figure 24] 24 is a diagram illustrating an example of a horizontal cross-sectional configuration of the imaging element of FIG. 23. [Diagram 25] 24 is a diagram illustrating an example of a horizontal cross-sectional configuration of the imaging element of FIG. 23. [Figure 26]FIG. 24 is a diagram illustrating an example of a wiring layout in a horizontal plane of the image sensor of FIG. 23. [Figure 27] 24 is a diagram illustrating an example of a wiring layout in a horizontal plane of the image sensor of FIG. 23. [Figure 28] 24 is a diagram illustrating an example of a wiring layout in a horizontal plane of the image sensor of FIG. 23. [Figure 29] FIG. 24 is a diagram illustrating an example of a wiring layout in a horizontal plane of the image sensor of FIG. 23. [Diagram 30] 13 is a diagram illustrating an example of a vertical cross-sectional configuration of an image sensor according to Modification 6. FIG. [Diagram 31] 13 is a diagram illustrating an example of a horizontal cross-sectional configuration of an image sensor according to Modification 7. FIG. [Diagram 32] 24 is a diagram illustrating another example of the horizontal cross-sectional configuration of the imaging element illustrated in FIG. 23. [Diagram 33] 13 is a diagram illustrating an example of a horizontal cross-sectional configuration of an image sensor according to Modification 8. FIG. [Diagram 34] 13 is a diagram illustrating an example of a horizontal cross-sectional configuration of an image sensor according to Modification 9. FIG. [Diagram 35] 23 is a diagram illustrating an example of a horizontal cross-sectional configuration of an image sensor according to Modification 10. FIG. [Diagram 36] 36 is a diagram illustrating another example (1) of the horizontal cross-sectional configuration of the imaging element illustrated in FIG. 35. FIG. [Figure 37] 36 is a diagram illustrating another example (2) of the horizontal cross-sectional configuration of the imaging element illustrated in FIG. 35. FIG. [Figure 38] 13 is a diagram illustrating an example of a circuit configuration of an image sensor according to the second embodiment and a modification thereof. FIG. [Figure 39] FIG. 39 is a diagram illustrating an example in which the imaging device of FIG. 38 is configured by stacking three substrates. [Diagram 40] 13 is a diagram illustrating an example in which a logic circuit is formed separately on a substrate on which pixels P are provided and a substrate on which a readout circuit is provided. FIG. [Diagram 41] FIG. 13 is a diagram illustrating an example in which a logic circuit is formed on a third substrate. [Diagram 42]FIG. 1 is a diagram illustrating an example of a schematic configuration of an imaging device including the imaging device according to the above embodiment and its modified example. [Diagram 43] 43 is a diagram showing an example of an imaging procedure in the imaging device of FIG. 42. [Diagram 44] 1 is a block diagram showing an example of a schematic configuration of an in-vivo information acquiring system. [Diagram 45] 1 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system. [Figure 46] 2 is a block diagram showing an example of a functional configuration of a camera head and a CCU. FIG. [Figure 47] 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; [Figure 48] 4 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit; FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, embodiments of the present technology will be described in detail with reference to the drawings. The description will be made in the following order. 1. First embodiment (an example of a solid-state imaging device provided with an amplifying transistor having a channel region of the same conductivity type as the source / drain region) 2. Modification 1 (Example in which the amplifying transistor has a Fin FET (Field Effect Transistor) structure) 3. Modification 2 (Example in which the amplifying transistor has a GAA (Gate All Around) structure) 4. Modification 3 (Example in which an amplification transistor is shared by multiple pixels) 5. Second embodiment (example of solid-state imaging device having a stacked structure of a first substrate, a second substrate, and a third substrate) 6. Modification 4 (Example in which the reset transistor, the amplification transistor, and the selection transistor have a FinFET structure) 7. Modification 5 (Example of FTI (Full Trench Isolation) Structure) 8. Modification 6 (Example of using Cu-Cu bonding on the outer edge of the panel) 9. Modification 7 (Example of Providing an Offset Between Pixels and Readout Circuits) 10. Modification 8 (Example in which the silicon substrate on which the readout circuit is provided is island-shaped) 11. Modification 9 (Example in which the silicon substrate on which the readout circuit is provided is island-shaped) 12. Modification 10 (Example in which FD is shared by four pixels P) 13. Modification 11 (Example in which the signal processing circuit is configured with a general column ADC circuit) 14. Modification 12 (Example in which the imaging element is configured by stacking three substrates) 15. Modification 13 (Logic circuit provided on first and second substrates) 16. Modification 14 (Logic circuit provided on third substrate) 17. Application Examples (Electronic Devices) 18. Application Examples

[0015] <First embodiment> (Overall configuration of the image sensor 10) 1 is a block diagram showing an example of a functional configuration of a solid-state imaging device (imaging device 10) according to a first embodiment of the present disclosure. The imaging device 10 is, for example, an amplification type solid-state imaging device such as a CMOS image sensor. The imaging device 10 may be another amplification type solid-state imaging device, or may be a charge transfer type solid-state imaging device such as a CCD.

[0016] The image sensor 10 has a semiconductor substrate 11 on which a pixel array section 12 and a peripheral circuit section are provided. The pixel array section 12 is provided, for example, in the center of the semiconductor substrate 11, and the peripheral circuit section is provided outside the pixel array section 12. The peripheral circuit section includes, for example, a vertical drive circuit 13, a signal processing circuit 14, a horizontal drive circuit 15, and a system control circuit 16.

[0017] In the pixel array section 12, unit pixels (pixels P) each having a photoelectric conversion section that generates and internally accumulates a signal charge whose amount corresponds to the amount of incident light are two-dimensionally arranged in a matrix. In other words, the pixels P are arranged along the X direction (first direction) and Y direction (second direction) in Fig. 1. The "unit pixels" referred to here are imaging pixels for obtaining imaging signals. A specific circuit configuration of the pixels P (imaging pixels) will be described later.

[0018] In the pixel array section 12, pixel drive lines 17 are wired in the row direction (the direction in which the pixels in the pixel row are arranged) for each pixel row in the matrix-like pixel arrangement, and vertical signal lines 18 are wired in the column direction (the direction in which the pixels in the pixel column are arranged) for each pixel column. The pixel drive lines 17 transmit drive signals for driving the pixels, which are output row by row from the vertical drive circuit 13. In FIG. 1, the pixel drive line 17 is shown as a single wire, but the number of lines is not limited to one. One end of the pixel drive line 17 is connected to an output terminal of the vertical drive circuit 13 corresponding to each row.

[0019] The vertical drive circuit 13 is composed of a shift register, an address decoder, etc., and drives each pixel of the pixel array section 12, for example, row by row. Although the specific configuration of the vertical drive circuit 13 is not shown here, it is generally configured to have two scanning systems, a read scanning system and a sweep scanning system.

[0020] The readout scanning system sequentially selects and scans the unit pixels of the pixel array section 12 row by row to read out signals from the unit pixels. The signals read out from the unit pixels are analog signals. The sweep scanning system performs sweep scanning on the readout row to be read out by the readout scanning system, prior to the readout scanning by the shutter speed.

[0021] The sweep-out scanning by this sweep-out scanning system sweeps out unnecessary charges from the photoelectric conversion units of the unit pixels of the readout row, thereby resetting the photoelectric conversion units. Then, the sweep-out (resetting) of unnecessary charges by this sweep-out scanning system performs a so-called electronic shutter operation. Here, the electronic shutter operation refers to the operation of discarding the signal charge of the photoelectric conversion unit and starting a new exposure (starting the accumulation of signal charge).

[0022] The signal read by the read operation by the read scanning system corresponds to the amount of light that has entered since the immediately preceding read operation or electronic shutter operation. The period from the read timing of the immediately preceding read operation or the sweep timing of the electronic shutter operation to the read timing of the current read operation is the accumulation period (exposure period) of the signal charge in the unit pixel.

[0023] The signals output from each unit pixel in the pixel row selected and scanned by the vertical drive circuit 13 are supplied to a signal processing circuit 14 through each vertical signal line 18. The signal processing circuit 14 performs predetermined signal processing on the signals output from each pixel in the selected row through the vertical signal line 18 for each pixel column in the pixel array section 12, and temporarily holds the pixel signals after signal processing.

[0024] Specifically, the signal processing circuit 14 receives a signal from a unit pixel and performs signal processing on the signal, such as noise removal using CDS (Correlated Double Sampling), signal amplification, AD (Analog-Digital) conversion, etc. The noise removal process removes fixed pattern noise specific to a pixel, such as reset noise and threshold variation of an amplification transistor. Note that the signal processing illustrated here is merely an example, and the signal processing is not limited to these. Here, the signal processing circuit 14 corresponds to a specific example of a drive circuit of the present disclosure.

[0025] The horizontal drive circuit 15 is composed of a shift register, an address decoder, etc., and performs scanning to sequentially select unit circuits corresponding to pixel columns of the signal processing circuit 14. By the selective scanning by the horizontal drive circuit 15, pixel signals processed in each unit circuit of the signal processing circuit 14 are output to the horizontal bus B in sequence and transmitted to the outside of the semiconductor substrate 11 through the horizontal bus B.

[0026] The system control circuit 16 receives a clock and data instructing an operation mode provided from outside the semiconductor substrate 11, and also outputs data such as internal information of the image sensor 10. Furthermore, the system control circuit 16 has a timing generator that generates various timing signals, and performs drive control of peripheral circuitry such as the vertical drive circuit 13, the signal processing circuit 14, and the horizontal drive circuit 15 based on the various timing signals generated by the timing generator.

[0027] (Circuit configuration of pixel P) FIG. 2 is a circuit diagram showing an example of a readout circuit 20 that outputs a pixel signal based on the charge output from each pixel P. As shown in FIG.

[0028] Each pixel P has, as a photoelectric conversion unit, for example, a photodiode 21. For example, a transfer transistor 22, a reset transistor 23, an amplification transistor 24, and a selection transistor 25 are connected to the photodiode 21 provided for each pixel P. Here, the amplification transistor 24 is a specific example of an output transistor of the present disclosure.

[0029] For the pixels P, three drive wirings, for example a transfer line 17a, a reset line 17b, and a selection line 17c, are provided as pixel drive lines 17 commonly for each pixel P in the same pixel row. One end of each of the transfer line 17a, the reset line 17b, and the selection line 17c is connected to an output terminal of the vertical drive circuit 13 corresponding to each pixel row on a pixel row basis, and transmits a transfer pulse φTRF, a reset pulse φRST, and a selection pulse φSEL, which are drive signals for driving the pixels P.

[0030] The photodiode 21 has an anode electrode connected to a negative power supply (e.g., ground), photoelectrically converts received light (incident light) into a signal charge with an amount of charge corresponding to the amount of light, and accumulates the signal charge. The cathode electrode of the photodiode 21 is electrically connected to the gate electrode of the amplification transistor 24 via the transfer transistor 22. The node electrically connected to the gate electrode of the amplification transistor 24 is called an FD (floating diffusion) section 26 (charge accumulation section).

[0031] The transfer transistor 22 is connected between the cathode electrode of the photodiode 21 and the FD section 26. A transfer pulse φTRF with a high level (for example, Vdd level) active (hereinafter referred to as High active) is applied to the gate electrode of the transfer transistor 22 via the transfer line 17a. This causes the transfer transistor 22 to become conductive, and the signal charge photoelectrically converted by the photodiode 21 is transferred to the FD section 26.

[0032] The drain electrode of the reset transistor 23 is connected to the pixel power supply Vdd, and the source electrode is connected to the FD section 26. A high active reset pulse φRST is applied to the gate electrode of the reset transistor 23 via the reset line 17b. This causes the reset transistor 23 to be in a conductive state, and the charge of the FD section 26 is discharged to the pixel power supply Vdd, thereby resetting the FD section 26.

[0033] The amplification transistor 24 has a gate electrode connected to the FD section 26 and a drain electrode connected to a pixel power supply Vdd. The amplification transistor 24 outputs the potential of the FD section 26 after it has been reset by the reset transistor 23 as a reset signal (reset level) Vrst. Furthermore, the amplification transistor 24 outputs the potential of the FD section 26 after the signal charge has been transferred by the transfer transistor 22 as a light accumulation signal (signal level) Vsig.

[0034] For example, the drain electrode of the selection transistor 25 is connected to the source electrode of the amplification transistor 24, and the source electrode is connected to the vertical signal line 18. A high active selection pulse φSEL is applied to the gate electrode of the selection transistor 25 via the selection line 17c. This causes the selection transistor 25 to be in a conductive state, and a signal supplied from the amplification transistor 24 with the unit pixel P in a selected state is output to the vertical signal line 18.

[0035] The vertical signal line 18 is connected to a constant current source transistor (not shown) biased by a constant voltage. Therefore, the amplifying transistor 24, the selection transistor 25 and the vertical signal line 18 configure a so-called source follower circuit.

[0036] In the example of Figure 2, the selection transistor 25 is configured to be connected between the source electrode of the amplification transistor 24 and the vertical signal line 18, but it is also possible to adopt a circuit configuration in which the selection transistor 25 is connected between the pixel power supply Vdd and the drain electrode of the amplification transistor 24.

[0037] The circuit configuration of each pixel P is not limited to the pixel configuration consisting of the four transistors described above. For example, it may be a pixel configuration consisting of three transistors that serve both as the amplification transistor 24 and the selection transistor 25, and the configuration of the pixel circuit is not limited.

[0038] (Specific Configuration of Pixel P) Hereinafter, a specific configuration of pixel P will be described with reference to Fig. 3, Fig. 4A, and Fig. 4B. Fig. 3 is a schematic representation of the planar configuration of pixel P, Fig. 4A is a schematic representation of the cross-sectional configuration along line A-A' shown in Fig. 3, and Fig. 4B is a schematic representation of the cross-sectional configuration along line B-B' shown in Fig. 3.

[0039] The imaging element 10 is, for example, a back-illuminated imaging element. A photodiode 21 having, for example, a substantially rectangular planar shape is provided across a wide area of ​​each pixel P. In the vicinity of an end of each pixel P, for example, a reset transistor 23, an amplification transistor 24, and a selection transistor 25 are arranged in this order. An FD section 26 and a transfer transistor 22 are provided between the reset transistor 23 and the photodiode 21 (FIG. 3). The amplification transistor 24 is provided on one surface (surface S11B described below) of the semiconductor substrate 11, and has a gate electrode 24G, a gate insulating film 24I, a channel region 24C, and a pair of source-drain regions 24A, 24B.

[0040] The semiconductor substrate 11 has a surface S11A on the light incident side and a surface S11B opposite to the surface S11A. The semiconductor substrate 11 is made of, for example, silicon (Si). The semiconductor substrate 11 is provided with a photodiode 21 for each pixel P. The photodiode 21 is, for example, a photodiode having a pn junction, and has a p-type impurity region 21a and an n-type impurity region 21b formed in the p-type well region 111. For example, the p-type impurity region 21a and the n-type impurity region 21b are provided in this order along the thickness direction from the surface S11B side of the semiconductor substrate 11. For example, the size of the p-type impurity region 21a in the depth direction (Z direction in FIG. 4B) is about 30 nm to 200 nm, and the size of the n-type impurity region 21b in the depth direction is about 1 μm to 5 μm. For example, the impurity concentration of the p-type impurity region 21a is about 1×10 18 cm -3 ~1×10 19 cm -3 The impurity concentration of the n-type impurity region 21b is about 1×10 15 cm -3 x1x10 18 cm -3 The impurity concentration of the p-type well region 111 is, for example, about 1×10 16 cm -3 ~1×10 18 cm -3 That's about it.

[0041] A channel region 24C and a pair of source / drain regions 24A, 24B of the amplifier transistor 24 are provided near the surface S11B in the semiconductor substrate 11. The pair of source / drain regions 24A, 24B are, for example, n-type (first conductivity type) impurity diffusion regions formed in the p-type well region 111 and are provided adjacent to the channel region 24C. The source / drain region 24A, the channel region 24C, and the source / drain region 24B are provided in this order along the channel length direction (Y direction in FIG. 4A) of the amplifier transistor 24. The impurity concentration of the source / drain regions 24A, 24B is, for example, 1×10 19 cm -3 x1x10 21 cm -3 In this embodiment, the channel region 24C of the amplifying transistor 24 is formed by an n-type impurity diffusion region of the same conductivity type as the source-drain regions 24A, 24B. In other words, the amplifying transistor 24 has a junctionless structure. As will be described in detail later, this makes it difficult for carriers flowing through the channel region 24C to be trapped at the interface with the gate insulating film 24I, thereby making it possible to suppress the generation of noise in the amplifying transistor 24.

[0042] The channel region 24C disposed between the pair of source / drain regions 24A and 24B is an n-type impurity diffusion region formed in the p-type well region 111. The impurity concentration of the channel region 24C is 5×10 17 cm -3 x1x10 19 cm -3 The channel region 24C is surrounded by the gate electrode 24G. The size of the channel region 24C in the channel length direction is, for example, about 200 nm to 3000 nm. The size of the channel region 24C in the channel width direction (X direction in FIG. 4B) is, for example, about 20 nm to 200 nm. The size of the channel region 24C in the depth direction (size D) is, for example, larger than the size of the pair of source-drain regions 24A, 24B in the depth direction and is, for example, about 50 nm to 500 nm.

[0043] The gate electrode 24G surrounding the channel region 24C has a pair of opposing side surfaces 241, 242 and an upper surface 243 connecting the pair of side surfaces 241, 242, and the pair of side surfaces 241, 242 and the upper surface 243 each face the channel region 24C. In other words, the pair of side surfaces 241, 242 and the upper surface 243 form a concave shape surrounding the channel region 24C.

[0044] The pair of side surfaces 241, 242 are planes (YZ plane in FIG. 4B) substantially perpendicular to the surface S11B of the semiconductor substrate 11, and face each other in the channel width direction. A channel region 24C is provided between the pair of side surfaces 241, 242. A part or the whole of the pair of side surfaces 241, 242 is embedded in the semiconductor substrate 11. The size in the depth direction of the portion of the pair of side surfaces 241, 242 embedded in the semiconductor substrate 11 is, for example, about 100 nm to 500 nm.

[0045] 5 shows another example of the pair of side surfaces 241, 242. A part of the channel region 24C may be exposed from the pair of side surfaces 241, 242. It is preferable that half or more of the size of the channel region 24C in the depth direction is covered by the pair of side surfaces 241, 242.

[0046] The upper surface 243 is a plane (the XY plane in FIG. 3B) substantially parallel to the surface S11B of the semiconductor substrate 11, and is provided outside the semiconductor substrate 11. That is, the upper surface 243 is provided facing the semiconductor substrate 11. The upper surface 243 contacts one end of each of the pair of side surfaces 241, 242.

[0047] The gate electrode 24G including the pair of side surfaces 241, 242 and the top surface 243 is made of, for example, p-type (second conductivity type) polysilicon (Poly-Si) etc. The gate electrode 24G may be made of a metal such as tungsten (W), titanium (Ti), titanium nitride (TiN), hafnium (Hf), hafnium silicide (HfSi), ruthenium (Ru), iridium (Ir), cobalt (Co) or the like.

[0048] A gate insulating film 24I is provided between each of the pair of side surfaces 241, 242 and the upper surface 243 and the channel region 24C. The gate insulating film 24I is made of an insulating film such as silicon oxide (SiO). The thickness of the gate insulating film 24I is, for example, about 3 nm to 15 nm.

[0049] An element isolation region (STI: Shallow Trench Isolation) 112 is provided around the side surfaces 241 and 242 embedded in the semiconductor substrate 11. The element isolation region 112 is made of an insulating material such as silicon oxide. In the semiconductor substrate 11, the element isolation region 112 is provided between the side surface 242 and the photodiode 21.

[0050] (Operation of the image sensor 10) In the image sensor 10, when light (e.g., light with a wavelength in the visible region) is incident on the photodiode 21 from the surface S11A of the semiconductor substrate 11, pairs of holes and electrons are generated (photoelectrically converted) in the photodiode 21. When the transfer transistor 22 is turned on, the signal charge accumulated in the photodiode 21 is transferred to the FD section 26. In the FD section 26, the signal charge is converted into a voltage signal, and this voltage signal is output to the vertical signal line 18 via the amplification transistor 24 and the selection transistor 25.

[0051] (Actions and Effects of the Imaging Device 10) In the image sensor 10 of the present embodiment, the amplifying transistor 24 is a so-called junctionless transistor, and has a channel region 24C of the same conductivity type (n type) as the conductivity type of the source / drain regions 24A, 24B. As a result, the current path of the channel region 24C is formed away from the interface with the gate insulating film 24I, so that carriers flowing through the channel region 24C are less likely to be captured at the interface with the gate insulating film 24I. Hereinafter, this effect will be described using a comparative example.

[0052] 6A and 6B show a schematic cross-sectional configuration of an amplifier transistor (amplifier transistor 124) according to a comparative example. FIG. 6A corresponds to the cross-sectional configuration along the line A-A' in FIG. 3, and FIG. 6B corresponds to the cross-sectional configuration along the line B-B' in FIG. 3. The gate electrode (gate electrode 124G) of this amplifier transistor 124 is composed of only one plane provided outside the semiconductor substrate 11. This gate electrode 124G is not embedded in the semiconductor substrate 11. The channel region 124C facing the gate electrode 124G is composed of, for example, an impurity diffusion region of a conductivity type (p type) opposite to the conductivity type (n type) of the pair of source-drain regions 24A and 24B. The channel region 124C may be a thin n type, but it is difficult to increase the size (size D100) of the channel region 124C in the depth direction (Z direction in FIG. 6A). This is because the gate electrode 124G provided only outside the semiconductor substrate 11 controls the on / off of the amplifier transistor 124. The size D100 of the channel region 124C in the depth direction is, for example, about 50 nm, which is smaller than the size of the source / drain regions 24A and 24B in the depth direction.

[0053] In such an amplifier transistor 124, the current path of the channel region 124C is formed near the interface with the gate insulating film 24I. Therefore, if a trap level exists in the gate insulating film 24I, carriers flowing through the channel region 124C are captured by the trap level or released from the trap level, causing fluctuations in the current flowing through the channel region 124C. Noise is generated due to the current fluctuations.

[0054] One possible method for suppressing noise is to increase the area occupied by the amplifier transistor, but this method reduces the area occupied by the photodiode provided on the same semiconductor substrate as the amplifier transistor, which affects the sensitivity and the saturated accumulation amount of signal charge, etc.

[0055] In contrast, in the image sensor 10, the channel region 24C is formed from an n-type impurity diffusion region with a high impurity concentration, so that a depletion layer is formed near the interface of the channel region 24C with the gate insulating film 24I, and a current path for the channel region 24C is formed at a position away from the gate insulating film 24I.

[0056] 7 is a schematic diagram showing a current (current C) flowing through the amplifying transistor 24 in an on-state. Thus, in the amplifying transistor 24, most of the current C flows through the center in the depth direction of the channel region 24C. In addition, since the pair of side surfaces 241, 242 of the gate electrode 24G are embedded in the semiconductor substrate 11, the size D (FIG. 4A) in the depth direction of the channel region 24C can be increased.

[0057] For this reason, even if a trap level exists in the gate insulating film 24I, carriers flowing through the channel region 24C of the amplifying transistor 24 are less likely to be captured by this trap level, thereby suppressing the generation of noise caused by fluctuations in the current flowing through the channel region 24C.

[0058] Moreover, since noise is suppressed without increasing the area occupied by the amplifying transistor 24, it is possible to maintain the area occupied by the photodiode 21. Therefore, the influence on the sensitivity and the saturated accumulation amount of the signal charge, etc., is also suppressed.

[0059] As described above, in the image sensor 10 of the present embodiment, the amplifying transistor 24 has the channel region 24C of the same conductivity type (n-type) as that of the source / drain regions 24A and 24B, so that it is possible to reduce noise caused by carriers captured at the interface of the channel region 24C on the gate electrode 24G side. Therefore, it is possible to suppress noise.

[0060] Furthermore, in the imaging element 10, the pair of side surfaces 241, 242 of the gate electrode 24G are embedded in the semiconductor substrate 11, so that it is easy to increase the size D of the channel region 24C in the depth direction. This makes it possible to more effectively suppress the generation of noise.

[0061] The image sensor 10 can suppress noise and achieve a high signal-to-noise ratio, thereby making it possible to obtain clear images even when shooting at night.

[0062] Below, modifications of the first embodiment and other embodiments will be described. In the following description, the same components as those in the first embodiment will be given the same reference numerals and descriptions thereof will be omitted as appropriate.

[0063] <Variation 1> Fig. 8 shows a schematic cross-sectional configuration of a main part of an image sensor 10 (Fig. 1) according to Modification 1 of the first embodiment. Fig. 8 corresponds to the cross-sectional configuration taken along line B-B' in Fig. 3. This image sensor 10 has an amplifying transistor 24 having a Fin FET structure. Except for this, the image sensor 10 according to Modification 1 has the same configuration as the image sensor 10 of the first embodiment, and also has the same actions and effects.

[0064] The amplifying transistor 24 having this Fin FET structure has a fin F in which a channel region 24C is provided, a gate electrode 24G provided around the fin F, and a gate insulating film 24I provided between the gate electrode 24G and the fin F.

[0065] The fin F is made of, for example, silicon (Si) in which n-type impurities are diffused. The fin F is provided on the surface S11B of the semiconductor substrate 11, approximately perpendicular to the surface S11B. That is, the amplifying transistor 24 having a FinFET structure has an n-type channel region 24C outside the semiconductor substrate 11 on which the photodiode 21 is provided. This makes it possible to increase the occupation area of ​​the amplifying transistor 24 while suppressing the effect on the occupation area of ​​the photodiode 21. The impurity concentration of the channel region 24C is, for example, 5×10 17 cm -3 ~1×10 19 cm -3The fin F extends in the channel length direction (Y direction in FIG. 8). The fin F is provided with source / drain regions 24A, 24B (FIG. 4A) adjacent to the channel region 24C. The source / drain regions 24A, 24B have the same conductivity type (n-type) as the channel region 24C.

[0066] The gate electrode 24G is provided on the surface S11B of the semiconductor substrate 11 together with the fin F. The gate electrode 24G includes a pair of side surfaces 241, 242 that face each other with the fin F therebetween, and an upper surface 243 that connects the pair of side surfaces 241, 242. The upper surface 243 faces the surface S11B of the semiconductor substrate 11 with the fin F therebetween. The gate electrode 24G is made of, for example, p-type polysilicon or the like. A gate insulating film 24I is provided between the fin F and each of the pair of side surfaces 241, 242 and the upper surface 234. The gate insulating film 24I is made of, for example, silicon oxide (SiO) or the like.

[0067] In the image sensor 10 according to this modification, similarly to the first embodiment, the amplifying transistor 24 has a channel region 24C of the same conductivity type (n-type) as that of the source-drain regions 24A, 24B, so that noise caused by carriers captured at the interface of the channel region 24C on the gate electrode 24G side can be reduced. In addition, the channel region 24C (fin F) is provided outside the semiconductor substrate 11 on which the photodiode 21 is provided, so that the area occupied by the amplifying transistor 24 can be increased. Therefore, noise can be more effectively suppressed.

[0068] <Variation 2> Fig. 9 shows a schematic cross-sectional configuration of a main part of an image sensor 10 (Fig. 1) according to Modification 2 of the first embodiment. Fig. 9 corresponds to the cross-sectional configuration taken along line B-B' in Fig. 3. This image sensor 10 has an amplifying transistor 24 having a GAA structure. Except for this, the image sensor 10 according to Modification 2 has the same configuration as the image sensor 10 of the first embodiment, and also has the same actions and effects.

[0069] The amplifying transistor 24 having this GAA structure has a semiconductor portion 24N in which a channel region 24C is provided, a gate electrode 24G surrounding this semiconductor portion 24N, and a gate insulating film 24I provided between the gate electrode 24G and the semiconductor portion 24N.

[0070] The semiconductor portion 24N is made of, for example, silicon (Si) in which n-type impurities are diffused. The semiconductor portion 24N may be made of, for example, nanowires. The semiconductor portion 24N is provided on the surface S11B of the semiconductor substrate 11, and extends in the channel length direction (Y direction in FIG. 9). An n-type channel region 24C is provided in a region surrounded by the gate electrode 24G of this semiconductor portion 24N, and n-type source-drain regions 24A, 24B (FIG. 4A) are provided in regions adjacent to the channel region 24C.

[0071] The gate electrode 24G is provided on the surface S11B of the semiconductor substrate 11 together with the semiconductor portion 24N. The gate electrode 24G includes a pair of side surfaces 241, 242 provided substantially perpendicular to the semiconductor substrate 11 (surface S11B), and an upper surface 243 and a lower surface 244 provided substantially parallel to the semiconductor substrate 11 (surface S11B). The pair of side surfaces 241, 242 face each other with the semiconductor portion 24N therebetween. The upper surface 243 and the lower surface 244 connect the pair of side surfaces 241, 242 and face each other with the nanowires therebetween. Of the upper surface 243 and the lower surface 244, the lower surface 244 is provided at a position closer to the semiconductor substrate 11. The gate electrode 24G is made of, for example, p-type polysilicon or the like.

[0072] In the image sensor 10 according to this modification, similarly to the first embodiment, the amplifying transistor 24 has a channel region 24C of the same conductivity type (n-type) as that of the source-drain regions 24A, 24B, so that noise caused by carriers captured at the interface of the channel region 24C on the gate electrode 24G side can be reduced. In addition, since the channel region 24C (semiconductor portion 24N) is provided outside the semiconductor substrate 11 on which the photodiode 21 is provided, it is possible to increase the area occupied by the amplifying transistor 24. Therefore, noise can be suppressed more effectively.

[0073] <Variation 3> 10 shows an example of the configuration of an equivalent circuit of an image sensor 10 (FIG. 1) according to Modification 3 of the first embodiment. In this image sensor 10, an amplifier transistor 24 and the like are shared by a plurality of pixels P. Except for this point, the image sensor 10 according to Modification 3 has the same configuration as the image sensor 10 of the first embodiment, and also has the same actions and effects.

[0074] In this imaging element 10, for example, four pixels P share the FD section 26, the reset transistor 23, the amplifying transistor 24, and the selection transistor 25.

[0075] Fig. 11 shows a schematic planar configuration of four pixels P and the FD section 26, the reset transistor 23, the amplification transistor 24, and the selection transistor 25 shared by the four pixels P. The configuration of the image sensor 10 of this modified example will be described using Fig. 11 together with Fig. 10.

[0076] Each of the four pixels P is provided with a photodiode (one of photodiodes 21-1, 21-2, 21-3, and 21-4). The photodiode 21-1 is connected to a transfer transistor 22-1, the photodiode 21-2 is connected to a transfer transistor 22-2, and the photodiode 21-3 is connected to a transfer transistor 22-4. That is, one pixel P is provided with one photodiode (one of photodiodes 21-1, 21-2, 21-3, and 21-4) and one transfer transistor (one of transfer transistors 22-1, 22-2, 22-3, and 22-4). Transfer pulses φTRF1, φTRF2, φTRF3, and φTRF4 are applied to the gate electrodes of the transfer transistors 22-1, 22-2, 22-3, and 22-4 via transfer lines 17a-1, 17a-2, 17a-3, and 17a-4 (FIG. 10).

[0077] The FD section 26 is provided in the center of the four pixels P (FIG. 11). The signal charges photoelectrically converted by the photodiodes 21-1, 21-2, 21-3, and 21-4 are transferred to the FD section 26 via the transfer transistors 22-1, 22-2, 22-3, and 22-4.

[0078] The reset transistor 23, the amplification transistor 24, and the selection transistor 25 are arranged, for example, side by side at the ends of the four shared pixels P (for example, the ends in the X direction in FIG. 11). The configuration of the amplification transistor 24 is, for example, similar to that described in the first embodiment (see FIGS. 4A and 4B). Alternatively, the configuration of the amplification transistor 24 may be similar to that described in the above modification 1 (FIG. 8) or modification 2 (FIG. 9).

[0079] As described in the first embodiment above, in the imaging element 10 of this modified example, the amplifying transistor 24 has a channel region 24C of the same conductivity type (N type) as the conductivity type of the source / drain regions 24A, 24B, so that it is possible to reduce noise caused by carriers captured at the interface of the channel region 24C on the gate electrode 24G side.

[0080] <Second embodiment> 12 shows a schematic configuration of a solid-state imaging element (imaging element 10A) according to a second embodiment of the present disclosure. The imaging element 10A has a laminated structure including a first substrate 11A on which a photodiode 21 and the like are provided, a second substrate 30 on which a readout circuit 20 (specifically, an amplifying transistor 24 and a selecting transistor 25) is provided, and a third substrate 40 on which a logic circuit (a driving circuit) is provided. Except for this point, the imaging element 10A according to the second embodiment has the same configuration as the imaging element 10 of the first embodiment, and also has the same functions and effects. Here, the amplifying transistor 24 and the selecting transistor 25 are a specific example of the output transistor of the present disclosure.

[0081] In the imaging element 10A, a first substrate 11A, a second substrate 30, and a third substrate 40 are laminated in this order. Light is incident on the imaging element 10A from the first substrate 11A side. That is, the imaging element 10A is a back-illuminated imaging element.

[0082] The first substrate 11A has a plurality of pixels P that perform photoelectric conversion in the semiconductor substrate 11. The second substrate 30 has a readout circuit 20 in the semiconductor layer 30S, for example, one for every four pixels P. The second substrate 30 has pixel drive lines 17 and vertical signal lines 18. The third substrate 40 has a logic circuit LC that processes pixel signals in the semiconductor layer 40S. The logic circuit LC has, for example, a vertical drive circuit 13, a signal processing circuit 14, a horizontal drive circuit 15, and a system control circuit 16. The logic circuit LC (specifically, the horizontal drive circuit 15) outputs an output voltage Vout for each pixel P to the outside. In the logic circuit LC, for example, a low-resistance region made of silicide formed by using a salicide (Self Aligned Silicide) process such as CoSi2 or NiSi may be formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode.

[0083] Fig. 13 shows an example of a pixel P and a readout circuit 20. Below, a case will be described in which four pixels P share one readout circuit 20 as shown in Fig. 13. Here, "shared" refers to the outputs of the four pixels P being input to a common readout circuit 20.

[0084] Each pixel P has components in common with the others. In Fig. 13, in order to distinguish the components of each pixel P from one another, identification numbers (1, 2, 3, 4) are added to the end of the reference numerals of the components of each pixel P. In the following, when it is necessary to distinguish the components of each pixel P from one another, an identification number is added to the end of the reference numerals of the components of each pixel P, but when it is not necessary to distinguish the components of each pixel P from one another, the identification number at the end of the reference numerals of the components of each pixel P is omitted.

[0085] Each pixel P has, for example, a photodiode 21, a transfer transistor 22 electrically connected to the photodiode 21, and an FD section 26 that temporarily holds the charge output from the photodiode 21 via the transfer transistor 22. The photodiode 21 performs photoelectric conversion to generate a charge according to the amount of received light. The cathode of the photodiode 21 is electrically connected to the source of the transfer transistor 22, and the anode of the photodiode 21 is electrically connected to a reference potential line (for example, ground). The drain of the transfer transistor 22 is electrically connected to the FD section 26, and the gate of the transfer transistor 22 is electrically connected to the pixel drive line 17. The transfer transistor 22 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) transistor.

[0086] The FD sections 26 of the pixels P sharing one readout circuit 20 are electrically connected to each other and to an input terminal of the common readout circuit 20. The readout circuit 20 has, for example, a reset transistor 23, a selection transistor 25, and an amplification transistor 24. The selection transistor 25 may be omitted as necessary. The source of the reset transistor 23 (the input terminal of the readout circuit 20) is electrically connected to the FD section 26, and the drain of the reset transistor 23 is electrically connected to a power supply line VDD and the drain of the amplification transistor 24. The gate of the reset transistor 23 is electrically connected to the pixel drive line 17 (see FIG. 12). The source of the amplification transistor 24 is electrically connected to the drain of the selection transistor 25, and the gate of the amplification transistor 24 is electrically connected to the source of the reset transistor 23. The source of the selection transistor 25 (the output terminal of the readout circuit 20) is electrically connected to the vertical signal line 18, and the gate of the selection transistor 25 is electrically connected to the pixel drive line 17 (see FIG. 12).

[0087] When the transfer transistor 22 is turned on, the transfer transistor 22 transfers the charge of the photodiode 21 to the FD section 26. The reset transistor 23 resets the potential of the FD section 26 to a predetermined potential. When the reset transistor 23 is turned on, the potential of the FD section 26 is reset to the potential of the power supply line VDD. The selection transistor 25 controls the output timing of the pixel signal from the readout circuit 20. The amplification transistor 24 generates a signal having a voltage corresponding to the level of the charge held in the FD section 26 as the pixel signal. The amplification transistor 24 constitutes a source follower type amplifier and outputs a pixel signal having a voltage corresponding to the level of the charge generated in the photodiode 21. When the selection transistor 25 is turned on, the amplification transistor 24 amplifies the potential of the FD section 26 and outputs a voltage corresponding to the potential to the signal processing circuit 14 via the vertical signal line 18. The reset transistor 23, the amplification transistor 24, and the selection transistor 25 are, for example, CMOS transistors.

[0088] As shown in FIG. 14, the selection transistor 25 may be provided between the power supply line VDD and the amplification transistor 24. In this case, the drain of the reset transistor 23 is electrically connected to the power supply line VDD and the drain of the selection transistor 25. The source of the selection transistor 25 is electrically connected to the drain of the amplification transistor 24, and the gate of the selection transistor 25 is electrically connected to the pixel drive line 17 (see FIG. 1). The source of the amplification transistor 24 (the output terminal of the readout circuit 20) is electrically connected to the vertical signal line 18, and the gate of the amplification transistor 24 is electrically connected to the source of the reset transistor 23. Also, as shown in FIG. 15 and FIG. 16, the FD transfer transistor 27 may be provided between the source of the reset transistor 23 and the gate of the amplification transistor 24.

[0089] The FD transfer transistor 27 is used when switching the conversion efficiency. In general, the pixel signal is small when shooting in a dark place. Based on Q=CV, when performing charge-voltage conversion, if the capacitance (FD capacitance C) of the FD section 26 is large, V when converted to a voltage by the amplification transistor 24 becomes small. On the other hand, in a bright place, the pixel signal becomes large, so if the FD capacitance C is not large, the FD section 26 cannot receive the charge of the photodiode 21. Furthermore, the FD capacitance C needs to be large so that V when converted to a voltage by the amplification transistor 24 does not become too large (in other words, so that it becomes small). In consideration of this, when the FD transfer transistor 27 is turned on, the gate capacitance of the FD transfer transistor 27 increases, so that the entire FD capacitance C becomes large. On the other hand, when the FD transfer transistor 27 is turned off, the entire FD capacitance C becomes small. In this way, by switching the FD transfer transistor 27 on and off, the FD capacitance C can be made variable and the conversion efficiency can be switched.

[0090] FIG. 17 shows an example of a connection between a plurality of readout circuits 20 and a plurality of vertical signal lines 18. When a plurality of readout circuits 20 are arranged side by side in the extension direction of the vertical signal lines 18 (for example, the column direction), a plurality of vertical signal lines 18 may be assigned to each readout circuit 20. For example, as shown in FIG. 17, when four readout circuits 20 are arranged side by side in the extension direction of the vertical signal lines 18 (for example, the column direction), a plurality of vertical signal lines 18 may be assigned to each readout circuit 20. In FIG. 17, in order to distinguish each vertical signal line 18, an identification number (1, 2, 3, 4) is added to the end of the reference numeral of each vertical signal line 18.

[0091] 18 shows an example of a vertical cross-sectional configuration of the imaging element 10A. The first substrate 11A has a semiconductor substrate 11 and an interlayer insulating film 19 on the semiconductor substrate 11. The second substrate 30 is provided opposite to the first substrate 11A, and has a semiconductor layer 30S, an interlayer insulating film 30I, and a multilayer wiring layer 30W, in this order, from the first substrate 11A (interlayer insulating film 19) side. The third substrate 40 has a multilayer wiring layer 40W, an interlayer insulating film 40I, and a semiconductor layer 40S, in this order, from the second substrate 30 (multilayer wiring layer 30W) side. A bonding surface S is provided between the multilayer wiring layer 30W of the second substrate 30 and the multilayer wiring layer 40W of the third substrate 40.

[0092] The semiconductor substrate 11 is provided with, for example, a photodiode 21 and an FD section 26. The FD section 26 is provided in the semiconductor substrate 11 near the surface S11B. The FD section 26 is formed of, for example, an impurity diffusion region in which an n-type impurity is diffused in the p-type well region 111. The concentration of the n-type impurity in the FD section 26 is, for example, 1×10 19 cm -3 ~1×10 20 cm -3 The surface S11A of the semiconductor substrate 11 serves as a light incident surface.

[0093] A transfer transistor 22 is provided together with the FD portion 26 in the vicinity of the surface S11B of the semiconductor substrate 11. The transfer transistor 22 includes, for example, a gate electrode 22G and a gate insulating film 22I. The gate electrode 22G is provided on the outside of the semiconductor substrate 11 so as to face the semiconductor substrate 11. The gate electrode 22G is made of, for example, p-type polysilicon or the like. The gate electrode 22G may be made of a metal such as tungsten (W), titanium (Ti), titanium nitride (TiN), hafnium (Hf), hafnium silicide (HfSi), ruthenium (Ru), iridium (Ir), cobalt (Co), or the like. The gate insulating film 22I is provided between the gate electrode 22G and the semiconductor substrate 11. The gate insulating film 22I is made of, for example, a silicon oxide film (SiO) or the like. The gate insulating film 22I may be made of a high dielectric insulating material such as hafnium oxide (HfO2), hafnium silicate (HfSiO), tantalum oxide (Ta2O5), hafnium aluminate (HfAlO), etc. The gate electrode 22G and the gate insulating film 22I are covered with an interlayer insulating film 19. The interlayer insulating film 19 is made of, for example, silicon oxide (SiO) or the like.

[0094] The first substrate 11A may further have, for example, a fixed charge film in contact with the surface S11A of the semiconductor substrate 11. The fixed charge film is negatively charged in order to suppress the generation of dark current due to the interface state on the light-receiving surface side of the semiconductor substrate 11. The fixed charge film is formed, for example, by an insulating film having a negative fixed charge. Examples of materials for such insulating films include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide. A hole accumulation layer is formed at the interface on the light-receiving surface side of the semiconductor substrate 11 by an electric field induced by the fixed charge film. This hole accumulation layer suppresses the generation of electrons from the interface. The imaging element 10A has, for example, a color filter (for example, the color filter 55 in FIG. 30) and a light-receiving lens (for example, the light-receiving lens 60 in FIG. 30) on the light-incident side of the first substrate 11A. The color filter is provided on the surface S11A side of the semiconductor substrate 11. The color filter is provided, for example, in contact with the fixed charge film, and is provided at a position facing the pixel P via the fixed charge film. The light receiving lens is provided, for example, in contact with the color filter, and is provided at a position facing the pixel P via the color filter and the fixed charge film.

[0095] The semiconductor layer 30S of the second substrate 30 faces the semiconductor substrate 11 with the interlayer insulating film 19 therebetween. The semiconductor layer 30S is made of, for example, a silicon (Si) layer having a thickness (size in the Z direction in FIG. 12) of 20 nm to 200 nm. In this semiconductor layer 30S, for example, channel regions 24C, 25C and source / drain regions 24A, 24B, 25A, 25B of the amplification transistor 24 and the selection transistor 25 are provided.

[0096] A pair of source / drain regions 24A, 24B of the amplifier transistor 24 are n-type impurity diffusion regions provided in the semiconductor layer 30S, and are provided, for example, from the interlayer insulating film 30I side of the semiconductor layer 30S over a part of the thickness direction (Z direction in FIG. 18). A channel region 24C is provided between the pair of source / drain regions 24A, 24B. As described in the first embodiment, the channel region 24C of the amplifier transistor 24 has the same conductivity type (n-type) as the source / drain regions 24A, 24B. The channel region 24C is provided, for example, over the entire thickness direction of the semiconductor layer 30S.

[0097] The selection transistors 25 are arranged, for example, at adjacent positions in the channel length direction (Y direction in FIG. 18) of the amplification transistor 24. One of the pair of source-drain regions 25A, 25B (source-drain region 25B) of the selection transistor 25 is adjacent to one of the pair of source-drain regions 24A, 24B (source-drain region 24A) of the amplification transistor 24, and may be shared. The pair of source-drain regions 25A, 25B of the selection transistor 25 are n-type impurity diffusion regions provided in the semiconductor layer 30S, and are provided, for example, from the interlayer insulating film 30I side of the semiconductor layer 30S over a part of the thickness direction. A channel region 25C is provided between the pair of source-drain regions 25A, 25B. The channel region 25C of the selection transistor 25 has, for example, the same conductivity type (n-type) as the source-drain regions 25A, 25B. The channel region 24C is provided, for example, over the entire thickness direction of the semiconductor layer 30S.

[0098] In the stacked type imaging element 10A, the channel regions 24C, 25C, etc. of the amplifying transistor 24 and the selecting transistor 25 are provided in a semiconductor layer 30S separate from the semiconductor substrate 11 on which the photodiode 21 and the FD section 26 are provided. This increases the area occupied by the amplifying transistor 24 and the selecting transistor 25, making it possible to more effectively suppress the generation of noise. In addition, since the amplifying transistor 24 and the selecting transistor 25 are manufactured separately from the photodiode 21, etc., it becomes easier to optimize the temperature when manufacturing the amplifying transistor 24 and the selecting transistor 25. Therefore, the generation of noise can be effectively suppressed in terms of the manufacturing process as well.

[0099] At least one of the channel region 24C of the amplification transistor 24 and the channel region 25C of the selection transistor 25 may have the same conductivity type as the source-drain regions 24A, 24B, 25A, and 25B. For example, the channel region 25C of the selection transistor 25 may be a p-type impurity diffusion region.

[0100] The semiconductor layer 30S is provided with an element isolation region 112. This element isolation region 112 is provided around the channel regions 24C, 25C and the pairs of source-drain regions 24A, 24B, 25A, 25B. This electrically isolates a plurality of transistors.

[0101] The amplification transistor 24 has a gate electrode 24G and a gate insulating film 241 in addition to a channel region 24C and a pair of source-drain regions 24A, 24B. The selection transistor 25 has a gate electrode 25G and a gate insulating film 251 in addition to a channel region 25C and source-drain regions 25A, 25B.

[0102] The amplification transistor 24 and the selection transistor 25 are, for example, planar type transistors. The gate electrodes 24G and 25G are provided outside the semiconductor layer 30S and are each composed of a single plane facing the channel regions 24C and 25C. That is, the gate electrodes 24G and 25G have a flat plate shape. For example, when the semiconductor layer 30S is formed using an SOI substrate (SOI substrate 50 in FIG. 15B described later) or the like and the thickness of the semiconductor layer 30S is small, it is easy to form a planar type junctionless transistor. The gate electrodes 24G and 25G are composed of, for example, p-type polysilicon. The gate electrodes 24G and 25G may be composed of a metal such as tungsten (W), titanium (Ti), titanium nitride (TiN), hafnium (Hf), hafnium silicide (HfSi), ruthenium (Ru), iridium (Ir), and cobalt (Co).

[0103] Gate insulating films 24I and 25I are provided between the gate electrodes 24G and 25G and the semiconductor layer 30S, respectively. The gate insulating films 24I and 25I are made of, for example, a silicon oxide film (SiO). The gate insulating films 24I and 25I may be made of a high dielectric insulating material such as hafnium oxide (HfO2), hafnium silicate (HfSiO), tantalum oxide (Ta2O5), and hafnium aluminate (HfAlO).

[0104] The gate electrodes 24G, 25G and the gate insulating films 24I, 25I are covered with an interlayer insulating film 30I. The interlayer insulating film 30I is made of, for example, silicon oxide (SiO) or the like. The interlayer insulating film 30I is provided with a connection hole reaching the gate electrode 24G of the amplifying transistor 24, and a connection hole penetrating the interlayer insulating film 30I, the semiconductor layer 30S, and the interlayer insulating film 19 and reaching the FD section 26. An electrode 24E is provided in the connection hole reaching the gate electrode 24G, and an electrode 26E is provided in the connection hole reaching the FD section 26.

[0105] The multilayer wiring layer 30W faces the semiconductor layer 30S with an interlayer insulating film 30I therebetween. The multilayer wiring layer 30W includes a plurality of wirings 31, an interlayer insulating film 32, and a contact electrode 33. The wiring 31 is made of, for example, a metal material such as copper (Cu) or aluminum (Al). The electrode 24E and the electrode 26E are connected to each other via the wiring 31. That is, the gate electrode 24G of the amplifying transistor 24 is connected to the FD section 26 via the wiring 31. The wiring 31 is electrically connected to, for example, the reset transistor 23 (FIG. 2). The interlayer insulating film 32 is for isolating the plurality of wirings 31 from each other, and is made of, for example, silicon oxide (SiO). The contact electrode 33 is for electrically connecting, for example, the wirings 31 of the multilayer wiring layer 30W to the multilayer wiring layer 40W (specifically, a contact electrode 43 described later). The contact electrode 33 is made of, for example, copper (Cu), and one surface is exposed to the bonding surface S.

[0106] In the semiconductor layer 40S of the third substrate 40, for example, channel regions 40SC and pairs of source-drain regions 40SA, 40SB of a plurality of transistors Tr are provided. The plurality of transistors Tr form, for example, a logic circuit. A signal charge is output from the photodiode 21 to the logic circuit via the amplification transistor 24 and the selection transistor 25. In this manner, in the imaging element 10A, the logic circuit LC is provided on a substrate (third substrate 40) separate from the semiconductor substrate 11 on which the photodiode 21 and the like are provided, and these are stacked. This makes it possible to reduce the chip size.

[0107] Each of the transistors Tr has a gate electrode 40IG and a gate insulating film 40II in addition to a channel region 40SC and a pair of source-drain regions 40SA, 40SB. The gate electrode 40IG of each of the transistors Tr is provided, for example, outside the semiconductor layer 40S and is formed of a single plane facing the channel region 40SC. A gate insulating film 40II is provided between the gate electrode 40IG and the semiconductor layer 40S. The gate electrode 40IG and the gate insulating film 40II are covered with an interlayer insulating film 40I.

[0108] The multi-layer wiring layer 40W of the third substrate 40 faces the semiconductor layer 40S with an inter-layer insulating film 40I therebetween. A bonding surface S is formed between this multi-layer wiring layer 40W and the multi-layer wiring layer 30W of the second substrate 30. The multi-layer wiring layer 40W includes a plurality of wirings 41, an inter-layer insulating film 42, and a contact electrode 43. The wirings 41 are made of a metal material such as copper (Cu) or aluminum (Al). The inter-layer insulating film 42 is for separating the plurality of wirings 41, and is made of, for example, silicon oxide (SiO). The contact electrode 43 is for electrically connecting, for example, the wirings 41 of the multi-layer wiring layer 40W and the contact electrode 33 of the multi-layer wiring layer 30W. The contact electrode 43 is made of, for example, copper (Cu), and one surface is exposed to the bonding surface S and is in contact with the contact electrode 33. That is, the third substrate 40 and the second substrate 30 are connected by CuCu bonding.

[0109] In the image sensor 10A according to the second embodiment, similarly to the first embodiment, the amplifying transistor 24 has a channel region 24C of the same conductivity type (n-type) as that of the source-drain regions 24A and 24B, so that it is possible to reduce noise caused by carriers captured at the interface of the channel region 24C on the gate electrode 24G side. Also, the selection transistor 25 has a channel region 25C of the same conductivity type (n-type) as that of the source-drain regions 25A and 25B, so that it is possible to reduce noise caused by carriers captured at the interface of the channel region 25C on the gate electrode 25G side.

[0110] Furthermore, since the imaging element 10A has a laminated structure of the first substrate 11A, the second substrate 30, and the third substrate 40, the amplification transistor 24 and the selection transistor are formed on a substrate (the second substrate 30) separate from the first substrate 11A on which the photodiode 21 and the FD section 26 are provided. This increases the area occupied by the amplification transistor 24 and the selection transistor 25, making it possible to more effectively suppress noise. Also, in terms of the manufacturing process, the manufacturing temperature of the amplification transistor 24 and the selection transistor 25 can be optimized to suppress the generation of noise.

[0111] In addition, since the third substrate 40 having the logic circuit LC is laminated on the first substrate 11A having the photodiode 21 and the like provided thereon, the chip size can be reduced.

[0112] <Modification 4> 19, 20A, and 20B show a schematic configuration of a main part of an image sensor 10A (FIG. 18) according to a modification (Modification 4) of the second embodiment. FIG. 19 shows a planar configuration of the reset transistor 23, the amplifying transistor 24, and the selecting transistor 25, FIG. 20A shows a cross-sectional configuration along the line A-A' shown in FIG. 19, and FIG. 20B shows a cross-sectional configuration along the line B-B' shown in FIG. 19. The reset transistor 23, the amplifying transistor 24, and the selecting transistor 25 of this image sensor 10A have a Fin FET structure. Except for this point, the image sensor 10A according to Modification 4 has the same configuration as the image sensor 10A according to the second embodiment, and the operation and effect are also the same.

[0113] The reset transistor 23 having a FinFET structure has a fin F1 having a channel region 23C, a gate electrode 23G provided around the fin F1, and a gate insulating film 23I provided between the gate electrode 23G and the fin F1 (FIGS. 19 and 20A). The amplification transistor 24 having a FinFET structure has fins F2 and F3 having a channel region 24C, a gate electrode 24G provided around the fins F2 and F3, and a gate insulating film 24I provided between the gate electrode 24G and the fins F2 and F3 (FIGS. 19 and 20A). The selection transistor 25 having a FinFET structure has fins F2 and F3 having a channel region 25C, a gate electrode 25G provided around the fins F2 and F3, and a gate insulating film 25I provided between the gate electrode 25G and the fins F2 and F3 (FIGS. 19 and 20B).

[0114] The fins F1, F2, and F3 are made of, for example, silicon (Si) in which n-type impurities are diffused. For example, the impurity concentration of the n-type impurity is 1×10 17 cm -3 ~1×10 19 cm -3The fins F1, F2, and F3 are formed of silicon of about 1000 nm. The fins F1, F2, and F3 are provided on the interlayer insulating film 19 and substantially perpendicular to the surface S11B of the semiconductor substrate 11. The fins F1, F2, and F3 form the semiconductor layer 30S of the second substrate 30. The fins F1, F2, and F3 extend, for example, parallel to each other. The fins F1, F2, and F3 are separated from each other by an element isolation region 112. The fin F2 and the fin F3 are connected to each other at both ends.

[0115] The fin F1 is provided with source / drain regions 23A and 23B adjacent to the channel region 23C, and the fins F2 and F3 are provided with source / drain regions 24A and 24B adjacent to the channel region 24C and source / drain regions 25A and 25B adjacent to the channel region 25C. That is, the reset transistor 23 has n-type source / drain regions 23A and 23B in the fin F1 outside the semiconductor substrate 11, and a channel region 23C of the same conductivity type (n-type) as the source / drain regions 23A and 23B. The amplifying transistor 24 has n-type source / drain regions 24A and 24B in the fins F2 and F3, and a channel region 24C of the same conductivity type (n-type) as the source / drain regions 24A and 24B. The selection transistor 25 has, for example, n-type source / drain regions 25A and 25B and a channel region 25C of the same conductivity type (n-type) as the source / drain regions 25A and 25B in the same fins F2 and F3 as the amplification transistor 24. In other words, a plurality of channel regions 24C and 25C and source / drain regions 24A, 24B, 25A, and 25B are continuously provided in the fins F2 and F3.

[0116] A contact portion FC1 is provided at one end of the fins F2, F3, and a contact portion FC2 is provided at the other end of the fins F2, F3. The contact portion FC1 is a portion that connects one of the pair of source-drain regions 24A, 24B (source-drain region 24B) of the amplification transistor 24 to a pixel power supply Vdd. The contact portion FC2 is a portion that connects one of the pair of source-drain regions 25A, 25B (source-drain region 25A) of the selection transistor 25 to the vertical signal line 18 (FIG. 2).

[0117] The gate electrode 23G is provided on the interlayer insulating film 19 together with the fin F1. The gate electrode 23G includes a pair of side surfaces 231, 232 facing each other with the fin F1 therebetween, and an upper surface 233 connecting the pair of side surfaces 231, 232. The upper surface 233 faces the interlayer insulating film 19 with the fin F1 therebetween. The upper surface 233 is covered with the interlayer insulating film 30I. A gate insulating film 23I is provided between the fin F1 and each of the pair of side surfaces 231, 232 and the upper surface 233.

[0118] The gate electrode 24G is provided on the interlayer insulating film 19 together with the fins F2 and F3. The gate electrode 24G includes a pair of side surfaces 241 and 242 facing each other with the fins F2 and F3 therebetween, an upper surface 243 connecting the pair of side surfaces 241 and 242, and a separation surface 245 between the fins F2 and F3. The pair of side surfaces 241 and 242 and the separation surface 245 are provided parallel to each other. The upper surface 243 faces the interlayer insulating film 19 with the fins F2 and F3 therebetween. The upper surface 243 is covered with the interlayer insulating film 30I. The gate insulating film 24I is provided between the fins F2 and F3 and each of the pair of side surfaces 241 and 242, the upper surface 233, and the separation surface 235.

[0119] The gate electrode 25G is provided on the interlayer insulating film 19 together with the fins F2 and F3. The gate electrode 25G includes a pair of side surfaces 251 and 252 facing each other with the fins F2 and F3 therebetween, an upper surface 253 connecting the pair of side surfaces 251 and 252, and a separation surface 255 between the fins F2 and F3. The pair of side surfaces 251 and 252 and the separation surface 255 are provided parallel to each other. The upper surface 253 faces the interlayer insulating film 19 with the fins F2 and F3 therebetween. The upper surface 253 is covered with the interlayer insulating film 30I. A gate insulating film 25I is provided between each of the fins F2 and F3 and the pair of side surfaces 251 and 252, the upper surface 253, and the separation surface 255.

[0120] Such gate electrodes 23G, 24G, 25G are made of, for example, p-type polysilicon, etc. The gate insulating films 23I, 24I, 25I are made of, for example, silicon oxide (SiO) or the like.

[0121] The interlayer insulating film 30I faces the interlayer insulating film 19 with the fins F1, F2, and F3 therebetween. The interlayer insulating film 30I is provided with connection holes reaching the upper surfaces 243 and 253 of the gate electrodes 24G and 25G, and a connection hole reaching the fin F1. An electrode 24E is provided in the connection hole reaching the upper surface 243, an electrode 25E is provided in the connection hole reaching the upper surface 253, and an electrode 23E is provided in the connection hole reaching the fin F1.

[0122] The imaging element 10A having such a reset transistor 23, amplifying transistor 24, and selecting transistor 25 can be manufactured, for example, as follows (FIGS. 21A to 22H). Note that although the reset transistor 23 is illustrated in FIGS. 21A to 22H, the amplifying transistor 24 and selecting transistor 25 can also be manufactured in a similar manner.

[0123] First, the first substrate 11A is formed as shown in Fig. 21A. The first substrate 11A is formed, for example, as follows.

[0124] First, the p-type impurity is, for example, 1×10 16 cm -3 ~1×10 18 cm -3 A semiconductor substrate 11 is prepared in which impurities are diffused to a concentration of about 1000 p-type impurities. A semiconductor substrate 11 having a lower p-type impurity concentration may be used, or a semiconductor substrate 11 in which n-type impurities are diffused may be used. Next, thermal oxidation is performed to form a silicon oxide film having a thickness of about 3 nm to 10 nm on the surface S11B of the semiconductor substrate 11. Then, for example, a polysilicon film is formed on the silicon oxide film. Thereafter, the polysilicon film and the silicon oxide film are formed into a predetermined shape using lithography and etching. As a result, a gate electrode 22G and a gate insulating film 22I of the transfer transistor 22 are formed.

[0125] After the gate electrode 22G and the gate insulating film 22I are formed, the photodiode 21 is formed in the semiconductor substrate 11. The photodiode 21 is formed of, for example, a p-type impurity region 21a having a depth dimension of about 30 nm to 200 nm and an n-type impurity region 21b having a depth dimension of about 1 μm to 5 μm. For example, the impurity concentration of the p-type impurity region 21a is 1×10 18 cm -3 x1x10 19 cm -3 The impurity concentration of the n-type impurity region 21b is about 1×10 15 cm -3 x1x10 18 cm -3 That's about it.

[0126] After the photodiode 21 is formed, the FD section 26 is formed in the semiconductor substrate 11. The FD section 26 is formed, for example, by an n-type impurity diffusion region. The concentration of the FD section 26 is, for example, 1×10 19 cm -3 x1x10 20 cm -3After the FD portion 26 is formed, oxidation annealing is performed at about 1000° C. to 1100° C. for 1 to 10 seconds, for example. Thereafter, an insulating film such as silicon oxide is formed on the semiconductor substrate 11 so as to cover the gate electrode 22G and the gate insulating film 22I of the transfer transistor 22. A planarization process such as CMP (Chemical Mechanical Polishing) is performed on this insulating film to form the interlayer insulating film 19. In this manner, the first substrate 11A is formed.

[0127] After the first substrate 11A is formed, as shown in FIG. 21B, an SOI substrate 50 is bonded to the first substrate 11A. The SOI substrate 50 has, for example, a first oxide film 52, a semiconductor layer 53F, and a second oxide film 54 on a substrate 51 in this order. The substrate 51 is made of, for example, a silicon (Si) substrate. The first oxide film 52 and the second oxide film 54 are made of, for example, a silicon oxide (SiO) film. The semiconductor layer 53F is made of, for example, a silicon layer in which an n-type impurity is diffused. The concentration of the n-type impurity in the semiconductor layer 53F is, for example, 1×10 17 cm -3 x1x10 19 cm -3 The thickness of the semiconductor layer 53F is about 200 nm to 1000 nm. The SOI substrate 50 is bonded to the first substrate 11A so that the second oxide film 54 and the interlayer insulating film 19 are in contact with each other. The bonding strength may be increased by subjecting the bonding surfaces to a plasma treatment in advance. The concentration of n-type impurities in the semiconductor layer 53F may be made lower, or p-type impurities may be diffused in the semiconductor layer 53F. The n-type impurities are implanted into such a semiconductor layer 53F in a later process. Instead of the SOI substrate 50, a bulk silicon substrate may be bonded.

[0128] After bonding the SOI substrate 50 to the first substrate 11A, the substrate 51 and the first oxide film 52 of the SOI substrate 50 are removed as shown in Fig. 21C. The substrate 51 and the first oxide film 52 are removed by using, for example, CMP. When a bulk silicon substrate is bonded to the first substrate 11A instead of the SOI substrate 50, the silicon substrate is shaved by CMP or the like to adjust it to a desired thickness.

[0129] After removing the substrate 51 and the first oxide film 52, the semiconductor layer 53F is shaped into a desired shape by using lithography and etching to form the fins F1 (and F2 and F3), as shown in Fig. 22A. Note that Figs. 22A to 22H only show layers above the interlayer insulating film 19.

[0130] After the fin F1 is formed, as shown in FIG. 22B, the element isolation region 112 is formed around the fin F1. For example, the element isolation region 112 is formed as follows. First, an insulating film such as silicon oxide is formed on the interlayer insulating film 19 so as to cover the fin F1. Thereafter, the insulating film is subjected to a planarization process such as CMP to form the element isolation region 112. In this manner, the semiconductor layer 30S including the fin F1 (and the fins F2 and F3) and the element isolation region 112 is formed.

[0131] After forming the element isolation region 112, as shown in Fig. 22C, a groove 112M is formed on both sides of the fin F1, penetrating the semiconductor layer 30S and reaching the interlayer insulating film 19. The groove 112M is for forming a pair of side surfaces 231, 232 (and side surfaces 241, 242, 251, 252) of the gate electrode 23G (and gate electrodes 24G, 25G). The groove 112M is formed by, for example, using an etching method.

[0132] After forming the groove 112M in the semiconductor layer 30S, as shown in FIG. 22D, the gate insulating film 23I (and the gate insulating films 24I and 25I) are formed around the fin F1 (and the fins F2 and F3). The gate insulating film 23I is, for example, a silicon oxide (SiO) film formed by subjecting the fin F1 to thermal oxidation, and has a thickness of about 3 nm to 10 nm. The gate insulating film 23I may be formed by a film formation process.

[0133] After forming the gate insulating film 23I, as shown in FIG. 22E, the gate electrode 23G (and the gate electrodes 24G and 25G) are formed. The gate electrode 23G is formed, for example, as follows. First, for example, p-type polysilicon is formed on the element isolation region 112 so as to fill the groove 112M. Next, the polysilicon film is subjected to a planarization process such as CMP. Thereafter, the polysilicon film is formed into a predetermined shape using a photolithography method and an etching method. In this way, the gate electrode 23G is formed. After forming the gate electrode 23G, the source / drain regions 23A and 23B (and the source / drain regions 24A and 24B) are formed at positions adjacent to the channel region 23C (and the channel regions 24C and 25C). The source / drain regions 23A and 23B are formed by injecting n-type impurities into the fin F1 (and the fins F2 and F3). Thereafter, activation annealing is performed at about 1000° C. to 1100° C. for 1 to 10 seconds, for example.

[0134] 22F, an interlayer insulating film 30I is formed on the semiconductor layer 30S. The interlayer insulating film 30I is formed by depositing an insulating film so as to cover the gate electrode 23G, and then performing a planarization process such as CMP on the insulating film.

[0135] After the interlayer insulating film 30I is formed, the electrode 26E (and electrodes 23E, 24E, and 25E) are formed as shown in FIG. 22G. The electrode 26E is formed, for example, as follows. First, a connection hole reaching the FD section 26 is formed, for example, by using an etching method. Next, a conductive material such as tungsten (W) is embedded in the connection hole. This forms the electrode 26E.

[0136] After the electrode 26E is formed, the wiring 31 is formed on the interlayer insulating film 30I as shown in Fig. 22H. The wiring 31 is formed using, for example, copper (Cu) or the like.

[0137] Next, a multilayer wiring layer 30W including other wirings 31, an interlayer insulating film 32, and a contact electrode 33 is formed. This forms the second substrate 30. Thereafter, the second substrate 30 is bonded to the third substrate 40 by, for example, CuCu bonding. In this manner, the image sensor 10A shown in FIGS. 19, 20A, and 20B is completed.

[0138] In the image sensor 10A according to this modification, similarly to the second embodiment, the amplifying transistor 24 has a channel region 24C of the same conductivity type (n-type) as that of the source-drain regions 24A and 24B, so that it is possible to reduce noise caused by carriers captured at the interface of the channel region 24C on the gate electrode 24G side. Also, the reset transistor 23 and the selection transistor 25 have channel regions 23C and 25C of the same conductivity type (n-type) as that of the source-drain regions 23A, 23B, 25A, and 25B, so that it is possible to reduce noise caused by carriers captured at the interface of the channel regions 23C and 25C on the gate electrodes 23G and 25G side.

[0139] In this modification, the reset transistor 23, the amplifying transistor 24, and the selecting transistor 25 having a Fin FET structure have been described, but the reset transistor 23, the amplifying transistor 24, and the selecting transistor 25 may have a GAA structure, as described in the above modification 2 (Figure 9).

[0140] <Variation 5> 23 shows a schematic cross-sectional configuration of a main part of an image sensor 10A (FIG. 18) according to a modification (Modification 5) of the second embodiment. In the image sensor 10A according to Modification 5, the photodiode 21 is provided at a position deeper than the surface S11B (on the surface S11A side), and the transfer transistor 22 is configured by a vertical transistor (transfer gate TG). Except for this, the image sensor 10A according to Modification 5 has the same configuration as the image sensor 10A of the second embodiment, and also has the same action and effect.

[0141] The gate (transfer gate TG) of the transfer transistor 22 extends from the surface of the semiconductor substrate 11 through the p-type well region 111 to a depth reaching the photodiode 21.

[0142] The first substrate 11A has a pixel separating section 21S separating each pixel P. The pixel separating section 21S is formed extending in a normal direction of the semiconductor substrate 11 (a direction perpendicular to the surface S11B of the semiconductor substrate 11). The pixel separating section 21S is provided between two adjacent pixels P. The pixel separating section 21S electrically separates the adjacent pixels P from each other. The pixel separating section 21S is made of, for example, silicon oxide. The pixel separating section 21S penetrates, for example, the semiconductor substrate 11. A p-type impurity region 21a and an n-type impurity region 21b are provided on the side surface of the pixel separating section 21S.

[0143] As shown in FIG. 23, the first substrate 11A and the second substrate 30 are electrically connected to each other by the electrode 26E. Furthermore, the first substrate 11A and the second substrate 30 are connected to each other by the electrodes E1 and E2 penetrating the interlayer insulating films 19 and 30I (see FIGS. 24 and 25 described later). In the image sensor 10A, for example, the electrodes E1 and E2 are provided for each pixel P. Also, as shown in FIG. 23, the second substrate 30 and the third substrate 40 are electrically connected to each other by the bonding of the contact electrodes 33 and 43. Here, the width of the electrode 26E is narrower than the width of the bonding portion between the contact electrodes 33 and 43. That is, the cross-sectional area of ​​the electrode 26E is smaller than the cross-sectional area of ​​the bonding portion between the contact electrodes 33 and 43. Therefore, the electrode 26E does not prevent the area per pixel in the first substrate 11A from being miniaturized. In addition, since the readout circuit 20 is formed on the second substrate 30 and the logic circuit LC is formed on the third substrate 40, the structure for electrically connecting the second substrate 30 and the third substrate 40 to each other can be formed with a more flexible layout in terms of the arrangement and the number of contacts for connection, compared to the structure for electrically connecting the first substrate 11A and the second substrate 30 to each other. Therefore, the bonding between the contact electrodes 33, 43 can be used as the structure for electrically connecting the second substrate 30 and the third substrate 40 to each other.

[0144] 24 and 25 show an example of a cross-sectional configuration of the imaging element 10A in the horizontal direction. The upper diagrams of FIG. 24 and FIG. 25 show an example of a cross-sectional configuration at the cross section Sec1 of FIG. 23, and the lower diagrams of FIG. 24 and FIG. 25 show an example of a cross-sectional configuration at the cross section Sec2 of FIG. 23. FIG. 24 shows an example of a configuration in which two sets of four pixels P of 2×2 are arranged in the second direction H, and FIG. 25 shows an example of a configuration in which four pixels P of 2×2 are arranged in the first direction V and the second direction H. In the upper cross-sectional views of FIG. 24 and FIG. 25, a diagram showing an example of a surface configuration of the semiconductor substrate 11 is superimposed on a diagram showing an example of a cross-sectional configuration at the cross section Sec1 of FIG. 23, and the interlayer insulating film 19 is omitted. In the lower cross-sectional views of FIG. 24 and FIG. 25, a diagram showing an example of a surface configuration of the semiconductor layer 30S is superimposed on a diagram showing an example of a cross-sectional configuration at the cross section Sec2 of FIG. 23.

[0145] As shown in FIG. 24 and FIG. 25, the electrodes 26E, the electrodes E2, and the electrodes E1 are arranged in a strip shape in the first direction V (the vertical direction in FIG. 10, the horizontal direction in FIG. 11) in the plane of the first substrate 11A. Note that FIG. 24 and FIG. 25 illustrate a case in which the electrodes 26E, the electrodes E2, and the electrodes E1 are arranged in two columns in the first direction V. The first direction V is parallel to one of two arrangement directions (e.g., the row direction and the column direction) of the pixels P arranged in a matrix shape (e.g., the column direction). In the four pixels P sharing the readout circuit 20, the four FD sections 26 are arranged close to each other, for example, via the pixel separation section 21S. In the four pixels P sharing the readout circuit 20, the four transfer gates TG are arranged so as to surround the four FD sections 26, and are shaped like a ring by the four transfer gates TG, for example.

[0146] The element isolation region 112 is composed of a plurality of blocks extending in the first direction V. The semiconductor layer 30S is composed of a plurality of island-shaped blocks 30SA extending in the first direction V and arranged in a line in a second direction H perpendicular to the first direction V via the element isolation region 112. Each block 30SA is provided with, for example, a plurality of sets of a reset transistor 23, an amplification transistor 24, and a selection transistor 25. One readout circuit 20 shared by four pixels P is composed of, for example, a reset transistor 23, an amplification transistor 24, and a selection transistor 25 in an area facing the four pixels P. One readout circuit 20 shared by four pixels P is composed of, for example, an amplification transistor 24 in a block 30SA to the left of the element isolation region 112, and a reset transistor 23 and a selection transistor 25 in a block 30SA to the right of the element isolation region 112.

[0147] Figures 26, 27, 28, and 29 show examples of wiring layouts in the horizontal plane of the image sensor 10A. Figures 26 to 29 show an example in which one readout circuit 20 shared by four pixels P is provided in a region facing the four pixels P. The wirings shown in Figures 26 to 29 are provided, for example, in different layers of the multilayer wiring layer 30W.

[0148] The four electrodes 26E adjacent to each other are electrically connected to the wiring 31, for example, as shown in Fig. 26. The four electrodes 26E adjacent to each other are further electrically connected to the gate of the amplification transistor 24 included in the block 30SA adjacent to the left of the element isolation region 112 and the gate of the reset transistor 23 included in the block 30SA adjacent to the right of the element isolation region 112, via the wiring 31 and the electrode 24E, for example, as shown in Fig. 26.

[0149] The power supply line VDD is disposed at a position facing each of the readout circuits 20 arranged side by side in the second direction H, as shown in FIG. 27, for example. The power supply line VDD is electrically connected to the drain of the amplification transistor 24 and the drain of the reset transistor 23 of each of the readout circuits 20 arranged side by side in the second direction H via an electrode 24E, as shown in FIG. 27, for example. Two pixel driving lines 17 are disposed at a position facing each of the readout circuits 20 arranged side by side in the second direction H, as shown in FIG. 27, for example. One pixel driving line 17 (second control line) is a wiring RSTG electrically connected to the gate of the reset transistor 23 of each of the readout circuits 20 arranged side by side in the second direction H, as shown in FIG. The other pixel driving line 17 (third control line) is a wiring SELG electrically connected to the gate of the selection transistor 25 of each of the readout circuits 20 arranged side by side in the second direction H, as shown in FIG. 27, for example. In each read circuit 20, the source of the amplification transistor 24 and the drain of the selection transistor 25 are electrically connected to each other via a wiring 31W, for example, as shown in FIG.

[0150] Two power supply lines VSS are arranged at positions facing the readout circuits 20 arranged side by side in the second direction H, as shown in FIG. 28, for example. Each power supply line VSS is electrically connected to a plurality of electrodes E1 at a position facing the pixels P arranged side by side in the second direction H, as shown in FIG. 28, for example. Four pixel driving lines 17 are arranged at positions facing the readout circuits 20 arranged side by side in the second direction H, as shown in FIG. 28, for example. Each of the four pixel driving lines 17 is a wiring TRG electrically connected to the electrode E2 of one pixel P among the four pixels P corresponding to each readout circuit 20 arranged side by side in the second direction H, as shown in FIG. 28, for example. That is, the four pixel driving lines 17 (first control lines) are electrically connected to the gates (transfer gates TG) of the transfer transistors 22 of the pixels P arranged side by side in the second direction H. In FIG. 28, in order to distinguish each wiring TRG, an identifier (1, 2, 3, 4) is added to the end of each wiring TRG.

[0151] The vertical signal line 18 is disposed at a position facing each readout circuit 20 arranged side by side in the first direction V, as shown in Fig. 29. The vertical signal line 18 (output line) is electrically connected to the output terminal (the source of the amplification transistor 24) of each readout circuit 20 arranged side by side in the first direction V, as shown in Fig. 29.

[0152] In this modification, the pixel P and the readout circuit 20 are formed on different substrates (the first substrate 11A and the second substrate 30). This allows the area of ​​the pixel P and the readout circuit 20 to be enlarged compared to when the pixel P and the readout circuit 20 are formed on the same substrate. As a result, the photoelectric conversion efficiency can be improved and the transistor noise can be reduced. In addition, the first substrate 11A having the pixel P and the second substrate 30 having the readout circuit 20 are electrically connected to each other by the electrodes 26E provided in the interlayer insulating films 19 and 30I. This allows the chip size to be further reduced compared to when the first substrate 11A and the second substrate 30 are electrically connected to each other by bonding between pad electrodes or by through wiring (for example, TSV (Thorough Si Via)) that penetrates the semiconductor substrate. In addition, the resolution can be further increased by further miniaturizing the area per pixel. In addition, when the chip size is the same as before, the formation area of ​​the pixel P can be enlarged. In this modification, the readout circuit 20 and the logic circuit LC are formed on different substrates (the second substrate 30 and the third substrate 40). This allows the areas of the readout circuit 20 and the logic circuit LC to be enlarged compared to when the readout circuit 20 and the logic circuit LC are formed on the same substrate. In addition, the areas of the readout circuit 20 and the logic circuit LC are not restricted by the pixel separating section 21S, so that noise characteristics can be improved. In this modification, the second substrate 30 and the third substrate 40 are electrically connected to each other by bonding the contact electrodes 33, 43 to each other. Here, since the readout circuit 20 is formed on the second substrate 30 and the logic circuit LC is formed on the third substrate 40, the structure for electrically connecting the second substrate 30 and the third substrate 40 to each other can be formed with a more flexible layout in terms of the arrangement and the number of contacts for connection compared to the structure for electrically connecting the first substrate 11A and the second substrate 30 to each other. Therefore, the bonding between the contact electrodes 33, 43 can be used for electrical connection between the second substrate 30 and the third substrate 40. In this manner, in this modification, the substrates are electrically connected to each other according to the integration density of the substrates.This prevents the chip size from increasing and prevents miniaturization of the area per pixel, which would otherwise be caused by the structure for electrically connecting the substrates together. As a result, it is possible to provide an image sensor 10A with a three-layer structure that has the same chip size as before and does not prevent miniaturization of the area per pixel.

[0153] In this modification, the pixel P having the photodiode 21, the transfer transistor 22, and the FD section 26 is formed on the first substrate 11A, and the readout circuit 20 having the reset transistor 23, the amplification transistor 24, and the selection transistor 25 is formed on the second substrate 30. This allows the area of ​​the pixel P and the readout circuit 20 to be enlarged compared to when the pixel P and the readout circuit 20 are formed on the same substrate. As a result, even when the contact electrodes 33, 43 are bonded to each other for electrical connection between the second substrate 30 and the third substrate 40, the chip size does not increase and the miniaturization of the area per pixel is not hindered. As a result, it is possible to provide an imaging element 10A having a three-layer structure that does not hinder the miniaturization of the area per pixel with the same chip size as before. Specifically, by reducing the number of transistors provided on the first substrate 11A, the area of ​​the photodiode 21 of the pixel P in particular can be enlarged. This increases the amount of saturated signal charge in photoelectric conversion, thereby improving the photoelectric conversion efficiency. In the second substrate 30, the degree of freedom in the layout of each transistor in the readout circuit 20 can be ensured. In addition, since the area of ​​each transistor can be enlarged, the area of ​​the amplification transistor 24 in particular can be enlarged, thereby reducing noise that affects pixel signals. Even if the contact electrodes 33, 43 are bonded to each other for electrical connection between the second substrate 30 and the third substrate 40, the chip size does not increase and miniaturization of the area per pixel is not hindered. As a result, it is possible to provide a three-layered imaging element 10A that has the same chip size as before and does not hinder miniaturization of the area per pixel.

[0154] In this modification, the second substrate 30 is bonded to the first substrate 11A with the back surface of the semiconductor layer 30S facing the front surface side of the semiconductor substrate 11, and the third substrate 40 is bonded to the second substrate 30 with the front surface side of the semiconductor layer 40S facing the front surface side of the semiconductor layer 30S. By using the electrode 26E for electrical connection between the first substrate 11A and the second substrate 30 and using the bonding between the contact electrodes 33, 43 for electrical connection between the second substrate 30 and the third substrate 40, it is possible to provide an image sensor 10A with a three-layer structure that has a chip size equivalent to that of the past and does not hinder miniaturization of the area per pixel.

[0155] In this modification, the cross-sectional area of ​​electrode 26E is smaller than the cross-sectional area of ​​the junction between contact electrodes 33 and 43. This makes it possible to provide an image sensor 10A with a three-layer structure that does not impede miniaturization of the area per pixel, while maintaining the same chip size as before.

[0156] In addition, in the logic circuit LC of this modification, a low-resistance region made of silicide formed by a salicide (Self Aligned Silicide) process such as CoSi2 or NiSi is formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode. The low-resistance region made of silicide is formed of a compound of the material of the semiconductor substrate and a metal. Here, the logic circuit LC is provided on the third substrate 40. Therefore, the logic circuit LC can be formed by a process different from the process for forming the pixels P and the readout circuit 20. As a result, a high-temperature process such as thermal oxidation can be used when forming the pixels P and the readout circuit 20. In addition, the logic circuit LC can be made of silicide, which is a material with low heat resistance. Therefore, when a low-resistance region made of silicide is provided on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode of the logic circuit LC, the contact resistance can be reduced, and as a result, the operation speed of the logic circuit LC can be increased.

[0157] In this modification, the first substrate 11A is provided with a pixel separator 21S for separating each pixel P. However, in this modification, the pixel P having the photodiode 21, the transfer transistor 22, and the FD section 26 is formed on the first substrate 11A, and the readout circuit 20 having the reset transistor 23, the amplifying transistor 24, and the selection transistor 25 is formed on the second substrate 30. This allows the area of ​​the pixel P and the readout circuit 20 to be enlarged even if the area surrounded by the pixel separator 21S is reduced due to miniaturization of the area per pixel. As a result, even if the pixel separator 21S is used, the chip size does not increase and miniaturization of the area per pixel is not hindered. Therefore, it is possible to provide a three-layered imaging element 10A that has the same chip size as before and does not hinder miniaturization of the area per pixel.

[0158] Furthermore, in this modification, the pixel separation portion 21S penetrates the semiconductor substrate 11. As a result, even if the distance between the pixels P is shortened due to miniaturization of the area per pixel, signal crosstalk between adjacent pixels P can be suppressed, and degradation of image quality due to reduced resolution and color mixing on a reproduced image can be suppressed.

[0159] In addition, in this modification, the laminated body consisting of the first substrate 11A and the second substrate 30 has three electrodes 26E, E1, and E2 for each pixel P. The electrode 26E is electrically connected to the gate (transfer gate TG) of the transfer transistor 22, the electrode E1 is electrically connected to the p-type well region 111 of the semiconductor substrate 11, and the electrode E2 is electrically connected to the FD section 26. That is, the number of the electrodes 26E, E1, and E2 is greater than the number of the pixels P included in the first substrate 11A. However, in this modification, the electrode 26E having a small cross-sectional area is used for the electrical connection between the first substrate 11A and the second substrate 30. This allows the chip size to be further reduced, and the area per pixel in the first substrate 11A to be further miniaturized. As a result, it is possible to provide an imaging element 10A having a three-layer structure that does not hinder miniaturization of the area per pixel with the same chip size as before.

[0160] <Variation 6> FIG. 30 shows a modified vertical cross-sectional configuration of an image sensor 10A according to a modified example (modification 6) of the second embodiment. In this modification, the second substrate 30 and the third substrate 40 are electrically connected in a region of the first substrate 11A facing the peripheral region 12B. The peripheral region 12B corresponds to a frame region of the first substrate 11A and is provided on the periphery of the pixel array section 12. In this modification, the second substrate 30 has a plurality of contact electrodes 33 in a region facing the peripheral region 12B, and the third substrate 40 has a plurality of contact electrodes 44 in a region facing the peripheral region 12B. The second substrate 30 and the third substrate 40 are electrically connected to each other by bonding the contact electrodes 33, 43 provided in the region facing the peripheral region 12B.

[0161] In this manner, in this modification, the second substrate 30 and the third substrate 40 are electrically connected to each other by bonding the contact electrodes 33, 43 provided in the region facing the peripheral region 12B. This reduces the risk of hindering miniaturization of the area per pixel compared to the case where the contact electrodes 33, 43 are bonded to each other in the region facing the pixel array section 12. Therefore, it is possible to provide an image sensor 10A with a three-layer structure that does not hinder miniaturization of the area per pixel with the same chip size as before.

[0162] <Variation 7> 31 and 32 show a modified horizontal cross-sectional configuration of the image sensor 10A according to the second embodiment. The upper views of FIGS. 31 and 32 show a modified cross-sectional configuration at the cross-section Sec1 of FIG. 23, and the lower view of FIG. 31 shows a modified cross-sectional configuration at the cross-section Sec2 of FIG. 23. In the upper cross-sectional views of FIGS. 31 and 32, a view showing a modified surface configuration of the semiconductor substrate 11 in FIG. 23 is superimposed on a view showing a modified cross-sectional configuration at the cross-section Sec1 of FIG. 23, and the interlayer insulating film 19 is omitted. In the lower cross-sectional views of FIGS. 31 and 32, a view showing a modified surface configuration of the semiconductor layer 30S is superimposed on a view showing a modified cross-sectional configuration at the cross-section Sec2 of FIG. 23.

[0163] As shown in FIG. 31 and FIG. 32, the electrodes 26E, the electrodes E2, and the electrodes E1 (the dots arranged in a matrix in the figures) are arranged in a strip shape in the first direction V (the left-right direction in FIG. 23 and FIG. 24) in the plane of the first substrate 11A. Note that FIG. 31 and FIG. 32 illustrate a case in which the electrodes 26E, the electrodes E2, and the electrodes E1 are arranged in two rows in the first direction V. In the four pixels P sharing the readout circuit 20, the four FD sections 26 are arranged close to each other, for example, via the pixel separation section 21S. In the four pixels P sharing the readout circuit 20, the four transfer gates TG (TG1, TG2, TG3, TG4) are arranged to surround the four FD sections 26, and are shaped like a ring by the four transfer gates TG, for example.

[0164] The element isolation region 112 is composed of a plurality of blocks extending in a first direction V. The semiconductor layer 30S is composed of a plurality of island-shaped blocks 30SA extending in the first direction V and arranged side by side in a second direction H perpendicular to the first direction V via the element isolation region 112. Each block 30SA is provided with, for example, a reset transistor 23, an amplification transistor 24, and a selection transistor 25. One readout circuit 20 shared by four pixels P is, for example, not arranged directly opposite the four pixels P, but arranged shifted in the second direction H.

[0165] 31, one readout circuit 20 shared by four pixels P is composed of a reset transistor 23, an amplification transistor 24, and a selection transistor 25 located in an area of ​​the second substrate 30 shifted in the second direction H from an area facing the four pixels P. One readout circuit 20 shared by the four pixels P is composed of, for example, the amplification transistor 24, the reset transistor 23, and the selection transistor 25 in one block 30SA.

[0166] 32, one readout circuit 20 shared by four pixels P is composed of a reset transistor 23, an amplification transistor 24, a selection transistor 25, and an FD transfer transistor 27 located in an area of ​​the second substrate 30 shifted in the second direction H from an area facing the four pixels P. One readout circuit 20 shared by the four pixels P is composed of, for example, the amplification transistor 24, the reset transistor 23, the selection transistor 25, and the FD transfer transistor 27 in one block 30SA.

[0167] In this modification, one readout circuit 20 shared by four pixels P is not disposed directly opposite the four pixels P, but is disposed shifted in the second direction H from a position directly opposite the four pixels P. In this case, the wiring 31W can be shortened, or the wiring 31W can be omitted and the source of the amplification transistor 24 and the drain of the selection transistor 25 can be configured as a common impurity region. As a result, the size of the readout circuit 20 can be reduced, or the size of other parts in the readout circuit 20 can be increased.

[0168] <Variation 8> 33 shows a modified horizontal cross-sectional configuration of the image sensor 10A according to the second embodiment. In FIG. 33, a modified version of the cross-sectional configuration in FIG.

[0169] In this modification, the semiconductor layer 30S is composed of a plurality of island-shaped blocks 30SA arranged side by side in the first direction V and the second direction H via an element isolation region 112. Each block 30SA is provided with, for example, a set of a reset transistor 23, an amplifying transistor 24, and a selection transistor 25. In this case, crosstalk between adjacent readout circuits 20 can be suppressed by the element isolation region 112, and degradation of image quality due to a decrease in resolution and color mixing on a reproduced image can be suppressed.

[0170] <Variation 9> 34 shows a modified horizontal cross-sectional configuration of the image sensor 10A according to the second embodiment. In FIG. 34, a modified cross-sectional configuration of FIG.

[0171] In this modification, one readout circuit 20 shared by four pixels P is not disposed directly opposite the four pixels P, but is disposed shifted in the first direction V. In this modification, similar to the modification 8, the semiconductor layer 30S is further configured with a plurality of island-shaped blocks 30SA arranged in the first direction V and the second direction H via the element isolation region 112. Each block 30SA is provided with, for example, a set of reset transistor 23, amplifying transistor 24, and selection transistor 25. In this modification, a plurality of electrodes E1 and a plurality of electrodes 26E are also arranged in the second direction H. Specifically, a plurality of electrodes E1 are disposed between four electrodes 26E sharing a certain readout circuit 20 and four electrodes 26E sharing another readout circuit 20 adjacent to the readout circuit 20 in the second direction H. In this case, crosstalk between adjacent readout circuits 20 can be suppressed by the element isolation region 112 and the electrode E1, and degradation of image quality due to a decrease in resolution and color mixing on a reproduced image can be suppressed.

[0172] <Modification 10> Fig. 35 shows an example of a horizontal cross-sectional configuration of an image sensor 10A according to the second embodiment and its modified example. Fig. 35 shows a modified example of the cross-sectional configuration of Fig. 24.

[0173] In this modification, the first substrate 11A has a photodiode 21 and a transfer transistor 22 for each pixel P, and the FD section 26 is shared by every four pixels P. Therefore, in this modification, one electrode 26E is provided for every four pixels P.

[0174] In the plurality of pixels P arranged in a matrix, the unit area corresponding to the four pixels P sharing one FD section 26 is shifted in the first direction V by one pixel P, and the four pixels P corresponding to the area are referred to as four pixels PA for convenience. In this modification, the first substrate 11A shares the electrode E1 with every four pixels PA. Therefore, in this modification, one electrode E1 is provided for every four pixels PA.

[0175] In this modification, the first substrate 11A has a pixel separation section 21S that separates the photodiode 21 and the transfer transistor 22 for each pixel P. When viewed from the normal direction of the semiconductor substrate 11, the pixel separation section 21S does not completely surround the pixel P, and has gaps (unformed regions) near the FD section 26 (electrode 26E) and near the electrode E1. These gaps enable four pixels P to share one electrode 26E, and four pixels PA to share one electrode E1. In this modification, the second substrate 30 has a readout circuit 20 for each of the four pixels P that share the FD section 26.

[0176] Fig. 36 shows an example of a horizontal cross-sectional configuration of an image sensor 10A according to this modification. Fig. 36 shows a modification of the cross-sectional configuration of Fig. 33. In this modification, the first substrate 11A has a photodiode 21 and a transfer transistor 22 for each pixel P, and the FD section 26 is shared by every four pixels P. Furthermore, the first substrate 11A has a pixel separation section 21S that separates the photodiode 21 and the transfer transistor 22 for each pixel P.

[0177] Fig. 37 shows an example of a horizontal cross-sectional configuration of an image sensor 10A according to this modification. Fig. 37 shows a modification of the cross-sectional configuration of Fig. 34. In this modification, the first substrate 11A has a photodiode 21 and a transfer transistor 22 for each pixel P, and the FD section 26 is shared by every four pixels P. Furthermore, the first substrate 11A has a pixel separation section 21S that separates the photodiode 21 and the transfer transistor 22 for each pixel P.

[0178] <Modification 11> 38 illustrates an example of a circuit configuration of an image sensor 10A according to the second embodiment and its modification. The image sensor 10A according to this modification is a CMOS image sensor equipped with a column-parallel ADC.

[0179] As shown in Figure 38, the imaging element 10A of this modified example has a pixel array section 12 in which a plurality of pixels P, each including a photoelectric conversion element, are arranged two-dimensionally in a matrix, as well as a vertical drive circuit 13, a signal processing circuit 14, a reference voltage supply section 38, a horizontal drive circuit 15, a horizontal output line 37, and a system control circuit 16.

[0180] In this system configuration, the system control circuit 16 generates clock signals and control signals that serve as standards for the operation of the vertical drive circuit 13, the signal processing circuit 14, the reference voltage supply unit 38, the horizontal drive circuit 15, etc., based on the master clock MCK, and provides these signals to the vertical drive circuit 13, the signal processing circuit 14, the reference voltage supply unit 38, the horizontal drive circuit 15, etc.

[0181] The vertical drive circuit 13 is formed on the first substrate 11A together with each pixel P of the pixel array section 12, and is also formed on the second substrate 30 on which the readout circuit 20 is formed. The signal processing circuit 14, the reference voltage supply section 38, the horizontal drive circuit 15, the horizontal output line 37, and the system control circuit 16 are formed on a third substrate 40.

[0182] Although not shown here, the pixel P may have, for example, a configuration including a photodiode 21 and a transfer transistor 22 that transfers the charge obtained by photoelectric conversion in the photodiode 21 to the FD section 26. Although not shown here, the readout circuit 20 may have, for example, a three-transistor configuration including a reset transistor 23 that controls the potential of the FD section 26, an amplification transistor 24 that outputs a signal according to the potential of the FD section 26, and a selection transistor 25 for pixel selection.

[0183] In the pixel array section 12, pixels P are arranged two-dimensionally, and pixel drive lines 17 are wired for each row of this pixel arrangement of m rows and n columns, and vertical signal lines 18 are wired for each column. One end of each of the pixel drive lines 17 is connected to an output terminal corresponding to each row of the vertical drive circuit 13. The vertical drive circuit 13 is composed of a shift register or the like, and controls row addresses and row scanning of the pixel array section 12 via the pixel drive lines 17.

[0184] The signal processing circuit 14 has, for example, ADCs (analog-to-digital conversion circuits) 34-1 to 34-m provided for each pixel column of the pixel array section 12, i.e., for each vertical signal line 18, and converts analog signals output for each column from each pixel P of the pixel array section 12 into digital signals and outputs the digital signals.

[0185] The reference voltage supply unit 38 has, for example, a DAC (digital-analog conversion circuit) 38A as a means for generating a reference voltage Vref having a so-called ramp waveform whose level changes in a sloping manner as time passes. Note that the means for generating the reference voltage Vref having a ramp waveform is not limited to the DAC 38A.

[0186] The DAC 38A generates a reference voltage Vref having a ramp waveform based on a clock CK provided from the system control circuit 16 under the control of a control signal CS1 provided from the system control circuit 16, and supplies the reference voltage Vref to the ADCs 34-1 to 34-m of the signal processing circuit 14.

[0187] Each of the ADCs 34-1 to 34-m is configured to selectively perform AD conversion operations corresponding to each operation mode, namely, a normal frame rate mode in a progressive scanning system in which information on all pixels P is read out, and a high frame rate mode in which the exposure time of the pixels P is set to 1 / N and the frame rate is increased to N times, for example, 2 times, compared to the normal frame rate mode. This switching of operation modes is executed under the control of control signals CS2 and CS3 provided from the system control circuit 16. An external system controller (not shown) also provides the system control circuit 16 with instruction information for switching between the normal frame rate mode and the high frame rate mode.

[0188] The ADCs 34-1 to 34-m all have the same configuration, and the ADC 34-m will be described here as an example. The ADC 34-m includes a comparator 34A, a counting means such as an up / down counter (denoted as U / DCNT in the drawing) 34B, a transfer switch 34C, and a memory device 34D.

[0189] The comparator 34A compares the signal voltage Vx of the vertical signal line 18 corresponding to the signal output from each pixel P in the nth column of the pixel array section 12 with a reference voltage Vref having a ramp waveform supplied from the reference voltage supply section 38, and, for example, when the reference voltage Vref is greater than the signal voltage Vx, the output Vco becomes an “H” level, and when the reference voltage Vref is equal to or less than the signal voltage Vx, the output Vco becomes an “L” level.

[0190] The up / down counter 34B is an asynchronous counter, and under the control of a control signal CS2 provided from the system control circuit 16, a clock CK is provided from the system control circuit 16 simultaneously with the DAC 18A, and the up / down counter 34B measures the comparison period from the start of the comparison operation in the comparator 34A to the end of the comparison operation by counting down (DOWN) or counting up (UP) in synchronization with the clock CK.

[0191] Specifically, in the normal frame rate mode, when reading out a signal from one pixel P, the comparison time during the first readout operation is measured by counting down during the first readout operation, and the comparison time during the second readout operation is measured by counting up during the second readout operation.

[0192] On the other hand, in the high-speed frame rate mode, the count result for pixels P in a certain row is retained as is, and then, for pixels P in the next row, counting down from the previous count result during the first read operation is performed to measure the comparison time during the first read operation, and counting up during the second read operation is performed to measure the comparison time during the second read operation.

[0193] In the normal frame rate mode, under the control of a control signal CS3 provided from the system control circuit 16, the transfer switch 34C turns on (closed) when the counting operation of the up / down counter 34B for a certain row of pixels P is completed, and transfers the counting result of the up / down counter 34B to the memory device 34D.

[0194] On the other hand, at a high frame rate of, for example, N=2, the up / down counter 34B remains in the off (open) state when it completes its counting operation for pixels P in a certain row, and then turns on when it completes its counting operation for pixels P in the next row, and transfers the count result of the up / down counter 34B for two vertical pixels to the memory device 34D.

[0195] In this manner, the analog signals supplied for each column from each pixel P of the pixel array section 12 via the vertical signal line 18 are converted into N-bit digital signals by the operations of the comparators 34A and the up / down counters 34B in the ADCs 34-1 to 34-m and stored in the memory device 34D.

[0196] The horizontal drive circuit 15 is configured with a shift register and the like, and controls the column addresses and column scanning of the ADCs 34-1 to 34-m in the signal processing circuit 14. Under the control of the horizontal drive circuit 15, the N-bit digital signals AD converted by each of the ADCs 34-1 to 34-m are sequentially read out to a horizontal output line 37 and output as imaging data via the horizontal output line 37.

[0197] In addition, although not specifically shown because it is not directly related to the present disclosure, it is also possible to provide circuits, etc. that perform various types of signal processing on the imaging data output via the horizontal output line 37 in addition to the above-mentioned components.

[0198] In the image sensor 10A equipped with a column-parallel ADC according to this modified example of the above configuration, the count result of the up / down counter 34B can be selectively transferred to the memory device 34D via the transfer switch 34C, so that it is possible to independently control the count operation of the up / down counter 34B and the read operation of the count result of the up / down counter 34B to the horizontal output line 37.

[0199] <Modification 12> FIG. 39 shows an example in which the imaging element of FIG. 38 is configured by stacking three substrates (first substrate 11A, second substrate 30, third substrate 40). In this modification, in the first substrate 11A, a pixel array section 12 including a plurality of pixels P is formed in the center, and a vertical drive circuit 13 is formed around the pixel array section 12. In addition, in the second substrate 30, a readout circuit region 20R including a plurality of readout circuits 20 is formed in the center, and the vertical drive circuit 13 is formed around the readout circuit region 20R. In the third substrate 40, a signal processing circuit 14, a horizontal drive circuit 15, a system control circuit 16, a horizontal output line 37, and a reference voltage supply section 38 are formed. As a result, as in the above embodiment and its modification, the chip size does not increase and the area per pixel is not hindered from being reduced in size due to the structure electrically connecting the substrates. As a result, it is possible to provide an imaging element 10A having a three-layer structure that has a chip size equivalent to that of the past and does not hinder the area per pixel from being reduced in size. The vertical drive circuit 13 may be formed only on the first substrate 11A or only on the second substrate 30.

[0200] <Modification 13> FIG. 40 shows a modified example of the cross-sectional configuration of the imaging element 10A according to the second embodiment and its modified example. In the second embodiment and its modified example, the imaging element 10A is configured by stacking three substrates (the first substrate 11A, the second substrate 30, and the third substrate 40). However, in the second embodiment and its modified example, the imaging element 10A may be configured by stacking two substrates (the first substrate 11A and the second substrate 30). In this case, the logic circuit LC is formed separately on the first substrate 11A and the second substrate 30, for example, as shown in FIG. 40. Here, in the logic circuit LC, the circuit LCA provided on the first substrate 11A side is provided with a transistor having a gate structure in which a high dielectric constant film made of a material (e.g., high-k) that can withstand high-temperature processes and a metal gate electrode are stacked. On the other hand, in the circuit LCB provided on the second substrate 30 side, a low resistance region 30SL made of silicide formed by a salicide (Self Aligned Silicide) process such as CoSi2 or NiSi is formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode. The low resistance region made of silicide is formed of a compound of the material of the semiconductor substrate and a metal. This allows a high temperature process such as thermal oxidation to be used when forming the pixel P. In addition, in the circuit LCB provided on the second substrate 30 side of the logic circuit LC, when the low resistance region 30SL made of silicide is provided on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode, the contact resistance can be reduced. As a result, the operation speed in the logic circuit LC can be increased.

[0201] <Modification 14> FIG. 41 shows a modified example of the cross-sectional configuration of the image sensor 10A according to the second embodiment and its modified example. In the logic circuit LC of the third substrate 40 according to the second embodiment and its modified example, a low-resistance region 40SL made of silicide formed by a salicide (Self Aligned Silicide) process such as CoSi2 or NiSi may be formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode. This allows a high-temperature process such as thermal oxidation to be used when forming the pixel P. In addition, when the low-resistance region 40SL made of silicide is provided on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode in the logic circuit LC, the contact resistance can be reduced. As a result, the operation speed in the logic circuit LC can be increased.

[0202] <Application Examples> FIG. 42 shows an example of a schematic configuration of an imaging device 2 including the imaging elements 10, 10A according to the first and second embodiments and their modifications.

[0203] The imaging device 2 is, for example, an electronic device such as an imaging device such as a digital still camera or a video camera, or a mobile terminal device such as a smartphone or a tablet terminal. The imaging device 2 includes, for example, the imaging elements 10 and 10A according to the first and second embodiments and their modifications, a DSP circuit 141, a frame memory 142, a display unit 143, a storage unit 144, an operation unit 145, and a power supply unit 146. In the imaging device 2, the imaging elements 10 and 10A according to the above embodiments and their modifications, the DSP circuit 141, the frame memory 142, the display unit 143, the storage unit 144, the operation unit 145, and the power supply unit 146 are connected to each other via a bus line 147.

[0204] The imaging elements 10 and 10A according to the first and second embodiments and their modifications output image data corresponding to incident light. The DSP circuit 141 is a signal processing circuit that processes signals (image data) output from the imaging elements 10 and 10A according to the above embodiments and their modifications. The frame memory 142 temporarily holds the image data processed by the DSP circuit 141 on a frame-by-frame basis. The display unit 143 is formed of a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays a moving image or a still image captured by the imaging elements 10 and 10A according to the above embodiments and their modifications. The storage unit 144 records image data of a moving image or a still image captured by the imaging elements 10 and 10A according to the above first and second embodiments and their modifications in a recording medium such as a semiconductor memory or a hard disk. The operation unit 145 issues operation commands for various functions of the imaging device 2 according to an operation by a user. The power supply unit 146 appropriately supplies various types of power sources to these targets as operating power sources for the image pickup elements 10, 10A, DSP circuit 141, frame memory 142, display unit 143, storage unit 144 and operation unit 145 according to the first and second embodiments and their modified examples.

[0205] Next, the imaging procedure in the imaging device 2 will be described.

[0206] 43 shows an example of a flowchart of the imaging operation in the imaging device 2. The user operates the operation unit 145 to instruct the start of imaging (step S101). Then, the operation unit 145 transmits an imaging command to the imaging elements 10 and 10A (step S102). Upon receiving the imaging command, the imaging elements 10 and 10A (specifically, the system control circuit 16) execute imaging in a predetermined imaging method (step S103).

[0207] The imaging elements 10 and 10A output image data obtained by imaging to the DSP circuit 141. Here, the image data refers to data for all pixels of pixel signals generated based on the charges temporarily stored in the FD section 26. The DSP circuit 141 performs predetermined signal processing (e.g., noise reduction processing, etc.) based on the image data input from the imaging elements 10 and 10A (step S104). The DSP circuit 141 stores the image data that has been subjected to the predetermined signal processing in the frame memory 142, and the frame memory 142 stores the image data in the storage section 144 (step S105). In this manner, imaging is performed in the imaging device 2.

[0208] In this application example, the imaging elements 10, 10A according to the above-described embodiment and the modified examples thereof are applied to an imaging device 2. This allows the imaging elements 10, 10A to be made smaller or have higher definition, and therefore a small or high-definition imaging device 2 can be provided.

[0209] <Application example to in-body information acquisition system> Furthermore, the technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0210] FIG. 44 is a block diagram showing an example of a schematic configuration of a patient's in-vivo information acquisition system using a capsule endoscope to which the technology according to the present disclosure (the present technology) can be applied.

[0211] The in-vivo information acquisition system 10001 includes a capsule endoscope 10100 and an external control device 10200 .

[0212] The capsule endoscope 10100 is swallowed by a patient during an examination. The capsule endoscope 10100 has an imaging function and a wireless communication function, and while moving inside an organ such as the stomach or intestines by peristalsis or the like until it is naturally discharged from the patient, sequentially captures images of the inside of the organ (hereinafter also referred to as in-vivo images) at predetermined intervals, and sequentially wirelessly transmits information about the in-vivo images to an external control device 10200 outside the body.

[0213] The external control device 10200 comprehensively controls the operation of the in-vivo information acquisition system 10001. In addition, the external control device 10200 receives information about the in-vivo image transmitted from the capsule endoscope 10100, and generates image data for displaying the in-vivo image on a display device (not shown) based on the received information about the in-vivo image.

[0214] In this manner, the in-vivo information acquiring system 10001 can obtain in-vivo images capturing images of the state inside the patient's body at any time from when the capsule endoscope 10100 is swallowed to when it is expelled.

[0215] The configurations and functions of the capsule endoscope 10100 and the external control device 10200 will be described in more detail.

[0216] The capsule endoscope 10100 has a capsule-shaped housing 10101, which houses a light source unit 10111, an imaging unit 10112, an image processing unit 10113, a wireless communication unit 10114, a power supply unit 10115, a power supply unit 10116, and a control unit 10117.

[0217] The light source unit 10111 is composed of a light source such as an LED (light emitting diode), and irradiates the imaging field of the imaging unit 10112 with light.

[0218] The imaging unit 10112 is composed of an imaging element and an optical system consisting of multiple lenses provided in front of the imaging element. Reflected light (hereinafter referred to as observation light) of light irradiated onto the body tissue to be observed is collected by the optical system and enters the imaging element. In the imaging unit 10112, the imaging element photoelectrically converts the observation light incident thereon, and generates an image signal corresponding to the observation light. The image signal generated by the imaging unit 10112 is provided to an image processing unit 10113.

[0219] The image processing unit 10113 is configured with a processor such as a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit), and performs various signal processing on the image signal generated by the imaging unit 10112. The image processing unit 10113 provides the image signal after the signal processing to the wireless communication unit 10114 as RAW data.

[0220] The wireless communication unit 10114 performs predetermined processing such as modulation processing on the image signal that has been subjected to signal processing by the image processing unit 10113, and transmits the image signal to the external control device 10200 via the antenna 10114A. The wireless communication unit 10114 also receives a control signal related to drive control of the capsule endoscope 10100 from the external control device 10200 via the antenna 10114A. The wireless communication unit 10114 provides the control signal received from the external control device 10200 to the control unit 10117.

[0221] The power supply unit 10115 is composed of an antenna coil for receiving power, a power regeneration circuit for regenerating power from a current generated in the antenna coil, a boost circuit, etc. In the power supply unit 10115, power is generated using the principle of so-called non-contact charging.

[0222] The power supply unit 10116 is composed of a secondary battery, and stores the power generated by the power supply unit 10115. In Fig. 44, to avoid cluttering the drawing, arrows and the like indicating the destination of the power supply from the power supply unit 10116 are omitted, but the power stored in the power supply unit 10116 is supplied to the light source unit 10111, the imaging unit 10112, the image processing unit 10113, the wireless communication unit 10114, and the control unit 10117 and can be used to drive these units.

[0223] The control unit 10117 is composed of a processor such as a CPU, and appropriately controls the driving of the light source unit 10111, the imaging unit 10112, the image processing unit 10113, the wireless communication unit 10114, and the power supply unit 10115 in accordance with control signals transmitted from the external control device 10200.

[0224] The external control device 10200 is composed of a processor such as a CPU or a GPU, or a microcomputer or a control board in which a processor and a storage element such as a memory are mixed. The external control device 10200 controls the operation of the capsule endoscope 10100 by transmitting a control signal to the control unit 10117 of the capsule endoscope 10100 via the antenna 10200A. In the capsule endoscope 10100, for example, the light irradiation conditions for the observation target in the light source unit 10111 can be changed by the control signal from the external control device 10200. Furthermore, the imaging conditions (for example, the frame rate and exposure value in the imaging unit 10112) can be changed by the control signal from the external control device 10200. Furthermore, the content of the processing in the image processing unit 10113 and the conditions for the wireless communication unit 10114 to transmit an image signal (for example, the transmission interval, the number of transmitted images, etc.) may be changed by the control signal from the external control device 10200.

[0225] The external control device 10200 also applies various image processing to the image signal transmitted from the capsule endoscope 10100 to generate image data for displaying the captured in-vivo image on a display device. As the image processing, various signal processing such as development processing (demosaic processing), image quality improvement processing (band enhancement processing, super-resolution processing, NR (Noise reduction) processing, and / or image stabilization processing, etc.), and / or enlargement processing (electronic zoom processing) can be performed. The external control device 10200 controls the driving of the display device to display the captured in-vivo image based on the generated image data. Alternatively, the external control device 10200 may record the generated image data in a recording device (not shown) or print out the image data on a printing device (not shown).

[0226] An example of an in-vivo information acquisition system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the imaging unit 10112 of the above-described configuration. This improves detection accuracy.

[0227] <Application example to endoscopic surgery system> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0228] FIG. 45 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0229] 45 shows a state in which an operator (doctor) 11131 is performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0230] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the illustrated example, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may be configured as a so-called flexible scope having a flexible lens barrel.

[0231] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an observation target in the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0232] An optical system and an image sensor are provided inside the camera head 11102, and reflected light (observation light) from an observation target is collected on the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to an observation image. The image signal is transmitted to a camera control unit (CCU) 11201 as RAW data.

[0233] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and performs overall control of the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102, and performs various types of image processing on the image signal, such as development processing (demosaic processing), for displaying an image based on the image signal.

[0234] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0235] The light source device 11203 is composed of a light source such as an LED (light emitting diode), and supplies the endoscope 11100 with irradiation light when photographing an operation site or the like.

[0236] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiated light, magnification, focal length, etc.) of the endoscope 11100.

[0237] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 sends gas into the body cavity of the patient 11132 via the insufflation tube 11111 to inflate the body cavity for the purpose of securing the field of view of the endoscope 11100 and securing the working space of the surgeon. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various formats such as text, image, or graph.

[0238] The light source device 11203 that supplies irradiation light to the endoscope 11100 when photographing the surgical site can be composed of a white light source composed of, for example, an LED, a laser light source, or a combination of these. When the white light source is composed of a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so that the white balance of the captured image can be adjusted in the light source device 11203. In this case, it is also possible to capture images corresponding to each of the RGB colors in a time-division manner by irradiating the observation object with laser light from each of the RGB laser light sources in a time-division manner and controlling the driving of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter to the image sensor.

[0239] The light source device 11203 may be controlled to change the intensity of the light it outputs at predetermined time intervals. The driving of the image sensor of the camera head 11102 may be controlled in synchronization with the timing of the change in the light intensity to obtain images in a time-division manner, and the images may be synthesized to generate an image with a high dynamic range that is free of so-called blackout and whiteout.

[0240] The light source device 11203 may be configured to supply light of a predetermined wavelength band corresponding to the special light observation. In the special light observation, for example, by utilizing the wavelength dependency of light absorption in body tissue, a narrow band light is irradiated compared to the irradiated light (i.e., white light) during normal observation, and a predetermined tissue such as blood vessels on the mucous membrane surface is photographed with high contrast, so-called narrow band imaging is performed. Alternatively, in the special light observation, a fluorescent observation may be performed in which an image is obtained by fluorescence generated by irradiating an excitation light. In the fluorescent observation, it is possible to irradiate an excitation light to a body tissue and observe the fluorescence from the body tissue (autofluorescence observation), or to locally inject a reagent such as indocyanine green (ICG) into the body tissue and irradiate the body tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow band light and / or excitation light corresponding to such special light observation.

[0241] FIG. 46 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0242] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other by a transmission cable 11400 so as to be able to communicate with each other.

[0243] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is configured by combining a plurality of lenses including a zoom lens and a focus lens.

[0244] The imaging unit 11402 may include one imaging element (so-called single-plate type) or multiple imaging elements (so-called multiple-plate type). When the imaging unit 11402 is configured as a multiple-plate type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining the image signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to a 3D (dimensional) display. By performing a 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical site. Note that when the imaging unit 11402 is configured as a multiple-plate type, the lens unit 11401 may also be provided in multiple systems corresponding to each imaging element.

[0245] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately behind the objective lens.

[0246] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be appropriately adjusted.

[0247] The communication unit 11404 is configured by a communication device for transmitting and receiving various information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0248] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201, and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of capturing the image, and / or information specifying the magnification and focus of the captured image.

[0249] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by a user, or may be automatically set by the control unit 11413 of the CCU 11201 based on an acquired image signal. In the latter case, the endoscope 11100 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0250] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404.

[0251] The communication unit 11411 is configured with a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0252] Furthermore, the communication unit 11411 transmits, to the camera head 11102, a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0253] The image processing unit 11412 performs various types of image processing on the image signal, which is RAW data sent from the camera head 11102 .

[0254] The control unit 11413 performs various controls related to imaging of the surgical site etc. by the endoscope 11100 and display of the captured image obtained by imaging the surgical site etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0255] Further, the control unit 11413 causes the display device 11202 to display the captured image showing the surgical site, etc., based on the image signal that has been image-processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition techniques. For example, the control unit 11413 can recognize surgical tools such as forceps, specific living body parts, bleeding, mist when the energy treatment tool 11112 is used, etc., by detecting the shape and color of the edge of an object included in the captured image. When the control unit 11413 causes the display device 11202 to display the captured image, it may use the recognition result to superimpose various types of surgery support information on the image of the surgical site. By superimposing and presenting the surgery support information to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0256] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for communication of electrical signals, an optical fiber for optical communication, or a composite cable of these.

[0257] Here, in the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0258] An example of an endoscopic surgery system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 11402 among the configurations described above. By applying the technology according to the present disclosure to the imaging unit 11402, detection accuracy is improved.

[0259] Although an endoscopic surgery system has been described here as an example, the technology disclosed herein may also be applied to other systems, such as a microsurgery system.

[0260] <Applications to moving objects> The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, a construction machine, an agricultural machine (tractor), etc.

[0261] FIG. 47 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving object control system to which the technology according to the present disclosure can be applied.

[0262] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 47, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also, as functional configurations of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053 are illustrated.

[0263] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0264] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as head lamps, back lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves or signals of various switches transmitted from a portable device that replaces a key may be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, and the like of the vehicle.

[0265] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for a person, a car, an obstacle, a sign, or characters on a road surface, based on the received image.

[0266] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0267] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing.

[0268] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the outside-of-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0269] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0270] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0271] The audio / video output unit 12052 transmits at least one output signal of audio and video to an output device capable of visually or audibly notifying information to passengers in the vehicle or the outside of the vehicle. In the example of Fig. 47, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as the output device. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

[0272] FIG. 48 is a diagram showing an example of the installation position of the imaging unit 12031.

[0273] In FIG. 48, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0274] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin is mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

[0275] 48 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0276] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of a plurality of imaging elements, or may be an imaging element having pixels for detecting a phase difference.

[0277] For example, the microcomputer 12051 can extract, as a preceding vehicle, a three-dimensional object that is the closest three-dimensional object on the travel path of the vehicle 12100 and travels at a predetermined speed (for example, 0 km / h or more) in approximately the same direction as the vehicle 12100, by calculating the distance to each three-dimensional object in the imaging ranges 12111 to 12114 and the change over time of this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. Furthermore, the microcomputer 12051 can set a vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving that travels autonomously without relying on the driver's operation.

[0278] For example, the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0279] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured images of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

[0280] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 among the above-described configurations. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to obtain a captured image that is easier to see, thereby reducing the fatigue of the driver.

[0281] Although the contents of the present disclosure have been described above by way of embodiments and modified examples, the contents of the present disclosure are not limited to the above-mentioned embodiments and can be modified in various ways. For example, the layer structure of the imaging element described in the above-mentioned embodiment is an example, and other layers may be further included. Furthermore, the material and thickness of each layer are also an example, and are not limited to those described above.

[0282] In addition, in the above-described embodiment and the like, the case where the amplifying transistor 24 is a junctionless transistor has been described, but it is sufficient that at least one of the reset transistor 23, the amplifying transistor 24, and the selection transistor 25 is a junctionless transistor.

[0283] In the second embodiment, the amplifying transistor 24 and the selecting transistor 25 have a single gate structure. However, the amplifying transistor 24 and the selecting transistor 25 may have a double gate structure.

[0284] In addition, in the above-mentioned variant example 4, a case has been described in which the channel region 23C of the reset transistor 23 is provided in one fin (fin F1), and the channel regions 24C, 25C of the amplification transistor 24 and the selection transistor 25 are provided in two fins (fins F2, F3), but the number of fins is not limited to this.

[0285] The effects described in the above embodiment and the like are merely examples, and other effects may be achieved, or further other effects may be included.

[0286] The present disclosure may be configured as follows. According to the solid-state imaging device and imaging device having the following configuration, the output transistor has a channel region of the same conductivity type (first conductivity type) as that of the source / drain region, so that noise caused by carriers captured at the interface of the channel region on the gate electrode side can be reduced. Therefore, it is possible to suppress noise. (1) Photoelectric conversion section 、 A transfer transistor electrically connected to the photoelectric conversion unit and a charge storage section to which the signal charge generated in the photoelectric conversion section is transferred from the transfer transistor. A first substrate having a gate electrode provided opposite the first substrate; and a first conductivity type channel region disposed opposite the gate electrode; First conductivity type a second substrate having an output transistor including a source-drain region of the first conductivity type adjacent to a channel region; a drive circuit for outputting the signal charge generated in the photoelectric conversion unit via the transfer transistor and the output transistor; Equipped with the first substrate includes a semiconductor substrate having a first surface serving as a light incident side and a second surface opposed to the first surface; the semiconductor substrate has a well region of a second conductivity type different from the first conductivity type; the photoelectric conversion portion is formed by being embedded in the second conductivity type well region, the charge accumulation portion is configured by an impurity diffusion region of the first conductivity type provided in a well region of the second conductivity type near the first surface of the semiconductor substrate, The transfer transistor has a channel region of the second conductivity type between the photoelectric conversion unit and the charge accumulation unit. Solid-state imaging element. (2) The gate electrode has a flat plate shape. The solid-state imaging device according to (1) above. (3) The display further includes a third substrate that faces the first substrate with the second substrate therebetween and on which the drive circuit is provided. The solid-state imaging device according to (1) or (2). (4) a semiconductor substrate having a first surface serving as a light incident side and a second surface opposed to the first surface; A photoelectric conversion unit; A transfer transistor electrically connected to the photoelectric conversion unit; a charge accumulation section to which the signal charge generated in the photoelectric conversion section is transferred from the transfer transistor; a first conductivity type channel region electrically connected to the transfer transistor; First conductivity type a gate electrode having a plurality of faces covering a channel region; First conductivity type an output transistor including a source-drain region of the first conductivity type adjacent to a channel region; a drive circuit for outputting the signal charge generated in the photoelectric conversion unit via the transfer transistor and the output transistor; Equipped with the semiconductor substrate has a well region of a second conductivity type different from the first conductivity type; the photoelectric conversion portion is formed by being embedded in the second conductivity type well region, the charge accumulation portion is configured by an impurity diffusion region of the first conductivity type provided in a well region of the second conductivity type near the first surface of the semiconductor substrate, The transfer transistor has a channel region of the second conductivity type between the photoelectric conversion unit and the charge accumulation unit. Solid-state imaging element. (5) Furthermore, the photoelectric conversion unit 、 A transfer transistor electrically connected to the photoelectric conversion unit and a charge storage section to which the signal charge generated in the photoelectric conversion section is transferred from the transfer transistor. A first substrate having a second substrate provided opposite to the first substrate and having the output transistor; a third substrate that faces the first substrate with the second substrate therebetween and on which the drive circuit is provided; The solid-state imaging device according to (4) above. (6) Furthermore, the gate electrode and the First conductivity type A gate insulating film is provided between the channel region and the The solid-state imaging device according to any one of (1) to (5) above. 。 (7) an amplifying transistor that outputs a signal corresponding to the magnitude of the potential of the charge storage section; a reset transistor that resets the potential of the charge storage unit; a selection transistor for controlling an output of the amplification transistor; At least one of the amplifying transistor, the reset transistor, and the selection transistor is the output transistor. Any one of (1) to (6) above The solid-state imaging device according to claim 1. (8) Furthermore, First conductivity type A fin in which a channel region and the source and drain regions are provided. Any one of (1) to (7) above The solid-state imaging device according to claim 1. (9) The fin has a plurality of First conductivity type A channel region and a plurality of source and drain regions are provided in series. (8) The solid-state imaging device according to claim 1. (10) The gate electrode First conductivity type The semiconductor device includes a first surface and a second surface that face each other with a channel region therebetween, and a third surface that connects the first surface and the second surface. Any one of (1) to (9) above The solid-state imaging device according to claim 1. (11) The gate electrode further comprises: First conductivity type a fourth surface facing the third surface with a channel region therebetween; The above (10) The solid-state imaging device according to claim 1. (12) The gate electrode includes polysilicon of a second conductivity type. Any one of (1) to (11) above The solid-state imaging device according to claim 1. (13) Photoelectric conversion section 、 A transfer transistor electrically connected to the photoelectric conversion unit and a charge storage section to which the signal charge generated in the photoelectric conversion section is transferred from the transfer transistor. A first substrate having a gate electrode provided opposite the first substrate; and a first conductivity type channel region disposed opposite the gate electrode; First conductivity type a second substrate having an output transistor including a source-drain region of the first conductivity type adjacent to a channel region; a drive circuit for outputting the signal charge generated in the photoelectric conversion unit via the transfer transistor and the output transistor; Equipped with the first substrate includes a semiconductor substrate having a first surface serving as a light incident side and a second surface opposed to the first surface; the semiconductor substrate has a well region of a second conductivity type different from the first conductivity type; the photoelectric conversion portion is formed by being embedded in the second conductivity type well region, the charge accumulation portion is configured by an impurity diffusion region of the first conductivity type provided in a well region of the second conductivity type near the first surface of the semiconductor substrate, The transfer transistor has a channel region of the second conductivity type between the photoelectric conversion unit and the charge accumulation unit. An imaging device equipped with a solid-state imaging element. (14) a semiconductor substrate having a first surface serving as a light incident side and a second surface opposed to the first surface; A photoelectric conversion unit; A transfer transistor electrically connected to the photoelectric conversion unit; a charge accumulation section to which the signal charge generated in the photoelectric conversion section is transferred from the transfer transistor; a first conductivity type channel region electrically connected to the transfer transistor; First conductivity type a gate electrode having a plurality of faces covering a channel region; First conductivity type an output transistor including a source-drain region of the first conductivity type adjacent to a channel region; a drive circuit for outputting the signal charge generated in the photoelectric conversion unit via the transfer transistor and the output transistor; Equipped with the semiconductor substrate has a well region of a second conductivity type different from the first conductivity type; the photoelectric conversion portion is formed by being embedded in the second conductivity type well region, the charge accumulation portion is configured by an impurity diffusion region of the first conductivity type provided in a well region of the second conductivity type near the first surface of the semiconductor substrate, The transfer transistor has a channel region of the second conductivity type between the photoelectric conversion unit and the charge accumulation unit. An imaging device equipped with a solid-state imaging element.

[0287] This application claims priority based on Japanese Patent Application No. 2018-203704, filed on October 30, 2018 in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0288] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur to those skilled in the art depending on design requirements and other factors, and that such modifications are within the scope of the appended claims and their equivalents.

Claims

1. a first substrate having a photoelectric conversion unit, a transfer transistor electrically connected to the photoelectric conversion unit, and a charge accumulation unit to which a signal charge generated in the photoelectric conversion unit is transferred from the transfer transistor; a second substrate provided opposite to the first substrate and having an output transistor including a gate electrode, a channel region of a first conductivity type disposed opposite to the gate electrode, and a source / drain region of the first conductivity type adjacent to the channel region of the first conductivity type; a drive circuit for outputting a signal charge generated by the photoelectric conversion unit via the transfer transistor and the output transistor; the first substrate includes a semiconductor substrate having a first surface serving as a light incident side and a second surface opposed to the first surface; the semiconductor substrate has a well region of a second conductivity type different from the first conductivity type; the photoelectric conversion portion is formed by being embedded in the second conductivity type well region, the charge accumulation portion is configured by an impurity diffusion region of the first conductivity type provided in a well region of the second conductivity type near the first surface of the semiconductor substrate, The transfer transistor has a channel region of the second conductivity type between the photoelectric conversion unit and the charge accumulation unit. Solid-state imaging element.

2. The gate electrode has a flat plate shape. The solid-state imaging device according to claim 1 .

3. The display further includes a third substrate that faces the first substrate with the second substrate therebetween and on which the drive circuit is provided. The solid-state imaging device according to claim 1 .

4. A semiconductor substrate having a first surface which is a light incident side and a second surface opposite to the first surface; A photoelectric conversion unit; A transfer transistor electrically connected to the photoelectric conversion unit; a charge accumulation section to which the signal charge generated in the photoelectric conversion section is transferred from the transfer transistor; an output transistor electrically connected to the transfer transistor, the output transistor including a channel region of a first conductivity type, a gate electrode having a plurality of surfaces covering the channel region of the first conductivity type, and a source / drain region of the first conductivity type adjacent to the channel region of the first conductivity type; a drive circuit for outputting a signal charge generated by the photoelectric conversion unit via the transfer transistor and the output transistor; the semiconductor substrate has a well region of a second conductivity type different from the first conductivity type; the photoelectric conversion portion is formed by being embedded in the second conductivity type well region, the charge accumulation portion is configured by an impurity diffusion region of the first conductivity type provided in a well region of the second conductivity type near the first surface of the semiconductor substrate, The transfer transistor has a channel region of the second conductivity type between the photoelectric conversion unit and the charge accumulation unit. Solid-state imaging element.

5. a first substrate including the photoelectric conversion unit, the transfer transistor electrically connected to the photoelectric conversion unit, and a charge accumulation unit to which a signal charge generated in the photoelectric conversion unit is transferred from the transfer transistor; a second substrate provided opposite to the first substrate and having the output transistor; a third substrate that faces the first substrate with the second substrate therebetween and on which the drive circuit is provided; The solid-state imaging device according to claim 4 .

6. Further, a gate insulating film is provided between the gate electrode and the first conductive type channel region. The solid-state imaging device according to claim 1 .

7. an amplifying transistor that outputs a signal corresponding to the magnitude of the potential of the charge storage section; a reset transistor that resets the potential of the charge storage unit; a selection transistor for controlling an output of the amplification transistor; At least one of the amplifying transistor, the reset transistor, and the selection transistor is the output transistor. The solid-state imaging device according to claim 1 .

8. The semiconductor device further includes a fin in which the first conductive type channel region and the source / drain regions are provided. The solid-state imaging device according to claim 1 .

9. The fin is provided with a plurality of the first conductivity type channel regions and a plurality of source / drain regions that are continuously formed. The solid-state imaging device according to claim 8 .

10. The gate electrode includes a first surface and a second surface opposing each other with the first conductivity type channel region therebetween, and a third surface connecting the first surface and the second surface. The solid-state imaging device according to claim 1 .

11. The gate electrode further includes a fourth surface facing the third surface with the first conductivity type channel region therebetween. The solid-state imaging device according to claim 10.

12. The gate electrode includes polysilicon of a second conductivity type. The solid-state imaging device according to claim 1 .

13. a first substrate having a photoelectric conversion unit, a transfer transistor electrically connected to the photoelectric conversion unit, and a charge accumulation unit to which a signal charge generated in the photoelectric conversion unit is transferred from the transfer transistor; a second substrate provided opposite to the first substrate and having an output transistor including a gate electrode, a channel region of a first conductivity type disposed opposite to the gate electrode, and a source / drain region of the first conductivity type adjacent to the channel region of the first conductivity type; a drive circuit for outputting a signal charge generated by the photoelectric conversion unit via the transfer transistor and the output transistor; the first substrate includes a semiconductor substrate having a first surface serving as a light incident side and a second surface opposed to the first surface; the semiconductor substrate has a well region of a second conductivity type different from the first conductivity type; the photoelectric conversion portion is formed by being embedded in the second conductivity type well region, the charge accumulation portion is configured by an impurity diffusion region of the first conductivity type provided in a well region of the second conductivity type near the first surface of the semiconductor substrate, The transfer transistor has a channel region of the second conductivity type between the photoelectric conversion unit and the charge accumulation unit. An imaging device equipped with a solid-state imaging element.

14. A semiconductor substrate having a first surface which is a light incident side and a second surface opposite to the first surface; A photoelectric conversion unit; A transfer transistor electrically connected to the photoelectric conversion unit; a charge accumulation section to which the signal charge generated in the photoelectric conversion section is transferred from the transfer transistor; an output transistor electrically connected to the transfer transistor, the output transistor including a channel region of a first conductivity type, a gate electrode having a plurality of surfaces covering the channel region of the first conductivity type, and a source / drain region of the first conductivity type adjacent to the channel region of the first conductivity type; a drive circuit for outputting a signal charge generated by the photoelectric conversion unit via the transfer transistor and the output transistor; the semiconductor substrate has a well region of a second conductivity type different from the first conductivity type; the photoelectric conversion portion is formed by being embedded in the second conductivity type well region, the charge accumulation portion is configured by an impurity diffusion region of the first conductivity type provided in a well region of the second conductivity type near the first surface of the semiconductor substrate, The transfer transistor has a channel region of the second conductivity type between the photoelectric conversion unit and the charge accumulation unit. An imaging device equipped with a solid-state imaging element.

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