Transistor Package with Improved Die Attach

Abstract

The transistor device structure can include a submount, a transistor device on the carrier submount, and a metallurgical bonding layer between the submount and the transistor die, the metallurgical bonding stack providing mechanical attachment of the transistor die to the submount. The metallurgical bonding stack can include gold, tin, and nickel. The weight percentage of the combined nickel and tin in the metallurgical bonding layer is greater than 50 percent, and the weight percentage of gold in the metallurgical bonding layer is less than 25 percent.

Description

[Technical field]

[0001] This application claims priority to U.S. Patent Application Serial No. 17 / 085,386, filed in the U.S. Patent and Trademark Office on October 30, 2020, the disclosure of which is incorporated herein by reference.

[0002] This disclosure relates to microelectronic devices, and more particularly to high power, high frequency transistors and related device packages. [Background technology]

[0003] Electrical circuits that require high power handling capabilities and / or operate at high frequencies such as R-band (0.5-1 GHz), S-band (3 GHz) and X-band (10 GHz) have become increasingly prevalent in recent years. In particular, there will be high demand for radio frequency (RF) transistor amplifiers used to amplify RF signals at high frequencies (including microwave). These RF transistor amplifiers may need to handle high output power levels while exhibiting high reliability, good linearity. Even beyond the RF domain, other types of transistor devices may need to handle high output power levels, including direct current (DC) biased transistor amplifiers and high power transistor switches.

[0004] Transistor devices may be implemented in silicon or using wide bandgap semiconductor materials (i.e., having a bandgap greater than 1.40 eV), such as silicon carbide ("SiC") and III-nitride materials. As used herein, the term "III-nitrides" refers to semiconductor compounds formed between nitrogen and elements in Group III of the periodic table, usually aluminum (Al), gallium (Ga), and / or indium (In). The term also refers to ternary and quaternary compounds, such as AlGaN and AlInGaN. These compounds have an empirical formula in which one mole of nitrogen is combined with one mole of total Group III elements.

[0005] Silicon-based transistor devices are typically implemented using laterally diffused metal oxide semiconductor ("LDMOS") transistors. Silicon LDMOS transistor devices can exhibit high levels of linearity and can be relatively inexpensive to manufacture. III-nitride based transistor devices are typically implemented using high electron mobility transistors ("HEMTs") and are primarily used in applications requiring high power and / or high frequency operation where LDMOS transistor devices may have inherent performance limitations.

[0006] A transistor amplifier may include one or more amplification stages, with each stage typically implemented as a transistor amplifier. To increase output power and current handling capabilities, transistor amplifiers are typically implemented in a "unit cell" configuration, where many individual "unit cell" transistors are placed electrically in parallel. A transistor amplifier may be implemented as a single integrated circuit chip or "die," or may include multiple dies. A die or chip may refer to a small block of semiconductor material or other substrate on which electronic circuitry is fabricated. When multiple transistor amplifier dies are used, the dies may be connected in series and / or in parallel.

[0007] Transistor amplifiers often include matching circuits, such as impedance matching circuits designed to improve the impedance match between the active transistor die (e.g., metal-oxide semiconductor field effect transistors (MOSFETs), HEMTs, LDMOSs, etc.) and the transmission lines connected to it for signals at the fundamental operating frequency, and harmonic termination circuits designed to at least partially terminate harmonics that may be generated during device operation, such as second and third harmonics. Harmonic termination also affects the generation of intermodulation distortion products.

[0008] The transistor amplifier die(s) and impedance matching and / or harmonic termination circuitry may be encapsulated in an integrated circuit device package. Integrated circuit packaging may refer to the encapsulation of one or more dies in a supporting case or package that protects the die from physical damage and / or corrosion and supports electrical contacts for connection to external circuitry. The input and output impedance matching circuitry in an integrated circuit device package typically includes an LC network that provides at least a portion of an impedance matching circuit configured to match the impedance of the active transistor die to a fixed value. The package typically includes an attachment surface or "submount" to which the die is attached, and an electrically insulating encapsulant material, such as plastic or ceramic, that seals and protects the die from moisture and dust particles. Conductive leads (also referred to herein as package leads) may extend from the package and are used to electrically connect the transistor amplifier to external circuit elements, such as input and output transmission lines and bias voltage sources.

[0009] As mentioned above, III-nitride based transistor amplifiers are often used in high power and / or high frequency applications. Typically, high levels of heat are generated within the III-nitride based amplifier die(s) during operation. If the transistor amplifier die(s) are too hot, the performance (e.g., output power, efficiency, linearity, gain, etc.) of the transistor amplifier may be degraded and / or the transistor amplifier die(s) may be damaged. Therefore, III-nitride based transistor amplifiers are typically mounted within packages that may be optimized for heat removal.

[0010] In some package designs, the package submount includes a thermally conductive substrate, sometimes referred to as a "heat slug" or "heat sink." The package-level heat slug is designed to both transfer heat away from the integrated circuit and to an external heat sink. Typically, the heat slug is formed from a thermally conductive material (e.g., metal). In some package configurations, the heat slug also serves as an electrical terminal that provides a reference potential (e.g., ground) for the attached die. For example, the submount can be a CPC (copper, copper-molybdenum, copper laminate) or a copper flange, which provides both the attachment surface for the die and the heat slug.

[0011] One semiconductor package design is the "open air cavity" or "open cavity" package, where a (typically ceramic) lid is placed over a metal heat slug. The ceramic lid seals the open air cavity which contains the transistor amplifier die and / or other integrated circuits and associated electrical connections. The package leads of the open air cavity ceramic package may be attached to the heat slug using a high temperature brazing process.

[0012] Another semiconductor package design is a molded design (or "overmolded package") in which plastic or other non-conductive material is molded (e.g., by injection molding or transfer molding) directly onto the heat slug to form a solid structure that directly contacts and encapsulates the transistor amplifier die and / or other integrated circuits and associated electrical connections as well as the heat slug. The package leads of the molded plastic package may be attached to the heat slug using a lead frame, where an outer frame containing the package leads is placed around the heat slug. After die attach and wire bonding, a plastic encapsulant material is molded around the heat slug and package leads. [Prior art documents] [Patent documents]

[0013] [Patent Document 1] U.S. Patent Application Serial No. 17 / 018,762 [Patent Document 2] U.S. Patent Application Serial No. 17 / 018,721 [Patent Document 3] U.S. Reissue Patent No. 34,861 [Patent Document 4] U.S. Patent No. 4,946,547 [Patent Document 5] U.S. Patent No. 5,200,022 [Patent Document 6] U.S. Patent No. 6,218,680 [Patent Document 7] U.S. Patent No. 5,210,051 [Patent Document 8] U.S. Patent No. 5,393,993 [Patent Document 9] U.S. Patent No. 5,523,589 [Patent Document 10] U.S. Patent No. 5,192,987 [Patent Document 11] U.S. Patent No. 5,296,395 [Patent Document 12] U.S. Patent No. 6,316,793 [Patent Document 13] U.S. Patent No. 6,548,333 [Patent Document 14] U.S. Patent No. 7,544,963 [Patent Document 15] U.S. Patent No. 7,548,112 [Patent Document 16] U.S. Patent No. 7,592,211 [Patent Document 17] U.S. Patent No. 7,615,774 [Patent Document 18] U.S. Patent No. 7,709,269 [Patent Document 19] U.S. Patent No. 7,030,428 Summary of the Invention [Means for solving the problem]

[0014] According to some embodiments of the present disclosure, a transistor device structure includes a transistor die on a submount and a metallurgical bonding layer between the submount and the transistor die, the metallurgical bonding layer including gold, tin and nickel, the combined weight percentage of nickel and tin in the metallurgical bonding layer being greater than 50 percent and the weight percentage of gold in the metallurgical bonding layer being less than 25 percent.

[0015] In some embodiments, the weight percentage of gold in the metallic bonding layer is less than 10 percent.

[0016] In some embodiments, the weight percentage of gold in the metallic bonding layer is less than 5 percent.

[0017] In some embodiments, the metallurgical bonding layer further comprises a barrier layer between the portion of the metallurgical bonding layer that comprises tin and the transistor die.

[0018] In some embodiments, the barrier layer comprises platinum.

[0019] In some embodiments, the metallurgical bonding layer is between the submount and the transistor die in a first direction, and a longest dimension of the metallurgical bonding layer in a second direction perpendicular to the first direction is greater than 3.5 mm.

[0020] In some embodiments, the transistor device structure further includes a substrate contact layer between the metallurgical bonding layer and the transistor die.

[0021] In some embodiments, the substrate contact layer comprises a gold layer having a thickness between 2 μm and 8 μm.

[0022] In some embodiments, the transistor die includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, and a via through the substrate, the channel layer, and the barrier layer, a first portion of the metallurgical bonding layer is between the substrate and the submount, and a second portion of the metallurgical bonding layer is on a sidewall of the via.

[0023] In some embodiments, the composition of the first portion of the metallic bonding layer differs from the composition of the second portion of the metallic bonding layer.

[0024] In some embodiments, the substrate comprises silicon carbide.

[0025] In some embodiments, the transistor die includes a gate terminal and a drain terminal, and the metallurgical bonding layer electrically connects the gate terminal to the submount.

[0026] In some embodiments, the operating frequency of the transistor device structure is between 500 MHz and 75 GHz.

[0027] In some embodiments, the power output of the transistor device structure is between 50W and 200W.

[0028] According to some embodiments of the present disclosure, a transistor device structure includes a submount, a transistor die on the submount, and a metallurgical bonding layer between the submount and the transistor die in a first direction, the metallurgical bonding layer providing mechanical attachment of the transistor die to the submount, the metallurgical bonding layer having a composition primarily including nickel and tin, and a longest dimension of the metallurgical bonding layer exceeding 3.5 mm in a second direction perpendicular to the first direction.

[0029] In some embodiments, the weight percentage of the combination of nickel and tin in the metallic bond layer is greater than 50 percent.

[0030] In some embodiments, the metallic bonding layer further comprises gold, and the weight percentage of gold in the metallic bonding layer is less than 10 percent.

[0031] In some embodiments, the metallurgical bonding layer further comprises a barrier layer between the tin portion of the metallurgical bonding layer and the transistor die.

[0032] In some embodiments, the barrier layer comprises platinum.

[0033] In some embodiments, the transistor device structure further includes a contact layer between the submount and the metal bonding layer.

[0034] In some embodiments, the contact layer comprises a gold layer having a thickness between 2 μm and 8 μm.

[0035] In some embodiments, the transistor die includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, and a via through the substrate, the channel layer, and the barrier layer, a first portion of the metallurgical bonding layer is between the substrate and the submount, and a second portion of the metallurgical bonding layer is on a sidewall of the via.

[0036] In some embodiments, the composition of the first portion of the metallic bonding layer differs from the composition of the second portion of the metallic bonding layer.

[0037] In some embodiments, the operating frequency of the transistor device structure is between 500 MHz and 75 GHz.

[0038] According to some embodiments of the present disclosure, a transistor device structure includes a transistor die having a semiconductor structure including a semiconductor substrate, a barrier layer, and a channel layer, a source contact on the semiconductor substrate, a via through the semiconductor substrate, the barrier layer, and the channel layer to be electrically connected to the source contact, a metallurgical bonding layer including a first portion within the via, and a submount on the metallurgical bonding layer, wherein the metallurgical bonding layer includes an alloy of tin and nickel.

[0039] In some embodiments, the metallic bonding layer further comprises gold, and the weight percentage of the combination of nickel and tin in the metallic bonding layer is greater than about 50 percent, and the weight percentage of gold in the metallic bonding layer is less than about 25 percent.

[0040] In some embodiments, the metallurgical bonding layer further includes a second portion that is outside the via and between the semiconductor substrate and the submount.

[0041] In some embodiments, the composition of the first portion of the metallic bonding layer differs from the composition of the second portion of the metallic bonding layer.

[0042] In some embodiments, the first portion of the metallurgical bonding layer is disposed at the same level as a portion of the channel layer.

[0043] In some embodiments, the metallurgical bonding layer further comprises a barrier layer between the tin portion of the metallurgical bonding layer and the transistor die.

[0044] In some embodiments, the barrier layer comprises platinum.

[0045] In some embodiments, a metallurgy bonding layer is spaced from the transistor die in a first direction, and a longest dimension of the metallurgy bonding layer in a second direction perpendicular to the first direction is greater than 3.5 mm.

[0046] In some embodiments, the operating frequency of the transistor device structure is between 500 MHz and 75 GHz.

[0047] According to some embodiments of the present disclosure, a method of forming a transistor device structure includes providing a submount, forming a metallurgical bonding stack on a transistor die, placing the transistor die with the metallurgical bonding stack on the submount such that the metallurgical bonding stack is between the transistor die and the submount, and applying heat and / or pressure to the transistor die and the metallurgical bonding stack to provide mechanical attachment of the transistor die to the submount. The metallurgical bonding stack includes a tin layer adjacent to a nickel layer.

[0048] In some embodiments, the metallurgical bond laminate further comprises gold, and the weight percentage of the combination of nickel and tin in the metallurgical bond laminate is greater than 50 percent, and the weight percentage of gold in the metallurgical bond laminate is less than 25 percent.

[0049] In some embodiments, the weight percentage of gold in the metallurgical bond stack is less than 10 percent.

[0050] In some embodiments, the metallurgical bonding stack further comprises a barrier layer between the tin layer of the metallurgical bonding stack and the transistor die.

[0051] In some embodiments, the barrier layer comprises platinum.

[0052] In some embodiments, the metallurgical bonding stack is laminated to the transistor die in a first direction.

[0053] In some embodiments, the longest dimension of the metallurgical bond laminate in a second direction perpendicular to the first direction is greater than 3.5 mm.

[0054] In some embodiments, the method further includes forming a substrate contact layer on the transistor die, wherein a metallurgical bonding stack is formed on the substrate contact layer.

[0055] In some embodiments, the substrate contact layer comprises a gold layer having a thickness between 2 μm and 8 μm.

[0056] In some embodiments, the transistor die includes a substrate, a channel layer on the substrate, and a barrier layer on the channel layer, and the method further includes forming a via through the substrate, the channel layer, and the barrier layer, and forming a metallurgical bonding stack on the transistor die includes forming a first portion of the metallurgical bonding stack on a bottom surface of the substrate and a second portion of the metallurgical bonding stack on a sidewall of the via.

[0057] In some embodiments, the substrate comprises silicon carbide.

[0058] In some embodiments, the method further includes patterning the metallurgical bond stack into a plurality of portions.

[0059] In some embodiments, the method further includes placing the transistor die on the submount with the metallurgical bonding stack such that multiple portions of the metallurgical bonding stack are between multiple terminals of the transistor die and the submount, respectively.

[0060] In some embodiments, the operating frequency of the transistor device structure is between 500 MHz and 75 GHz.

[0061] In some embodiments, the power output of the transistor device structure is between 50W and 200W.

[0062] Other devices, apparatus, and / or methods according to some embodiments will become apparent to one of ordinary skill in the art upon review of the following figures and detailed description. Any and all combinations of the above embodiments, as well as all such additional embodiments, are intended to be included within this specification, be within the scope of the invention, and be protected by the accompanying claims. [Brief description of the drawings]

[0063] [Figure 1A] 1 is a schematic side view of a packaged III-nitride based transistor amplifier according to various embodiments of the present disclosure. [Figure 1B] 1B is a schematic horizontal cross-sectional view of a transistor amplifier die according to various embodiments of the present disclosure taken along line BB' of FIG. 1A. [Figure 1C] FIG. 1C is a schematic cross-sectional view of a transistor amplifier die unit cell according to various embodiments of the present disclosure, taken along line CC' of FIG. [Figure 1D] 1D is a schematic cross-sectional view showing a detail of area D in FIG. 1C. [Figure 1E] 1 is a schematic side view of another packaged III-nitride based transistor amplifier according to various embodiments of the present disclosure. [Figure 2A] 1 is a schematic cross-sectional view of an exemplary metallurgical bond stack according to various embodiments of the present disclosure. [Figure 2B] 1 is a schematic cross-sectional view of an exemplary metallurgical bond stack according to various embodiments of the present disclosure. [Figure 3A] 1 is a schematic cross-sectional view of a unit cell of a vertical MOSFET device according to various embodiments of the present disclosure. [Figure 3B] 3B is a schematic cross-sectional view showing a detail of area E of FIG. 3A. [Figure 4A] 1 is a schematic cross-sectional view of a transistor amplifier die unit cell according to various embodiments of the present disclosure. [Figure 4B] 4B is a schematic cross-sectional view showing a detail of area F in FIG. 4A. [Figure 5A] 1 is a schematic cross-sectional view of an exemplary metallurgical bond stack according to various embodiments of the present disclosure. [Figure 5B] 1 is a schematic cross-sectional view of an exemplary metallurgical bond stack according to various embodiments of the present disclosure. [Figure 6A] 1 is a schematic cross-sectional view of a unit cell of a HEMT device in a flip-chip configuration, according to various embodiments of the present disclosure. [Figure 6B] 6B is a schematic cross-sectional view showing a detail of area G in FIG. 6A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0064] Previous methods of bonding a transistor die to a submount include using various metal layers in a manner either the same as or similar to soldering or brazing. In many situations, a titanium (Ti) layer is formed or deposited on each of the surfaces to be bonded, and then further layers of bonding metal are added to form a bonded metal structure on the first and / or second substrates (sometimes called donor and acceptor substrates) having the respective surfaces to be bonded.

[0065] Gold (Au) has been the predominant element in these bond metal layers for many reasons. Gold is also attractive for its corrosion resistance, i.e., to resist oxidation and other chemical reactions and to avoid undesirable reactions with its surroundings. Gold's ability to form alloys or compounds with relatively low melting points (relative to pure gold) makes it desirable for soldering.

[0066] Nevertheless, the gold consumption is significant, even if only a very small amount is used for each semiconductor device, which is several million times that of each transistor device. As used herein, "transistor device" includes both power transistor switching devices and transistor amplifier devices, including transistor amplifier devices operating in the RF domain. Another factor is that soldering the wafers together requires some application of heat. Thus, the soldering step used to join the transistor die to the submount heats the transistor die to some degree. As will be well understood by those skilled in the art, as the temperature of the semiconductor epitaxial layer increases, the likelihood of defects occurring in the epitaxial layer increases. Typically, gold-tin based soldering (bonding, brazing) systems require temperatures in excess of about 300° C. Although epitaxial layers of, for example, III-nitride materials, can theoretically withstand such temperatures, in practice, these temperatures significantly increase the likelihood that the bonding step will produce noticeable defects.

[0067] As yet a further factor, once individual transistor dies are separated from the wafer and mounted within a package (e.g., package 170 in FIG. 1A), they typically undergo other soldering and / or bonding operations. Thus, the temperature at which these further soldering and / or bonding operations can be performed is limited by the temperature that the die-submount bond can withstand without melting. Stated differently, the thermal properties of the die-submount bond metallurgy can adversely limit the types of soldering and / or bonding operations that can be performed.

[0068] Similarly, as discussed above, transistor devices are often used in high power and / or high frequency applications that generate high levels of heat during operation. For example, GaN-based amplifiers may operate at junction temperatures in the range of 250-275°C. In some embodiments, power transistor dies may have output powers in excess of 50 W (e.g., between 50 W and 200 W), which may generate similar temperatures. This temperature may approach the remelting temperature of some bonding systems, and therefore the die-submount bond may be adversely affected by the use of certain types of metals, such as AuSn, as a metallurgical bonding system.

[0069] In some cases, alternatives to the use of gold-tin have been developed. As an example, transistor devices may use sintered silver as a die attach material to avoid some of the disadvantages of gold-tin. Sintered silver is a porous silver material that bonds the semiconductor die to the substrate as part of the packaging process. However, the properties of the sintered silver material may limit it to being used primarily during package level processing instead of wafer level processing. This may increase the complexity of its use during the manufacturing process of transistor devices.

[0070] Transistor devices are often subjected to thermal shock and thermal cycling tests to simulate their ability to withstand operating environments that they may encounter. In thermal shock tests, the transistor device is subjected to rapid, large temperature changes. In thermal cycling tests, the transistor device is subjected to repeated cycles of high and low temperatures. These tests have shown that the vulnerability of a particular transistor device (e.g., a transistor amplifier and / or a transistor switch) may depend on the longest dimension (e.g., diagonal, length, or width) of the transistor device. Transistor devices may be larger than other devices, such as light emitting devices, and may have a longest dimension of more than 3.5 mm. Thus, the large size of the transistor device, coupled with the high temperatures of the transistor device during operation, may make the transistor device particularly vulnerable to the types of materials used in the metallurgical bonding system.

[0071] The examples herein describe metallurgical bond stacks with a metallurgical bond system that is primarily nickel and tin. The use of nickel and tin provided as a metallurgical bond stack allows for the creation of nickel-tin alloys at relatively low temperatures that have higher remelting temperatures than traditional metallurgical bond systems used in previous transistor devices. Reducing the Au content of the bond stack can reduce the sensitivity of the die-submount bond from higher operating temperatures while also reducing the overall cost of the stack.

[0072] 1A and 1B show a packaged III-nitride based transistor device. In particular, FIG. 1A is a schematic side view of a packaged III-nitride based transistor device 100, and FIG. 1B is a schematic top cross-sectional view of a transistor die 110 included in the packaged III-nitride based transistor device 100, taken along line B-B' of FIG. 1A. FIG. 1C is a schematic cross-sectional view of a unit cell 116 of the transistor die 110, taken along line C-C' of FIG. 1B. FIG. 1D is a schematic cross-sectional view showing a detail of area D of FIG. 1C. In some embodiments, the packaged III-nitride based transistor device 100 is a transistor amplifier, and in some embodiments, may be configured to operate in the RF domain. However, the present disclosure is not limited thereto. It will be understood that embodiments of the present invention may be used with other transistor devices, including power switching devices. It will be appreciated that Figures 1A-1D (and some other figures) are highly simplified diagrams, and that actual transistor devices may include many more unit cells and various circuits and elements not shown in the simplified diagrams herein. More generally, the diagrams herein are intended to represent structures for identification and explanation purposes, and are not intended to represent structures to physical scale.

[0073] As shown in FIG. 1A, III-nitride based transistor device 100 includes a transistor die 110 mounted within a package 170, also referred to herein as a packaged transistor device. In some embodiments, transistor device 100 may be an RF transistor amplifier device 100 configured to operate with an input signal in the RF range, although embodiments of the present disclosure are not limited thereto. Package 170 includes a submount (also referred to herein as a base or flange) 176 having one or more electrically conductive package leads thereon, such as one or more input (e.g., gate) leads 172 and one or more output (e.g., drain) leads 174. Transistor die 110 is attached to a top surface of submount 176. Submount 176 may be or include an electrically conductive attachment surface, such as a metal substrate (or "slug") that acts as a thermally conductive heat sink. In some embodiments, the submount 176 additionally or alternatively includes a redistribution layer (RDL) stack including a conductive layer fabricated using semiconductor processing techniques, a printed circuit board with metal traces, and / or a ceramic substrate including conductive vias and / or pads. In some embodiments, a metal lead frame may be formed and then processed to provide the metal submount 176 and / or the package leads (e.g., gate and drain leads) 172 and 174. The transistor device 100 also includes a housing 178 (e.g., a plastic overmold) that at least partially surrounds the transistor die 110, the package leads 172, 174, and the metal submount 176.

[0074] The transistor die 110 has a top side 112 and a bottom side 114. The transistor die 110 includes a bottom side (also referred to as the "back" side) metallization structure 120, a semiconductor layer structure 130, and a top side metallization structure 140, which are stacked in sequence. The back side metallization structure 120 includes a metal source terminal 126. The transistor device 100 may be a HEMT-based transistor device, in which case the semiconductor layer structure 130 may include at least a channel layer 324 and a barrier layer 326, which are typically formed on a substrate 322 (see FIG. 1C, discussed in detail below). The substrate 322 may be a semiconductor or insulating growth substrate (such as a SiC or sapphire substrate). The growth substrate may be considered to be part of the semiconductor layer structure 130 even if it is formed from a non-semiconductor material. As used herein, the term "semiconductor layer structure" refers to a structure that includes one or more semiconductor layers, e.g., a semiconductor substrate and / or a semiconductor epitaxial layer. The upper metallization structure 140 includes, among other things, a metal gate terminal 142 and a metal drain terminal 144 .

[0075] An input matching circuit 190 and / or an output matching circuit 192 may also be mounted within the package 170. The matching circuits 190, 192 may be impedance matching circuits that match the impedance of a fundamental component of a signal input to or output from the transistor device 100 to an impedance at the input or output, respectively, of the transistor die 110, and / or harmonic termination circuits configured to short to ground harmonics of the fundamental frequency of the signal that may be present at the input or output of the transistor die 110, such as second or third harmonics. As shown diagrammatically in FIG. 1A, the input and output matching circuits 190, 192 may be mounted to the metal submount 176. The gate lead 172 may be connected to the input matching circuit 190 by one or more first bond wires 182, and the input matching circuit 190 may be connected to the gate terminal 142 of the transistor die 110 by one or more second bond wires 183. Similarly, the drain lead 174 may be connected to an output matching circuit 192 by one or more fourth bond wires 185, and the output matching circuit 192 may be connected to the drain terminal 144 of the transistor die 110 by one or more third bond wires 184. The source terminal 126 of the transistor die 110 may be directly attached to the metal submount 176. The metal submount 176 may provide an electrical connection to the source terminal 126 and may also serve as a heat dissipation structure. The first bond wire 182 through the fourth bond wire 185 may form part of the input matching circuit and / or the output matching circuit. The gate lead 172 and the drain lead 174 may extend through the housing 178.

[0076] Although FIG. 1A illustrates a package 170 incorporating a plastic overmold 178, embodiments of the present disclosure are not limited to such a package configuration. FIG. 1E is a schematic side view of another example packaged III-nitride-based transistor device 100', which is similar to the transistor device 100 described above with reference to FIG. 1A. The transistor device 100' differs from the transistor device 100 of FIG. 1A in that it includes a different package 170'. The package 170' includes a metal submount 176 (which acts as a metal heat sink and can be implemented as a metal slug), as well as gate leads 172' and drain leads 174'. In some embodiments, a metal lead frame may be formed, which may then be processed to provide the metal submount 176, and / or the gate leads 172' and drain leads 174'. The transistor device 100' also includes a housing 178' that at least partially encloses the transistor die 110, the leads 172', 174', and the metal submount 176. The housing 178' may include a ceramic housing in some embodiments, and the gate lead 172' and the drain lead 174' may extend through the housing 178'. In some embodiments, the housing 178' may include plastic and / or a printed circuit board. The housing 178' may include multiple pieces, such as a frame that forms a lower portion of the sidewalls and supports the gate lead 172' and the drain lead 174', and a lid that is disposed over the frame. The interior of the device may include an air-filled cavity. The sidewalls and lid of the housing 178' of FIG. 1E take the place of the plastic overmold 178 included in the transistor device 100 shown in FIG. 1A.

[0077] 1A and 1E of the transistor die 110, input matching circuit 190, and output matching circuit 192, including the bond wire arrangements, are merely illustrative and are not intended to limit the present disclosure. Depending on the embodiment, the packaged transistor device 100 may include, for example, a monolithic microwave integrated circuit (MMIC) as the transistor device 110, where the transistor die 110 incorporates multiple discrete devices. If the transistor die 110 is an MMIC implementation, the input matching circuit 190 and / or the output matching circuit 192 may be omitted (as they may instead be implemented within the transistor die 110), and the bond wires 182 and / or 185 may extend directly from the gate lead 172 and the drain lead 174 to the gate terminal 142 and the drain terminal 144. In some embodiments, the packaged transistor device 100, 100' may include multiple transistor dies connected in series to form a multi-stage transistor device, and / or may include multiple transistor dies arranged in multiple amplifier paths (e.g., in parallel) to form a transistor device having multiple transistor dies and multiple paths, such as in a dual path driver amplifier and / or Doherty amplifier configuration.

[0078] In some embodiments, input matching circuit 190 and / or output matching circuit 192 may be omitted. In some embodiments, bond wires 182-185 may be omitted. For example, in some embodiments, input matching circuit 190 and / or output matching circuit 192 may be incorporated using interconnect circuits and / or circuit modules such as those described in U.S. patent application Ser. No. 17 / 018,762, entitled “RF AMPLIFIER DEVICES AND METHODS OF MANUFACTURING,” filed Sep. 11, 2020, and U.S. patent application Ser. No. 17 / 018,721, entitled “PACKAGING FOR RF TRANSISTOR AMPLIFIERS,” filed Sep. 11, 2020, the contents of which are incorporated herein by reference in their entireties.

[0079] 1B is a schematic top cross-sectional view of transistor die 110 taken through a portion of upper metallization structure 140. Dielectric layers that insulate the various conductive elements of upper metallization structure 140 from one another are not shown in FIG. 1B for simplicity of drawing.

[0080] As shown in FIG. 1B, the transistor die 110 is illustratively shown as a III-nitride based HEMT transistor device having a plurality of unit cell transistors 116, each of which includes a gate finger 152, a drain finger 154, and a source finger 156. However, it will be appreciated that the transistor die 110 may be implemented in a different technology, such as, for example, a silicon LDMOS transistor. The gate fingers 152 are electrically connected to a common gate bus 147, and the drain fingers 154 are electrically connected to a common drain bus 148. The gate bus 147 is electrically connected (e.g., via a deposited conductive material such as a metal) to a gate terminal 142 (see FIG. 1A), which is implemented as a gate bond pad, and the drain bus 148 is electrically connected (e.g., via a deposited conductive material such as a metal) to a drain terminal 144 (see FIG. 1A), which is implemented as a drain bond pad. The source fingers 156 are electrically connected to the source terminal 126 through a plurality of conductive source vias 166 that extend through the semiconductor layer structure 130. The conductive source vias 166 may be metal plated vias that extend completely through the semiconductor layer structure 130. The number of gate fingers 152, drain fingers 154, and source fingers 156 shown in FIG. 1B is merely illustrative, and the total number of gate fingers 152, drain fingers 154, and source fingers 156 present in the transistor die 110 may be more or less than the number shown in FIG. 1B.

[0081] Depending on the number of unit cell transistors 116 incorporated into the transistor die 110, the transistor die 110 may have a longest dimension W. In FIG. 1B, the longest dimension W is shown as being diagonal (e.g., from a first lower left corner to a second upper right corner in a plan view), although the disclosure is not so limited. In some embodiments, the longest dimension W of the transistor die 110 may be greater than 3.5 mm. In some embodiments, the longest dimension W of the transistor die may be greater than 5 mm. In some embodiments, the longest dimension W of the transistor device may be between 4 mm and 10 mm. Because the longest dimension of the transistor die 110 may be larger than the longest dimensions of other types of devices, the material used to bond the transistor die 110 to the submount 176 may be particularly vulnerable to rapid temperature changes, such as those present in thermal shock / thermal cycling operations.

[0082] Referring to FIG. 1C, a semiconductor layer structure 130, such as a semiconductor structure for a III-nitride semiconductor HEMT, may be formed on a substrate 322, such as a silicon carbide SiC substrate or a sapphire substrate. The substrate 322 may be a semi-insulating silicon carbide substrate, which may be, for example, silicon carbide (SiC) of 4H polytype. Other silicon carbide candidate polytypes may include 3C, 6H, and 15R polytypes. The substrate may be a High Purity Semi-Insulating (HPSI) substrate available from Cree, Inc. The term "semi-insulating" is used descriptively herein, not in an absolute sense.

[0083] In some embodiments of the present invention, the silicon carbide bulk crystal of the substrate 322 has a crystallinity of approximately 1×10 5It may have a resistivity of ohm-cm or greater. Exemplary SiC substrates that may be used in some embodiments of the present invention are manufactured, for example, by Cree, Inc. of Durham, North Carolina, the assignee of the present invention, and methods for manufacturing such substrates are described, for example, in U.S. Reissue Patent No. 34,861, U.S. Pat. No. 4,946,547, U.S. Pat. No. 5,200,022, and U.S. Pat. No. 6,218,680, the disclosures of which are incorporated herein by reference in their entireties. Although silicon carbide may be used as the substrate material, embodiments of the present application may use any suitable substrate, such as sapphire (Al2O3), aluminum nitride (AIN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), silicon (Si), GaAs, LGO, zinc oxide (ZnO), LAO, indium phosphide (InP), and the like. The substrate 322 may be a silicon carbide wafer, and the transistor die 110 may be formed, at least in part, via wafer level processing, and the wafer may then be diced to provide a plurality of transistor dies 110.

[0084] Substrate 322 may have a bottom surface 322A and a top surface 322B. In some embodiments, substrate 322 of transistor die 110 may be a thin substrate 322. In some embodiments, a thickness (e.g., in the vertical Z direction in FIG. 1C ) of substrate 322 may be 150 μm or less. In some embodiments, a thickness of substrate 322 may be 100 μm or less. In some embodiments, a thickness of substrate 322 may be 75 μm or less. In some embodiments, a thickness of substrate 322 may be 50 μm or less.

[0085] A channel layer 324 is formed on the top surface 322B of the substrate 322 (or on optional layers described further herein), and a barrier layer 326 is formed on the top surface of the channel layer 324. The channel layer 324 and the barrier layer 326 may each be formed by epitaxial growth in some embodiments. Techniques for epitaxial growth of III-nitrides are described, for example, in U.S. Pat. Nos. 5,210,051, 5,393,993, and 5,523,589, the disclosures of which are also incorporated by reference herein in their entireties. The channel layer 324 may have a bandgap smaller than that of the barrier layer 326, and the channel layer 324 may also have a higher electron affinity than the barrier layer 326. The channel layer 324 and the barrier layer 326 may include III-nitride based materials.

[0086] In some embodiments, the channel layer 324 is Al, provided that the energy of the conduction band edge of the channel layer 324 is less than the energy of the conduction band edge of the barrier layer 326 at the interface between the channel layer 324 and the barrier layer 326. x Ga 1-x N, 0≦x<1. In a particular embodiment of the invention, x=0, indicating that the channel layer 324 is GaN. The channel layer 324 may also be other III-nitrides, such as InGaN, AlGaN, etc. The channel layer 324 may be undoped ("unintentionally doped") or may be grown to a thickness of greater than about 0.002 μm. The channel layer 324 may also be a multi-layer structure, such as a superlattice or a combination of GaN, AlGaN, etc. The channel layer 324 may be compressively strained in some embodiments.

[0087] In some embodiments, the barrier layer 326 is AlN, AlInN, AlGaN, or AlInGaN, or a combination of these layers. The barrier layer 326 may include a single layer or may be a multilayer structure. In certain embodiments of the present invention, when the barrier layer 326 is embedded under the ohmic contact metal, the barrier layer 326 can be thick enough and have a high enough aluminum (Al) composition and doping to induce a significant carrier concentration at the interface between the channel layer 324 and the barrier layer 326 due to the polarization effect. The barrier layer 326 can be, for example, from about 0.1 nm to about 30 nm thick, but not so thick as to cause cracks or significant defect formation inside. A barrier layer thickness in the range of 15 - 30 nm is common. In certain embodiments, the barrier layer 326 is not doped or is doped to a concentration of less than about 10 19 cm -3 −1. In some embodiments of the present invention, the barrier layer 326 is Al x Ga 1-x N with 0 < x < 1. In certain embodiments, the aluminum concentration is about 25%. However, in other embodiments of the present invention, the barrier layer 326 includes AlGaN having an aluminum concentration between about 5% and less than about 100%. In certain embodiments of the present invention, the aluminum concentration is greater than about 10%. The channel layer 324 and / or the barrier layer 326 can be deposited, for example, by metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE). The 2DEG layer is induced in the channel layer 324 at the junction between the channel layer 324 and the barrier layer 326. The 2DEG layer serves as a highly conductive layer that enables conduction between the source region and the drain region of the device, which are under the source finger 156 and the drain finger 154, respectively. The channel layer 324 and the barrier layer 326 form part of the semiconductor layer structure 130.

[0088] Although the semiconductor layer structure 130 is shown with the channel layer 324 and the barrier layer 326 for illustrative purposes, the semiconductor layer structure 130 may include additional layers / structures / elements, such as a buffer layer and / or nucleation layer(s) between the channel layer 324 and the substrate 322, and / or a cap layer on the barrier layer 326. HEMT structures including substrates, channel layers, barrier layers, and other layers are illustratively described in U.S. Pat. Nos. 5,192,987, 5,296,395, 6,316,793, 6,548,333, 7,544,963, 7,548,112, 7,592,211, 7,615,774, 7,548,112, and 7,709,269, the disclosures of which are incorporated herein by reference in their entireties. For example, an AlN buffer layer may be formed on the top surface 322B of the substrate 322 to effect a suitable crystal structure transition between the substrate 322 and the remainder of the semiconductor layer structure 130. Additionally, a strained balanced transition layer(s) may also and / or alternatively be provided as described, for example, in commonly assigned U.S. Patent No. 7,030,428, the disclosure of which is incorporated herein by reference as if fully set forth herein. The optional buffer / nucleation / transition layers may be deposited by MOCVD, MBE, and / or HVPE.

[0089] The source fingers 156 may be coupled to a reference signal, such as a ground voltage. The coupling to the reference signal may be provided by a via 166 extending from the lower surface 322A of the substrate 322 through the substrate 322 to the upper surface 326A of the barrier layer. The via 166 may expose a bottom surface of the source fingers 156, although the disclosure is not limited thereto. A back metal layer 136 may be formed on the lower surface 322A of the substrate 322 and on a sidewall of the via 166. The back metal layer 136 may be electrically connected to the source fingers 156.

[0090] 1A and 1D , metal submount 176 can act as a heat sink to dissipate heat generated within transistor die 110. The heat is primarily generated within the top portion of transistor die 110, where a relatively high current density is generated, for example, within the channel region of unit cell transistor 116. This heat can be transferred to metal submount 176 (e.g., via semiconductor layer structure 130).

[0091] The back metal layer 136 may be connected to a submount contact layer 146 on the submount 176. In some embodiments, the back metal layer 136 and the submount contact layer 146 may form some portion of the source terminal 126. The back metal layer 136 may include a substrate contact layer 134 and a metallurgical bonding layer 135. The metallurgical bonding layer 135 may be used to form a bond between the substrate contact layer 134 and the submount contact layer 146. In some embodiments, the bond between the substrate contact layer 134 and the submount contact layer 146 may be thermally and / or electrically conductive. In some embodiments, the substrate contact layer 134 and / or the submount contact layer 146 may be optional and may not be present.

[0092] In some embodiments, substrate contact layer 134 may include Ti, TiW, and / or Au, although embodiments of the present disclosure are not limited thereto. In some embodiments, substrate contact layer 134 may include materials other than Ti, TiW, and / or Au, or may include materials in addition thereto. In some embodiments, substrate contact layer 134 may include a Ti layer and / or a TiW layer that are each 3000-6000 Å thick. In some embodiments, a layer of Au (e.g., between 2 μm and 8 μm) may be present on the Ti layer and / or the TiW layer in substrate contact layer 134. In some embodiments, submount contact layer 146 may be formed similarly to substrate contact layer 134 (e.g., may include a 2 μm-8 μm Au layer), although embodiments of the present disclosure are not limited thereto. In some embodiments, the Au layer may be absent or may have a different thickness than described herein. In some embodiments, substrate contact layer 134 and / or submount contact layer 146 may include more or fewer layers than those described, may include layers of different materials or material compositions, the layers may be in a different order than those described, and / or may have different thicknesses than those described without departing from the scope of the invention.

[0093] 1D , metal bonding layer 135 may be formed between substrate contact layer 134 and submount contact layer 146. In some embodiments, metal bonding layer 135 may be in some portions of substrate contact layer 134 that are in via 166. Thus, some portions of metal bonding layer 135 may be at the same height and / or level as some portions of substrate 322, channel layer 324, and / or barrier layer 326 above submount 176.

[0094] Metallic bonding layer 135 is primarily comprised of nickel (Ni) and tin (Sn) by weight. In particular, metallic bonding layer 135 includes greater than 50 weight percent nickel and tin, in some embodiments greater than 75 weight percent nickel and tin, and in some embodiments greater than 85 weight percent nickel and tin. In some embodiments, metallic bonding layer 135 can include a nickel-tin alloy.

[0095] The metal bonding layer 135 provides a method for bonding semiconductor wafers together. In this embodiment, the method for creating the metal bonding layer 135 includes a step of heating a multi-layer metal structure between two semiconductor wafers. The layers include adjacent first and second metal layers (e.g., Sn and Ni), where the first metal layer (Sn) has a lower melting point than the second metal layer (Ni) (e.g., melting point of Sn at 232° C. vs. melting point of Ni at 1455° C.). The metal structure has a relative amount of the first metal layer (Sn) that is greater than the amount consumed by reacting with the second layer (Ni) alone during the heating step, but less than the amount that provides an excess of the first metal (Sn) between the two bonded wafers. The heating step is performed at a temperature between the melting point of the first layer (Sn) and the melting point of the second layer (Ni) until the first layer (Sn) is substantially completely reacted with the second layer (Ni) and the surface of the adjacent wafer.

[0096] As used herein, "functional overreaction" refers to an amount of the lower melting metal that adversely affects the functionality of the bond at temperatures approaching or near the lower melting point. Illustratively speaking, with a first tin layer (melting point 232°C) adjacent to a second nickel layer (melting point 1455°C), if a sufficient amount of unreacted tin remains after the heating step, the tin will melt and defeat the purpose of the bond system when the temperature just exceeds 232°C. Thus, the relative amounts of metals are selected such that a small amount or area of ​​the lower melting metal may remain after the reaction, but not enough to melt the bond at such an undesirably low temperature. This compromises the mechanical integrity of the bonded structure. That is, the post-reaction melting point of the metal bond layer 135 is higher than that of the metal layer with the lower melting point. Thus, conventional practice may have avoided the use of Sn without the application of high power and high temperature. However, by using less Sn than would result in a functional excess between two bonded wafers, the risk that excess Sn would result in a structure vulnerable to problems under high temperature operation is reduced.

[0097] Specifically, in a two layer situation, the metal structure is first placed on a first wafer and the higher melting point (second) metal is placed between the first wafer and the lower melting point (first) metal layer, i.e., the lower melting point layer is "exposed." As a result, when the lower melting point metal melts, it will be in contact with both the second metal and the second wafer. Stated another way, in a Ni-Sn example, the lower melting point metal (Sn) may be in place to wet both the higher temperature metal (Ni) and the second substrate.

[0098] The heating step is also typically performed at a temperature below the melting point of any alloy or compound that forms between the metal layers during the heating step of the bonding / attachment process. The phrase "during the heating step" is used to make it clear that the relative amounts and the manner in which these relative amounts react described in the claims are understood to be with respect to the heating step that results in attachment to the submount, and not with respect to any other duration over time that the metals may be in contact.

[0099] Although the nickel-tin system is exemplary and useful for purposes of the present invention (including, among other things, higher throughput and lower cost than the previous gold-tin system), the lower temperature metal may also be selected to be other than tin, with bismuth or combinations thereof as useful alternatives. Similarly, the higher melting point metal, although nickel is presented as an example, may be selected from the group consisting of nickel, cobalt, iron, copper, and combinations thereof.

[0100] Due in part to the functional reaction between the first and second metal layers, the metallurgical bond layer 135 may include an alloy (e.g., a NiSn alloy) of the constituent first and second metal layers. Because the metals form compounds, the heating step may typically be performed at a temperature of about 250° C. or higher. For the metals alone, the upper limit for the heating step is set by the melting point of the alloy formed by the metals in the bond system. Such theoretical upper limits are typically relatively high, i.e., the melting points of Ni-Sn compounds ranging from about 30 to 70 weight percent tin are all above 750° C. Thus, practical upper limits are typically selected based on the thermal properties of the substrate or the thermal properties of the devices on the substrate. These are generally much lower; for example, as described herein, the III-nitride layers are preferably maintained below about 300° C. during other process steps. Because the melting point of the alloy of the two metals is much higher than the melting point of the metal with the lower melting point (e.g., tin), the temperature used to form the metallurgical bond layer 135 can be much lower than the remelting temperature of the resulting alloy. As a result, a metallurgical bond layer 135 formed from an alloy of nickel and tin can be able to withstand higher processing and / or operating temperatures than one or more of the constituent metal layers (e.g., a first metal layer such as Sn). In contrast, a conventional AuSn alloy can remelt at temperatures much lower than that of a NiSn alloy, such as between 280-320° C., depending on the amount of Sn present. Thus, once formed, the metallurgical bond layer 135 can advantageously be processed and / or operated at higher temperatures than conventional devices.

[0101] In some embodiments, metal bonding layer 135 may include first portion 135A and second portion 135B. First portion 135A of metal bonding layer 135 may be positioned between substrate 322 and submount 176 (e.g., in the vertical or Z direction in FIG. 1D ). Second portion 135B of metal bonding layer 135 may be positioned on a sidewall of via 166. In some embodiments, the composition and / or physical properties of first portion 135A of metal bonding layer 135 may differ from the composition and / or physical properties of second portion 135B of metal bonding layer 135. For example, as part of the process of forming metal bonding layer 135, pressure (e.g., downward pressure) may be applied to transistor die 110 to facilitate contact with submount 176. Due to the location of the first portion 135A of the metal bonding layer 135 between the transistor die 110 and the submount 176, the first portion 135A may be thinner (e.g., in the vertical Z direction) than the second portion 135B. Also, due to the contact between the first portion 135A of the metal bonding layer 135 and the contact layer 146 of the submount 176, the composition of the first portion 135A of the metal bonding layer 135 may include components from the contact layer 146 due to intermixing. The second portion 135b of the metal bonding layer 135 may be free of such components. Furthermore, in some embodiments, application of pressure to the first portion 135A may cause the composition of the alloy (e.g., NiSn alloy) of the first and second metal layers in the first portion 135A to be different from the composition of the second portion 135B. For example, different amounts of the first metal layer (e.g., Sn) may react with the second metal layer (e.g., Ni) during application of heat (e.g., via substrate 176) and / or pressure during formation of metallurgical bonding layer 135. For example, in some embodiments, second portion 135B of metallurgical bonding layer 135 may contain a greater amount of unreacted first metal or second metal than first portion 135A.

[0102] Metal bonding layer 135 may be spaced apart from transistor die 110 in a first direction (e.g., a vertical direction in FIG. 1D ). Metal bonding layer 135 may have a longest dimension W of transistor die 110 in a second direction (e.g., a horizontal direction in FIGS. 1B and 1D ) that is perpendicular to the first direction. For example, metal bonding layer 135 may have at least one longest dimension greater than 3.5 mm.

[0103] 1D shows that the metallurgical bonding layer 135 is a single collective layer, it will be understood that the present disclosure is not so limited. In some embodiments, the metallurgical bonding layer 135 can include multiple layers. For example, in some embodiments, the metallurgical bonding layer 135 can include one or more layers of a first metal (e.g., Sn), one or more layers of a second metal (e.g., Ni), one or more layers of an additional metal (e.g., Au, Ti), one or more layers of a bonding barrier metal (e.g., platinum Pt), and / or one or more layers of an alloy of at least two of the aforementioned metals.

[0104] As discussed above, the metallurgical bonding layer 135 may be formed by applying heat and / or pressure to multiple layers of a metallurgical bonding stack. Figures 2A and 2B are schematic cross-sectional views of an exemplary metallurgical bonding stack according to various embodiments of the present disclosure. Figures 2A and 2B depict an area of ​​the transistor die 110 similar to that shown in Figure 1D (e.g., area D of Figure 1C) prior to the formation of the metallurgical bonding layer 135 that bonds the transistor die 110 to the submount 176.

[0105] 2A, a metallurgical bond stack 435 may be formed on the substrate contact layer 134, which may be further formed on the substrate 322 of the transistor die 110. The substrate contact layer 134 may include one or more layers of Ti, TiW, and / or Au, but the invention is not limited thereto. In some embodiments, the substrate contact layer 134 may include or may include materials other than Ti, TiW, and / or Au. In some embodiments, the Ti and / or TiW may be sputtered onto the substrate 322. In some embodiments, each of the Ti and / or TiW layers may be 3000-6000 Å thick. In some embodiments, a layer of Au (e.g., 1000-3000 Å) may be sputtered onto the Ti and / or TiW, and then a thicker layer of Au may be formed by plating (e.g., greater than 2 μm) the sputtered Au to form the substrate contact layer 134. In some embodiments, the Au layer may be absent or may have a different thickness than described herein. In some embodiments, the substrate contact layer 134 may include more or fewer layers than described, may include layers of different materials or material compositions, the layers may be in a different order than described, and / or may have a different thickness than described without departing from the scope of the invention.

[0106] Metallurgical bond stack 435 may include sequentially stacked layers. Metallurgical bond stack 435 may include, for example, from closest to substrate contact layer 134 to furthest from substrate contact layer 134, adhesion layer 402 (e.g., Ti), bond barrier layer 404 (e.g., Pt), nickel layer 406, tin layer 408, and gold layer 410.

[0107] Adhesion layer 402 may be sputtered onto substrate contact layer 134. In some embodiments, adhesion layer 402 may be formed from Ti. In some embodiments, adhesion layer 402 may be formed to have a thickness between 250-750 Å. Adhesion layer 402 may aid in attaching additional layers of metallurgical bonding stack 435 to substrate contact layer 134.

[0108] Bond barrier layer 404 may be sputtered onto adhesion layer 402. In some embodiments, bond barrier layer 404 may be formed from Pt. In some embodiments, bond barrier layer 404 may be formed to have a thickness between 1200-1800 Å. Bond barrier layer 404 may reduce and / or prevent tin from migrating from tin layer 408 through nickel layer 406 to adhesion layer 402. Bond barrier layer 404 may not be present in all embodiments.

[0109] The nickel layer 406 may be sputtered onto the bond barrier layer 404. In some embodiments, the nickel layer 406 may be formed to have a thickness between 4500 and 7500 Å. The tin layer 408 may be sputtered onto the nickel layer 406. In some embodiments, the tin layer 408 may be formed to have a thickness between 1.5 μm and 4.5 μm. Although exemplary values ​​are shown for the thicknesses of the nickel layer 406 and the tin layer 408, the disclosure is not limited to these thicknesses. Generally speaking, the relative thicknesses of the nickel layer 406 and the tin layer 408 may be selected to be sufficient to react with adjacent nickel layers to provide a desired Ni-Sn composition, while still providing additional tin to wet and react with other adjacent metal layers.

[0110] A gold layer 410 may be sputtered onto the tin layer 408. In some embodiments, the gold layer 410 may be formed to have a thickness between 150-450 Å. The gold layer 410 may be used to enhance the bonding connection, but may be provided in much less amount than previously used.

[0111] A metal bonding stack 435 may be formed on the bottom of the substrate 322 and on the sidewalls of the via 166. The transistor die 110 with the metal bonding stack 435 may be disposed on the submount contact layer 146 and the submount 176. In some embodiments, the metal bonding stack 435 may be disposed to have at least a portion in direct contact with the submount contact layer 146 or the submount 176, although the disclosure is not limited thereto. In some embodiments, the submount bonding stack may further be present on the submount contact layer 146 or the submount 176 such that it is between the metal bonding stack 435 and the submount 176. The submount bonding stack, if present, may be similar to the metal bonding stack 435. That is, the submount bonding stack may include Ni and Sn in similar amounts relative to the metal bonding stack 435. However, the disclosure is not limited thereto. In some embodiments, the substrate contact layer 134 and / or the submount contact layer 146 may be optional and may not be present. In some embodiments, substrate contact layer 134 and / or submount contact layer 146 may include more or fewer layers than those described, may include layers of different materials or material compositions, the layers may be in a different order than those described, and / or may have different thicknesses than those described without departing from the scope of the invention.

[0112] Once metallurgical bonding stack 435 is positioned adjacent to submount contact layer 146 or submount 176, heat and / or pressure may be applied to the combination of transistor die 110 and submount 176 to form metallurgical bonding layer 135 (see FIG. 1D).

[0113] 2B is a schematic cross-sectional view of another example metallurgical bond stack 535 according to some embodiments of the present disclosure. For example, the metallurgical bond stack 535 can include selectively deposited layers. The metallurgical bond stack 535 can include, for example, an adhesion layer 402 (e.g., Ti), a bond barrier layer 404 (e.g., Pt), a first nickel layer 506, a first tin layer 508, a first gold layer 510, a second nickel layer 512, a second tin layer 514, and a second gold layer 516, in that order from closest to the substrate contact layer 134 to furthest from the substrate contact layer 134.

[0114] The formation and structure of the substrate contact layer 134, adhesion layer 402, and bonding barrier layer 404 in FIG. 2B may be similar to the substrate contact layer 134, adhesion layer 402, and bonding barrier layer 404 described with respect to FIG. 2A, and therefore, a duplicate description thereof will be omitted.

[0115] The first nickel layer 506 may be sputtered onto the bond barrier layer 404. In some embodiments, the first nickel layer 506 may be formed to have a thickness between 4000-6500 Å. The first tin layer 508 may be sputtered onto the first nickel layer 506. In some embodiments, the first tin layer 508 may be formed to have a thickness between 1.25 μm-2.0 μm. The first gold layer 510 may be sputtered onto the first tin layer 508. In some embodiments, the first gold layer 510 may be formed to have a thickness between 140-180 Å. In some embodiments, the first gold layer 510 may be absent. The second nickel layer 512 may be sputtered onto the first gold layer 510 (if present) or the first tin layer 508. In some embodiments, the second nickel layer 512 may be formed to have a thickness between 6800 and 7750 Å. The second tin layer 514 may be sputtered onto the second nickel layer 512. In some embodiments, the second tin layer 514 may be formed to have a thickness between 1.25 μm and 2.0 μm. The second gold layer 516 may be sputtered onto the second tin layer 514. In some embodiments, the second gold layer 516 may be formed to have a thickness between 300 and 380 Å.

[0116] Although exemplary values ​​are given for the thicknesses of the first nickel layer 506, the first tin layer 508, the second nickel layer 512, and the second tin layer 514, the disclosure is not limited to these thicknesses. Generally speaking, the relative thicknesses of the first nickel layer 506, the first tin layer 508, the second nickel layer 512, and the second tin layer 514 may be selected to be sufficient to react with adjacent nickel layers to provide the desired Ni-Sn composition, while still providing additional tin to wet and react with other adjacent metal layers. The use of multiple nickel and tin layers may increase the amount of nickel and tin that react together, while reducing the amount of unreacted tin remaining in the resulting metal bond layer 135.

[0117] As with metal bonding stack 435 of FIG. 2A, metal bonding stack 535 of FIG. 2B may be formed on the bottom of substrate 322 and on the sidewalls of via 166. Transistor die 110 with metal bonding stack 535 may be disposed on submount contact layer 146 and submount 176. In some embodiments, at least a portion of metal bonding stack 535 may be disposed in direct contact with submount contact layer 146 or submount 176, although the disclosure is not so limited. In some embodiments, a submount bonding stack may also be present on submount contact layer 146 or submount 176 such that it is between metal bonding stack 535 and submount 176. If present, the submount bonding stack may be similar to metal bonding stack 535 and / or metal bonding stack 435 described with respect to FIG. 2A. That is, the submount bonding stack may include Ni and Sn in amounts similar to metal bonding stack 435 or metal bonding stack 535. In some embodiments, substrate contact layer 134 and / or submount contact layer 146 may be optional or absent. In some embodiments, substrate contact layer 134 and / or submount contact layer 146 may include more or fewer layers than those described, may include layers of different materials or material compositions, the layers may be in a different order than those described, and / or may have different thicknesses than those described without departing from the scope of the invention.

[0118] The embodiment of the metallurgical bond stack 535 of FIG. 2B may differ from the metallurgical bond stack 435 of FIG. 2A in that additional second nickel layer 512, second tin layer 514, and second gold layer 516 are formed on the first nickel layer, first tin layer, and first gold layer. The additional layers may provide higher die shear and may provide more robustness against thermal stress. For example, the additional nickel and / or gold in the metallurgical bond stack 535 may reduce the area of ​​unreacted tin in the resulting metallurgical bond layer.

[0119] 1A-2B illustrate the use of a metal bonding stack to provide a metal bonding layer in a transistor device implemented as a HEMT, but the present disclosure is not so limited. FIGS. 3A and 3B illustrate the application of embodiments of the present disclosure in a vertical metal oxide semiconductor field effect transistor (MOSFET). The NiSn die attach system described herein can function equally well with both HEMT and MOSFET devices, and in amplifier and / or power switching structures. FIG. 3A is a schematic cross-sectional view of a unit cell 316 of a vertical MOSFET device according to various embodiments of the present disclosure. FIG. 3B is a schematic cross-sectional view showing a detail of area E of FIG. 3A.

[0120] FIG. 3A is a schematic cross-sectional view of a first wide bandgap power MOSFET unit cell 616 formed in transistor die 610. MOSFET unit cell 616 may be part of an amplifier or a power switching device, although the disclosure is not limited thereto. As shown in FIG. 3A, power MOSFET unit cell 616 includes a heavily doped (n + ) n-type substrate 622 (e.g., silicon carbide). - 6. A heavily doped n-type drift region 620 is provided in a substrate 622. A moderately doped p-type well layer 670 is formed on top of the n-type drift region 620. The moderately doped p-type well layer 670 may be formed by, for example, epitaxial growth. The moderately doped p-type well layer 670 may provide a p-well 672 for the unit cell 616. + The source region 660 may be formed in an upper region of a p-type well layer 670. + The source region 660 may be formed, for example, by ion implantation.

[0121] The substrate 622, the drift region 620, the moderately doped p-type well layer 670, and the heavily doped n + The source region 660 includes the semiconductor layer structure 606 of the MOSFET unit cell 616 in addition to the various regions / patterns that are formed.

[0122] A gate trench 680 is formed in the semiconductor layer structure 606. The gate trench 680 is formed of a heavily doped n + The source region 660 may extend through the moderately doped p-type well layer 670 into the drift region 620. A gate insulation layer 686 may be formed on the bottom surface and sidewalls of each gate trench 680. A gate electrode 684 may be formed in each gate insulation layer 686 to fill the respective gate trench 680.

[0123] A source contact (not shown) may be formed to the heavily doped n-type source region 660. A gate contact (not shown) may be formed to the gate electrode 684. A drain contact 626 may be formed on the underside of the substrate 622. In a packaged device, the drain contact 626 may be connected to the submount 176.

[0124] 3A shows an embodiment in which the MOSFET uses a trench gate configuration, it will be understood that this is merely an example and is not intended to limit the present disclosure, and in some embodiments a planar gate configuration may be used without departing from the scope of the present disclosure.

[0125] 3A and 3B, the submount 176 may act as a heat sink to dissipate heat generated in the transistor die 610. The submount 176 may also provide a connection to a drain contact 626. The drain contact 626 may include a substrate contact layer 634 electrically connected to the submount contact layer 146 in the submount 176. The substrate contact layer 634 may be formed similarly to the substrate contact layer 134 described herein. For example, the substrate contact layer 634 may include Ti, TiW, and / or Au, but the embodiments of the present disclosure are not limited thereto. In some embodiments, the substrate contact layer 634 may include materials other than Ti, TiW, and / or Au, or may include materials other than those. The substrate contact layer 634 may be bonded to the submount contact layer 146 by a metal bonding layer 635. In some embodiments, the bond provided by metallurgical bond layer 635 between substrate contact layer 634 and submount contact layer 146 may be thermally and / or electrically conductive. In some embodiments, substrate contact layer 634 and / or submount contact layer 146 may be optional and may not be present. In some embodiments, substrate contact layer 634 and / or submount contact layer 146 may include more or fewer layers than those described, may include layers of different materials or material compositions, the layers may be in a different order than those described, and / or may have different thicknesses than those described without departing from the scope of the invention.

[0126] 3B, a metallurgical bonding layer 635 may be formed between the substrate contact layer 634 and the submount contact layer 146. The metallurgical bonding layer 635 is predominantly nickel (Ni) and tin (Sn) by weight. The metallurgical bonding layer 635 may include a NiSn alloy. In particular, the metallurgical bonding layer 635 includes greater than 50 weight percent nickel and tin, in some cases greater than 75 weight percent nickel and tin, and in some embodiments greater than 85 weight percent nickel and tin. The metallurgical bonding layer 635 of FIG. 3B may differ from the metallurgical bonding layer 135 of FIG. 1D in that the transistor die 610 may not incorporate a via (e.g., via 166 of FIG. 1C) in the substrate 622. Thus, the metallurgical bonding layer 635 of FIG. 3B may not be disposed within a via of the device. The metallurgical bonding layer 635 may be formed using a metallurgical bonding stack that is substantially similar to the metallurgical bonding stack 435 of Fig. 2A or the metallurgical bonding stack 535 of Fig. 2B, and therefore will not be described again.

[0127] The previously described figures included examples using a metal bonding layer to provide electrical connection to the submount. However, the present disclosure is not so limited. In some embodiments, a metal bonding layer may be used to provide thermal connection to the submount. For example, FIG. 4A is a schematic cross-sectional view of a transistor die unit cell 116' of a transistor die 110' according to various embodiments of the present disclosure. The transistor die unit cell 116' may be part of an amplifier or a power switching device, although the present disclosure is not so limited. FIG. 4B is a schematic cross-sectional view showing details of area F of FIG. 4A. Given the similarity of FIG. 4A to that of FIG. 1C, a description of similar or identical features will be omitted and the description will focus primarily on the differences between the two embodiments.

[0128] The transistor die unit cell 116' of FIG. 4A differs from the transistor die unit cell 116 of FIG. 1C in that the vias 166 are not provided. For example, a source connection may be provided by application of a signal to the source fingers 156 (e.g., by metal contact) rather than by a via in the substrate 322. As a result, the die unit cell 116' may not require a source terminal on the underside of the substrate 322. Thus, the metal bonding layer 135' may connect the substrate 322 to the submount 176 without the use of a substrate and / or submount contact layer.

[0129] In some embodiments, a thermal layer 446 may be provided between the transistor die 110' and the submount 176. The thermal layer 446 may be a thermally conductive material, such as a metal layer, that may facilitate heat transfer from the substrate 322 to the submount 176. The thermal layer 446 may be omitted in some embodiments.

[0130] 4B, metallurgical bonding layer 135' may include a NiSn alloy and may be formed between substrate 322 and submount 176 and / or thermal layer 446. Metallurgical bonding layer 135' is predominantly nickel (Ni) and tin (Sn) by weight. In particular, metallurgical bonding layer 135' includes greater than 50 weight percent nickel and tin, in some cases greater than 75 weight percent nickel and tin, and in some embodiments greater than 85 weight percent nickel and tin.

[0131] The metallurgical bonding stack used to form metallurgical bonding layer 135' may be similar to the metallurgical bonding stack used to form metallurgical bonding layer 135 of FIG. 1D, except that there is no contact layer (e.g., substrate contact layer 134 of FIG. 1D) between the metallurgical bonding stack and substrate 322. Figures 5A and 5B are schematic cross-sectional views of an exemplary metallurgical bonding stack according to various embodiments of the present disclosure. Figures 5A and 5B depict an area of ​​transistor die 110' that is similar to the area shown in FIG. 4B (e.g., area F of FIG. 4A) prior to the formation of metallurgical bonding layer 135'.

[0132] For example, Figure 5A is a schematic cross-sectional view of an example metallurgy bond stack 435 according to some embodiments of the present disclosure. Referring to Figure 5A, metallurgy bond stack 435 may be formed on substrate 322 of transistor die 110'.

[0133] Metallurgical bond stack 435 may include selectively deposited layers. Metallurgical bond stack 435 may include, for example, from closest to substrate 322 to furthest from substrate 322, adhesion layer 402 (e.g., Ti), adhesion barrier layer 404 (e.g., Pt), nickel layer 406, tin layer 408, and gold layer 410. The formation and structure of adhesion layer 402, adhesion barrier layer 404, nickel layer 406, tin layer 408, and gold layer 410 may be similar to those discussed herein with respect to FIG. 2A, and therefore a repeated description thereof will be omitted.

[0134] The metal bonding stack 435 may be formed on the bottom of the substrate 322. The transistor die 110' with the metal bonding stack 435 may be disposed on the thermal layer 446 (if present) and the submount 176. In some embodiments, the metal bonding stack 435 may be disposed in direct contact with the thermal layer 446 (if present) or the submount 176, although the disclosure is not limited thereto. In some embodiments, a submount bonding stack may also be present on the thermal layer 446 (if present) or the submount 176 such that it is between the metal bonding stack 435 and the submount 176. The submount bonding stack, if present, may be similar to the metal bonding stack 435. That is, the submount bonding stack may include Ni and Sn in amounts similar to the metal bonding stack 435. However, the disclosure is not limited thereto.

[0135] Once metallurgical bonding stack 435 is positioned adjacent to thermal layer 446 or submount 176, heat and / or pressure may be applied to the combination of transistor die 110' and submount 176 to form metallurgical bonding layer 135' (see FIG. 4B).

[0136] Embodiments in which no contact layer is present may similarly use the metallurgical bond stack described above with respect to Figure 2B. Figure 5B is a schematic cross-sectional view of another exemplary metallurgical bond stack 535 in which no contact layer is present, according to some embodiments of the present disclosure.

[0137] For example, the metallurgical bonding stack 535 may include selectively deposited layers. The metallurgical bonding stack 535 may include, for example, from closest to the substrate 322 to furthest from the substrate contact layer 134, an adhesion layer 402 (e.g., Ti), a bonding barrier layer 404 (e.g., Pt), a first nickel layer 506, a first tin layer 508, a first gold layer 510, a second nickel layer 512, a second tin layer 514, and a second gold layer 516. The formation and structure of the adhesion layer 402, the bonding barrier layer 404, the first nickel layer 506, the first tin layer 508, the first gold layer 510, the second nickel layer 512, the second tin layer 514, and the second gold layer 516 are similar to those discussed herein with respect to FIG. 2B, and therefore a repeated description thereof will be omitted.

[0138] Although the previous figures show the use of a metal bonding stack to provide a metal bonding layer between the device substrate and the submount, the disclosure is not so limited. FIGS. 6A and 6B show the use of embodiments of the disclosure in a flip chip configuration. FIG. 6A is a schematic cross-sectional view of a unit cell 716 of a HEMT device in a flip chip configuration, according to various embodiments of the disclosure. The unit cell 716 can be part of an amplifier or a power switching device, although the disclosure is not so limited. FIG. 6B is a schematic cross-sectional view showing a detail of area G of FIG. 6A. Given the similarity of FIG. 6A to the similarities of FIGS. 1C and 4A, a description of similar or identical features will be omitted and the description will focus primarily on the differences between the two embodiments. In a flip chip configuration, the semiconductor layer structure 130 is "flipped" such that the substrate 322 is the top layer of the unit cell 716. In contrast to the embodiments of Figures 1C and 4A, the gate terminal 152, the drain terminal 154, and the source terminal 156 may be electrically connected to the submount 176 using gate contact 752, drain contact 754, and source contact 756, respectively.

[0139] 6A and 6B, the submount 176 can provide electrical connections to the terminals of the unit cell 716 through the gate contact 752, the drain contact 754, and the source contact 756, respectively. Because each of the gate terminal 152, the drain terminal 154, and the source terminal 156 can be electrically isolated from each other, each of the gate terminal 152, the drain terminal 154, and the source terminal 156 can be electrically connected to separate portions of the submount contact layer 146. For example, the submount contact layer 146 can be separated into a first portion 146A, a second portion 146B, and a third portion (not shown). Similarly, the contacts connecting the gate terminal 152, the drain terminal 154, and the source terminal 156 to the portions of the submount contact layer 146 can include portions of the terminal contact layer 734 and the metal bonding layer 735. The terminal contact layer 734 can be formed similarly to the substrate contact layer 134 described herein. For example, the terminal contact layer 734 may include Ti, TiW, and / or Au, although embodiments of the present disclosure are not limited thereto. In some embodiments, the terminal contact layer 734 may include materials other than Ti, TiW, and / or Au, or may include materials in addition thereto. The terminal contact layer 734 may be separated into a first portion 734A, a second portion 734B, and a third portion (not shown). The metal bonding layer 735 may be separated into a first portion 735A, a second portion 735B, and a third portion (not shown). In some embodiments, the substrate contact layer 734 and / or the submount contact layer 146 may be optional and may not be present. In some embodiments, the substrate contact layer 734 and / or the submount contact layer 146 may include more or fewer layers than those described, may include layers of different materials or material compositions, the layers may be in a different order than those described, and / or may have different thicknesses than those described without departing from the scope of the present invention.

[0140] The source contact 756 may include a terminal contact layer first portion 734A electrically connected to a submount contact layer first portion 146A of the submount 176. The terminal contact layer first portion 734A may be connected to the submount contact layer first portion 146A by a metallurgical bonding layer first portion 735A. In some embodiments, the bond provided by the metallurgical bonding layer first portion 735A between the terminal contact layer first portion 734A and the submount contact layer first portion 146A may be thermally and / or electrically conductive.

[0141] The gate contact 752 may include a terminal contact layer second portion 734B electrically connected to a submount contact layer second portion 146B of the submount 176. The terminal contact layer second portion 734B may be coupled to the submount contact layer second portion 146B by a metallurgical bonding layer second portion 735B. In some embodiments, the bond provided by the metallurgical bonding layer second portion 735B between the terminal contact layer second portion 734B and the submount contact layer second portion 146B may be thermally and / or electrically conductive.

[0142] 6B does not explicitly show drain contact 754, it will be understood that its structure is similar to that of gate contact 752 and source contact 756. In some embodiments, for example, drain contact 754 may include a third portion of a terminal contact layer that is electrically connected to a third portion of a submount contact layer in submount 176. The third portion of the terminal contact layer may be bonded to the third portion of the submount contact layer by a third portion of a metallurgical bonding layer. In some embodiments, the bond provided by the third portion of the metallurgical bonding layer between the third portion of the terminal contact layer and the third portion of the submount contact layer may be thermally and / or electrically conductive.

[0143] In some embodiments, an insulating layer 726 may be disposed between the gate terminal 152, the drain terminal 154, and the source terminal 156, and / or between the gate contact 752, the drain contact 754, and the source contact 756, although embodiments of the present disclosure are not so limited. In some embodiments, the gate terminal 152, the drain terminal 154, and the source terminal 156, and / or the gate contact 752, the drain contact 754, and the source contact 756 may alternatively or additionally be separated by an air gap 786. Although FIGS. 6A and 6B show an insulating layer 726 having an air gap 786 therebetween that does not extend to the submount 176, embodiments of the present disclosure are not so limited. In some embodiments, the insulating layer 726 may extend to the submount 176. In some embodiments, the insulating layer 726 may be omitted, and the air gap 786 may extend from the submount 176 to the top surface of the semiconductor layer structure 130.

[0144] 6B, a first portion 735A, a second portion 735B, and a third portion of the metal bonding layer 735 may be formed between the respective first portion, second portion, and third portion of the terminal contact layer 734 and the submount contact layer 146. The terminal contact layer 734 may be similar to the substrate contact layer 134 described with respect to FIGS. 1A-1E. In particular, in some embodiments, the terminal contact layer 734 and / or the submount contact layer 146 may include a layer of Au (e.g., between 2 μm and 8 μm), although the disclosure is not limited thereto. In some embodiments, the submount contact layer 146 may be omitted.

[0145] The metallurgical bonding layer 735 is predominantly nickel (Ni) and tin (Sn) by weight. The metallurgical bonding layer 735 may include a NiSn alloy. In particular, the metallurgical bonding layer 735 includes more than 50 weight percent nickel and tin, in some cases more than 75 weight percent nickel and tin, and in some embodiments more than 85 weight percent nickel and tin. The metallurgical bonding layer 735 of FIG. 6B may differ from the metallurgical bonding layer 135 of FIG. 1D in that the metallurgical bonding layer 735 may be separated into a first portion 735A, a second portion 735B, and a third portion with gaps between each of the portions. The metallurgical bonding layer 735 may be formed using a metallurgical bonding stack that is substantially similar to the metallurgical bonding stack 435 of FIG. 2A or the metallurgical bonding stack 535 of FIG. 2B. Therefore, a duplicate description thereof will be omitted. In some embodiments, a metallurgical bonding stack may be deposited first and then patterned to form first, second, and third portions that are subsequently transformed into the first, second, and third portions of metallurgical bonding layer 735 by application of heat and / or pressure when attaching gate terminal 152, drain terminal 154, and source terminal 156 to submount 176.

[0146] 6A illustrates an embodiment in which a source via, such as source via 166 of FIG. 1C, is not present, it will be understood that this is merely an example and is not intended to limit the present disclosure. In some embodiments, a source via may be used without departing from the scope of the present disclosure. In embodiments in which a source via is present, source terminal 156 (and its associated contact and bonding layers) may or may not be present depending on the design of the device and its associated interconnects.

[0147] Although various embodiments of transistor configurations have been described and illustrated herein with reference to regions of particular conductivity types (i.e., n-type and p-type) as examples, it will be understood that the conductivity types of the regions in any of the illustrated examples may be reversed (i.e., p-type and n-type) in accordance with embodiments of the present disclosure. Thus, it will be appreciated that the present invention covers both n-channel and p-channel devices for each of the different device structures.

[0148] Many different embodiments have been disclosed herein with reference to the above description and drawings. It will be understood that to describe and show every combination and subcombination of these embodiments verbatim would be unduly repetitive and confusing. Thus, all embodiments can be combined in any manner and / or combination, and the specification, including the drawings, shall be construed as constituting a complete written description of all combinations and subcombinations of the embodiments described herein, and the manner and process of making and using them, and shall support claims to any such combinations or subcombinations.

[0149] It will be understood that some of the drawings in this disclosure are schematic cross-sectional views and are sized for illustrative purposes, not to scale and without precision. As described herein, some of the layers shown actually vary in thickness from one another by several orders of magnitude, and attempting to show such verbatim would diminish rather than enhance the clarity of the specification.

[0150] Various embodiments have been described herein with reference to the accompanying drawings, in which exemplary embodiments are shown. However, these embodiments may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the inventive concepts to those skilled in the art. Various modifications to the exemplary embodiments and the general principles and features described herein will be readily apparent. In the drawings, the sizes and relative sizes of layers and regions are not shown to scale, and in some instances may be exaggerated for clarity.

[0151] It will be understood that although terms such as "first", "second" and the like may be used herein to describe various elements, the elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the present invention. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0152] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including" as used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0153] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which this invention belongs. Terms used herein should be interpreted to have a meaning consistent with their meaning in the context of this specification and the related art, and will be further understood not to be interpreted in an idealized or overly formal sense unless expressly defined as such in this specification.

[0154] When an element, such as a layer, region, or substrate, is referred to as being "on," "attached," or extending "on to" another element, it will be understood that the element can be directly on the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly attached," or extending "directly onto" another element, there are no intervening elements present. Also, when an element is referred to as being "connected" or "coupled" to another element, it will be understood that the element can be directly connected or coupled to the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0155] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "lateral" or "vertical" may be used herein to describe the relationship of one element, layer or region to another element, layer or region shown in the figures. It will be understood that these terms are intended to encompass various orientations of the device in addition to the orientation depicted in the figures.

[0156] Embodiments of the present invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include, for example, deviations in shapes that result from manufacturing. Elements indicated by dotted lines may be optional in the illustrated embodiments.

[0157] Like numbers refer to like elements throughout, and thus the same or similar numbers may be described with reference to other drawings even if not mentioned or described in the corresponding drawing, and elements not designated by a reference number may be described with reference to other drawings.

[0158] In the drawings and specification, exemplary embodiments of the invention have been disclosed and specific terms have been employed, but these terms are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the appended claims.

Claims

1. A submount and a transistor die on the submount; a metallurgical bonding layer between the submount and the transistor die, the metallurgical bonding stack providing mechanical attachment of the transistor die to the submount; A transistor device structure comprising: the metallurgical bonding layer comprises gold, tin and nickel, the weight percentage of the combination of nickel and tin in the metallurgical bonding layer being greater than 50 percent and the weight percentage of gold in the metallurgical bonding layer being less than 25 percent; the transistor die includes at least one terminal; The metallurgical bonding layer electrically connects the at least one terminal to the submount.

2. 2. The transistor device structure of claim 1, wherein the weight percentage of gold in the metallurgical bonding layer is less than ten percent.

3. 2. The transistor device structure of claim 1, wherein the weight percentage of gold in the metallurgical bonding layer is less than five percent.

4. 2. The transistor device structure of claim 1, wherein the metallurgical bonding layer further comprises a barrier layer between a portion of the metallurgical bonding layer comprising tin and the transistor die.

5. The transistor device structure of claim 4 , wherein the barrier layer comprises platinum.

6. the metallurgical bonding layer is between the submount and the transistor die in a first direction; 2. The transistor device structure of claim 1, wherein a longest dimension of the metallurgical bonding layer in a second direction perpendicular to the first direction is greater than 3.5 mm.

7. 10. The transistor device structure of claim 1, further comprising a substrate contact layer between said metallurgical bonding layer and said transistor die.

8. 8. The transistor device structure of claim 7, wherein the substrate contact layer comprises a gold layer having a thickness between 2 μm and 8 μm.

9. The transistor die includes: A substrate; a channel layer on the substrate; a barrier layer on the channel layer; a via extending through the substrate, the channel layer, and the barrier layer; Including, a first portion of the metallurgical bonding layer between the substrate and the submount; The transistor device structure of claim 1 , wherein the second portion of the metallurgical bonding layer is on a sidewall of the via.

10. 10. The transistor device structure of claim 9, wherein a composition of the first portion of the metallurgical bonding layer is different from a composition of the second portion of the metallurgical bonding layer.

11. The transistor device structure of claim 9 , wherein the substrate comprises silicon carbide.

12. the at least one terminal includes a gate terminal and a drain terminal; The transistor device structure of claim 1 , wherein the metallurgical bonding layer electrically connects the gate terminal to the submount.

13. 2. The transistor device structure of claim 1, wherein an operating frequency of said transistor device structure is between 500 MHz and 75 GHz.

14. 10. The transistor device structure of claim 1, wherein the power output of said transistor device structure is between 50W and 200W.

15. A submount and a transistor die on the submount; a metallurgy bonding layer between the submount and the transistor die in a first direction, the metallurgy bonding layer providing a mechanical attachment of the transistor die to the submount; A transistor device structure comprising: The composition of the metal bonding layer mainly includes nickel and tin, the longest dimension of the metallurgical bonding layer is greater than 3.5 mm in a second direction perpendicular to the first direction; A transistor device structure, wherein an interface between the metallurgical bonding layer and the transistor die is substantially free of unreacted tin.

16. 16. The transistor device structure of claim 15, wherein the weight percentage of the combination of nickel and tin in the metallurgical bonding layer is greater than 50 percent.

17. the metal bonding layer further comprises gold; 17. The transistor device structure of claim 16, wherein the weight percentage of gold in said metallurgical bonding layer is less than 10 percent.

18. 16. The transistor device structure of claim 15, wherein the metallurgical bonding layer further comprises a barrier layer between a tin portion of the metallurgical bonding layer and the transistor die.

19. 20. The transistor device structure of claim 18, wherein the barrier layer comprises platinum.

20. 16. The transistor device structure of claim 15, further comprising a contact layer between the submount and the metallurgical bonding layer.

21. 21. The transistor device structure of claim 20, wherein the contact layer comprises a gold layer having a thickness between 2 μm and 8 μm.

22. The transistor die includes: A substrate; a channel layer on the substrate; a barrier layer on the channel layer; a via extending through the substrate, the channel layer, and the barrier layer; Including, a first portion of the metallurgical bonding layer between the substrate and the submount; The transistor device structure of claim 15 , wherein the second portion of the metallurgical bonding layer is on a sidewall of the via.

23. 23. The transistor device structure of claim 22, wherein a composition of the first portion of the metallurgical bonding layer is different from a composition of the second portion of the metallurgical bonding layer.

24. 16. The transistor device structure of claim 15, wherein an operating frequency of the transistor device structure is between 500 MHz and 75 GHz.

25. a transistor die having a semiconductor structure including a semiconductor substrate, a barrier layer, and a channel layer; a source contact on the semiconductor structure; a via extending through the semiconductor substrate, the barrier layer, and the channel layer so as to be electrically connected to the source contact; a metallurgical bonding layer including a first portion within the via; a submount on the metallurgical bonding layer, the metallurgical bonding layer further including a second portion outside the via and between the semiconductor substrate and the submount; A transistor device structure comprising: the metallic bonding layer comprises an alloy of tin and nickel; A transistor device structure, wherein a composition of the first portion of the metallurgical bonding layer is different from a composition of the second portion of the metallurgical bonding layer.

26. 26. The transistor device structure of claim 25, wherein the metallurgical bonding layer further comprises gold, and wherein a weight percentage of the combination of nickel and tin in the metallurgical bonding layer is greater than about 50 percent and a weight percentage of gold in the metallurgical bonding layer is less than about 25 percent.

27. 26. The transistor device structure of claim 25, wherein the first portion of the metallurgical bonding layer is disposed at the same level as a portion of the channel layer.

28. 26. The transistor device structure of claim 25, wherein the metallurgical bonding layer further comprises a barrier layer between a tin portion of the metallurgical bonding layer and the transistor die.

29. 30. The transistor device structure of claim 28, wherein the barrier layer comprises platinum.

30. the metallurgical bonding layer is spaced from the transistor die in a first direction; 26. The transistor device structure of claim 25, wherein a longest dimension of the metallurgical bonding layer in a second direction perpendicular to the first direction is greater than 3.5 mm.

31. 26. The transistor device structure of claim 25, wherein an operating frequency of the transistor device structure is between 500 MHz and 75 GHz.

32. providing a submount; forming a metallurgical bond stack on a transistor die; placing the transistor die with the metallurgical bonding stack on the submount such that the metallurgical bonding stack is between the transistor die and the submount, a respective portion of the metallurgical bonding stack being between a respective terminal of the transistor die and the submount; applying heat and / or pressure to the transistor die and the metallurgical bonding stack to provide a mechanical attachment of the transistor die to the submount; 1. A method of forming a transistor device structure, comprising: The method of claim 1, wherein the metallurgical bond laminate comprises a layer of tin adjacent to a layer of nickel.

33. 33. The method of claim 32, wherein the metallurgical bonded laminate further comprises gold, the weight percentage of the combination of nickel and tin in the metallurgical bonded laminate being greater than 50 percent and the weight percentage of gold in the metallurgical bonded laminate being less than 25 percent.

34. 34. The method of claim 33, wherein the weight percentage of gold in the metallurgical bond stack is less than 10 percent.

35. 33. The method of claim 32, wherein the metallurgical bond stack further comprises a barrier layer between the tin layer of the metallurgical bond stack and the transistor die.

36. 36. The method of claim 35, wherein the barrier layer comprises platinum.

37. the metallurgical bond stack is laminated to the transistor die in a first direction; 33. The method of claim 32, wherein a longest dimension of the metallurgical bond laminate in a second direction perpendicular to the first direction is greater than 3.5 mm.

38. The method further includes forming a substrate contact layer on the transistor die; 33. The method of claim 32, wherein the metallurgical bond stack is formed on the substrate contact layer.

39. 39. The method of claim 38, wherein the substrate contact layer comprises a gold layer having a thickness between 2 μm and 8 μm.

40. The transistor die includes: A substrate; a channel layer on the substrate; a barrier layer on the channel layer; Including, The method further includes forming a via through the substrate, the channel layer, and the barrier layer; 33. The method of claim 32, wherein forming the metal bonding stack on the transistor die includes forming a first portion of the metal bonding stack on a bottom surface of the substrate and a second portion of the metal bonding stack on a sidewall of the via.

41. The method of claim 40, wherein the substrate comprises silicon carbide.

42. 33. The method of claim 32, further comprising patterning the metallurgical bond stack into the respective portions.

43. 33. The method of claim 32, wherein the operating frequency of the transistor device structure is between 500 MHz and 75 GHz.

44. 33. The method of claim 32, wherein the power output of the transistor device structure is between 50W and 200W.

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