Semiconductor Module

Abstract

To increase the reliability of a semiconductor module.SOLUTION: A semiconductor module includes a circuit board including a predetermined circuit pattern, a semiconductor chip placed on the circuit board, a wiring member connecting the semiconductor chip and the circuit pattern, and sealing resin for sealing the semiconductor chip and the wiring member. The sealing resin includes first resin containing inorganic filler and epoxy resin and covering the semiconductor chip, and second resin provided to a surface of the first resin and having a smaller coefficient of elasticity than the first resin. The second resin is apart from the semiconductor chip and the circuit board.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor module. [Background technology]

[0002] Conventionally, there has been known a semiconductor module in which a semiconductor chip is mounted on a circuit board and the semiconductor chip and the circuit pattern of the circuit board are connected by a wiring member. In such a semiconductor module, a sealing resin is used to protect the semiconductor chip (for example, see Patent Document 1). Patent Document 1: JP 2017-28159 A Summary of the Invention [Problem to be solved by the invention]

[0003] It is preferable to increase the reliability of a semiconductor module. [Means for solving the problem]

[0004] In order to solve the above problem, one aspect of the present invention provides a semiconductor module. The semiconductor module may include a circuit board having a predetermined circuit pattern. The semiconductor module may include a semiconductor chip mounted on the circuit board. The semiconductor module may include a wiring member that connects the semiconductor chip and the circuit pattern. The semiconductor module may include a sealing resin that seals the semiconductor chip and the wiring member. The sealing resin may include a first resin that contains an inorganic filler and an epoxy resin and covers the semiconductor chip. The sealing resin may include a second resin that is provided on a surface of the first resin and has a smaller elastic modulus than the first resin. The second resin may be spaced apart from the semiconductor chip and the circuit board.

[0005] The above summary of the invention does not list all of the necessary features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0006] [Figure 1] 1 is a diagram illustrating an example of a semiconductor module 100 according to an embodiment of the present invention. [Diagram 2] 1 is a diagram illustrating an example of a semiconductor module 100 as viewed from above. [Diagram 3] FIG. 1 is a diagram illustrating an example of a semiconductor module 200 according to an embodiment of the present invention. [Figure 4] 2 is a diagram illustrating an example of a semiconductor module 200 as viewed from above. [Diagram 5] FIG. 1 is a diagram showing an example of a semiconductor module 300 according to an embodiment of the present invention. [Figure 6] 2 is a diagram illustrating an example of a semiconductor module 300 as viewed from above. [Figure 7] 3A to 3C are diagrams illustrating an example of a method for forming the sealing resin 12. [Figure 8] 3A to 3C are diagrams illustrating an example of a method for forming the sealing resin 12 of the semiconductor module 300. [Figure 9] 13A and 13B are diagrams illustrating an example of a semiconductor module 300 in an inner resin curing step S203. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] The present invention will be described below through the embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention. In this specification and drawings, elements having substantially the same functions and configurations are given the same reference numerals to avoid repeated explanations, and elements not directly related to the present invention are not shown. In addition, in one drawing, elements having the same functions and configurations may be given the same reference numerals as representative elements, and the reference numerals may be omitted for the others.

[0008] In this specification, one side in a direction parallel to the depth direction of a semiconductor chip is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor module is mounted.

[0009] In this specification, technical matters may be described using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components, and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. The +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without indicating positive or negative, it means a direction parallel to the +Z-axis and -Z-axis. In this specification, the orthogonal axes parallel to the upper and lower surfaces of the semiconductor chip are the X-axis and the Y-axis. Also, the axis perpendicular to the upper and lower surfaces of the semiconductor substrate is the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Also, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and the Y-axis, may be referred to as the horizontal direction.

[0010] In this specification, when the term "same" or "equal" is used, it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0011] FIG. 1 is a diagram showing an example of a semiconductor module 100 according to an embodiment of the present invention. The semiconductor module 100 may function as a power conversion device such as an inverter. The semiconductor module 100 includes one or more circuit boards 20. In this specification, the orthogonal axes on the plane on which the one or more circuit boards 20 are provided are the X-axis and the Y-axis, and the axis perpendicular to the XY plane is the Z-axis. FIG. 1 shows an example of the arrangement of each member on the YZ plane. The circuit board 20 is provided with a predetermined circuit pattern 26 on one side of an insulating substrate 21, and a heat sink 22 on the other side. The circuit pattern 26 and the heat sink 22 may be formed by directly bonding a copper plate or an aluminum plate, or a plate plated with these materials, to an insulating substrate 21 such as silicon nitride ceramics or aluminum nitride ceramics, or by bonding the plate directly or via a brazing layer. The circuit board 20 may be formed by bonding an insulating sheet to a conductive member such as a copper plate or an aluminum plate. In other words, the circuit board 20 may be a plate-shaped member in which a conductive member and an insulating member are integrated.

[0012] One or more semiconductor chips 40 are mounted on the circuit board 20. In the example of FIG. 1, one semiconductor chip 40 is mounted. The bonding layer 30 bonds the semiconductor chip 40 to the circuit pattern 26 of the circuit board 20. The bonding layer 30 is solder or the like. The semiconductor chip 40 and the like are protected by a resin package such as a resin case 10 that surrounds the circuit pattern 26 of the circuit board 20 and a sealing resin 12 that is filled in the resin case 10. Note that the semiconductor chip 40 and the like may be protected by transfer molding using the sealing resin 12 without providing the resin case 10.

[0013] The semiconductor chip 40 may include an insulated gate bipolar transistor (IGBT), a diode such as a free wheel diode (FWD), a reverse conducting (RC)-IGBT that combines these, and a MOS transistor. The amount of heat generated by the semiconductor chip 40 changes depending on the operating state. For example, in an RC-IGBT, the amount of heat generated changes because the current flows through different points when the IGBT is on and when the IGBT is off and a current flows through the FWD. For this reason, the temperature of the semiconductor chip 40 increases and decreases during switching.

[0014] The semiconductor chip 40 of this example is a vertical chip with electrodes (e.g., an emitter electrode and a collector electrode) formed on the upper and lower surfaces. The semiconductor chip 40 is connected to the circuit pattern 26 of the circuit board 20 by the electrodes formed on the lower surface, and is connected to a wiring member by the electrodes formed on the upper surface. It should be noted that the semiconductor chip 40 is not limited to a vertical chip. The semiconductor chip 40 may have electrodes on the upper surface that are connected to the circuit pattern 26.

[0015] The resin case 10 is provided to surround a space 94 that houses the semiconductor chip 40. In Fig. 1, the resin case 10 has a sidewall 18. The sidewall 18 surrounds the space 94 in the XY plane. The insulating substrate 21 is provided below the sidewall 18. Note that the space 94 may be an area above the insulating substrate 21 and surrounded by the resin case 10.

[0016] In this example, the resin case 10 is molded from a resin such as a thermosetting resin that can be formed by injection molding, or an ultraviolet-curing resin that can be formed by UV molding. The resin may include one or more polymer materials selected from, for example, polyphenylene sulfide (PPS) resin, polybutylene terephthalate (PBT) resin, polyamide (PA) resin, acrylonitrile butadiene styrene (ABS) resin, and acrylic resin.

[0017] The heat sink 22 may cover at least a part or the entire lower surface of the insulating substrate 21. The cooler 16 is directly or indirectly connected to the circuit board 20. In this example, the cooler 16 may cover at least a part or the entire lower surface of the heat sink 22. The bonding layer 24 bonds the heat sink 22 to the cooler 16. The bonding layer 24 is solder or the like. The cooler 16 contains a refrigerant such as water inside. The cooler 16 cools the semiconductor chip 40 via the heat sink 22 or the like.

[0018] The semiconductor chip 40 has an upper surface connected to a wiring member via a bonding layer (not shown) such as solder. The wiring member in this example is a lead frame 50 and wires 27. The lead frame 50 is a member formed of a metal material such as copper or aluminum. At least a part of the surface of the lead frame 50 may be plated with nickel or the like. At least a part of the surface of the lead frame 50 may be coated with resin or the like. The lead frame 50 may have a plate-like portion. The plate-like shape refers to a shape in which the areas of two main surfaces arranged opposite to each other are larger than the area of ​​the other surfaces. At least the portion of the lead frame 50 that is connected to the semiconductor chip 40 may be plate-like. The lead frame 50 may be formed by bending a single metal plate.

[0019] The lead frame 50 connects the semiconductor chip 40 and the circuit pattern 26. A main current may flow through the lead frame 50. Here, the main current is the maximum current among the currents flowing through the semiconductor chip 40. The lead frame 50 of this example has a chip connection portion 52, a bridge portion 54, and a circuit pattern connection portion 56. The chip connection portion 52 is a portion joined to the upper surface of the semiconductor chip 40. The circuit pattern connection portion 56 is a portion connected to the upper surface of the circuit pattern 26. The chip connection portion 52 and the circuit pattern connection portion 56 may be plate-shaped portions that are approximately parallel to the XY plane. Note that approximately parallel refers to a state in which the angle is, for example, 10 degrees or less.

[0020] The bridging portion 54 connects the chip connecting portion 52 and the circuit pattern connecting portion 56. The bridging portion 54 is disposed away from conductive members such as the circuit pattern 26. The bridging portion 54 in this example is disposed above the circuit pattern 26, etc., and is provided from the chip connecting portion 52 to the circuit pattern connecting portion 56 so as to straddle the circuit pattern 26, etc.

[0021] The wires 27 connect the semiconductor chip 40 and the circuit pattern 26. A voltage for controlling the gate of the semiconductor chip 40 may be applied to the wires 27.

[0022] In this example, the sealing resin 12 is provided inside the resin case 10. The sealing resin 12 seals the semiconductor chip 40, and the lead frame 50 and wires 27 serving as wiring members. In other words, the sealing resin 12 covers the entire semiconductor chip 40 and the wiring members so that the semiconductor chip 40 and the wiring members are not exposed. The sealing resin 12 can protect the semiconductor chip 40 and the wiring members. Note that external terminals connected to the wiring members may be exposed from the sealing resin 12.

[0023] The sealing resin 12 in this example has a first resin 42 and a second resin 44. The first resin 42 contains an inorganic filler and an epoxy resin as a filling agent. The first resin 42 may cover the semiconductor chip 40 and the wiring member so that they are not exposed. Here, the first resin 42 may cover at least a part of the wiring member, that is, either the lead frame 50 or the wire 27. In one example, the first resin 42 contains an epoxy resin, a hardener, and an inorganic filler as main components. The first resin 42 may also contain additives such as a hardening accelerator, a release agent, a colorant, and a flame retardant.

[0024] The first resin 42 contains 50 wt% or more of inorganic filler. As an example, the first resin 42 contains 50 wt% or more and 90 wt% or less of inorganic filler. The inorganic filler has a high glass transition temperature Tg. The glass transition temperature Tg is the temperature at which glass transition occurs. Therefore, when the first resin 42 contains a predetermined amount or more of inorganic filler, the glass transition temperature Tg of the entire first resin 42 can be increased and the heat resistance can be improved. In other words, the semiconductor chip 40 and its periphery can be sealed with the first resin 42 having a high glass transition temperature Tg, and the insulating properties and strength properties of the semiconductor module 100 can be maintained. The inorganic filler may be, for example, a silica filler containing SiO2.

[0025] On the other hand, when the first resin 42 contains a certain amount of inorganic filler or more, the possibility of cracks occurring due to brittle behavior increases relatively. When brittle fracture occurs, plastic deformation is hardly involved. If a crack occurs in the first resin 42 and the crack progresses to the upper end of the sealing resin 12, the semiconductor chip 40 is exposed to the outside air, and the protection of the semiconductor chip 40 is weakened. This can result in poor pressure resistance and reduced reliability.

[0026] Therefore, the second resin 44 is provided on the surface of the first resin 42. The second resin 44 is provided on the surface of the first resin 42 opposite to the cooler 16. The glass transition temperature Tg of the second resin 44 may be relatively lower than the glass transition temperature Tg of the first resin 42. Note that the first resin 42 and the second resin 44 may be provided to form a layer structure.

[0027] The second resin 44 may have a smaller elastic modulus than the first resin 42. The elastic modulus is the ratio of stress to strain within an elastic range when an elastic body is deformed by applying an external force. The elastic modulus represents the resistance to deformation. Young's modulus may be used as the elastic modulus. By filling the space 94 with the first resin 42 and the second resin 44, which is relatively softer than the first resin 42, the stress generated during high-temperature operation is alleviated more than when the space 94 is filled only with the first resin 42. This is because the stress generated between the side wall 18 and the second resin 44, which is relatively softer than the first resin 42, is alleviated. Furthermore, even if a crack occurs in the first resin 42, the second resin 44, which has different mechanical properties, can suppress linear crack growth. That is, it is possible to suppress the crack from penetrating the second resin 44 and reaching the surface of the semiconductor module 100. This can improve the reliability of the semiconductor module 100.

[0028] The second resin 44 may have a smaller yield stress than the first resin 42. This causes the second resin 44 to plastically deform faster than the first resin 42. Therefore, the second resin 44 is more likely to break (become fragile) first. This makes it possible to prevent the first resin 42 from reaching its yield stress and plastically deforming. This makes it possible to improve the reliability of the semiconductor module 100.

[0029] In this example, the first resin 42 covers the semiconductor chip 40 and the lead frame 50, and the second resin 44 is separated from the semiconductor chip 40, the lead frame 50, and the circuit board 20. That is, in this example, the second resin 44 does not contact any of the upper surface, lower surface, or side surface of the semiconductor chip 40, the lead frame 50, and the circuit board 20. The second resin 44 in this example does not contact any of the upper surface, lower surface, or side surface of the insulating substrate 21. The second resin 44 in this example does not contact any of the upper surface, lower surface, or side surface of the heat sink 22. The second resin 44 in this example does not contact any surface of the circuit pattern 26. The side surface of the insulating substrate 21 may be in contact with the outside air, or may be in contact with a member different from the second resin 44. This allows the conductive members such as the semiconductor chip 40, the lead frame 50, and the circuit board 20 to be protected by the first resin 42 having heat resistance. In addition, since the second resin 44 does not come into contact with the conductive members, heat resistance is not required. In this example, the first resin 42 functions to protect the conductive members as a semiconductor package, and the second resin 44 functions to protect the first resin 42.

[0030] Therefore, the first resin 42 may have a larger total volume than the second resin 44. The first resin 42 may have a larger total weight than the second resin 44. In addition, the first resin 42 may be thicker than the second resin 44 in a cross-sectional or side view. As an example, the thickness T1 of the first resin 42 in FIG. 1 is 1 cm or more. As an example, the thickness T2 of the second resin 44 in FIG. 1 is 1 mm or more and 1 cm or less. This is because the protection of the first resin 42 by the second resin 44 does not require a large volume or thickness for the second resin 44. This allows the ratio of the first resin 42 and the second resin 44 to be optimized and costs to be reduced.

[0031] In this example, the second resin 44 contains an epoxy resin, and the sealing resin 12 is configured as a two-layer structure of epoxy resins with different physical properties. Here, the content (wt%) of inorganic filler in the second resin 44 may be smaller than that in the first resin 42. As an example, the second resin 44 may contain less than 50 wt% of inorganic filler. The second resin 44 may or may not contain inorganic filler. This makes the glass transition temperature Tg of the second resin 44 relatively lower than the glass transition temperature Tg of the first resin 42. Note that, like the first resin 42, the second resin 44 may also contain an epoxy resin, a hardener, and an inorganic filler as main components. The second resin 44 may also contain additives such as a hardening accelerator, a release agent, a colorant, and a flame retardant.

[0032] The second resin 44 may be configured to contain silicone gel or silicone rubber instead of or in addition to the epoxy resin. In this case, the yield stress of the second resin 44 does not need to be smaller than that of the first resin 42. The silicone gel or silicone rubber may also contain other additives.

[0033] FIG. 2 is a diagram showing an example of a semiconductor module 100 in a top view. The resin case 10 has an inner side wall 17. The inner side wall 17 is an example of a side wall 18. The inner side wall 17 divides a space 94 that houses a semiconductor chip 40. In FIG. 2, the inner side wall 17 divides the space 94 into a space 94-1, a space 94-2, and a space 94-3. The circuit board 20 may be provided commonly to the space 94-1, the space 94-2, and the space 94-3. The circuit board 20 may be provided individually to the space 94-1, the space 94-2, and the space 94-3. In addition, the resin case 10 may be provided with a through hole 84 into which a fastening member such as a screw for fixing a cooling device or the like is inserted.

[0034] The sealing resin 12 may be filled into the space 94 of the resin case 10 so that the wires 27, the semiconductor chip 40, and the lead frame 50 are not exposed. In Fig. 2, the second resin 44 of the sealing resin 12 is exposed in a top view. Note that an external terminal (not shown) may also be exposed from the sealing resin 12.

[0035] FIG. 3 is a diagram showing an example of a semiconductor module 200 according to an embodiment of the present invention. The semiconductor module 200 in FIG. 3 is different from the semiconductor module 100 in FIG. 1 in that the sealing resin 12 has a third resin 46. The other configurations in FIG. 3 may be the same as those in FIG. 1. The third resin 46 is provided on at least a part of the surface of the second resin 44. In the example in FIG. 2, the third resin 46 covers the entire upper surface of the second resin 44. That is, in FIG. 3, the sealing resin 12 is configured as a three-layer structure of epoxy resins in which the physical properties of adjacent layers are different. In one example, the third resin 46 contains an epoxy resin, a hardener, and an inorganic filler as main components. The third resin 46 may also contain additives such as a hardening accelerator, a release agent, a colorant, and a flame retardant.

[0036] The third resin 46 may have a higher inorganic filler content (wt%) than the second resin 44. As an example, the third resin 46 may contain 20 wt% or more of inorganic filler. Therefore, the glass transition temperature Tg of the third resin 46 may be higher than the glass transition temperature Tg of the second resin 44. Furthermore, the third resin 46 may have a lower inorganic filler content (wt%) than the first resin 42. This can relatively reduce the possibility of cracks occurring due to brittle behavior.

[0037] The third resin 46 may have a higher elastic modulus than the second resin 44. The surface of the sealing resin 12 may be covered with the third resin 46. This exposes the third resin 46, which is harder than the second resin 44, and therefore the surface of the second resin 44 can be protected. Even if a crack occurs in the first resin 42, the second resin 44 and the third resin 46, which have different mechanical properties, are present, so that linear crack growth can be suppressed. That is, the crack can be suppressed from penetrating the second resin 44 and the third resin 46 and reaching the surface of the sealing resin 12. This improves the reliability of the semiconductor module 200.

[0038] The third resin 46 may have a higher yield stress than the second resin 44. This allows the second resin 44 to plastically deform faster than the third resin 46. As a result, the third resin 46 exposed on the surface of the sealing resin 12 can be prevented from reaching its yield stress and plastically deforming. This makes it possible to prevent outside air from entering through the third resin 46 on the surface of the sealing resin 12. This makes it possible to improve the reliability of the semiconductor module 200. The third resin 46 may have a lower yield stress than the first resin 42.

[0039] The second resin 44 may have a larger total volume than the third resin 46. The second resin 44 may have a larger total weight than the third resin 46. The second resin 44 may be thicker than the third resin 46. As an example, the thickness T2 of the second resin 44 in FIG. 3 is 1 mm or more and 1 cm or less. As an example, the thickness T3 of the third resin 46 in FIG. 3 is 1 mm or more. If the thickness T3 of the third resin 46 is large, the second resin 44 may be deformed due to the weight of the third resin 46. By making the second resin 44 thicker than the third resin 46, the deformation of the second resin 44 can be suppressed. The third resin 46 in this example is separated from the semiconductor chip 40, the lead frame 50, and the circuit board 20. That is, the third resin 46 in this example does not contact any of the upper surface, lower surface, or side surface of the semiconductor chip 40, the lead frame 50, and the circuit board 20. The third resin 46 in this example does not contact any of the upper surface, lower surface, or side surface of the insulating substrate 21. The third resin 46 in this example does not contact any of the upper surface, lower surface, or side surface of the heat sink 22. The third resin 46 in this example does not contact any surface of the circuit pattern 26.

[0040] Fig. 4 is a diagram showing an example of a semiconductor module 200 as viewed from above. Fig. 4 shows the resin case 10 and the sealing resin 12 as in Fig. 2. In Fig. 2, the third resin 46 of the sealing resin 12 is exposed as viewed from above. Note that external terminals (not shown) may also be exposed from the sealing resin 12.

[0041] Fig. 5 is a diagram showing an example of a semiconductor module 300 according to an embodiment of the present invention. The semiconductor module 300 in Fig. 5 differs from the semiconductor module 200 in Fig. 3 in that a buffer layer 48 is provided between the side wall 18 and the sealing resin 12. Other configurations in Fig. 5 may be the same as those in Fig. 3.

[0042] The buffer layer 48 may surround the first resin 42, the second resin 44, and the third resin 46 in a top view. The buffer layer 48 may be provided to cover a surface of the side wall 18 that faces the space 94. In other words, by providing the buffer layer 48, the first resin 42, the second resin 44, and the third resin 46 do not contact the side wall 18.

[0043] The elastic modulus of the buffer layer 48 may be smaller than that of the second resin 44. In other words, the elastic modulus of the buffer layer 48 may be smaller than that of any of the first resin 42, the second resin 44, and the third resin 46. By providing the buffer layer 48 having an elastic modulus smaller than that of the second resin 44, when the semiconductor module 300 is deformed as a whole, the buffer layer 48 follows the deformation. Therefore, it is possible to prevent the sealing resin 12 from peeling off from the side wall 18.

[0044] When the first resin 42, the second resin 44, and the third resin 46 each contain an epoxy resin as a main component, the buffer layer 48 contains, for example, a silicone gel as a main component. The main component is a component that has the largest content (wt%) in the resin. By including the silicone gel in the buffer layer 48, the elastic modulus of the buffer layer 48 can be made smaller than the elastic modulus of the second resin 44.

[0045] In the Z-axis direction, the thickness T4 of the buffer layer 48 may be the same as the total thickness (T1+T2+T3) of the first resin 42, the second resin 44, and the third resin 46. It is also preferable that the buffer layer 48 does not contact the wires 27, the semiconductor chip 40, and the lead frame 50. The width W of the buffer layer 48 may be 5 mm or less. The width W of the buffer layer 48 may be 3 mm or less. The width W of the buffer layer 48 may be 1 mm or less. By reducing the width W of the buffer layer 48, it is possible to configure the buffer layer 48 so that it does not cover the wires 27, the semiconductor chip 40, and the lead frame 50.

[0046] Fig. 6 is a diagram showing an example of a semiconductor module 300 as viewed from above. Fig. 6 shows the resin case 10 and the sealing resin 12 as in Fig. 2. In Fig. 6, the third resin 46 and the buffer layer 48 of the sealing resin 12 are exposed as viewed from above. Note that external terminals (not shown) may also be exposed from the sealing resin 12.

[0047] 6, the buffer layer 48 surrounds the third resin 6 in a top view. The buffer layer 48 has a width W in a top view and surrounds the third resin 46. The buffer layer 48 is also provided opposite the sidewall 18, including the inner sidewall 17.

[0048] 7 is a diagram showing an example of a method for forming the sealing resin 12. The method for forming the sealing resin 12 includes a first resin introducing step S101, a first resin temporary curing step S102, a second resin introducing step S103, a second resin temporary curing step S104, a third resin introducing step S105, a third resin temporary curing step S106, and a main curing step S107.

[0049] In the first resin introducing step S101, the first resin 42 is introduced into the resin case 10. In the first resin introducing step S101, the first resin 42 is introduced so as to cover the wires 27, the semiconductor chip 40, and the lead frame 50.

[0050] In the first resin provisionally curing step S102, the first resin 42 is provisionally cured. In the first resin provisionally curing step S102, the first resin 42 is not completely cured. The temperature in the first resin provisionally curing step S102 is, for example, 50° C. to 65° C. In the first resin provisionally curing step S102, gas is generated from the first resin 42.

[0051] In the second resin introducing step S103, the second resin 44 is introduced into the resin case 10. In the second resin introducing step S103, the second resin 44 is introduced above the first resin 42. Since the first resin 42 is provisionally cured, the second resin 44 can be provided above.

[0052] In the second resin provisionally curing step S104, the second resin 44 is provisionally cured. In the second resin provisionally curing step S104, the first resin 42 and the second resin 44 are not completely cured. The temperature in the second resin provisionally curing step S104 is, for example, 50° C. to 65° C. In the second resin provisionally curing step S104, gas is generated from the second resin 44.

[0053] In a third resin introducing step S105, a third resin 46 is introduced into the resin case 10. In the third resin introducing step S105, the third resin 46 is introduced so as to fill the space 94 above the second resin 44. Since the second resin 44 is provisionally cured, it is possible to provide the third resin 46 at the top.

[0054] In the third resin provisionally curing step S106, the third resin 46 is provisionally cured. In the third resin provisionally curing step S106, the first resin 42, the second resin 44, and the third resin 46 are not completely cured. The temperature in the third resin provisionally curing step S106 is, for example, 50° C. to 65° C. In the third resin provisionally curing step S106, gas is generated from the third resin 46.

[0055] In the main curing step S107, the sealing resin 12 is main cured. Main curing refers to curing the sealing resin 12 at a temperature higher than that of the temporary curing. The temperature of the main curing step S107 is, for example, 185° C. In the main curing step S107, gas is also generated from the sealing resin 12. By carrying out the main curing step S107, the sealing resin 12 can be completely cured.

[0056] When forming the sealing resin 12 of the semiconductor module 100, the third resin introducing step S105 and the third resin provisional curing step S106 do not need to be performed. In this case, in the second resin introducing step S103, the second resin 44 is introduced so as to fill the space 94.

[0057] 8 is a diagram showing an example of a method for forming the sealing resin 12 of the semiconductor module 300. The method for forming the sealing resin 12 of the semiconductor module 300 includes a frame providing step S201, an inner resin introducing step S202, an inner resin hardening step S203, a frame removing step S204, a buffer layer introducing step S205, and a buffer layer hardening step S206.

[0058] In a frame setting step S201, a frame 60 (see FIG. 9) is set in the resin case 10. The frame 60 is provided so as to surround the areas where the first resin 42, the second resin 44, and the third resin 46 are introduced. The frame 60 may or may not be set in contact with the side wall 18.

[0059] In the inner resin introducing step S202 and the inner resin curing step S203, the first resin 42, the second resin 44, and the third resin 46 are introduced and cured. That is, in the inner resin introducing step S202 and the inner resin curing step S203, the first resin introducing step S101, the first resin provisional curing step S102, the second resin introducing step S103, the second resin provisional curing step S104, the third resin introducing step S105, the third resin provisional curing step S106, and the main curing step S107 in Fig. 7 may be performed. In this example, the first resin 42, the second resin 44, and the third resin 46 are introduced inside the frame 60.

[0060] In the frame removing step S204, the frame 60 is removed. By removing the frame 60, gaps are generated between the first resin 42, the second resin 44, and the third resin 46 and the resin case 10.

[0061] In the buffer layer introducing step S205, the buffer layer 48 is introduced. In this example, the buffer layer 48 is introduced into the gaps between the first resin 42, the second resin 44, and the third resin 46 and the resin case 10.

[0062] In the buffer layer curing step S206, the buffer layer 48 is cured. The temperature in the buffer layer curing step S206 is, for example, 185°C.

[0063] Fig. 9 is a diagram showing an example of the semiconductor module 300 in the inner resin curing step S203. In this example, the frame 60 is not installed in contact with the side wall 18. As shown in Fig. 9, the first resin 42, the second resin 44, and the third resin 46 are provided inside the frame 60. After the frame 60 is removed in the frame removing step S204, a buffer layer 48 is introduced between the first resin 42, the second resin 44, and the third resin 46 and the resin case 10 in the buffer layer introducing step S205.

[0064] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention. [Explanation of symbols]

[0065] 10 resin case, 12 sealing resin, 16 cooler, 17 inner side wall, 18 side wall, 20 circuit board, 21 insulating board, 22 heat sink, 24 bonding layer, 26 circuit pattern, 27 wire, 30 bonding layer, 40 semiconductor chip, 42 first resin, 44 second resin, 46 third resin, 48 buffer layer, 50 lead frame, 52 chip connection portion, 54 bridging portion, 56 circuit pattern connection portion, 60 frame, 84 through hole, 94 space, 100 semiconductor module, 200 semiconductor module, 300 semiconductor module

Claims

1. A circuit board having a predetermined circuit pattern; A semiconductor chip mounted on the circuit board; a wiring member that connects the semiconductor chip and the circuit pattern; a sealing resin that seals the semiconductor chip and the wiring member; Equipped with The sealing resin is a first resin including an inorganic filler and an epoxy resin and covering the semiconductor chip; a second resin having a smaller elastic modulus than the first resin, the second resin being provided on a surface of the first resin; having the second resin is spaced from the semiconductor chip and the circuit board; The second resin has a lower yield stress than the first resin. Semiconductor module.

2. A circuit board having a predetermined circuit pattern; A semiconductor chip mounted on the circuit board; a wiring member that connects the semiconductor chip and the circuit pattern; a sealing resin that seals the semiconductor chip and the wiring member; Equipped with The sealing resin is a first resin including an inorganic filler and an epoxy resin and covering the semiconductor chip; a second resin having a smaller elastic modulus than the first resin, the second resin being provided on a surface of the first resin; having the second resin is spaced from the semiconductor chip and the circuit board; the second resin includes an epoxy resin; The second resin has a smaller content (wt%) of inorganic filler than the first resin. Semiconductor module.

3. A circuit board having a predetermined circuit pattern; A semiconductor chip mounted on the circuit board; a wiring member that connects the semiconductor chip and the circuit pattern; a sealing resin that seals the semiconductor chip and the wiring member; a resin case having a side wall and surrounding a space for accommodating the semiconductor chip; Equipped with The sealing resin is a first resin including an inorganic filler and an epoxy resin and covering the semiconductor chip; a second resin having a smaller elastic modulus than the first resin, the second resin being provided on a surface of the first resin; having the second resin is spaced from the semiconductor chip and the circuit board; the sealing resin is provided inside the resin case, a buffer layer between the side wall and the sealing resin; The buffer layer has a smaller elastic modulus than the second resin and is in contact with the first resin. Semiconductor module.

4. A circuit board having a predetermined circuit pattern; A semiconductor chip mounted on the circuit board; a wiring member that connects the semiconductor chip and the circuit pattern; a sealing resin that seals the semiconductor chip and the wiring member; Equipped with The sealing resin is a first resin including an inorganic filler and an epoxy resin and covering the semiconductor chip; a second resin provided on a surface of the first resin and having a smaller elastic modulus than the first resin; a third resin including an inorganic filler and an epoxy resin and having a higher elastic modulus than the second resin and provided on a surface of the second resin; having the second resin is spaced from the semiconductor chip and the circuit board; The third resin has a smaller inorganic filler content (wt%) than the first resin. Semiconductor module.

5. The thickness of the third resin is 1 mm or more, The second resin is thicker than the third resin. The semiconductor module according to claim 4 .

6. the wiring member is a lead frame, the first resin covers the lead frame; The second resin is spaced from the lead frame. The semiconductor module according to claim 1 .

7. The first resin has a larger volume than the second resin. The semiconductor module according to claim 1 .

8. The first resin contains the inorganic filler in an amount of 50 wt % or more. The semiconductor module according to claim 1 .

9. The second resin includes silicone gel or silicone rubber. The semiconductor module according to claim 3 .

10. Further comprising a cooler connected directly or indirectly to the circuit board; The second resin is provided on a surface of the first resin opposite to the cooler. The semiconductor module according to claim 3 .

11. The first resin is thicker than the second resin. The semiconductor module according to claim 3 or 10.

12. The thickness of the second resin is 1 mm or more and 1 cm or less. The semiconductor module according to claim 3 , 10 or 11 .

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