Semiconductor Device

Abstract

To suppress the occurrence of damage and prevent the lowering of insulation resistance.SOLUTION: A first wiring member 71 is bent in an L-shape in a side view at a first bent portion 71c, and includes a first horizontal portion 71a parallel to a main surface of the semiconductor chip and a first vertical portion 71b vertical to the first horizontal portion 71a. A second wiring member 72 is bent in an L-shape at a second bent portion 72c, in a direction opposite to the first wiring member 71 in a side view, and includes a second horizontal portion 72a that is coplanar with the first horizontal portion 71a, and a second vertical portion 72b that is parallel to the first vertical portion 71b and is spaced apart from the first vertical portion 71b by a predetermined distance. Furthermore, a wire holding portion 73 is filled in the gaps between the first and second vertical portions 71b and 72b, and in the gaps between the first and second bent portions 71c and 72c. Because of this, stresses can be mitigated which are generated in the vicinity of the first and second bent portions 71c and 72c.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] The semiconductor device includes a power device and is used, for example, as a power conversion device constituting an inverter. The power device is, for example, an IGBT (Insulated Gate Bipolar Transistor) or a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The semiconductor device includes a semiconductor chip including the power device and a plurality of insulated circuit boards. The semiconductor device further includes a plurality of lead frames electrically connected to the semiconductor chip. As the frequency of the power conversion device increases, it is required to reduce the inductance generated from such a plurality of lead frames. In order to reduce the inductance, for example, it has been proposed to form the first power supply potential output electrode (lead frame), the load electrode, and the second power supply potential output electrode (lead frame) constituting the internal electrodes into plate shapes and arrange them close to each other with an insulator between them. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2004-214452 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the above semiconductor device, a high voltage is applied between the lead frames. Therefore, the lead frames need to be insulated with an insulator. Furthermore, when one end is exposed, the insulator needs to be in close contact with the lead frames to prevent moisture from entering the semiconductor device. However, when the insulator is a resin, damage such as cracks and peeling may occur in the resin if the lead frames are arranged close to each other. If damage occurs to the resin that insulates the lead frames, the insulation of the lead frames may not be maintained. As a result, the reliability of the semiconductor device may be reduced.

[0005] The present invention has been made in view of the above-mentioned circumstances, and has an object to provide a semiconductor device capable of suppressing the occurrence of damage and preventing a decrease in dielectric strength. [Means for solving the problem]

[0006] According to one aspect of the present invention, there is provided a semiconductor device comprising: a first semiconductor chip and a second semiconductor chip; a wiring unit having a first wiring member, one end of which is electrically connected to the first semiconductor chip; a second wiring member, one end of which is electrically connected to the second semiconductor chip; and a wiring holding portion that includes a portion of each of the first wiring member and the second wiring member, wherein the first wiring member is bent in an L-shape at a first bend in a side view and includes a first horizontal portion parallel to a main surface of the first semiconductor chip and a first vertical portion perpendicular to the first horizontal portion, and the second wiring member is bent in an L-shape at a second bend in a direction opposite to the first wiring member in a side view and includes a second horizontal portion that forms the same plane as the first horizontal portion and a second vertical portion that is parallel to the first vertical portion with a predetermined distance between them and the first vertical portion, and the wiring holding portion fills a gap between the first vertical portion and the second vertical portion and a gap between the first bend and the second bend. Effect of the Invention

[0007] According to the disclosed technique, it is possible to suppress the occurrence of damage, prevent a decrease in dielectric strength, prevent breakage of the semiconductor device, and suppress a decrease in the reliability of the semiconductor device. [Brief description of the drawings]

[0008] [Figure 1] 1 is an external view of a semiconductor device according to a first embodiment; [Diagram 2] 1 is a plan view of a semiconductor device according to a first embodiment. [Diagram 3] 1 is a side cross-sectional view of a semiconductor device according to a first embodiment. [Figure 4] 1 is a plan view of an insulating circuit substrate included in the semiconductor device of the first embodiment. [Diagram 5] FIG. 2 is a diagram illustrating an equivalent circuit of the semiconductor device according to the first embodiment. [Figure 6] 1 is a diagram (part 1) of a wiring member of a wiring unit included in the semiconductor device of the first embodiment; [Figure 7] 4 is a diagram (part 2) of a wiring member of a wiring unit included in the semiconductor device of the first embodiment. FIG. [Figure 8] 2 is a cross-sectional view of a main part of a wiring unit included in the semiconductor device of the first embodiment. FIG. [Figure 9] 11 is a cross-sectional view of a main part of a wiring unit included in a semiconductor device according to a first modified example of the first embodiment. FIG. [Figure 10] 11 is a cross-sectional view of a main part of a wiring unit included in a semiconductor device according to a second modification of the first embodiment. FIG. [Figure 11] 13 is a cross-sectional view of a main part of a wiring unit included in a semiconductor device according to a third modification of the first embodiment. FIG. [Figure 12] 13 is a diagram of a wiring unit included in a semiconductor device according to a second embodiment. FIG. [Figure 13] FIG. 13 is a plan view of a wiring unit included in a semiconductor device according to a second embodiment. [Figure 14] 13 is a perspective view of a main portion of first and second wiring members of a wiring unit included in a semiconductor device according to a third embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the embodiment will be described with reference to the drawings. In the following description, the "front surface" and "upper surface" refer to the XY surface facing upward (+Z direction) in the semiconductor device 10 in the figure. Similarly, "up" refers to the upward (+Z direction) direction in the semiconductor device 10 in the figure. The "rear surface" and "lower surface" refer to the XY surface facing downward (-Z direction) in the semiconductor device 10 in the figure. Similarly, "lower" refers to the downward (-Z direction) direction in the semiconductor device 10 in the figure. Similar orientations are used in other figures as necessary. The terms "front surface", "upper surface", "upper", "rear surface", "lower surface", "lower", and "side surface" are merely convenient expressions for identifying relative positional relationships and do not limit the technical idea of ​​the present invention. For example, "upper" and "lower" do not necessarily mean a vertical direction relative to the ground. In other words, the directions of "upper" and "lower" are not limited to the direction of gravity. In the following description, the term "main component" refers to a case in which the component contains 80 vol% or more.

[0010] [First embodiment] The appearance of the semiconductor device of the first embodiment will be described with reference to Fig. 1. Fig. 1 is an appearance diagram of the semiconductor device of the first embodiment. In the semiconductor device 10, components to be described later are covered in a case 60 as shown in Fig. 1. A heat sink 30 having a rectangular shape in a plan view is provided on the back surface of the semiconductor device 10 (the back side of the case 60) (see Fig. 3).

[0011] The case 60 includes a lid 61, side walls 62a to 62d, and terminal ports 63 and 64. The lid 61 further includes terminal blocks 61a, 61b, and 61c formed in the center along the longitudinal direction. Screw holes 61a1, 61b1, and 61c1 are formed on the front surfaces of the terminal blocks 61a, 61b, and 61c. The terminal blocks 61a, 61b, and 61c have first, second, and third wiring members 71, 72, and 74 extending upward. Note that FIG. 1 shows a case in which the first, second, and third wiring members 71, 72, and 74 extend upward. The extending first, second and third wiring members 71, 72 and 74 are bent toward the front surface side of the terminal blocks 61a, 61b and 61c, and the opening holes formed in the first, second and third wiring members 71, 72 and 74 correspond to the screw holes 61a1, 61b1 and 61c1, and the screw holes 61a1, 61b1 and 61c1 are screwed through the respective opening holes.

[0012] The side walls 62a to 62d surround the heat sink 30 on all four sides. That is, the side walls 62a to 62d surround the components arranged on the heat sink 30 (see FIG. 2). The side walls 62a to 62d are fixed to the heat sink 30 with an adhesive. The terminal openings 63 and 64 are provided on the side wall 62c. The control terminals 75 and 76 are exposed from the terminal openings 63 and 64, respectively. Fixing holes 65 are formed near the corners of the area surrounded by the side walls 62a to 62d, respectively. When the semiconductor device 10 is mounted in a desired position, it can be fixed with screws through the fixing holes 65.

[0013] The side walls 62a to 62d, the terminal ports 63, 64, and the fixing hole 65 included in the case 60 are formed by integral molding using resin. The lid 61 is also formed by integral molding using resin. Such resin is mainly composed of thermoplastic resin. The thermoplastic resin is, for example, polyphenylene sulfide resin, polybutylene terephthalate resin, polybutylene succinate resin, polyamide resin, or acrylonitrile butadiene styrene resin. The case 60 may have the lid 61 formed separately attached to the openings of the side walls 62a to 62d by adhesive.

[0014] Next, components housed in the semiconductor device 10 will be described with reference to FIGS. 2 to 8. FIG. 2 is a plan view of the semiconductor device of the first embodiment, and FIG. 3 is a side cross-sectional view of the semiconductor device of the first embodiment. FIG. 4 is a plan view of an insulating circuit board included in the semiconductor device of the first embodiment. FIG. 5 is a diagram showing an equivalent circuit of the semiconductor device of the first embodiment. FIGS. 6 and 7 are diagrams of wiring members of a wiring unit included in the semiconductor device of the first embodiment. FIG. 8 is a cross-sectional view of a main part of a wiring unit included in the semiconductor device of the first embodiment. Note that FIG. 2 shows a case where the cover portion 61 is removed from the case 60 of the semiconductor device 10 and the sealing member 80 is omitted. Also, FIGS. 2 and 3 show the control terminals 75, 76, the terminal openings 63, 64, and the fixing hole 65. FIGS. 2 and 3 show a case where the first wiring member 71, the second wiring member 72, and the third wiring member 74 are bent. FIG. 3 is a cross-sectional view taken along the dashed line XX in FIG. 2. In addition, in Fig. 3, the terminal blocks 61a, 61b, 61c, etc. of the cover portion 61 are omitted for simplicity. Fig. 6 omits a part of the first and second leg portions 71d, 72d of the first and second wiring members 71, 72. Fig. 7(A) is a perspective view of the first and second vertical portions 71b, 72b and the first and second horizontal portions 71a, 72a of the first and second wiring members 71, 72. Fig. 7(B) is a cross-sectional view taken along the arrow C in Fig. 7(A).

[0015] 2 to 4, the semiconductor device 10 includes insulating circuit boards 20a and 20b, and a heat sink 30 on the front surface of which the insulating circuit boards 20a and 20b are provided. Semiconductor chips 41a to 44a and 41b to 44b are disposed on the insulating circuit boards 20a and 20b, respectively. The semiconductor device 10 also includes first to third wiring members 71, 72, and 74. The first to third wiring members 71, 72, and 74 are, for example, plate-shaped lead frames.

[0016] The case 60 is provided on the periphery of the heat sink 30 and has side walls 62a to 62d surrounding the insulating circuit boards 20a and 20b, and a lid 61 provided on the upper opening of the side walls 62a to 62d. The semiconductor chips 41a to 44a, 41b to 44b, and the insulating circuit boards 20a and 20b (and the bonding wires 51a to 54a, 51b to 54b, 55, 56) are housed inside the case 60 and the heat sink 30. Furthermore, the semiconductor chips 41a to 44a, 41b to 44b, and the insulating circuit boards 20a and 20b (and the bonding wires 51a to 54a, 51b to 54b, 55, 56) are sealed with a sealing member 80. The lid 61 is provided with first to third wiring members 71, 72, and 74 for electrical connection with an external device. It should be noted that the control terminals 75 and 76 are not shown in the figure.

[0017] The first to third wiring members 71, 72, and 74 each have one end connected to the insulating circuit board 20a or the insulating circuit board 20b inside the case 60. The other end extends from the case 60 to the outside. The other end may be connected to an external device (not shown). Specifically, one end of the first wiring member 71 is electrically and mechanically connected to the conductive patterns 23a3 and 23a5 of the insulating circuit board 20a. Then, the first wiring member 71 is electrically connected to the semiconductor chips 41a, 42a, 43a, and 44a via the conductive patterns 23a3 and 23a5 and the conductive members of the bonding wires 53a and 54a. The first external connection portion 71e at the other end extends from the lid portion 61 to the outside of the case 60 and is exposed along the front surface of the lid portion 61. One end of the second wiring member 72 is electrically and mechanically connected to the conductive pattern 23b2 of the insulating circuit board 20b. The third wiring member 74 is electrically and mechanically connected to the conductive pattern 23a2 of the insulating circuit board 20a. The third wiring member 74 is electrically and mechanically connected to the semiconductor chips 41a, 42a, 43a, and 44a via the conductive pattern 23a2. ...e is electrically and mechanically connected to the conductive pattern 23a2 of the insulating circuit board 20a. The third wiring member 74e is electrically and mechanically connected to the conductive pattern 23a2 of the insulating circuit board 20a.

[0018] The wiring unit 70 includes first and second wiring members 71, 72 and a wiring holding portion 73. In the wiring unit 70, parts of the first and second wiring members 71, 72 are integrally molded with the wiring holding portion 73. In this case, insulation is maintained between the first and second wiring members 71, 72 by the wiring holding portion 73. The wiring unit 70 will be described in detail later.

[0019] The insulating circuit boards 20a and 20b include insulating plates 21a and 21b, metal plates 22a and 22b formed on the rear surfaces of the insulating plates 21a and 21b, and conductive patterns 23a1 to 23a5 and 23b1 to 23b5 formed on the front surfaces of the insulating plates 21a and 21b. The insulating plates 21a and 21b and the metal plates 22a and 22b are rectangular in plan view. The insulating plates 21a and 21b and the metal plates 22a and 22b may have corners chamfered into an R shape or a C shape. The size of the metal plates 22a and 22b is smaller than the size of the insulating plates 21a and 21b in plan view, and they are formed inside the insulating plates 21a and 21b.

[0020] The insulating plates 21a and 21b are mainly made of ceramics with good thermal conductivity. The ceramics are mainly made of aluminum oxide, aluminum nitride, or silicon nitride. The thickness of the insulating plates 21a and 21b is 0.2 mm or more and 2.5 mm or less.

[0021] The metal plates 22a and 22b are mainly composed of a metal having excellent thermal conductivity. Such metals are, for example, copper, aluminum, or an alloy containing at least one of these. The thickness of the metal plates 22a and 22b is 0.1 mm or more and 5.0 mm or less. The surfaces of the metal plates may be plated to improve corrosion resistance. Examples of plating materials used in this case include nickel, nickel-phosphorus alloy, and nickel-boron alloy.

[0022] The conductive patterns 23a1-23a5, 23b1-23b5 are mainly composed of a metal having excellent conductivity. Examples of such metals include copper, aluminum, and alloys containing at least one of these. The thickness of the conductive patterns 23a1-23a5, 23b1-23b5 is 0.1 mm or more and 5.0 mm or less. The surfaces of the conductive patterns 23a1-23a5, 23b1-23b5 may be plated to improve corrosion resistance. Examples of plating materials used in this case include nickel, nickel-phosphorus alloy, and nickel-boron alloy. The conductive patterns 23a1-23a5, 23b1-23b5 are obtained by forming a metal layer on the front surface of the insulating plates 21a and 21b and performing a process such as etching on the metal layer. Alternatively, the conductive patterns 23a1-23a5 and 23b1-23b5 cut out in advance from a metal layer may be pressure-attached to the front surfaces of the insulating plates 21a and 21b. Note that the shapes and numbers of the conductive patterns 23a1-23a5 and 23b1-23b5 shown in Figures 2-4 are merely examples.

[0023] For example, a DCB (Direct Copper Bonding) board or an AMB (Active Metal Brazed) board may be used as the insulating circuit board 20a, 20b having such a configuration. The insulating circuit board 20a, 20b can conduct heat generated in the semiconductor chips 41a to 44a, 41b to 44b to the outside via the conductive patterns 23a2, 23b2, the insulating plates 21a, 21b, and the metal plates 22a, 22b.

[0024] Moreover, one end (first leg 71d (see FIG. 3)) of the first wiring member 71 is connected to the conductive patterns 23a3 and 23a5 of the insulating circuit board 20a via solder (not shown). One end (second leg 72d (see FIG. 3)) of the second wiring member 72 is connected to the conductive pattern 23b2 of the insulating circuit board 20b via solder (not shown). One end (third leg 74d (see FIG. 3)) of the third wiring member 74 is connected to the conductive pattern 23a2 of the insulating circuit board 20a via solder (not shown). The squares shown on the conductive patterns 23a2, 23a3, 23a5, and 23b2 represent the bonding regions of the third, first, and second wiring members 74, 71, and 72, respectively.

[0025] The semiconductor chips 41a to 44a, 41b to 44b are mainly composed of silicon or silicon carbide. The semiconductor chips 41a, 42a, 41b, 42b are switching elements. The switching elements are, for example, IGBTs and power MOSFETs. The semiconductor chips 41a, 42a, 41b, 42b each have a drain electrode or a collector electrode as an input electrode (main electrode) on the back surface. The semiconductor chips 41a, 42a, 41b, 42b each have a gate electrode 41a1, 42a1, 41b1, 42b1 as a control electrode and a source electrode or an emitter electrode as an output electrode (main electrode) on the front surface. The semiconductor chips 41a, 42a, 41b, 42b each have a back surface bonded to the conductive patterns 23a2, 23b2 by solder (not shown).

[0026] The solder used to join the semiconductor chips 41a to 44a, 41b to 44b to the conductive patterns 23a2, 23b2 is lead-free solder. The lead-free solder is mainly composed of an alloy containing at least two of tin, silver, copper, zinc, antimony, indium, and bismuth. Furthermore, the solder may contain additives. A metal sintered body may be used instead of the solder. The material of the metal sintered body is mainly composed of silver or a silver alloy. Moreover, such solder and metal sintered body may be used not only for joining the semiconductor chips 41a to 44a, 41b to 44b to the conductive patterns 23a2, 23b2, but also for joining the first to third wiring members 71, 72, 74 to the conductive patterns 23a3, 23a5, 23b2, 23a2.

[0027] The semiconductor chips 43a, 44a, 43b, and 44b are diode elements. The diode elements are FWD (Free Wheeling Diode). Such diode elements include, for example, SBD (Schottky Barrier Diode) and PN junction diodes. Such semiconductor chips 43a, 44a, 43b, and 44b each have a cathode electrode as an output electrode (main electrode) on the back surface and an anode electrode as an input electrode (main electrode) on the front surface. The back surfaces of the semiconductor chips 43a, 44a, 43b, and 44b are joined to the conductive patterns 23a2 and 23b3 by solder (not shown). The semiconductor chips 41a to 44a, 41b to 44b may be RC (Reverse Conductive)-IGBT elements in which a switching element and a diode element are integrated into one semiconductor chip.

[0028] The following bonding wires 51a-54a, 51b-54b, 55, 56 are wired to the insulating circuit boards 20a, 20b and the semiconductor chips 41a-44a, 41b-44b. The bonding wires 51a, 52a, which are control wiring, are electrically connected to the conductive pattern 23a1 and the gate electrodes 41a1, 42a1 of the semiconductor chips 41a, 42a, respectively. The bonding wires 53a, 54a electrically connect the conductive patterns 23a3, 23a5 and the main electrodes of the semiconductor chips 41a, 42a and the main electrodes of the semiconductor chips 43a, 44a, respectively.

[0029] Bonding wires 51b and 52b, which are control wirings, are electrically connected to the conductive pattern 23b1 and the gate electrodes 41b1 and 42b1 of the semiconductor chips 41b and 42b, respectively. Bonding wires 53b and 54b electrically connect the conductive patterns 23b3 and 23b5 to the main electrodes of the semiconductor chips 41b and 42b and the main electrodes of the semiconductor chips 43b and 44b, respectively.

[0030] Bonding wires 55, 56 electrically connect conductive pattern 23a2 of insulating circuit board 20a to conductive patterns 23b3, 23b5 of insulating circuit board 20b, respectively. Bonding wires 51a-54a, 51b-54b, 55, 56 are made of metal such as aluminum or copper having excellent conductivity, or an alloy containing at least one of these metals. The diameter of control bonding wires 51a, 52a, 51b, 52b is, for example, 50 μm or more and 400 μm or less, and the diameter of main current bonding wires 53a, 54a, 53b, 54b, 55, 56 is, for example, 300 μm or more and 600 μm or less.

[0031] In such insulating circuit boards 20a, 20b, one end of the first wiring member 71 is bonded onto the conductive patterns 23a3, 23a5. The conductive patterns 23a3, 23a5 are bonded to the main electrodes on the front surfaces of the semiconductor chips 41a, 42a, 43a, 44a via bonding wires 53a, 54a. Therefore, the first wiring member 71 is electrically connected to the main electrodes of the semiconductor chips 41a, 42a, 43a, 44a, and a main current flows through the first wiring member 71.

[0032] Moreover, one end of the second wiring member 72 is joined onto the conductive pattern 23b2. The conductive pattern 23b2 is electrically connected to the main electrodes on the rear surfaces of the semiconductor chips 41b, 42b, 43b, and 44b. Therefore, the second wiring member 72 is electrically connected to the main electrodes of the semiconductor chips 41b, 42b, 43b, and 44b, and a main current flows through the second wiring member 72.

[0033] Moreover, one end of the third wiring member 74 is joined onto the conductive pattern 23a2. The conductive pattern 23a2 is electrically connected to the main electrodes on the rear surfaces of the semiconductor chips 41a to 44a. Therefore, the third wiring member 74 is electrically connected to the main electrodes of the semiconductor chips 41a to 44a, and a main current flows through the third wiring member 74.

[0034] Although detailed illustration is omitted, the control terminals 75 and 76 are electrically connected to the conductive patterns 23a1 and 23b1, respectively. A control signal input from the outside is input to the gate electrodes 41a1, 42a1, 41b1, and 42b1 of the semiconductor chips 41a, 42a, 41b, and 42b via the conductive patterns 23a1 and 23b1 and the bonding wires 51a, 52a, 51b, and 52b.

[0035] The heat sink 30 is plate-like and has a rectangular shape in a plan view. The heat sink 30 is mainly composed of a metal having excellent electrical conductivity. Examples of such metals include copper, aluminum, and an alloy containing at least one of these metals.

[0036] A cooling unit may be attached to the rear surface of the heat sink 30 of such a semiconductor device 10 via thermal grease. The thermal grease is, for example, silicone mixed with a metal oxide filler. This cooling unit is also mainly composed of a material with excellent thermal conductivity, and the surface may be plated as necessary. The cooling unit is, for example, a heat sink composed of multiple fins and a cooling device that uses water cooling. The heat sink 30 may be integrally formed with such a cooling unit.

[0037] As shown in FIG. 5, the semiconductor device 10 configures a half-bridge circuit including an upper arm portion A and a lower arm portion B. The upper arm portion A of the semiconductor device 10 includes an insulating circuit board 20b, bonding wires 51b-54b arranged on the insulating circuit board 20b, semiconductor chips 41b-44b, and a second wiring member 72. It further includes a conductive pattern 23a2 of the insulating circuit board 20a, and a third wiring member 74 arranged on the conductive pattern 23a2. The lower arm portion B of the semiconductor device 10 includes an insulating circuit board 20a, bonding wires 51a-54a arranged on the insulating circuit board 20a, semiconductor chips 41a-44a, and a first wiring member 72. It further includes a third wiring member 74. The two insulating circuit boards 20a and 20b are connected to each other by bonding wires 55 and 56. This connects the upper arm portion A and the lower arm portion B. In this way, the semiconductor device 10 can function as a half-bridge circuit including the upper arm portion A and the lower arm portion B.

[0038] In this case, in the semiconductor device 10, the wiring connecting the connection point P connected to the positive electrode of the external power supply (not shown) and the connection point C1 on the collector side of the semiconductor chips 41b and 42b corresponds to the second wiring member 72. That is, the second wiring member 72 is a P terminal constituting a positive input terminal in a half-bridge circuit. The wiring connecting the connection point M connected to a terminal of a load (not shown) and the connection points E1C2 on the emitter side of the semiconductor chips 41b and 42b and the collector side of the semiconductor chips 41a and 42a corresponds to the third wiring member 74. That is, the third wiring member 74 is an M terminal constituting an output terminal in a half-bridge circuit. The wiring connecting the connection point N connected to the negative electrode of the external power supply and the connection point E2 on the emitter side of the semiconductor chips 41a and 42a corresponds to the first wiring member 71. That is, the first wiring member 71 is an N terminal constituting a negative input terminal in a half-bridge circuit.

[0039] 3, the wiring unit 70 has first and second wiring members 71 and 72 and a wiring holder 73 that holds the first and second wiring members 71 and 72. The first and second wiring members 71 and 72 are plate-shaped lead frames. That is, the first and second wiring members 71 and 72 have main surfaces in the XY plane corresponding to the front and back surfaces of the semiconductor device 10 and the YZ plane corresponding to one opposing side surface of the semiconductor device 10. The first and second wiring members 71 and 72 have side surfaces in the XZ plane corresponding to the other opposing side surface of the semiconductor device 10.

[0040] 3 and 6, in the side view of the first wiring member 71 seen from a direction parallel to the main surface (Y direction), the first horizontal portion 71a and the first vertical portion 71b are bent into an L-shape at the first bent portion 71c. Specifically, one end of the first horizontal portion 71a and one end of the first vertical portion 71b are connected at the first bent portion 71c. The first horizontal portion 71a extends from the first bent portion 71c in a direction parallel to the main surface (XY plane) of the semiconductor chips 41a to 44a and the insulating circuit board 20a and in the opposite direction (-X direction) to the second wiring member 72. The first vertical portion 71b extends from the first bent portion 71c upward (+Z direction) perpendicular to the main surface (XY plane) of the semiconductor chips 41a to 44a and the insulating circuit board 20a. The first and second bent portions 71c and 72c have curved surfaces on the outer corners between the rear surfaces (surfaces facing the semiconductor chips 41a to 44a and 41b to 44b) of the first and second horizontal portions 71a and 72b and the surfaces facing the first and second vertical portions 71b and 72b. The curvature of the outer corner of the first bent portion 71c may be the same as the curvature of the outer corner of the second bent portion 72c. For example, the curvature of the outer corner of the first bent portion 71c is 1 / T1 with respect to the plate thickness T1 of the first wiring member 71. The curvature of the outer corner of the second bent portion 72c is 1 / T2 with respect to the plate thickness T2 of the second wiring member 72. Furthermore, the first wiring member 71 includes a first leg portion 71d and a first external connection portion 71e. The first horizontal portion 71a and the first vertical portion 71b are formed at a predetermined interval in the height direction (Z direction) between the insulating circuit board 20a and the lid portion 61 of the case 60. On the other hand, as described above, one end of the first wiring member 71 is electrically connected to the conductive patterns 23a3 and 23a5, and the other end extends from the lid portion 61 of the case 60 to the outside. The first leg portion 71d extends downward (-Z direction) from the other end of the first horizontal portion 71a and includes the one end connected to the conductive patterns 23a3 and 23a5. The first external connection portion 71e extends further upward (+Z direction) from the other end of the first vertical portion 71b with respect to the semiconductor chips 41a to 44a (insulating circuit board 20a) and includes the other end extending from the lid portion 61 of the case 60 to the outside. Note that FIG. 6 shows a case where the first external connection portion 71e extends upward.First external connection portion 71e may be exposed to the outside from lid portion 61 at the dashed line portion, bent, and extend parallel to the upper surface of lid portion 61 in the opposite direction to second wiring member 72 (−X direction).

[0041] As shown in Fig. 3 and Fig. 6, in the side view of the second wiring member 72 seen from the direction parallel to the main surface (Y direction), the second horizontal portion 72a and the second vertical portion 72b are bent into an L-shape at the second bent portion 72c. Specifically, one end of the second horizontal portion 72a and one end of the second vertical portion 72b are connected at the second bent portion 72c. The second horizontal portion 72a extends from the second bent portion 72c in parallel with the main surface (XY plane) of the semiconductor chips 41a to 44a and the insulating circuit board 20a in the opposite direction (+X direction) to the first wiring member 71. The second horizontal portion 72a forms the same plane as the first horizontal portion 71a. The second vertical portion 72b extends from the second bent portion 72c upward (+Z direction) perpendicular to the main surface (XY plane) of the semiconductor chips 41a to 44a and the insulating circuit board 20a. That is, the main surface of the second vertical portion 72b is parallel to the main surface of the first vertical portion 71b, and is formed with a predetermined distance therebetween. The gap between the main surface of the first vertical portion 71b and the main surface of the second vertical portion 72b may be set by the current and voltage applied to the first wiring member 71 and the second wiring member 72. The gap is preferably 0.25 mm or more and 4.0 mm or less. More preferably, it is 0.5 mm or more and 2.0 mm or less. If the gap is too small, the insulation between the first wiring member 71 and the second wiring member 72 may decrease, causing a short circuit. If the gap is too large, the inductance cannot be reduced. The width (length in the Y direction) of the second vertical portion 72b is shorter than the width (length in the Y direction) of the first vertical portion 71b. Such first and second vertical portions 71b, 72b are positioned so that their center lines perpendicular to the width direction coincide with each other in a plan view (see FIG. 13). In addition, this is not limited to the above, but it is sufficient that the width (length in the Y direction) of the first vertical portion 71b and the width (length in the Y direction) of the second vertical portion 72b are different. For example, the width (length in the Y direction) of the first vertical portion 71b may be shorter than the width (length in the Y direction) of the second vertical portion 72b. This suppresses the concentration of stress applied to the wiring holding portion 73 from the side surfaces of the first vertical portion 71b and the second vertical portion 72b, and further suppresses the occurrence of cracks in the wiring holding portion 73.

[0042] Further, the second wiring member 72 includes a first leg portion 71d, a first external connection portion 71e, and a coupling portion 72f. The second horizontal portion 72a and the second vertical portion 72b are formed at a predetermined interval in the height direction (Z direction) between the insulating circuit board 20a and the lid portion 61 of the case 60. On the other hand, as described above, the second wiring member 72 has one end electrically connected to the conductive pattern 23b2 and the other end extending from the lid portion 61 of the case 60 to the outside. The second leg portion 72d extends downward (-Z direction) from the other end of the second horizontal portion 72a and includes the one end connected to the conductive pattern 23b2. The second external connection portion 72e extends further upward (+Z direction) from the second vertical portion 72b with respect to the semiconductor chips 41b to 44b (insulating circuit board 20b) and includes the other end extending from the lid portion 61 of the case 60 to the outside. 6 shows a case where the second external connection portion 72e extends upward. The second external connection portion 72e may be exposed to the outside from the lid portion 61 at the broken line portion, bent, and extended in the opposite direction (+X direction) to the first wiring member 71 in parallel with the upper surface of the lid portion 61. The connecting portion 72f extends to the second vertical portion 72b in a direction away from the first vertical portion 71b. That is, the connecting portion 72f is parallel to the second horizontal portion 72a and connects the upper end of the second vertical portion 72b to the lower end of the second external connection portion 72e. Therefore, the first and second external connection portions 71e, 72e are spaced apart by a distance equal to the sum of the gap between the first and second vertical portions 71b, 72b and the length of the connecting portion 72f.

[0043] As shown in FIG. 7, the first and second wiring members 71, 72 have a bent portion 72c of the second wiring member 72 whose width (length in the Y direction) is shorter than the width (length in the Y direction) of the bent portion 71c of the first wiring member 71. The second horizontal portion 72a of the second wiring member 72 has a curved surface at a corner where the back surface (the XY plane facing the front surface of the insulating circuit board 20a) intersects with the side surface in the width direction (the XZ plane). For example, an R-shape having a predetermined curvature is formed. The curvature 1 / R in this case is, for example, the thickness T of the second horizontal portion 72a. 72a For 0.05 / T 72a Above, 0.5 / T 72a The following is the result.

[0044] 3 are merely examples. The first and second legs 71d, 72d may have any shape that allows them to be electrically connected to the conductive patterns 23a3, 23a5, and 23b2. The first and second external connection parts 71e, 72e may have any shape that allows them to be exposed from the lid 61 and electrically connected to an external device.

[0045] 3, the third wiring member 74 includes a third horizontal portion 74a parallel to the main surface of the semiconductor chips 41a-44a (insulated circuit board 20a), a third leg portion 74d, and a third external connection portion 74e perpendicular to the third horizontal portion 74a. The third wiring member 74 also has one end electrically connected to the conductive pattern 23a2 and the other end extending from the lid portion 61 of the case 60 to the outside. The third leg portion 74d includes the one end extending from the third horizontal portion 74a to the conductive pattern 23a2 and connected thereto. The third external connection portion 74e includes the other end extending upward from the third horizontal portion 74a toward the semiconductor chips 41a-44a (insulated circuit board 20a) and extending from the outside of the lid portion 61 of the case 60. FIG. 3 shows a case in which the third external connection portion 74e extends upward from the lid portion 61 and is bent towards the front surface of the lid portion 61.

[0046] The first to third wiring members 71, 72, 74 are mainly composed of a metal having excellent electrical conductivity. Examples of such metals include aluminum, copper, iron, nickel, and alloys containing at least one of these. The surfaces of the first to third wiring members 71, 72, 74 may also be plated to improve corrosion resistance. Examples of plating materials used in this case include nickel, nickel-phosphorus alloys, and nickel-boron alloys. The first to third wiring members 71, 72, 74 and the conductive patterns 23a3, 23a5, 23b2, 23a2 are bonded to each other using solder and a metal sintered body, as in the case of bonding the semiconductor chips 41a to 44a, 41b to 44b. The first to third wiring members 71, 72, 74 and the conductive patterns 23a3, 23a5, 23b2, 23a2 may also be bonded directly to each other using ultrasonic waves or lasers.

[0047] 8, the wiring holding portion 73 includes at least a first portion 73a filling the gap between the first vertical portion 71b and the second vertical portion 72b of the first and second wiring members 71 and 72 and the gap between the first bent portion 71c and the second bent portion 72c. It may further include the outer corners of the first and second bent portions 71c and 72c. The outer corners of the first and second bent portions 71c and 72c refer to the corners between the rear surfaces of the first and second horizontal portions 71a and 72a and the opposing surfaces of the first and second vertical portions 72a and 72b.

[0048] Furthermore, the wiring holding portion 73 includes a second portion 73b1 that includes the main surface of the first vertical portion 71b on the opposite side (-X side) to the second vertical portion 72b and the inner angle side of the first bent portion 71c. The wiring holding portion 73 also includes a second portion 73b2 that includes the main surface of the second vertical portion 72b on the opposite side (+X side) to the first vertical portion 71b and the inner angle side of the second bent portion 72c. Furthermore, the wiring holding portion 73 includes a part of the main surfaces of the first and second horizontal portions 71a and 72a of the first and second wiring members 71 and 72. As shown in FIG. 2, the wiring holding portion 73 may also cover the side surfaces of the first and second vertical portions 71b and 72b. Therefore, either one or both of the first and second vertical portions 71b and 72b may be completely included in the wiring holding portion 73. 3, the wiring holding portion 73 includes the connecting portion 72f of the second wiring member 72. In this manner, the included upper surface of the wiring holding portion 73 only needs to have a height sufficient to completely include the connecting portion 72f. The included lower surface 73a1 of the first portion 73a is flush with the lower surfaces of the first and second horizontal portions 71a and 72a.

[0049] Such a wiring holding portion 73 is made of a resin having insulating properties, for example, a thermoplastic resin. Such a resin is, for example, a polyphenylene sulfide resin, a polybutylene terephthalate resin, a polybutylene succinate resin, a polyamide resin, or an acrylonitrile butadiene styrene resin. In addition, an insulating ceramic filler may be added to such a resin. Such a ceramic filler is, for example, an oxide, a nitride, or a carbide. Specific examples of such a filler include silicon, aluminum, and boron.

[0050] In the wiring unit 70, the area where the first and second wiring members 71 and 72 are close to each other is enclosed by the wiring holding portion 73 as described above. Therefore, while maintaining the insulation of the first and second wiring members 71 and 72, it is possible to reduce stress on the wiring holding portion 73 in the vicinity of the first and second bent portions 71c and 72c where stress is likely to concentrate. This reduces the occurrence of damage such as cracks on the wiring holding portion 73 in the vicinity of the first and second bent portions 71c and 72c. In addition, the second external connection portion 72e of the second wiring member 72 is separated from the second vertical portion 72b by the connecting portion 72f. Therefore, when the second wiring member 72 is attached to the conductive pattern 23b2, the stress on the second bent portion 72c is reduced. This also contributes to reducing the occurrence of damage to the wiring holding portion 73 in the vicinity of the second bent portion 72c.

[0051] The first and second horizontal parts 71a and 72a extend in opposite directions. Therefore, the first and second leg parts 71d and 72d are spaced apart. Therefore, the first and second leg parts 71d and 72d are kept insulated because they are spaced apart, and do not need to be enclosed by the wiring holding part 73. Therefore, damage to the wiring holding part 73 near the first and second bent parts 71c and 72c can be reduced. Furthermore, the first and second external connection parts 71e and 72e above the enclosed upper surface of the wiring holding part 73 are kept insulated because they are spaced apart by the connecting part 72f. Therefore, the first and second external connection parts 71e and 72e do not need to be enclosed by the wiring holding part 73, and damage to the wiring holding part 73 near the first and second bent parts 71c and 72c can be reduced. In addition, the first and second horizontal portions 71a, 72a and the first and second leg portions 71d, 72d of the first and second wiring members 71, 72 that do not include the wiring holding portion 73 may be sealed by a sealing member 80, as described below.

[0052] In addition, the corners of the back surface of the second horizontal portion 72a of the second wiring member 72 are formed into a curved surface with a small curvature (see FIG. 7). This allows stress on the second horizontal portion 72a of the second wiring member 72 to be dispersed. This also contributes to reducing the occurrence of damage to the wiring holding portion 73 in the vicinity of the second horizontal portion 72a. By reducing the occurrence of damage to the wiring holding portion 73 in this manner, the insulation of the first and second wiring members 71 and 72, particularly in the vicinity of the first and second bent portions 71c and 72c, is maintained.

[0053] The sealing member 80 seals the insulating circuit boards 20a, 20b and the semiconductor chips 41a-44a, 41b-44b, and the bonding wires 51a-54a, 51b-54b, 55, 56 on the heat sink 30. While sealing these, the sealing member 80 fills the space above the first and second horizontal portions 71a, 72a of the first and second wiring members 71, 72 of the wiring unit 70 shown in Fig. 3 and below the upper inclusive surface of the wiring holding portion 73. More preferably, the sealing member 80 fills the wiring holding portion 73 up to the portion corresponding to the connecting portion 72f.

[0054] At this time, as described above, the wiring unit 70 includes the adjacent range of the first and second wiring members 71, 72 in the wiring holding portion 73. The first and second horizontal portions 71a, 72a and the first and second leg portions 71d, 72d of the first and second wiring members 71, 72 that are not included in the wiring holding portion 73 are sealed by the sealing member 80 and insulation is maintained. Furthermore, even if the first and second external connection portions 71e, 72e above the upper surface of the wiring holding portion 73 are not sealed by the sealing member 80, insulation is maintained because they are separated by the connecting portion 72f. Furthermore, the first and second external connection portions 71e, 72e extend outward from the lid portion 61 and are bent in opposite directions to each other and separated from each other, so insulation is maintained.

[0055] Furthermore, side walls 62a-62d of case 60 need to be taller than sealing member 80 so that they can be filled with sealing member 80. Therefore, side walls 62a-62d need to have a height that is equal to or greater than the height corresponding to insulating circuit boards 20a, 20b, 41a-44a, 41b-44b, and bonding wires 51a-54a, 51b-54b, 55, and 56.

[0056] The sealing member 80 used here is silicone gel. Alternatively, the sealing member 80 includes a thermosetting resin and a filler contained in the thermosetting resin. The thermosetting resin is, for example, an epoxy resin, a phenolic resin, or a maleimide resin. An example of such a sealing member 80 is an epoxy resin containing a filler. An inorganic material is used as the filler. Examples of inorganic materials include silicon oxide, aluminum oxide, boron nitride, and aluminum nitride.

[0057] The semiconductor device 10 includes the semiconductor chips 41a-44a, 41b-44b, and a wiring unit 70. The wiring unit 70 includes first and second wiring members 71, 72, one end of which is electrically connected to the semiconductor chips 41a-44a, 41b-44b, respectively, and a wiring holder including a part of the first and second wiring members 71, 72.

[0058] The first wiring member 71 is bent in an L-shape at a first bent portion 71c in a side view, and includes a first horizontal portion 71a parallel to the main surfaces of the semiconductor chips 41a to 44a and a first vertical portion 71b perpendicular to the first horizontal portion 71a. The second wiring member 72 is bent in an L-shape at a second bent portion 72c in a direction opposite to the first wiring member 71 in a side view, and includes a second horizontal portion 72a that is flush with the first horizontal portion 71a and a second vertical portion 72b that is parallel to the first vertical portion 71b with a predetermined distance between them. Furthermore, the wiring holder 73 fills the gap between the first and second vertical portions 71b and 72b, and the gap between the first and second bent portions 71c and 72c.

[0059] In such a semiconductor device 10, since the first and second bent portions 71c, 72c of the first and second wiring members 71, 72 are enclosed by the wiring holding portion 73, the insulation of the first and second wiring members 71, 72 can be ensured. In addition, stress occurring near the first and second bent portions 71c, 72c can be alleviated. Therefore, damage such as cracks to the wiring holding portion 73 is prevented, and the insulation of the first and second wiring members 71, 72 enclosed by the wiring holding portion 73 is maintained. In addition, the first and second horizontal portions 71a, 72a and the first and second leg portions 71d, 72d of the first and second wiring members 71, 72 not enclosed by the wiring holding portion 73 are spaced apart from each other and sealed by the sealing member 80, thereby maintaining insulation. Furthermore, the first and second external connection parts 71e, 72e above the upper enclosed surface of the wiring holding part 73 maintain their insulation because they are separated by the connecting part 72f even though they are not sealed by the sealing member 80. This suppresses a decrease in the dielectric strength of the wiring unit 70, prevents damage to the semiconductor device 10, and suppresses a decrease in reliability.

[0060] In the wiring unit 70 including such a semiconductor device 10, by increasing the distance between the enclosed lower surface 73a1 of the wiring holding part 73 and the first and second bent parts 71c, 72c, the stress generated near the first and second bent parts 71c, 72c can be further alleviated and the insulation properties can be improved. Various modified examples in which the distance between the enclosed lower surface 73a1 of the wiring holding part 73 and the first and second bent parts 71c, 72c is increased will be described below.

[0061] [Variation 1] The wiring unit 70 of the first modification will be described with reference to FIG. 9. FIG. 9 is a cross-sectional view of a main part of the wiring unit included in the semiconductor device of the first modification of the first embodiment. In the wiring unit 70 of the first modification, the included lower surface 73a1 of the first portion 73a of the wiring holding portion 73 protrudes toward the front surface of the insulating circuit boards 20a, 20b (in the -Z direction in FIG. 9) beyond the rear surfaces of the first and second horizontal portions 71a, 72a, compared to the wiring unit 70 of FIG. 8. The protrusion amount of the included lower surface 73a1 of the first portion 73a from the rear surfaces of the first and second horizontal portions 71a, 72a may be 50% or more and 200% or less of the gap between the main surface of the first vertical portion and the main surface of the second vertical portion 72b. For example, it is 0.25 mm or more and 4.0 mm or less. More preferably, it is 0.5 mm or more and 2.0 mm or less. Therefore, the distance between the enclosed lower surface 73a1 of the first portion 73a of the wiring holding portion 73 and the first and second bent portions 71c, 72c of the first and second wiring members 71, 72 can be made longer than that in the case of FIG. 8. The width of the first portion 73a in the X direction may be at least equal to or greater than the width W between the first and second bent portions 71c, 72c. In this way, the first portion 73a can be enclosed while ensuring a predetermined thickness in a direction perpendicular to the curved surface on the outer corner side of the first and second bent portions 71c, 72c. Therefore, the stress on the wiring holding portion 73 near the first and second bent portions 71c, 72c of the first and second wiring members 71, 72 is relaxed, and damage is less likely to occur. Therefore, the tolerance of damage occurrence in the wiring holding portion 73 of the wiring unit 70 can be improved. And, by suppressing the occurrence of damage, insulation is maintained.

[0062] [Variation 2] The wiring unit 70 of the second modification will be described with reference to FIG. 10. FIG. 10 is a cross-sectional view of a main part of the wiring unit included in the semiconductor device of the second modification of the first embodiment. In the wiring unit 70 of the second modification, the curvature of the first and second bent portions 71c, 72c of the first and second wiring members 71, 72 is made smaller than the curvature of the first and second bent portions 71c, 72c of the first and second wiring members 71, 72 included in the wiring unit 70 of FIG. 8. That is, in the wiring unit 70 of the second modification, the first and second bent portions 71c, 72c of the first and second wiring members 71, 72 draw a curve that is gentler than the first and second bent portions 71c, 72c of the first and second wiring members 71, 72 included in the wiring unit 70 of FIG. 8. For example, the curvature of the outer corner side of the first bent portion 71c is smaller than 1 / T1 with respect to the plate thickness T1 of the first wiring member 71. The curvature of the outer corner of the second bent portion 72c is smaller than 1 / T2 with respect to the plate thickness T2 of the second wiring member 72. Also, in this case, the curvature of the outer corner of the first bent portion 71c may be the same as the curvature of the outer corner of the second bent portion 72c. Therefore, the distance between the enclosed lower surface 73a1 of the first part 73a of the wiring holding portion 73 and the first and second bent portions 71c, 72c of the first and second wiring members 71, 72 can be made longer than in the case of FIG. 8. Therefore, the stress on the wiring holding portion 73 near the first and second bent portions 71c, 72c of the first and second wiring members 71, 72 is relaxed, and damage is less likely to occur. Therefore, the tolerance of damage occurrence in the wiring holding portion 73 of the wiring unit 70 can be improved. And, by suppressing the occurrence of damage, the insulation is maintained.

[0063] In addition, in the second modification, the enclosed lower surface 73a1 of the first portion 73a of the wiring holding portion 73 may be protruded toward the front surfaces of the insulating circuit boards 20a, 20b beyond the rear surfaces of the first and second horizontal portions 71a, 72a as in the first modification, as in the first modification. This makes it possible to further prevent damage to the wiring holding portion 73 of the wiring unit 70.

[0064] [Variation 3] The wiring unit 70 of the third modification will be described with reference to FIG. 11. FIG. 11 is a cross-sectional view of a main part of the wiring unit included in the semiconductor device of the third modification of the first embodiment. In the wiring unit 70 of the third modification, notches are formed on the gap sides of the first and second bent portions 71c and 72c of the first and second wiring members 71 and 72 of FIG. 8. Therefore, the distance between the enclosed lower surface 73a1 of the first part 73a of the wiring holding portion 73 and the first and second bent portions 71c and 72c of the first and second wiring members 71 and 72 can be made longer than that in FIG. 8. Therefore, the stress on the wiring holding portion 73 near the first and second bent portions 71c and 72c of the first and second wiring members 71 and 72 is relaxed, and damage is less likely to occur. Therefore, the tolerance to damage occurrence in the wiring holding portion 73 of the wiring unit 70 can be improved. And, by suppressing the occurrence of damage, insulation is maintained.

[0065] In the third modification, the enclosed lower surface 73a1 of the first portion 73a of the wiring holding portion 73 may be protruded toward the front surfaces of the insulating circuit boards 20a and 20b beyond the rear surfaces of the first and second horizontal portions 71a and 72a as in the first modification, as in the first modification. This can further prevent damage to the wiring holding portion 73 of the wiring unit 70.

[0066] [Second embodiment] A wiring unit 70 according to a second embodiment in which the range covered by the wiring holder 73 is different from that of the wiring unit 70 in Fig. 2 will be described with reference to Figs. 12 and 13. Figs. 12 and 13 are diagrams of a wiring unit included in a semiconductor device according to the second embodiment. Note that Figs. 12(A) and 12(B) are perspective views of the wiring unit 70 from different directions. Fig. 13 is a plan view of the wiring unit 70 according to the second embodiment from above (+Z direction).

[0067] In the wiring unit 70, openings 73c1 and 73c2 are formed at the outer edge of the second vertical portion 72b in the width direction (Y direction) with respect to the wiring holding portion 73 of the wiring unit 70 in Fig. 2. That is, the outer edge of the second vertical portion 72b in the width direction, which is included in the wiring holding portion 73, is exposed from the openings 73c1 and 73c2. The openings 73c1 and 73c2 are formed at the outer edge of the wiring holding portion 73 along the extension direction (Z direction) of the second vertical portion 72b. In this case, even if stress occurs at the outer edge in the width direction of the second vertical portion 72b of the second wiring member 72, the wiring holding portion 73 that includes the second wiring member 72 is opened by the openings 73c1 and 73c2, so the wiring holding portion 73 is not damaged. Therefore, it is possible to more effectively prevent the insulation of the wiring holding portion 73 from decreasing. In addition, since the first horizontal portion 71a and the first bent portion 71c of the first wiring member 71 are included in the wiring holding portion 73, the insulation between the first and second horizontal portions 71a and 72a of the first and second wiring members 71 and 72 is more appropriately maintained. Therefore, it is possible to more effectively prevent the insulation of the wiring holding portion 73 from decreasing than in the case of FIG. 2.

[0068] [Third embodiment] In the third embodiment, a case where at least one of the first and second vertical portions 71b, 72b of the first and second wiring members 71, 72 included in the wiring unit 70 is open will be described with reference to Fig. 14. Fig. 14 is a perspective view of the main parts of the first and second wiring members of the wiring unit included in the semiconductor device of the third embodiment. Note that Figs. 14(A) and (B) each show a different case.

[0069] In the second wiring member 72 of FIG. 14(A), a plurality of through holes 72b1 are formed as openings in the second vertical portion 72b of the second wiring member 72 of FIG. 6. The size, number, and position of the through holes 72b1 are merely examples. The through holes 72b1 can be formed to such an extent that the strength of the second vertical portion 72b is not reduced relative to the second vertical portion 72b. In addition, in the second wiring member 72 of FIG. 14(B), a plurality of through holes 72b1 are formed as openings in the outer edge portion in the width direction of the second vertical portion 72b of the second wiring member 72 of FIG. 6. The size, number, and position of the notch portion 72b2 are also merely examples. The notch portion 72b2 can be formed to such an extent that the strength of the second vertical portion 72b is not reduced relative to the second vertical portion 72b. Furthermore, such through holes 72b1 and cutout portions 72b2 are not limited to being formed in the second vertical portion 72b of the second wiring member 72, but may also be formed in the first vertical portion 71b of the first wiring member 71, or only in the first vertical portion 71b.

[0070] When the wiring holding portion 73 is integrally molded with the first and second wiring members 71 and 72, the material of the wiring holding portion 73 enters the through hole 72b1 and the notch portion 72b2. This improves the adhesion of the wiring holding portion 73 to the first and second wiring members 71 and 72, and suppresses misalignment of the wiring holding portion 73 with respect to the first and second wiring members 71 and 72 and misalignment between the first and second wiring members 71 and 72. This reduces stress on the wiring holding portion 73 near the first and second bent portions 71c and 72c of the first and second wiring members 71 and 72. This suppresses damage to the wiring holding portion 73 near the first and second bent portions 71c and 72c of the first and second wiring members 71 and 72, and maintains the insulation of the wiring unit 70. As a result, damage to the semiconductor device 10 can be prevented, and a decrease in reliability is suppressed. [Explanation of symbols]

[0071] 10 Semiconductor device 20a, 20b Insulated circuit board 21a, 21b Insulating plate 22a,22b Metal plate 23a1~23a5, 23b1~23b5 Conductive patterns 30 Heat sink 41a to 44a, 41b to 44b Semiconductor chips 41a1, 42a1, 41b1, 42b1 Gate electrode 51a to 54a, 51b to 54b, 55, 56 Bonding wire 60 cases 61 Lid 61a,61b,61c terminal block 61a1, 61b1, 61c1 screw holes 62a~62d Side wall part 63,64 Terminal port 65 Fixed hole 70 Wiring unit 71 First wiring member 71a 1st horizontal section 71b 1st vertical section 71c 1st bend 71d 1st leg 71e First external connection part 72 Second wiring member 72a 2nd horizontal section 72b 2nd vertical section 72b1 Through hole 72b2 Notch 72c 2nd bend 72d Second leg 72e Second external connection 72f Connection 73 Wiring holding part 73a Part 1 73a1 Inclusion lower surface 73b1 2nd part 73c1,73c2 opening 74 Third wiring member 74a 3rd horizontal section 74d 3rd leg 74e Third external connection part 75,76 Control terminal 80 Sealing member

Claims

1. a first semiconductor chip and a second semiconductor chip; a wiring unit including a first wiring member having one end electrically connected to the first semiconductor chip, a second wiring member having one end electrically connected to the second semiconductor chip, and a wiring holder including a part of each of the first wiring member and the second wiring member; Equipped with the first wiring member is bent in an L-shape at a first bent portion in a side view, and includes a first horizontal portion parallel to a main surface of the first semiconductor chip and a first vertical portion perpendicular to the first horizontal portion; the second wiring member is bent in an L-shape at a second bend portion in a direction opposite to the first wiring member in a side view, and includes a second horizontal portion that is flush with the first horizontal portion and a second vertical portion that is parallel to the first vertical portion with a predetermined distance therebetween, the wiring holding portion is filled in a gap between the first vertical portion and the second vertical portion and a gap between the first bent portion and the second bent portion; Semiconductor device.

2. The wiring holding portion further includes: the first bent portion is a corner between a surface of the first horizontal portion facing the first semiconductor chip and a surface of the first vertical portion facing the second vertical portion, the second horizontal portion includes a surface facing the second semiconductor chip and the second vertical portion includes a surface facing the first vertical portion, the second vertical portion including an outer corner of the second bent portion. The semiconductor device according to claim 1 .

3. The wiring holding portion further includes: the first vertical portion includes an opposite side of the second vertical portion; the second vertical portion includes an opposite side of the first vertical portion; 3. The semiconductor device according to claim 1 or 2.

4. a first conductive plate to which the first semiconductor chip is electrically connected; a second conductive plate to which the second semiconductor chip is electrically connected; a case that houses the first semiconductor chip, the second semiconductor chip, the first wiring member, the second wiring member, and the wiring unit; Further equipped with a first end of the first wiring member electrically connected to the first conductive plate and a first other end of the first wiring member extending to an outside of the case; a second end of the second wiring member electrically connected to the second conductive plate, and a second end of the second wiring member extending to the outside of the case; 4. The semiconductor device according to claim 1.

5. Filling the case, sealing the first semiconductor chip, the second semiconductor chip, the first conductive plate, the second conductive plate, a portion of the first wiring member, and a portion of the second wiring member; a sealing member having a sealing surface above the first horizontal portion and the second horizontal portion and below the inclusion upper surface of the wiring holding portion; The semiconductor device according to claim 4.

6. the first wiring member further includes a first leg portion extending from the first horizontal portion to the first conductive plate and including the first end portion connected to the first conductive plate, the second wiring member further includes a second leg portion extending from the second horizontal portion to the second conductive plate and including the second one end portion connected to the second conductive plate.

6. The semiconductor device according to claim 4.

7. the first wiring member includes a first external connection portion that extends upward with respect to the first semiconductor chip and includes the first other end portion that extends from the outside of the case; the second wiring member includes a second external connection portion that extends upward relative to the second semiconductor chip and includes the second other end portion that extends from the outside of the case; 7. The semiconductor device according to claim 4.

8. the second wiring member further includes a connecting portion extending from the second vertical portion in a direction away from the first vertical portion; 8. The semiconductor device according to claim 1.

9. The wiring holding portion further seals the connecting portion. The semiconductor device according to claim 8.

10. The predetermined distance between the first vertical portion and the second vertical portion is 0.25 mm or more and 4.0 mm or less.

10. The semiconductor device according to claim 1.

11. The second wiring member is a P terminal constituting an upper arm portion, The first wiring member is an N terminal constituting a lower arm portion. The semiconductor device according to claim 1 .

12. a lower surface of the wiring holding portion including the first bent portion and the second bent portion, the lower surface facing the first semiconductor chip and the second semiconductor chip, protruding toward the main surfaces of the first semiconductor chip and the second semiconductor chip with respect to the first horizontal portion and the second horizontal portion; The semiconductor device according to claim 1 .

13. a curvature of the first bent portion is smaller than 1 / T1 where T1 is a plate thickness of the first wiring member; a curvature of the second bent portion is smaller than 1 / T2 where T2 is a plate thickness of the second wiring member; 13. The semiconductor device according to claim 1.

14. The first bent portion and the second bent portion each have a notch formed on the gap side.

13. The semiconductor device according to claim 1.

15. In a plan view, a width of the first vertical portion is greater than a width of the second vertical portion.

15. The semiconductor device according to claim 1.

16. the wiring holding portion includes the entire second vertical portion and includes the first vertical portion except for an end portion in a width direction of the second vertical portion in a plan view; The semiconductor device according to claim 15.

17. A corner portion on a back side of an end surface in a width direction relative to the second horizontal portion in a plan view has a curved surface.

17. The semiconductor device according to claim 15 or 16.

18. A plurality of openings are formed in at least one of the first vertical portion and the second vertical portion.

18. The semiconductor device according to claim 1.

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