Semiconductor device and its manufacturing method

Abstract

To reduce variation in etching in a semiconductor device that comprises a via wiring line part for a lamination structure having an insulation layer and a wiring layer and performs electrical connection with a pattern wiring line.SOLUTION: A semiconductor device is formed in a stepped shape having a stepped part between piezoelectric layers 50 penetrating through each other and has a structure in which a partial portion of a wiring layer 40 of one layer of a plurality of wiring layers 40 that are arranged between the piezoelectric layers 50 constituting the stepped part is arranged around the stepped part. In other words, the semiconductor device has a multilayer structure in which a plurality of layers of the piezoelectric layer 50 are formed and a wiring layer of a more upper layer is formed at a position corresponding to an opening that is formed to a deep position of the piezoelectric layer 50 to expose a wiring layer of a lower layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, in which a via wiring portion is provided for electrically connecting to the pattern wiring in a laminated structure of an insulating layer such as a piezoelectric layer arranged on a semiconductor substrate and a wiring layer constituting the pattern wiring. [Background technology]

[0002] Conventionally, in semiconductor devices, an insulating layer such as a piezoelectric layer laminated on a semiconductor substrate and a via wiring portion are provided for the pattern wiring to achieve electrical connection with the pattern wiring. In such a configuration, after the piezoelectric layer and the pattern wiring are laminated on the semiconductor substrate, holes are opened in the piezoelectric layer by dry etching, and the via wiring portion is disposed in the hole to achieve electrical connection between the via wiring portion and the pattern wiring. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 9,055,372 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in dry etching, the difference in etching rate between the metal constituting the pattern wiring, such as Mo (molybdenum), and the material constituting the piezoelectric layer, such as ScAlN, is not very large, and the selectivity is small. For this reason, when dry etching is performed on a piezoelectric layer formed to a thickness of, for example, 1 mm or more, the etching variation cannot be absorbed, and the pattern wiring may be penetrated or the pattern wiring may not be reached. The amount of etching is controlled by detecting the etching end point based on the plasma emission intensity, but the end point cannot be detected with high accuracy, making it difficult to absorb the etching variation.

[0005] On the other hand, in the case of wet etching, the difference in etching rate between the metal constituting the pattern wiring and the material constituting the piezoelectric layer is large, and the selection ratio is large. For this reason, it is possible to first dry etch the piezoelectric layer to the extent that a thin piezoelectric layer remains on the pattern wiring, and then remove the thin remaining part by wet etching to open holes. However, since the thick piezoelectric layer is removed by dry etching, the thickness of the thin piezoelectric layer that remains varies due to etching variations, and the wet etching time may become long. In particular, in the case of wet etching, the etching rate is smaller than that of dry etching, so it takes time even if the part to be removed is thin. In addition, since the end point cannot be detected by the plasma emission intensity in wet etching, it is not possible to confirm that the pattern wiring has been reached.

[0006] In view of the above, an object of the present invention is to provide a structure and a manufacturing method thereof that can reduce etching variations in a semiconductor device that has a via wiring portion in a laminated structure of an insulating layer and a wiring layer to electrically connect to pattern wiring. [Means for solving the problem]

[0007] In order to achieve the above object, the semiconductor device described in claim 1 comprises a semiconductor substrate (10), a plurality of wiring layers (40) formed in a multilayer structure on the semiconductor substrate and constituting a wiring portion, a plurality of insulating layers (50) formed on each of the wiring layers (41, 42, 43) constituting the plurality of wiring layers and having a multilayer structure in which each layer (51, 52, 53) is repeatedly formed alternately with the wiring layers, and a plurality of via wiring portions (60) formed to cover the respective inner wall surfaces of a plurality of openings (50a to 50c) formed at different depths in the plurality of insulating layers and electrically connected to different layers in the plurality of wiring layers having the multilayer structure. Among the multiple openings, openings (50a, 50c) that penetrate two or more insulating layers in the multiple insulating layers are formed in a stepped shape having a stepped portion between the insulating layers through which they penetrate, and a portion (42a, 42c, 43a, 43c) of one wiring layer (42, 43) of the multiple wiring layers arranged between the insulating layers that form the stepped portion is arranged surrounding the stepped portion, and this portion is insulated from a portion (42b, 42d, 43b) that forms a wiring portion in the one wiring layer.

[0008] In this way, a stepped shape is formed between the penetrating insulating layers, and a part of one of the wiring layers among the wiring layers arranged between the insulating layers constituting the stepped portion is arranged to surround the stepped portion. In other words, a multi-layer structure is formed by forming multiple insulating layers, and an upper wiring layer is formed at a position corresponding to an opening formed deep in the insulating layer to expose the lower wiring layer.

[0009] In the case of such a structure, when forming an opening in an insulating layer, an upper layer among the multiple insulating layers is first etched until an upper wiring layer formed between the upper layer and the layer below it is reached, and when the upper wiring layer is reached, the upper wiring layer is removed, and then the lower layers among the insulating layers are removed until the lower wiring layer is reached.

[0010] In this way, the thickness of each layer becomes thinner than the total thickness of the insulating layer. Therefore, even if etching variations occur, the variations are due to the thickness of one of the insulating layers having a multi-layer structure, and are smaller than when the entire insulating layer is dry-etched at once. Therefore, even if etching variations occur, they can be suppressed within the range of the thickness of the upper wiring layer, and dry etching can be terminated before the upper wiring layer is penetrated. Then, if the insulating layer is removed until the lower wiring layer is reached after removing the upper wiring layer, the etching variations at that time will also be due to the thickness of one of the insulating layers having a multi-layer structure. Therefore, it is possible to prevent the lower wiring layer from being not reached or the lower wiring layer from being penetrated.

[0011] Therefore, in a semiconductor device in which a via wiring portion is provided in a laminated structure of an insulating layer and a wiring layer to electrically connect to the wiring layer, it is possible to achieve a structure in which etching variations can be reduced.

[0012] In addition, the manufacturing method of a semiconductor device described in claim 4 includes alternately stacking wiring layers (41, 42, 43) of a plurality of wiring layers (40) constituting a wiring portion and insulating layers (51, 52, 53) of a plurality of insulating layers (50) on a semiconductor substrate (10) to form a multilayer structure of the plurality of wiring layers and insulating layers, forming a plurality of openings (50a-50c) of different depths in the plurality of insulating layers, and forming a plurality of via wiring portions (60) electrically connected to different layers in the plurality of wiring layers having the multilayer structure by covering each of the plurality of openings. Forming the multiple openings means forming at least a first opening (50a) and a second opening (50b) having different depths, and includes etching an upper insulating layer (52) of the multiple insulating layers to reach an upper wiring layer (42) of the multiple wiring layers formed between the upper insulating layer (52) and an insulating layer (51) below the upper insulating layer, thereby forming a part of the first opening and forming a second opening; removing the upper wiring layer exposed in the part of the first opening to expose the lower insulating layer; and etching the lower insulating layer exposed by removing the upper wiring layer to reach a lower wiring layer (41) of the multiple wiring layers located below the upper wiring layer, thereby forming a step portion between the upper insulating layer and the lower insulating layer while forming the remaining part of the first opening.

[0013] In this way, when forming the first opening and the second opening in the insulating layer, the upper insulating layer among the multiple insulating layers is first etched until the upper wiring layer formed between the upper insulating layer and the insulating layer below it is reached. Then, when the upper wiring layer is reached, the upper wiring layer exposed in a part of the first opening is removed, and then the lower insulating layer is removed until the lower wiring layer is reached to form the remaining part of the first opening.

[0014] In this way, the thickness of each layer becomes thinner than the total thickness of the insulating layer. Therefore, even if etching variations occur, the variations are due to the thickness of one of the insulating layers having a multi-layer structure, and are smaller than when the entire insulating layer is dry-etched at once. Therefore, even if etching variations occur, they can be suppressed within the range of the thickness of the upper wiring layer, and dry etching can be terminated before the upper wiring layer is penetrated. Then, if the insulating layer is removed until the lower wiring layer is reached after removing the upper wiring layer, the etching variations at that time will also be due to the thickness of one of the insulating layers having a multi-layer structure. Therefore, it is possible to prevent the lower wiring layer from being not reached or the lower wiring layer from being penetrated.

[0015] Therefore, in a semiconductor device in which a via wiring portion is provided in a laminated structure of an insulating layer and a wiring layer to electrically connect to the wiring layer, a manufacturing method capable of reducing etching variations can be achieved.

[0016] Note that the reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and specific components described in the embodiments described below. [Brief description of the drawings]

[0017] [Figure 1] 1 is a diagram showing a cross-sectional configuration of a semiconductor device according to a first embodiment. [Diagram 2] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor device shown in FIG. [Diagram 3] 11A to 11C are cross-sectional views showing a state during a manufacturing process of a semiconductor device shown as a comparative example. [Figure 4] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor device according to a second embodiment. [Diagram 5] FIG. 13 is a diagram showing a cross-sectional configuration of a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0019] (First embodiment) First, the configuration of a semiconductor device according to a first embodiment will be described with reference to FIG.

[0020] 1, the semiconductor device of this embodiment is formed using a semiconductor substrate 10. A laminated structure of a wiring layer 40 and a piezoelectric layer 50 is formed on the semiconductor substrate 10 via an insulating film 20 and a seed layer 30, and a via wiring portion 60 is disposed in a portion where a hole is formed in the piezoelectric layer 50. A semiconductor device having such a structure is used for, for example, a microphone.

[0021] The semiconductor substrate 10 is made of Si (silicon) or the like, and has a thickness of, for example, 400 μm. When the semiconductor device is applied to a microphone or the like, the semiconductor substrate 10 has a structure in which recesses (not shown) are formed in desired locations so that a membrane is formed by the piezoelectric layer 50 or the like. When the semiconductor device is applied to a microphone or the like, when the membrane is vibrated based on external sound, a voltage is generated by the piezoelectric effect of the piezoelectric layer 50 based on the vibration, and the sound is detected by extracting the voltage.

[0022] The insulating film 20 is made of TEOS (tetraethoxysilane) or the like, and has a thickness of, for example, 2000 nm. This insulating film 20 provides insulation between the semiconductor substrate 10 and the wiring layer 40, etc. The seed layer 30 is made of AlN or the like, and has a thickness of, for example, 40 nm.

[0023] The wiring layer 40 is a metal conductor pattern constituting a pattern wiring having various wiring parts formed in a semiconductor device. The wiring layer 40 has a multi-layer structure. Various wiring parts are formed by electrically connecting desired parts of the wiring layer 40 of each layer constituting the multi-layer structure, and the pattern wiring having various wiring parts is constituted.

[0024] In this embodiment, the wiring layer 40 has a two-layer structure of a first wiring layer 41 and a second wiring layer 42. The first wiring layer 41 is formed on the surface of the seed layer 30, and is located below the piezoelectric layer 50. The second wiring layer 42 is formed inside the piezoelectric layer 50. The wiring layer 40 is made of a metal that serves as a wiring material, such as Mo. The thickness of the wiring layer 40, and in this embodiment, the thickness of the first wiring layer 41 and the second wiring layer 42, may be any thickness, but when the wiring layer 40 is made of Mo, the thickness is set to, for example, 25 to 100 nm.

[0025] The piezoelectric layer 50 constitutes an insulating layer and has a multi-layer structure formed of multiple layers, and in this embodiment, has a two-layer structure of a first insulating layer 51 and a second insulating layer 52. Specifically, the first insulating layer 51 is formed on the seed layer 30 and the first wiring layer 41, the second wiring layer 42 is formed on the first insulating layer 51, and the second insulating layer 52 is further formed thereon. The thickness of the piezoelectric layer 50, and in this embodiment, the thickness of the first insulating layer 51 and the second insulating layer 52 are arbitrary, but when the piezoelectric layer 50 is made of ScAlN, the thickness is set to, for example, 500 nm.

[0026] A first opening 50a is formed in the piezoelectric layer 50, penetrating from the surface of the second insulating layer 52 through the second insulating layer 52 and the first insulating layer 51 to reach the first wiring layer 41. In addition, a second opening 50b is formed in the piezoelectric layer 50, penetrating only the second insulating layer 52 from the surface of the second insulating layer 52 to reach the second wiring layer 42.

[0027] The first opening 50a is an opening for connecting a first via wiring portion 61 (to be described later) of the via wiring portion 60 to the first wiring layer 41. The second opening 50b is an opening for connecting a second via wiring portion 62 (to be described later) of the via wiring portion 60 to the second wiring layer 42.

[0028] The first opening 50a has a stepped shape, and the opening dimension is larger on the second insulating layer 52 side than on the first insulating layer 51 side, and a stepped portion is formed between the second insulating layer 52 and the first insulating layer 51. In this embodiment, the second wiring layer 42 is formed between the first insulating layer 51 and the second insulating layer 52 so as to surround the stepped portion formed between the second insulating layer 52 and the first insulating layer 51. Therefore, the periphery of the portion of the first opening 50a formed in the first insulating layer 51 is surrounded by a part 42a of the second wiring layer 42. The opening end of the first insulating layer 51 and the opening end of the second wiring layer 42 are shaped to coincide with each other.

[0029] The via wiring portion 60 is electrically connected to the wiring layer 40 through the first opening 50a and the second opening 50b formed in the piezoelectric layer 50. The thickness of the via wiring portion 60 is arbitrary, but when the via wiring portion 60 is made of Al (aluminum), the thickness is set to, for example, 25 to 100 nm.

[0030] In this embodiment, the via wiring portion 60 has a first via wiring portion 61 arranged to cover the inner wall surface of the first opening 50a, and a second via wiring portion 62 arranged to cover the inner wall surface of the second opening 50b. The first via wiring portion 61 is formed up to the bottom surface of the first opening 50a, that is, to the lowest position, and is electrically connected to the first wiring layer 41 at the bottom surface of the first opening 50a. The second via wiring portion 62 is formed up to the bottom surface of the second opening 50b, that is, to the middle position in the thickness direction of the piezoelectric layer 50, and is electrically connected to the second wiring layer 42 at the bottom surface of the second opening 50b.

[0031] The first via wiring portion 61 and the second via wiring portion 62 are electrically connected to different wiring portions constituted by the first wiring layer 41 and the second wiring layer 42. As described above, the portion 42a of the second wiring layer 42 is disposed between the first insulating layer 51 and the second insulating layer 52, and therefore the portion exposed therebetween may be in contact with the first via wiring portion 61. However, this portion 42a is insulated from the portion 42b of the second wiring layer 42 formed at the position of the second opening 50b. Therefore, the first via wiring portion 61 is electrically connected to the first wiring layer 41, and the second via wiring portion 62 is electrically connected to the portion 42b of the first wiring layer 41 and the second wiring layer 42 insulated from the portion 42a, and are electrically connected to different wiring portions.

[0032] Next, a method for manufacturing the semiconductor device configured as above will be described. In the method for manufacturing the semiconductor device, steps other than the steps of forming the wiring layer 40 and the piezoelectric layer 50, and the steps of forming the first opening 50a and the second opening 50b, may be similar to known methods, and therefore these steps will be mainly described.

[0033] First, the insulating film 20 and the seed layer 30 are formed on the semiconductor substrate 10, and then the process of forming the wiring layer 40 and the piezoelectric layer 50 is performed. That is, the first wiring layer 41 is formed on the seed layer 30, and the first wiring layer 41 is patterned by photoetching to form a pattern wiring of a part of the wiring part. Next, the first insulating layer 51 is formed, and the second wiring layer 42 is formed thereon, and the second wiring layer 42 is patterned by photoetching. As a result, the wiring part is formed by the part 42b of the second wiring layer 42. At this time, the part 42a of the second wiring layer 42 is left at a position corresponding to the planned position of the first opening 50a, that is, at a position corresponding to the first wiring layer 41. Then, the second insulating layer 52 is formed so as to cover the second wiring layer 42.

[0034] 2, photolithography and etching processes are performed on the intermediate via and the stepped portion. That is, an intermediate via and a second opening 50b are formed up to the middle position of the first opening 50a. First, a resist 100 is formed on the surface of the second insulating layer 52, opening at the planned position of the portion of the first opening 50a to be formed in the second insulating layer 52 and the planned position of the second opening 50b. The second insulating layer 52 is removed by dry etching, for example, plasma etching, using the resist 100 as a mask. Then, the second wiring layer 42 formed below the second insulating layer 52 is exposed, and the dry etching is completed.

[0035] At this time, in the case of dry etching, etching variations occur, making it difficult to detect the etching end point with high accuracy, and since the difference in etching rate between the second insulating layer 52 and the second wiring layer 42 is small, there is a concern that dry etching may not be performed properly.

[0036] However, by forming the piezoelectric layer 50 in a multi-layer structure as in this embodiment, the thickness of each layer is thinner than the overall thickness of the piezoelectric layer 50. In addition, the second wiring layer 42 serves as an etching stopper. Therefore, even if etching variations occur, the variations are caused by the thickness of one layer of the second insulating layer 52, and are smaller than when the entire piezoelectric layer 50 is dry-etched at once.

[0037] 3, when the first opening 50a is formed by dry etching the entire piezoelectric layer 50 at once, etching variations may occur according to the overall thickness of the piezoelectric layer 50. For this reason, as shown in the figure, when the dry etching time reaches a predetermined time, the first opening 50a may not yet reach the first wiring layer 41. Conversely, the first opening 50a may already reach the first wiring layer 41 and be formed to a depth that penetrates the first wiring layer 41.

[0038] In contrast, in this embodiment, dry etching is once performed only to the thickness of the second insulating layer 52, so that the dry etching can be terminated when the second wiring layer 42 is reliably reached. Even if the second wiring layer 42 is etched due to etching variations, the amount of etching can be kept within the range of the thickness of the second wiring layer 42, and the dry etching can be terminated before the second wiring layer 42 is penetrated.

[0039] After that, the resist 100 is removed, and then, as shown in FIG. 2, a photolithography process and an etching process are performed on the second wiring layer 42 in the step portion. First, a resist 101 is formed in which an opening is formed to expose the second wiring layer 42 located on the bottom surface of the first opening 50a. Then, dry etching, for example, plasma etching, or wet etching is performed using the resist 101 as a mask. As a result, the second wiring layer 42 exposed on the bottom surface of a part of the first opening 50a is entirely removed, and the first insulating layer 51 is exposed in the step portion. With regard to the portion 42a of the second wiring layer 42, the portion exposed from the first opening 50a is removed, but the portion formed between the first insulating layer 51 and the second insulating layer 52 remains without being etched. At this time, since the second wiring layer 42 is mainly removed, etching with a high selectivity to the first insulating layer 51 can be performed.

[0040] Furthermore, after removing the resist 101, a photolithography process and an etching process for the lower via are performed as shown in FIG. 2. That is, a lower via that becomes the lower part of the first opening 50a is formed. First, a resist 102 is formed with an opening that exposes a part of the surface of the first insulating layer 51 in the first opening 50a. That is, the resist 102 is arranged with an opening in the region where the remaining part to be formed in the first insulating layer 51 is to be formed in the first opening 50a. The first insulating layer 51 is removed by dry etching, for example, plasma etching, using the resist 102 as a mask. Then, the dry etching is completed when the first wiring layer 41 formed below the first insulating layer 51 is exposed.

[0041] In this case, there is also a concern that dry etching may not be performed appropriately. However, as in the case of etching the second insulating layer 52, only etching variations due to the thickness of one layer of the first insulating layer 51 occur, so that it is possible to prevent the first wiring layer 41 from being reached or the first wiring layer 41 from being penetrated.

[0042] Thereafter, the resist 102 is removed, and then a process of forming the via wiring portion 60 is performed as shown in FIG. 2. That is, the via wiring portion 60 is formed so as to cover the inside of the first opening 50a and the second opening 50b and the second insulating layer 52. Then, after forming the resist 103 in a desired pattern, the via wiring portion 60 is patterned using the resist 103 as a mask. As a result, the first via wiring portion 61 is formed so as to cover the inner wall surface of the first opening 50a, and the second via wiring portion 62 is formed so as to cover the inner wall surface of the second opening 50b.

[0043] In this manner, the steps of forming the wiring layer 40 and the piezoelectric layer 50, the steps of forming the first opening 50a and the second opening 50b, and the step of forming the via wiring portion 60 are completed. If the semiconductor device is to be a microphone, a resist (not shown) is then placed that opens at a position where a recess is to be formed on the back surface of the semiconductor substrate 10, and the semiconductor substrate 10 is etched from the back surface to form the recess. This completes the semiconductor device of this embodiment.

[0044] In the semiconductor device described above, a stepped shape is formed between the penetrating piezoelectric layers 50, and a part of one of the wiring layers 40 arranged between the piezoelectric layers 50 constituting the stepped portion is arranged to surround the stepped portion. In other words, in a multi-layer structure in which a plurality of piezoelectric layers 50 are formed, an opening formed deep in the piezoelectric layer 50, that is, a wiring layer 40 of an upper layer is formed at a position corresponding to an opening exposing the wiring layer 40 of the lower layer. In the case of this embodiment, a second wiring layer 42 of an upper layer is formed at a position corresponding to a first opening 50a exposing the first wiring layer 41 of the lower layer.

[0045] In the case of such a structure, when forming an opening in the piezoelectric layer 50, an upper layer among the plurality of piezoelectric layers 50 is first etched until an upper wiring layer 40 formed between the upper layer and the layer below it is reached. Then, when the upper wiring layer 40 is reached, the upper wiring layer 40 is removed, and then the lower layers of the piezoelectric layer 50 are removed until the lower wiring layer 40 is reached.

[0046] In this way, the thickness of each layer is thinner than the entire thickness of the piezoelectric layer 50. Therefore, even if etching variations occur, the variations are due to the thickness of one layer of the piezoelectric layer 50 having a multi-layer structure, and are smaller than when the entire piezoelectric layer 50 is dry-etched at once. Therefore, even if etching variations occur, they can be suppressed within the range of the thickness of the upper wiring layer 40, and dry etching can be completed before the upper wiring layer 40 is penetrated. Then, if the piezoelectric layer 50 is removed until it reaches the lower wiring layer 40 after removing the upper wiring layer 40, the etching variations at that time will also be due to the thickness of one layer of the piezoelectric layer 50 having a multi-layer structure. Therefore, it is possible to prevent the lower wiring layer 40 from being not reached or the lower wiring layer 40 from being penetrated.

[0047] Therefore, in a semiconductor device in which the via wiring portion 60 is provided for the laminated structure of the piezoelectric layer 50 and the wiring layer 40 to establish electrical connection with the wiring layer 40, it is possible to achieve a structure that can reduce etching variations.

[0048] Second embodiment The second embodiment will be described. This embodiment is different from the first embodiment in the method of removing the portion 42a of the second wiring layer 42, and is otherwise similar to the first embodiment, so only the differences from the first embodiment will be described.

[0049] In the first embodiment, the second insulating layer 52 is removed to form the first opening 50a until the second wiring layer 42 is exposed, and then, of the portion 42a of the second wiring layer 42, the portion exposed on the surface of the stepped portion is entirely removed. In contrast, in the present embodiment, only the portion of the portion 42a corresponding to the first opening 50a to be formed in the first insulating layer 51 is removed.

[0050] Specifically, as shown in Fig. 4, photolithography and etching processes are performed on the intermediate via and the stepped portion in the same manner as in the first embodiment, and then photolithography and etching processes are performed on the lower via.

[0051] First, a resist 102 is formed with an opening that exposes a part of the surface of the second wiring layer 42 in the first opening 50a. That is, the resist 102 is arranged with an opening in the region of the first opening 50a where the remaining part to be formed in the first insulating layer 51 is to be formed. Using this resist 102 as a mask, the first insulating layer 51 is removed together with the second wiring layer 42 by dry etching, for example, plasma etching. Then, when the first wiring layer 41 formed below the first insulating layer 51 is exposed, the dry etching is terminated. Thereafter, the process of forming the via wiring portion 60 is performed in the same manner as in the first embodiment.

[0052] In this manner, the remainder of the first opening 50a may be formed by removing the first insulating layer 51 simultaneously with the second wiring layer .

[0053] When such a manufacturing method is used, the periphery of the portion of first opening 50a formed in first insulating layer 51 is surrounded by portion 42a of second wiring layer 42. Then, portion 42a is also formed on the surface of the stepped portion, and the opening end of first insulating layer 51 and the opening end of portion 42a of second wiring layer 42 are aligned.

[0054] Also, similar to the first embodiment, the first via wiring portion 61 and the second via wiring portion 62 are electrically connected to different wiring portions configured by the first wiring layer 41 and the second wiring layer 42. The first via wiring portion 61 is brought into contact with the portion 42a of the second wiring layer 42 over a wider area than in the first embodiment. However, the portion 42a is insulated from the portion 42b of the second wiring layer 42 formed at the position of the second opening 50b. Therefore, similar to the first embodiment, the first via wiring portion 61 is electrically connected to the first wiring layer 41, and the second via wiring portion 62 is electrically connected to the portion 42b, and thus they are electrically connected to different wiring portions.

[0055] Third embodiment A third embodiment will be described. This embodiment has a via structure with a different depth from that of the first embodiment, and is otherwise similar to the first and second embodiments, so only the differences from the first and second embodiments will be described.

[0056] As shown in FIG. 5, in this embodiment, the piezoelectric layer 50 and the wiring layer 40 have a three-stage structure, and are provided with a third opening 50c that is deeper than the first opening 50a and the second opening 50b, and a third via wiring portion 63.

[0057] In this way, in the case of a structure including the third via wiring portion 63, the wiring layer 40 has a three-layer structure having a first wiring layer 41, a second wiring layer 42, and a third wiring layer 43. In addition, the piezoelectric layer 50 also has a three-layer structure having a first insulating layer 51, a second insulating layer 52, and a third insulating layer 53.

[0058] The first opening 50a is stepped and is formed so as to penetrate the second insulating layer 52 from the surface of the third insulating layer 53 to reach the second wiring layer 42 formed on the surface of the first insulating layer 51. The first via wiring portion 61 formed so as to cover the inner wall surface of the first opening 50a is electrically connected to the portion 42d of the second wiring layer 42 which is a part of the wiring portion. A stepped portion is formed between the second insulating layer 52 and the third insulating layer 53, and the third wiring layer 43 is formed between the second insulating layer 52 and the third insulating layer 53 so as to surround the periphery of the stepped portion. The portion 43a of the third wiring layer 43 which is provided so as to surround the periphery of the stepped portion is not a portion which is made into a wiring portion. Thus, in this embodiment, the first opening 50a and the first via wiring portion 61 are formed in the same structure as in the first embodiment in the upper two layers of the three-layer structure.

[0059] Similarly, the second opening 50b is formed so as to penetrate the third insulating layer 53 from the surface of the third insulating layer 53 and reach the third wiring layer 43 formed on the surface of the second insulating layer 52. The second via wiring portion 62 formed so as to cover the inner wall surface of the second opening 50b is electrically connected to a portion 43b of the third wiring layer 43 that is a part of the wiring portion. Thus, in this embodiment, the second opening 50b and the second via wiring portion 62 are formed in the same structure as in the first embodiment in one of the upper layers of the three-layer structure.

[0060] The third opening 50c has a stepped shape and is formed so as to penetrate from the surface of the third insulating layer 53 through the second insulating layer 52 and the first insulating layer 51 to reach the first wiring layer 41 formed on the surface of the first insulating layer 51. A third via wiring portion 63 formed so as to cover the inner wall surface of the third opening 50c is electrically connected to the first wiring layer 41 which is a part of the wiring portion. A stepped portion is formed between the first insulating layer 51 and the second insulating layer 52, and a portion 42c of the second wiring layer 42 is formed between the first insulating layer 51 and the second insulating layer 52 so as to surround the periphery of this stepped portion. In addition, a stepped portion is also formed between the second insulating layer 52 and the third insulating layer 53, and a portion 43c of the third wiring layer 43 is formed between the second insulating layer 52 and the third insulating layer 53 so as to surround the periphery of this stepped portion. The portion 42c of the second wiring layer 42 that is provided so as to surround the periphery of the stepped portion and the portion 43c of the third wiring layer 43 that is provided so as to surround the periphery of the stepped portion are not included in the wiring portion. In this manner, in this embodiment, the third opening 50c and the third via wiring portion 63 are formed using all three layers of the three-layer structure.

[0061] In a semiconductor device having such a structure, when first opening 50a and second opening 50b are formed, third opening 50c is also formed at the same time.

[0062] Specifically, when the third insulating layer 53 is dry etched to form the upper portion of the first opening 50a and the second opening 50b, an upper via that becomes the upper portion of the third opening 50c is also formed. At this time, even if etching variations occur, the variations are due to the thickness of one layer of the piezoelectric layer 50 having a multi-layer structure, and are smaller than when the entire piezoelectric layer 50 is dry etched at once. Therefore, even if etching variations occur, they can be suppressed within the thickness of the third wiring layer 43.

[0063] Thereafter, for the first opening 50a and the third opening 50c, the third wiring layer 43 on the stepped portion between the second insulating layer 52 and the third insulating layer 53 is etched and removed. Then, when the second insulating layer 52 is dry etched to form the lower portion of the first opening 50a, a middle via that becomes the middle portion of the third opening 50c is also formed. At this time, even if etching variations occur, they are caused by the thickness of one layer of the piezoelectric layer 50, as described above, and can be suppressed within the thickness of the second wiring layer 42.

[0064] Thereafter, for the third opening 50c, the second wiring layer 42 on the stepped portion between the first insulating layer 51 and the second insulating layer 52 is etched and removed. Then, the first insulating layer 51 is dry etched to form a lower via that becomes the lower portion of the third opening 50c. At this time, even if etching variations occur, they are caused by the thickness of one layer of the piezoelectric layer 50, as described above, and can be suppressed within the thickness of the second wiring layer 42.

[0065] In this way, even when the piezoelectric layer 50 and the wiring layer 40 have a three-layer structure and the via wiring portion 60 has three stages with different depths, the structure can be the same as that of the first and second embodiments, and the same effects can be obtained. Note that, here, as in the first embodiment, the portion 43a surrounding the stepped portion between the second insulating layer 52 and the third insulating layer 53 and the like is removed from the surface of the stepped portion, but as in the second embodiment, it may be left on the surface of the stepped portion.

[0066] (Other embodiments) Although the present disclosure has been described based on the above-described embodiment, it is not limited to the embodiment, and includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

[0067] (1) For example, in the above embodiments, the insulating layer is configured by the piezoelectric layer 50 because the semiconductor device applied to a microphone or the like has been described as an example. That is, the piezoelectric layer 50 having a piezoelectric effect is applied in order to extract a voltage generated by the piezoelectric effect when the piezoelectric layer 50 is vibrated by sound to detect the sound, but other insulating layers may be applied when the piezoelectric effect is not used. For example, instead of the piezoelectric layer 50, an insulating layer made of an insulating material such as AlN or Si may be used. For example, applications other than microphones include semiconductor sensors and ASICs (Application Specific Integrated Circuits).

[0068] (2) In the above embodiments, as an example of forming the via wiring portion 60 for the multi-layered wiring layer 40 and piezoelectric layer 50, the wiring layer 40 and the piezoelectric layer 50 are provided with a two-layer structure or a three-layer structure. However, these numbers of layers are merely examples, and a multi-layer structure of four or more layers may be used. However, when the semiconductor device is used as a microphone, if the number of layers of the piezoelectric layer 50 becomes too large, the piezoelectric characteristics are degraded and the sensitivity is reduced. Therefore, a two-layer structure of the first insulating layer 51 and the second insulating layer 52 as in the first embodiment is preferable.

[0069] That is, a multi-layer structure is formed by alternately forming each layer of a plurality of insulating layers on each wiring layer of a plurality of wiring layers constituting a wiring part. Also, a plurality of via wiring parts are provided so as to cover the inner wall surfaces of a plurality of openings formed at different depths in the plurality of insulating layers, and are electrically connected to different layers in the plurality of wiring layers formed in a multi-layer structure. In such a structure, an opening penetrating two or more insulating layers in the plurality of insulating layers is made to have a stepped shape having a stepped part between the penetrating insulating layers. Then, a part of one wiring layer among the plurality of wiring layers arranged between the insulating layers constituting the stepped part is arranged surrounding the stepped part, and the part is insulated from a part constituting the wiring part in the one wiring layer. In this way, it is possible to make a structure capable of reducing etching variations in a semiconductor device in which a via wiring part is provided in a laminated structure of an insulating layer and a wiring layer constituting a pattern wiring to electrically connect to the pattern wiring.

[0070] Specifically, when etching an upper insulating layer, if etching is performed until the wiring layer formed on the surface of the insulating layer one layer below it is reached, even if etching variations occur, they can be suppressed within the range of the thickness of the wiring layer. By repeating such etching from the upper layer to the lower layer in order, etching variations can be suppressed to those caused by the thickness of one insulating layer, and the same effects as those of the above embodiments can be obtained.

[0071] (3) The metal constituting the wiring layer 40 is Mo, and the metal constituting the via wiring portion 60 is Al, but these are merely examples, and these may be composed of other metal conductors. For example, the wiring layer 40 may be Ti-based metals such as Ti and TiN, Cu-based metals such as Cu, SiCu, and CuSn, W-based metals, etc., and the via wiring portion 60 may be Al-based metals such as AlSi. Here, the metal conductors applicable to the wiring layer 40 and the via wiring portion 60 are described separately, but the metal conductors listed here can be used for either the wiring layer 40 or the via wiring portion 60 without distinction. The wiring layer 40 and the via wiring portion 60 may be composed of the same metal conductor, or may be composed of different metal conductors.

[0072] In each of the above embodiments, it goes without saying that the elements constituting the embodiment are not necessarily essential, except when it is specifically stated that they are essential or when it is clearly considered essential in principle. In addition, in each of the above embodiments, when the numbers, values, amounts, ranges, etc. of the components of the embodiment are mentioned, they are not limited to the specific numbers, except when it is specifically stated that they are essential or when it is clearly limited to a specific number in principle. In addition, in each of the above embodiments, when the shapes, positional relationships, etc. of the components are mentioned, they are not limited to the shapes, positional relationships, etc., except when it is specifically stated that they are essential or when it is clearly limited to a specific shape, positional relationship, etc. in principle. [Explanation of symbols]

[0073] 10. Semiconductor Substrate 40 wiring layer 41~43 1st~3rd wiring layer 50 Piezoelectric layer 50a~50c 1st~3rd opening 51-53 1st to 3rd insulating layers 60 Via wiring section 61 to 63 First to third via wiring sections

Claims

1. A semiconductor device comprising: A semiconductor substrate (10); A plurality of wiring layers (40) formed in a multi-layer structure on the semiconductor substrate and constituting a wiring section; A plurality of insulating layers (50) formed on each of the wiring layers (41, 42, 43) constituting the plurality of wiring layers, each of which is formed by repeatedly alternately forming each of the insulating layers (51, 52, 53) and the wiring layers, to form a multi-layer structure; a plurality of via wiring portions (60) formed to cover the respective inner wall surfaces of a plurality of openings (50a to 50c) formed at different depths in the plurality of insulating layers and electrically connected to different layers in the plurality of wiring layers having a multilayer structure; Among the plurality of openings, an opening (50a, 50c) penetrating two or more insulating layers in the plurality of insulating layers has a stepped shape having a stepped portion between the penetrating insulating layers, a portion (42a, 42c, 43a, 43c) of one of the wiring layers (42, 43) arranged between the insulating layers constituting the stepped portion is arranged to surround the stepped portion, and the portion is insulated from a portion (42b, 42d, 43b) of the one wiring layer that constitutes the wiring portion.

2. The semiconductor device according to claim 1 , wherein said portion surrounding said stepped portion is also formed on a surface of said stepped portion.

3. The plurality of wiring layers have a two-layer structure including a first wiring layer (41) and a second wiring layer (42) formed on the first wiring layer, The plurality of insulating layers are constituted by a piezoelectric layer (50), and have a two-layer structure including a first insulating layer (51) disposed on the first wiring layer, and a second insulating layer (52) disposed on the second wiring layer formed on the first insulating layer, the plurality of openings include a first opening (50a) that penetrates from a surface of the second insulating layer through the second wiring layer and the first insulating layer to reach the first wiring layer, and a second opening (50b) that penetrates from the surface of the second insulating layer through the second wiring layer to reach the second wiring layer; The plurality of via wiring portions include a first via wiring portion (61) formed to cover an inner wall surface of the first opening portion, and a second via wiring portion (62) formed to cover an inner wall surface of the second opening portion, the first opening has a stepped shape, and a portion between the first insulating layer and the second insulating layer in the first opening forms the stepped portion; 3. The semiconductor device according to claim 1, wherein the stepped portion is surrounded by a portion (42a) of the second wiring layer that surrounds a periphery of a portion formed in the first insulating layer in the first opening.

4. A method for manufacturing a semiconductor device, comprising: On a semiconductor substrate (10), wiring layers (41, 42, 43) of a plurality of wiring layers (40) constituting a wiring section and insulating layers (51, 52, 53) of a plurality of insulating layers (50) are alternately and repeatedly stacked to configure the plurality of wiring layers and the plurality of insulating layers in a multilayer structure; forming a plurality of openings (50a-50c) having different depths in the plurality of insulating layers; and forming a plurality of via wiring portions (60) electrically connected to different layers in the plurality of wiring layers having a multi-layer structure by covering each of the plurality of openings, Forming the plurality of openings means forming at least a first opening (50a) and a second opening (50b) having different depths; etching an insulating layer (52) located in an upper layer of the plurality of insulating layers to reach an upper wiring layer (42) of the plurality of wiring layers formed on an insulating layer (51) located in a lower layer of the insulating layer, thereby forming a part of the first opening and forming the second opening; removing the upper wiring layer exposed in a portion of the first opening to expose the underlying insulating layer; and etching the lower insulating layer exposed by removing the upper wiring layer to reach a lower wiring layer (41) located below the upper wiring layer among the plurality of wiring layers, and forming a remaining portion of the first opening while forming a step portion between the upper insulating layer and the lower insulating layer.

5. 5 . The method for manufacturing a semiconductor device according to claim 4 , wherein exposing the underlying insulating layer comprises removing all of the upper wiring layer exposed at a bottom of the part of the first opening.

6. In the exposing of the insulating layer located in the lower layer, a mask (102) having an opening at a position where the remaining part of the first opening is to be formed is used to remove a portion of the upper wiring layer exposed at a bottom part of the first opening, the portion corresponding to the remaining part of the first opening; The method for manufacturing a semiconductor device according to claim 4 , wherein forming the remaining portion of the first opening comprises performing etching using the mask.

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