Ultra-thin bridge and multi-die ultra-fine pitch patch architecture and fabrication method

Abstract

To provide a semiconductor device having a package substrate including an ultrathin bridge and a multi-die ultrafine pitch patch architecture.SOLUTION: A semiconductor package 100 includes: a bridge 140 having a hybrid layer including a conductive pad 141, a surface finishing layer 143 and / or a dielectric layer 142 on a high-density packaging (HDP) substrate 130; a plurality of dies 110 to 112 over the bridge and the HDP substrate; and a plurality of through mold vias (TMVs) 122a to 122b on the HDP substrate. The bridge is coupled between the dies and the HDP substrate. The bridge is directly coupled to two dies among the dies with the hybrid layer, in which a top surface of the hybrid layer is in direct contact with bottom surfaces of the dies, and the bottom surface of the bridge is in direct contact with a top surface of the HDP substrate. The TMVs couple the HDP substrate to the dies, and have a thickness that is substantially equal to a thickness of the bridge.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] Embodiments relate to packaging semiconductor devices, and more particularly, to semiconductor devices having a package substrate that includes an ultra-thin bridge and multi-die ultra-fine pitch patch architecture. [Background technology]

[0002] For the past few decades, the scaling of integrated circuit (IC) features has been a driving force behind the ever-growing semiconductor industry. Scaling smaller and smaller features allows for a higher density of functional units in the limited physical real estate of a semiconductor device. However, driving the scaling down of IC features while optimizing the performance of each device is not without challenges.

[0003] Heterogeneous integration in multiple chip / die packages is essential for data-centric work. Interconnecting these chips with high bandwidth density at the lowest power requires ultra-fine line / space / via pads in the package substrate. Recently, embedded bridge die technology has addressed this need in server products. However, with the ever-increasing demand for multi-die interconnects, the package substrate needs to embed external bridge dies (e.g., more than 10 bridge dies) to accommodate these multiple dies and multi-die interconnects. More importantly, the package assembly process for such package substrates also requires soldering multiple dies to these external bridge die areas to obtain the desired results with high yield and increased bridge die bump pitch. However, such a process requires additional assembly steps and time, and requires precise control of the substrate planarity over the large areas of these packages.

[0004] This limits the bridge die bump pitch for solder-based embedded bridge die connections. These limitations on bridge die bump pitch result in several major packaging issues, including less than desired bump density, resulting in increased interconnect physical area within the die, and increased cost due to such increased silicon area. Furthermore, existing technologies also use silicon interposers in an attempt to solve these pitch scaling limitations and issues. For multi-die architectures, silicon interposers can be larger than twice the reticle size (or more), but require reticle bonding, adding excessive cost and complexity. [Brief description of the drawings]

[0005] Embodiments are illustrated herein by way of non-limiting example in the figures of the accompanying drawings, in which like references indicate like features, and in which certain prior art details have been omitted so as not to obscure the inventive concepts described herein.

[0006] [Figure 1] 1 is a cross-sectional view of a semiconductor package having multiple dies, a high density packaging (HDP) substrate, a thin bridge having a hybrid layer, a plurality of first and second through mold vias (TMVs), and a package substrate according to one embodiment.

[0007] [Figure 2A] 1A-1C are cross-sectional views of a process flow for forming a semiconductor package according to some embodiments having multiple dies, an HDP substrate, a thin bridge having a hybrid layer, multiple first and second TMVs, and a package substrate. [Figure 2B] 1A-1C are cross-sectional views of a process flow for forming a semiconductor package according to some embodiments having multiple dies, an HDP substrate, a thin bridge having a hybrid layer, multiple first and second TMVs, and a package substrate. [Figure 2C]1A-1C are cross-sectional views of a process flow for forming a semiconductor package according to some embodiments having multiple dies, an HDP substrate, a thin bridge having a hybrid layer, multiple first and second TMVs, and a package substrate. [Figure 2D] 1A-1C are cross-sectional views of a process flow for forming a semiconductor package according to some embodiments having multiple dies, an HDP substrate, a thin bridge having a hybrid layer, multiple first and second TMVs, and a package substrate. [Figure 2E] 1A-1C are cross-sectional views of a process flow for forming a semiconductor package according to some embodiments having multiple dies, an HDP substrate, a thin bridge having a hybrid layer, multiple first and second TMVs, and a package substrate. [Figure 2F] 1A-1C are cross-sectional views of a process flow for forming a semiconductor package according to some embodiments having multiple dies, an HDP substrate, a thin bridge having a hybrid layer, multiple first and second TMVs, and a package substrate. [Figure 2G] 1A-1C are cross-sectional views of a process flow for forming a semiconductor package according to some embodiments having multiple dies, an HDP substrate, a thin bridge having a hybrid layer, multiple first and second TMVs, and a package substrate. [Figure 2H] 1A-1C are cross-sectional views of a process flow for forming a semiconductor package according to some embodiments having multiple dies, an HDP substrate, a thin bridge having a hybrid layer, multiple first and second TMVs, and a package substrate. [Figure 2I] 1A-1C are cross-sectional views of a process flow for forming a semiconductor package according to some embodiments having multiple dies, an HDP substrate, a thin bridge having a hybrid layer, multiple first and second TMVs, and a package substrate. [Figure 2J] 1A-1C are cross-sectional views of a process flow for forming a semiconductor package according to some embodiments having multiple dies, an HDP substrate, a thin bridge having a hybrid layer, multiple first and second TMVs, and a package substrate. [Figure 2K] 1A-1C are cross-sectional views of a process flow for forming a semiconductor package according to some embodiments having multiple dies, an HDP substrate, a thin bridge having a hybrid layer, multiple first and second TMVs, and a package substrate. [Figure 2L] 1A-1C are cross-sectional views of a process flow for forming a semiconductor package according to some embodiments having multiple dies, an HDP substrate, a thin bridge having a hybrid layer, multiple first and second TMVs, and a package substrate.

[0008] [Diagram 3] 1 is a cross-sectional view of a semiconductor package having multiple dies, multiple HDP substrates, multiple thin bridges with hybrid layers, multiple first and second TMVs, and a package substrate according to one embodiment.

[0009] [Figure 4] FIG. 1 is a schematic block diagram illustrating a computer system utilizing a semiconductor package according to one embodiment having multiple dies, an HDP substrate, a thin bridge having a hybrid layer, multiple first and second TMVs, and a package substrate. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Described herein are package substrates, ultra-thin (or thin) bridges, semiconductor packages having multi-die ultra-fine pitch patch architectures, and methods of forming such semiconductor packages. The semiconductor packages and methods of forming such semiconductor packages described below may include, according to some embodiments, a plurality of dies, a high density package (HDP) substrate, a thin bridge, a plurality of first through-molded vias, a plurality of second TMVs, and a package substrate. These embodiments of the semiconductor packages described herein bond the HDP substrate (e.g., high density (HD)-organic substrate) and the thin bridge (e.g., a thin embedded multi-die interconnect bridge (EMIB)) without solder balls / connections, minimizing the number of bridges, and allowing the thin bridge to be directly bonded (or attached) between the HDP substrate and the die by a hybrid dielectric / conductive bonding layer (e.g., a silicon dioxide / copper (SiO2 / Cu) bonding layer).

[0011] As used herein, a "bridge" may refer to a silicon interconnect bridge or an interconnect bridge made of any other substrate material suitable for forming such an interconnect bridge (e.g., an embedded multi-die interconnect bridge (EMIB)). Thus, as used herein, a "thin bridge" (or an "ultra-thin bridge") may refer to a bridge that may have a thickness of about 10um-15um and / or a thickness of less than about 10um. As noted above, the thin bridge described herein does not require solder balls to be bonded to the die, rather the thin bridge may be bonded (and / or communicatively coupled) directly to the die by a hybrid layer (or hybrid bonding layer). As used herein, a "hybrid layer" (hybrid bonding layer) may refer to a thin layer (or ultra-thin layer) comprised of a plurality of conductive pads (or Cu pads), a dielectric layer (or SiO2 layer), and a surface finish layer (or Tin (Sn) layer), where the dielectric layer may surround the conductive pads, the top surfaces of the conductive pads are substantially flush with the top surface of the dielectric layer used to insulate the conductive pads, and the surface finish layer may be disposed (or applied) directly on the top surfaces of the conductive pads.

[0012] For example, to bond a solderless thin bridge directly to a die by a hybrid layer, the thin bridge can have Sn directly disposed on the thin Cu pads of the thin bridge, where the Sn of the ultra-thin bridge reacts directly with the Cu pads of the die to (i) achieve a Sn / Cu intermetallic between the thin bridge and the die, and (ii) lock (or bond in place) the thin bridge directly to the die, such as by a hybrid bonding process. The hybrid bonding process may include temperature heating, pressure, and a reducing atmosphere to achieve locking between the ultra-thin bridge and the die, according to one embodiment. Note that the hybrid layer may omit the surface finish layer, if desired, as described below.

[0013] The combination of HDP substrate and thin bridge described herein aids in semiconductor packaging by significantly reducing (or eliminating / mitigating) the total number of thin bridges typically required as described above in existing technology. The semiconductor package embodiments described below enable improved routing and power distribution capabilities for input / output (I / O) circuitry such as a die. The embodiments described herein also provide improved warpage benefits for the semiconductor package. For example, the semiconductor package can be mounted on a temporary glass carrier that substantially reduces coefficient of thermal expansion (CTE) mismatch stresses, especially after the encapsulation layer (or mold layer) processing step.

[0014] The embodiments described herein provide an improvement over existing packaging solutions by eliminating solder-based bridge interconnects (i.e., the bridges (or EMIBs) described herein can be bonded to another component without a solder connection), thereby providing improved bridge pitch scaling, reduced interconnect physical area on the die, and lower cost of assembly. Another improvement over existing packaging solutions also includes eliminating the need for expensive silicon interposers, thereby reducing overall package costs. These semiconductor packages further provide improvements over packaging solutions by implementing and combining solderless bridge (or EMIB) interconnects, bridge-glass-patch hybrid bonding (e.g., SiO2 / Cu bonding), HDP substrate routing layers with significantly reduced line / spacing (L / S) (e.g., L / S less than 2 / 2), ultra-fine lithographically defined (litho) vias, and zero misalignment via architectures.

[0015] The technology described herein can be implemented in one or more electronic devices. Non-limiting examples of electronic devices that can utilize the technology described herein include any type of mobile and / or fixed device, such as microelectromechanical systems (MEMS) based electric systems, gyroscopes, advanced driving assistance systems (ADAS), 5G communication systems, cameras, mobile phones, computer terminals, desktop computers, e-readers, facsimile machines, kiosks, netbook computers, notebook computers, Internet devices, payment terminals, personal digital assistants, media players and / or recorders, servers (e.g., blade servers, rack mounted servers, combinations thereof, etc.), set-top boxes, smart phones, tablet personal computers, ultra-mobile personal computers, wired telephones, combinations thereof, etc. Such devices may be portable or stationary. In some embodiments, the techniques described herein may be used in desktop computers, laptop computers, smart phones, tablet computers, netbook computers, notebook computers, personal digital assistants, servers, combinations thereof, etc. More generally, the techniques described herein may be used in any of a variety of electronic devices, including package substrates, dies, HDP substrates, thin bridges (or thin EMIBs) with hybrid layers, and semiconductor packages with TMVs having different widths.

[0016] In the following description, various aspects of the exemplary implementation are described using terms commonly used by those skilled in the art to convey the contents of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present embodiment may be implemented using only some of the described aspects. For purposes of explanation, specific numbers, materials, and configurations are set forth to provide a thorough understanding of the specific embodiment. However, it will be apparent to those skilled in the art that the present embodiment may be implemented without the specific details. In other cases, well-known features are omitted or simplified so as not to obscure the exemplary implementation.

[0017] Although various operations are described in a manner that is most useful in understanding the present embodiment as multiple separate operations, the order of description should not be construed to imply that these operations are necessarily order dependent. Various operations are described as composite, and in particular, these operations do not have to be performed in the order they appear.

[0018] As used herein, the terms "top," "bottom," "upper," "lower," "lowest," and "top" when used in connection with one or more elements are intended to convey a relative, rather than an absolute physical configuration. Thus, an element described as the "top element" or "top element" in a device may, conversely, form the "bottom element" or "bottom element" in the device when the device is inverted. Similarly, an element described as the "bottom element" or "bottom element" in a device may, conversely, form the "top element" or "top element" in the device when the device is inverted.

[0019] 1, a cross-sectional view of a semiconductor package 100 according to one embodiment is shown. In one embodiment, the semiconductor package 100 may include a plurality of dies 110-112, an HDP substrate 130, a thin bridge 140 having hybrid layers 141-143, a plurality of TMVs 122a-122b, and a package substrate 102. In one embodiment, the semiconductor package 100 may combine (or stack) the dies 110-112, the thin bridge 140, and the HDP substrate 130, and the thin bridge 140 may be directly combined (or attached) between the HDP substrate 130 and the dies 110-112 by the hybrid layers 141-143, and the hybrid layers 141-143 are comprised of a plurality of conductive pads 141 (or Cu pads), a dielectric layer 142 (SiO2 layer), and a surface finish layer 143 (Sn layer or exposed Cu surface layer) (i.e., a hybrid dielectric / conductive bonding layer).

[0020] According to some embodiments, the dies 110-112 may be disposed over the HDP substrate 130 and thin bridge 140, and the thin bridge 140 may be disposed directly below and between the dies 110-112, while the HDP substrate 130 may be disposed over the package substrate 102. Although one HDP substrate 130, one thin bridge 140, and three dies 110-112 are shown in FIG. 1, it should be understood that any number of HDP substrates 130, thin bridges 140, and dies 110-112 may be combined / stacked, contacted / disposed over, and bonded to the package substrate 102.

[0021] In one embodiment, the package substrate 102 may include, but is not limited to, a package, a substrate, a printed circuit board (PCB), and / or a motherboard. In one embodiment, the package substrate 102 is a PCB. In one embodiment, the PCB is constructed of a FR-4 glass-epoxy base with thin copper foil laminated on both sides. In certain embodiments, a multi-layer PCB may be used, where pre-preg and copper foil are used to create additional layers. For example, a multi-layer PCB may include one or more dielectric layers, where each dielectric layer may be a photosensitive dielectric layer. In one embodiment, the PCB 102 may include multiple conductive layers, which may further include copper (or metal) traces, lines, pads, vias, via pads, holes, and / or planes.

[0022] As shown in FIG. 1, the HDP substrate 130 may be disposed over the package substrate 102, and the HDP substrate 130 may be conductively coupled to the package substrate 102 by a plurality of solder balls 123. In some embodiments, the HDP substrate 130 may include a plurality of redistribution layers (RDLs) comprised of traces with an L / S of about 2 / 2 um or less, litho vias, zero misalignment vias, and / or via pads with a thickness of about 18 um or less. The HDP substrate 130 may be a silicon substrate with increased (or high) input / output (I / O) density and bandwidth for communication with the dies 110-112 and / or the thin bridge 140. In one embodiment, the HDP substrate 130 may have a thickness of about 10 um to 200 um.

[0023] In one embodiment, the HDP substrate 130 may have a plurality of first conductive pads 118 and a plurality of conductive interconnects 131. The first conductive pads 118 may be disposed on a bottom surface of the HDP substrate 130. In one embodiment, the first conductive pads 118 may have a pitch greater than about 80 um. The first conductive pads 118 may be a plurality of ball grid array (BGA) pads, or the like. The conductive interconnects 131 of the HDP substrate 130 may include vias, traces, lines, pads, or the like. For example, the conductive interconnects 131 may be directly bonded to the first conductive pads 118, or solder balls 123 may conductively bond the first conductive pads 118 of the HDP substrate 130 to the top surface of the package substrate 102.

[0024] The conductive interconnects 131 may extend vertically from a bottom surface to a top surface of the HDP substrate 130. For example, the bottom surface of the conductive interconnects 131 of the HDP substrate 130 may be directly bonded to the first conductive pad 118, and the bottom surface of the conductive interconnects 131 may be substantially flush with the bottom surface of the HDP substrate 130. Meanwhile, in another example, the top surface of the conductive interconnects 131 of the HDP substrate 130 may be directly bonded to the plurality of TMVs 122a-122b, and the top surface of the conductive interconnects 131 may be substantially flush with the top surface of the HDP substrate 130.

[0025] In one embodiment, the thin bridge 140 may be disposed directly over or in contact with the HDP substrate 130, and the bottom surface of the thin bridge 140 may be directly bonded to the top surface of the HDP substrate 130. In one embodiment, the thin bridge 140 may include hybrid layers 141-143, which are comprised of conductive pads 141, a dielectric layer 142, and a surface finish layer 143. In one embodiment, the conductive pads 141 may be a plurality of Cu pads, or the like. In one embodiment, the dielectric layer 142 may be a passivation layer formed of a SiO2 material, and / or any known dielectric / insulating material that insulates the conductive pads 141. Additionally, as discussed above in one embodiment, the surface finish layer 143 may include one or more conductive materials capable of providing additional solder, such as tin. For example, the conductive pads 141 and the dielectric layer 142 may be disposed directly on the top surface of the thin bridge 140, where the dielectric layer 142 surrounds the conductive pads 141. Additionally, the top surface of the conductive pad 141 may be substantially coplanar with the top surface of the dielectric layer 142 , and the surface finish layer 143 may be disposed directly on the top surface of the conductive pad 141 .

[0026] In one embodiment, the thin bridge 140 may have a thickness of about 10 um to 15 um. In another embodiment, the thin bridge 140 may have a thickness of about 10 um or less. In one embodiment, the conductive pads 141 and the dielectric layer 142 of the bridge 140 may have a thickness of about 5 um. In another embodiment, the conductive pads 141 and the dielectric layer 142 of the bridge 140 may have a thickness of less than about 10 um. In one embodiment, the surface finish layer 143 of the bridge 140 may have a thickness of about 1 um to 2 um. In another embodiment, the surface finish layer 143 of the bridge 140 may have a thickness of about 5 um or less. Note that in some alternative embodiments, the surface finish layer 143 may be omitted as shown in FIG. 2C. Thus, in one embodiment, the hybrid layers 141-143 may have a thickness of about 5 um to 7 um, while in another embodiment, the hybrid layers 141-143 may have a thickness of about 7 um or less.

[0027] 1, the TMVs 122a-122b may be disposed and bonded directly to / on the top surface of the conductive interconnect 131 of the HDP substrate 130. For example, the TMVs 122a-122b may extend vertically from the top surface of the conductive interconnect 131 of the HDP substrate 130 to approximately the bottom surface of the die 110-112 (or to the bottom surfaces of the second conductive pads 151a-151b of the die 110-112). Note that in some embodiments, the TMVs 122a-122b may not be aligned straight (or perfectly) on the conductive interconnect 131 of the HDP substrate 130.

[0028] In one embodiment, the TMVs 122a-122b may be formed of a conductive material such as Cu. The TMVs 122a-122b may be formed by a lithography process (or the like) so that the TMVs 122a-122b may be electrolessly grown, encapsulated in a mold, and then planarized. Additionally, the TMVs 122a-122b may include a plurality of first TMVs 122a and a plurality of second TMVs 122b. In one embodiment, the first TMV 122a may have a width that is greater than a width of the second TMV 122b. Additionally, in some embodiments, the first TMV 122a may have tapered sidewalls while the second TMV 122b may have substantially vertical sidewalls and / or may have a slightly tapered sidewall angle that is substantially less than the tapered sidewall angle of the first TMV 122a.

[0029] In some embodiments, the TMVs 122a-122b can surround a thin bridge 140. In one embodiment, the thin bridge 140 can be communicatively coupled to the first die 110, the second die 111, the third die 112, and / or the HDP substrate 130. As shown in FIG. 1, the thin bridge 140 can be directly coupled to the dies 111-112. However, it should be noted that the thin bridge 140 can be coupled to any two or more of the dies 110-112. In one embodiment, the thin bridge 140 can include electrical routing (or interconnect structures (e.g., through silicon vias (TSVs))) to communicatively couple the second die 111 to the third die 112 by the conductive pads 141 and / or the surface finish layer 143. As mentioned above, thin bridge 140 does not require solder balls to be directly bonded to dies 111-112, instead thin bridge 140 can be directly bonded to dies 111-112 by a hybrid layer comprised of conductive pads 141, dielectric layer 142, and surface finish layer 143. In some embodiments, thin bridge 140 may be referred to as an EMIB. For further embodiments, thin bridge 140 may include a number of TSVs that can be further used to bond thin bridge 140 to dies 111-112 and / or HDP substrate 130.

[0030] As shown in FIG. 1, the dies 110-112 may include a first die 110, a second die 111, and a third die 112. The first, second, and third dies 110-112 may be disposed over the HDP substrate 130. The second and third dies 111-112 may be disposed over both the HDP substrate 130 and the thin bridge 140. In some embodiments, the dies 110-112 may include second conductive pads 151a-151b and a dielectric layer 155. Both the second conductive pads 151a-151b and the dielectric layer 155 may be disposed directly on the bottom surface of the dies 110-112, and the dielectric layer 155 may surround the second conductive pads 151a-151b.

[0031] In one embodiment, the second conductive pads 151a-151b may be a plurality of Cu pads, or the like. In one embodiment, the dielectric layer 155 may be a passivation layer formed of SiO2 material and / or any known dielectric / insulating material that insulates the second conductive pads 151a-151b. In one embodiment, the dies 110-112 may have a thickness of about 200 um or more. In another embodiment, the dies 110-112 may have a thickness of about 200 um or less. In one embodiment, the conductive pads 151a-151b and the dielectric layer 155 of the dies 110-112 may have a thickness of about 2 um. In another embodiment, the conductive pads 151a-151b and the dielectric layer 155 of the dies 110-112 may have a thickness of about 5 um or less.

[0032] In one embodiment, the second conductive pads 151a-151b may include a plurality of second conductive pads 151a and a plurality of second conductive pads 151b. In these embodiments, the second conductive pads 151a may have a width greater than a width of the second conductive pads 151b. For example, the first TMV 122a may conductively couple the second conductive pads 151a of the dies 110-112 to the conductive interconnects 131 of the HDP substrate 130. Similarly, the second TMV 122b may conductively couple the second conductive pads 151b of the first and second dies 110-111 to the conductive interconnects 131 of the HDP substrate 130, while the second conductive pads 151b of the second and third dies 111-112 may be directly coupled to the surface finish layer 143 and the conductive pads 141 of the thin bridge 140.

[0033] In one embodiment, the dies 110-112 may include, but are not limited to, semiconductor dies, electronic devices (e.g., wireless devices), integrated circuits (ICs), central processing units (CPUs), microprocessors, platform controller hubs (PCHs), memory (e.g., high-bandwidth memory (HBM)), and / or field programmable gate arrays (FPGAs). The dies 110-112 may be formed from a material such as silicon and may have circuitry thereon coupled to the HDP substrate 130 and the thin bridge 140.

[0034] In one embodiment, the encapsulation layer 180 may be disposed over the dies 110-112 with the second conductive pads 151a-b and the dielectric layer 155, the TMVs 122a-b, the thin bridge 140 with the conductive pads 141, the dielectric layer 142 and the surface finish layer 143, and the HDP substrate 130 with the first conductive pads 118. In this manner, the TMVs 122a-122b may be surrounded by the encapsulation layer 180 and may extend vertically through the encapsulation layer 180 to conductively couple the HDP substrate 130 to the dies 110-111. In one embodiment, the encapsulation layer 180 may include one or more encapsulation materials, such as a molding material, an underfill material, a filling material, any similar material, and / or any combination thereof. In one embodiment, the encapsulation layer 180 may be planarized such that the top surface of the encapsulation layer 180 is substantially flush with the top surfaces of the dies 110-112, in which case the encapsulation layer 180 may also be disposed between the dies 110-112.

[0035] The encapsulation layer 180 may also be disposed over the underfill material 154 (or underfill layer). In one embodiment, the underfill material 154 may be disposed over the package substrate 102, with the underfill material 154 disposed between a top surface of the package substrate 102 and a bottom surface of the encapsulation layer 180 and the first conductive pads 118. The underfill material 154 may surround (or be embedded in) a portion of the encapsulation layer 180 and the solder balls 123 disposed between the encapsulation layer 180 and the package substrate 102.

[0036] In further embodiments, a thermal solution (or thermal device) may be disposed on a top surface of the die 110-112 and / or encapsulation layer 180, and the thermal solution may include a heat sink, an integrated heat spreader (IHS), a manifold, a cold plate, etc.

[0037] It should be noted that semiconductor package 100 may include fewer or additional package components based on the desired package design.

[0038] 2A-2L are cross-sectional views of a process flow for forming a semiconductor package 200 according to one embodiment. In one embodiment, the semiconductor package 200 may include a plurality of dies 210-212, an HDP substrate 230, a thin bridge 240 having hybrid layers 241-243, a plurality of TMVs 222a-222b, and a package substrate 202. The process flow illustrated in FIGS. 2A-2L forms a semiconductor package 200 that is substantially similar to the semiconductor package 100 described above in FIG. 1. Similarly, the components of the semiconductor package 200 are substantially similar to the components of the semiconductor package 100 described above in FIG. 1. Thus, as described above, the process flow of package substrate 200 illustrates one approach for bonding die 210-212, thin bridge 240, and HDP substrate 230, where thin bridge 240 is bonded directly between HDP substrate 230 and die 210-212 by hybrid layers 241-243 - without solder connections - using TMVs 222a-b and conductive pads 255a-b at an ultra-fine interconnect / wiring pitch.

[0039] 2A, a cross-sectional view of a semiconductor package 200 is shown according to one embodiment. In one embodiment, the semiconductor package 200 may include an adhesive layer 261 (or adhesive film, bonding film, etc.) disposed on a carrier 201. In one embodiment, the carrier 201 may be a glass carrier (or a temporary glass panel carrier), a metal carrier, and / or any similar flat, rigid carrier / substrate.

[0040] Further, in one embodiment, a plurality of dies 210-212 may be disposed on the adhesive layer 261 and the carrier 201, and the dies 210-212 may be disposed adjacent to each other and bonded to the carrier 201 together with the adhesive layer 261. For example, the dies 210-212 may be disposed adjacent to each other with a die-to-die spacing of about 50 um or less. Further, as shown in FIG. 2A, the top surfaces of the dies 210-212 may be disposed directly on the adhesive layer 261 to bond the dies 210-212 to the carrier 201. The dies 210-212 may be substantially similar to the above-mentioned dies 110-112 of FIG. 1. The dies 210-212 may have a plurality of second conductive pads 251a-251b and a dielectric layer 255, and the width of the second conductive pad 251a may be greater than the width of the second conductive pad 251b.

[0041] Further, as shown in FIG. 2A, the top surfaces of the second conductive pads 251a-251b may protrude beyond the top surface of the dielectric layer 255. For example, the second conductive pads 251a-251b may be overplated to a thickness of about 2 μm-3 μm greater than the thickness of the dielectric layer. Further, in one embodiment, the second conductive pads 251b may have a pitch of about 5 um or less, which may be implemented for bridge interfaces and HD interconnects (e.g., TMV 222b in FIG. 2E), while in other embodiments, the second conductive pads 251a may have a pitch of about 25 um or greater, which may be implemented for non-bridge interfaces. These overplated second conductive pads 251a-251b help mitigate thickness variations between the dies 210-212, where the thickness of the dielectric layer 255 may also be adjusted (or selected) to accommodate such thickness variations between the dies 210-212.

[0042] 2B, a cross-sectional view of semiconductor package 200 is shown according to one embodiment. In one embodiment, the overplated second conductive pads 251a-251b are planarized such that the top surfaces of the second conductive pads 251a-251b are substantially flush with the top surface of the dielectric layer 255. This planarization process also allows the second conductive pads 251a-251b to have substantially the same thickness as one another, thereby reducing any thickness variations in the semiconductor package 200.

[0043] In an embodiment, the planarization may be performed using a chemical mechanical planarization (CMP) process or the like. The planarization process may have high precision due to the presence of the dielectric layer 255 acting as a stopping point. After the second conductive pads 251a-251b are planarized, the exposed top surfaces of the second conductive pads 251a-251b may be substantially flush with the top surface of the dielectric layer 255, but may be slightly recessed. For example, the second conductive pads 251a-251b may be selectively etched to form a slight recess (or under-etch) of about 0.5 μm or less below the top surface of the dielectric layer 255, which helps the bridge (e.g., bridge 240 in FIG. 2D) to remain locked in place with the second and third dies 211-212, as described above and shown in FIG. 2D below.

[0044] 2C, a cross-sectional view of a semiconductor package 200 is shown according to one embodiment. In one embodiment, a plurality of thin bridges 240 may be disposed directly on the second and third dies 211-212 (as shown in the lower diagram of FIG. 2D). The thin bridges 240 may be substantially similar to the thin bridge 140 described above in FIG. 1. Thus, in one embodiment, the thin bridge 240 may include hybrid layers 241-243 (the thin bridge 240 is shown on the right side of FIG. 2C), where the hybrid layers 241-243 are comprised of multiple layers of conductive pads 241, dielectric layers 242, and surface finish layers 243 (e.g., the hybrid layers 241-243 may include a combination of Cu / SiO2 / Sn, etc.). In one embodiment, the conductive pads 241 and the dielectric layers 242 may be planarized over the thin bridge 240, such as by a fly-cut process. Subsequently, in these embodiments, surface finish layer 243 may then be disposed directly on the exposed top surface of conductive pad 241 using a Sn coating process or the like (e.g., the Sn coating process may be performed using immersion Sn plating, electroplating, and / or the like). Also, note that surface finish layer 243 may protrude beyond the top surface of dielectric layer 242, as shown in FIG. 2C.

[0045] In another embodiment, thin bridge 240 may include hybrid layers 241'-242' (shown in the left thin bridge 240 in FIG. 2C), where hybrid layers 241'-242' are comprised of a plurality of conductive pads 241' and a dielectric layer 242'. After omitting surface finish layer 243, hybrid layers 241'-242' may be substantially similar to hybrid layers 241-243.

[0046] 2D, a cross-sectional view of a semiconductor package 200 is shown according to one embodiment. In one embodiment, a thin bridge 240 having hybrid layers 241-243 may be placed over the second and third dies 211-212. In one embodiment, the thin bridge 240 may be precisely positioned (i.e., over fine pitch conductive (or Cu) pads (with slight recesses)) with the hybrid layers 241-243 facing downwardly over the second conductive pads 251b of the second and third dies 211-212. In these embodiments, the surface finish layer 243 and conductive pads 241 of the thin bridge 240 may be a plurality of Sn-coated Cu pads. In one embodiment, the Sn-coated Cu pads of the thin bridge 240 may be precisely placed over the second conductive pads 251b of the second and third dies 211-212 using a precision pick-and-place tool (or similar). Furthermore, as described above, a hybrid bonding process (or a Cu / SiO2-Cu / SiO2 hybrid bonding process) is performed on the Sn-coated Cu pads of the thin bridge 240, where the Sn-coated Cu pads are heated to about 240°C-250°C to form Cu-Sn-Cu intermetallic bonds between the conductive pads 241 of the thin bridge 240 and the second conductive pads 251b of the second and third dies 211-212, respectively. Thus, in these embodiments, the Cu-Sn-Cu intermetallic bonds can lock (i.e., hold firmly in place) the thin bridge 240 onto the second and third dies 211-212.

[0047] 2E, a cross-sectional view of the semiconductor package 200 is shown according to one embodiment. In one embodiment, a litho patterning and plating process (or similar) can be performed to deposit (or plate / form) the plurality of TMVs 222a-222b directly on the second conductive pads 251a-251b of the dies 210-212, respectively. The litho process may include several steps as described below. For example, a seed layer may be deposited on the second conductive pads 251a-251b of the dies 210-212 and the exposed surface of the dielectric layer 255. In one embodiment, the seed layer may include copper, titanium, any combination thereof, and / or the like. The seed layer may be formed using a sputtering process or the like.

[0048] After disposing the seed layer, in one embodiment, a resist layer may be disposed over the seed layer. In one embodiment, the resist layer may be a dry film resist, or the like. In one embodiment, the resist layer may be patterned (or exposed / developed) to form via openings by a lithography process, a laser drilling process, or the like. The via openings may expose top surfaces of the second conductive pads 251a-251b of the dies 210-212 in the non-bridge interfaces (or portions / regions).

[0049] In some embodiments, a conductive material (e.g., Cu) is deposited (or plated) into the via openings (or into litho vias that may be electrolessly grown and then mold sealed and planarized) to form TMVs 222a-222b on the exposed top surfaces of the second conductive pads 251a-251b of the dies 210-212, respectively. The TMVs 222a-222b may be referred to as conductive pillars / interconnects. The TMVs 222a-222b may be substantially similar to the TMVs 122a-122b described above in FIG. 1. In embodiments, the TMVs 222 may be overplated over the top surface of the resist layer to ensure complete filling of the via openings in the resist layer. In one embodiment, the TMVs 222a-222b may extend vertically from the second conductive pads 251a-251b to / beyond the top surface of the resist layer. In one embodiment, the TMVs 222a-222b may be formed by an electroplating process or the like.

[0050] In one embodiment, once the TMVs 222a-222b are overplated, the overplated TMVs 222a-222b can be planarized such that the top surfaces of the TMVs 222a-222b are substantially flush with the top surface of the resist layer. This planarization process also allows the TMVs 222a-222b to have substantially the same thickness as one another, thereby reducing any thickness variations in the semiconductor package 200. For example, after the TMVs 222a-222b are planarized, the exposed surfaces of the TMVs 222a-222b can be substantially flush with the exposed surface of the bridge 240. In one embodiment, the planarization can be performed using a CMP process or the like. The planarization process can have a high degree of accuracy due to the presence of the resist layer acting as a blocking point. Finally, the resist layer can be stripped with any suitable process, such as ashing, wet stripping, or the like. After removing the resist layer, portions of the seed layer can be exposed. The thus exposed seed layer can be etched, such as by an etching process.

[0051] 2F, a cross-sectional view of a semiconductor package 200 is shown according to one embodiment. In one embodiment, an encapsulation layer 280 may be disposed on the TMVs 222a-22b, the thin bridge 240 with the dielectric layer 242, the die 210-212 with the conductive pads 251a-251b and the dielectric layer 255, and the adhesive layer 261. In one embodiment, the encapsulation layer 280 may be disposed to cover the top surface of the TMVs 222a-222b. In one embodiment, the encapsulation layer 280 may be a mold layer and / or any similar encapsulation material. In one embodiment, the mold layer 280 may include an epoxy (e.g., soft epoxy, hard epoxy, opaque epoxy, etc.) with one or more filler materials. According to an embodiment, the encapsulation layer 280 may be compression molded, laminated, etc.

[0052] Encapsulation layer 280 may be substantially similar to encapsulation layer 180 described above in FIG. 1. In an embodiment, encapsulation layer 280 may be planarized (or polished) such that the top surfaces of TMVs 222a-222b are substantially flush with the top surfaces of encapsulation layer 280 and / or bridge 240. Further, encapsulation layer 280 is planarized / polished to expose the top surfaces of TMVs 222a-222b and / or bridge 240. In an embodiment, planarization may be performed using a CMP process, or the like.

[0053] 2G, a cross-sectional view of a semiconductor package 200 is shown according to one embodiment. In one embodiment, the HDP substrate 230 can be disposed over the encapsulation layer 280, the TMVs 222a-222b, and the top surface of the bridge 240. In this manner, the bridge interface of the HDP substrate 230 can be disposed directly on the exposed surface of the bridge 240, such that the bridge 240 with the hybrid layers 241-243 is sandwiched between the dies 211-212 and the HDP substrate 230. The HDP substrate 230 can be substantially similar to the HDP substrate 130 described in FIG. 1. Accordingly, the HDP substrate 230 can include a plurality of conductive interconnects 231 and a plurality of first conductive pads 218. The conductive interconnects 231 of the HDP substrate 230 can conductively couple the TMVs 222a-222b and the dies 210-212 to the first conductive pads 218.

[0054] In one embodiment, the first conductive pad 218 may be disposed (or plated) on the top surface of the HDP substrate 230 by the litho process described above. Note that after the semiconductor package 200 is flipped over as shown in FIG. 2L, the first conductive pad 218 will ultimately be below the HDP substrate 230 and bonded to the bottom surface of the HDP substrate 230, similar to the first conductive pad 118 described above in FIG. 1. In one embodiment, the HDP substrate 230 may include one or more RDL layers having conductive traces (or lines) with an L / S of about 2 / 2 or less, litho vias, zero misaligned vias, and / or via pads of about 18 um or less. In one embodiment, the first conductive pads 218 of the HDP substrate 230 may have a pitch of about 80 um or more.

[0055] 2H, a cross-sectional view of the semiconductor package 200 is shown according to one embodiment. In one embodiment, an encapsulation layer 280 may be further disposed over the first conductive pads 218, the HDP substrate 230, and the existing encapsulation layer 280 to completely enclose (or surround / embed) the HDP substrate 230, the bridge 240, and the dies 210-212. The encapsulation layer 280 may be substantially the same as the encapsulation layer 280 described above in FIG. 2F. Furthermore, in one embodiment, the encapsulation layer 280 may be planarized to expose a top surface of the first conductive pads 218, which may be substantially flush with the top surface of the encapsulation layer 280. As described above, the encapsulation layer 280 may be planarized, such as by a CMP process.

[0056] 2I, a cross-sectional view of a semiconductor package 200 is shown according to one embodiment. In an optional embodiment, a plurality of solder balls 223 may be disposed and coupled directly onto the exposed surface of the first conductive pad 218. The solder balls 223 may be substantially similar to the solder balls 123 described above in FIG.

[0057] 2J, a cross-sectional view of semiconductor package 200 is shown according to one embodiment. In one embodiment, carrier 201 and adhesive layer 261 may be removed from the underlying dies 210-212 and encapsulation layer 280 to expose the (top) surfaces of dies 210-212. After removing carrier 201 along with adhesive layer 261, the (top) surfaces of dies 210-212 may be substantially coplanar with the (top) surface of encapsulation layer 280.

[0058] 2K, a cross-sectional view of a semiconductor package 200 is shown according to one embodiment. In one embodiment, the semiconductor package 200 is capable of singulating multiple patches (packages) to form individual patches (or packages), which may be substantially similar to the semiconductor package 100 described above in FIG. 1. Singulating the patches of the semiconductor package 200 may be accomplished by dicing, sawing, laser machining, etc., into a single patch, as shown for the package in FIG. 2K.

[0059] 2L, a cross-sectional view of a semiconductor package 200 is shown according to one embodiment. In one embodiment, the first conductive pads 218 of the HDP substrate 230 may be disposed and coupled to a top surface of the package substrate 202. The package substrate 202 may be substantially similar to the package substrate 102 described above in FIG. 1. Further, as described above, an underfill material 254 may be disposed over the encapsulation layer 280 and the package substrate 202, where the underfill material 254 may be disposed between the HDP substrate 230 and the package substrate 202. The underfill material 254 may surround the first solder balls 223 and a portion of the encapsulation layer 280. The underfill material 254 may be substantially similar to the underfill material 154 described above in FIG. 1.

[0060] It should be noted that the semiconductor package 200 of FIGS. 2A-2L may include fewer or additional package components based on the desired package design.

[0061] 3, a cross-sectional view of a semiconductor package 300 is shown according to one embodiment. The semiconductor package 300 may be substantially similar to the semiconductor packages 100 and 200 of FIGS. 1 and 2A-2L, with the following differences: each of the two sets of dies 310-312 is disposed on and coupled to two HDP substrates 330 and two thin bridges 340, and one or more of the thin bridges 340 may include multiple TSVs, if desired, such that the TSVs of the thin bridges 340 may be directly coupled (or soldered) to the HDP substrate 330 to provide power directly to I / O circuitry, such as the dies 310-312 and / or substrate 301.

[0062] While one set of dies 110-112 is disposed on and coupled to one HDP substrate 130 and one thin bridge 140 in FIG. 1, two sets of dies 310-312 are disposed on and communicatively coupled to respective HDP substrates 330 and thin bridges 340 with ultra-fine pitch in FIG. 3, thereby maintaining a significantly reduced overall thickness (or z-height) of semiconductor package 300 using only one thin bridge 340 with ultra-thin hybrid layers 341-343 while adding additional desired ICs, such as additional dies, to improve the overall performance of semiconductor package 300.

[0063] Also, while the thin bridge 140 has hybrid layers 141-143 without any TSVs in FIG. 1, the thin bridge 340 can realize hybrid layers 341-343 with TSVs in FIG. 3, thereby providing power directly to each die 310-312 and / or substrate 301 to improve the overall power performance of the semiconductor package 300. Although two dies 310-312, one HDP substrate 330, and one thin bridge 340 are shown in each patch, it should be understood that any number of dies 310-312, HDP substrates 330, and thin bridges 340 may be positioned (or positioned) against / over the substrate 301 in each patch. Note that the semiconductor package 300 may be singulated from two patches (or multiple packages) into individual patches (or multiple packages) as described above in FIGS. 2K-2L.

[0064] In one embodiment, the substrate 301 may be a package substrate, a carrier, an interposer, and / or the like. As mentioned above, the semiconductor package 300 may be substantially similar to the above-described semiconductor package 100 of FIG. 1. Similarly, the components of the above-described semiconductor package 300 may be substantially similar to the components of the above-described semiconductor package 100 of FIG. 1. Additionally, the substrate 301, die 310-312, TMV 322a-b, solder balls 323, HDP substrate 330, conductive interconnects 331, thin bridge 340, hybrid layers 341-343, first and second conductive pads 318-351a-b, dielectric layer 355, and encapsulation layer 380 may be substantially similar to the package substrate 101, die 110-112, TMV 122a-b, solder balls 123, HDP substrate 130, conductive interconnects 131, thin bridge 140, hybrid layers 141-143, first and second conductive pads 118-151a-b, dielectric layer 155, and encapsulation layer 180 illustrated in FIG.

[0065] It should be noted that semiconductor package 300 may include fewer or additional package components based on the desired package design.

[0066] FIG. 4 is a schematic block diagram illustrating a device package 410 (or semiconductor package) computer system 400 having multiple dies, an HDP substrate, a thin bridge with hybrid layers, multiple TMVs, and a package substrate, according to one embodiment. FIG. 4 illustrates an example of a computing device 400. The computing device 400 houses a motherboard 402. The motherboard 402 may include a number of components, including but not limited to a processor 404, a device package 410 (or semiconductor package), and at least one communication chip 406. The processor 404 is physically and electrically coupled to the motherboard 402. In some embodiments, the at least one communication chip 406 is also physically and electrically coupled to the motherboard 402. In other embodiments, the at least one communication chip 406 is part of the processor 404.

[0067] Depending on the application, computing device 400 may include other components that may or may not be physically and electrically coupled to motherboard 402. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touchscreen displays, touchscreen controllers, batteries, audio codecs, video codecs, power amplifiers, Global Positioning System (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (such as hard disk drives, compact discs (CDs), digital versatile discs (DVDs), etc.).

[0068] At least one communication chip 406 enables wireless communication for data transfer to and from the computing device. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can communicate data by utilizing modulated electromagnetic radiation over a non-solid medium. The term does not imply that the associated device does not include any wires, although in some embodiments it may not. At least one communication chip 406 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.112 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols designated as 3G, 4G, 5G and beyond. Computing device 400 may include multiple communication chips 406. For example, the first communications chip 406 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, and the second communications chip 406 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, and Ev-DO.

[0069] The processor 404 of the computing device 400 includes an integrated circuit die packaged within the processor 404. The device package 410 may be a semiconductor package that may include, but is not limited to, a substrate, a package substrate, and / or a PCB. In one embodiment, the device package 410 may be substantially similar to the semiconductor package of FIGS. 1-3 described herein. The device package 410 may include a die, an HDP substrate, a thin bridge with a hybrid layer, interconnects having various widths (e.g., conductive pads 151a-151b and TMVs 122a-122b of FIG. 1), and a package substrate as described herein (e.g., as described above with the semiconductor package of FIGS. 1-3), or any other components in the figures described herein.

[0070] It should be noted that device package 410 may be a single component / device, a subset of components, and / or an entire system, as the materials, features, and components may be limited to device package 410 and / or any other components of computing device 400 (e.g., motherboard 402, processor 404, and / or any other components of computing device 400 that may require an embodiment of a semiconductor package described herein) that may require a solderless ultra-thin bridge locked / bonded / placed between the die and the HDP substrate having an ultra-fine pitch and ultra-thin hybrid layer as described herein.

[0071] In certain embodiments, an integrated circuit die may be packaged with one or more devices on a package substrate, including a thermally stable RFIC and an antenna for use in wireless communications, as described herein, to reduce the z-height of the computing device. The term "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory.

[0072] At least one of the communications chips 406 also includes an integrated circuit die packaged within the communications chip 406. In some embodiments, the integrated circuit die of the communications chip 406 may be packaged with one or more devices on a packaging substrate that includes one or more device packages, as described herein.

[0073] In the above description, the embodiments have been described with reference to certain exemplary embodiments thereof. It should be borne in mind, however, that these and all similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. It should be apparent that various modifications may be made thereto without departing from the broader spirit and scope. The specification and drawings should therefore be regarded in an illustrative rather than a restrictive sense.

[0074] The following examples relate to further examples: The various features of the various embodiments may be combined in various ways, with some included and others excluded, to suit a wide variety of applications.

[0075] The following specific examples relate to further embodiments:

[0076] Example 1 is a semiconductor package comprising: a bridge on an HPD substrate and including a hybrid layer; a plurality of dies on the bridge and the HDP substrate, where the bridge is coupled between the plurality of dies and the HDP substrate, the bridge is directly coupled to two of the plurality of dies by the hybrid layer, a top surface of the hybrid layer of the bridge directly contacts bottom surfaces of the plurality of dies and a bottom surface of the bridge directly contacts a top surface of the HDP substrate; and a plurality of TMVs on the HDP substrate, where the plurality of TMVs couple the HDP substrate to the plurality of dies, the plurality of TMVs having a thickness substantially equal to a thickness of the bridge.

[0077] In Example 2, the subject matter of Example 1 may optionally include the following features: the hybrid layer of the bridge includes a plurality of conductive pads and a dielectric, the dielectric surrounding the plurality of conductive pads.

[0078] In Example 3, the subject matter of Examples 1-2 may optionally include the following features: the hybrid layer of the bridge further includes a surface finish, the surface finish being in direct contact with top surfaces of the plurality of conductive pads.

[0079] In Example 4, the subject matter of Examples 1-3 can optionally include the following features: the plurality of conductive pads are a plurality of copper pads, the dielectric comprises a silicon dioxide material, and the surface finish comprises a tin material.

[0080] In example 5, the subject matter of examples 1-4 can optionally include the following features: the bridge is an EMIB, the EMIB communicatively coupled to the plurality of dies.

[0081] In Example 6, the subject matter of Examples 1-5 can optionally include the following features: the HDP substrate includes a plurality of conductive interconnects, the plurality of dies include a plurality of second conductive pads and a first dielectric, the plurality of second conductive pads and the first dielectric are on the bottom surfaces of the plurality of dies, the first dielectric surrounds the plurality of second conductive pads, the plurality of TMVs extend vertically from the top surface of the HDP substrate to the bottom surfaces of the plurality of dies, and the plurality of TMVs conductively couple the plurality of conductive connections of the HDP substrate to the plurality of second conductive pads of the plurality of dies.

[0082] In example 7, the subject matter of examples 1-6 can optionally include the following features: a plurality of first conductive pads on a bottom surface of the HDP substrate, the HDP substrate overlying a package substrate, the plurality of first conductive pads of the HDP substrate being conductively coupled to the package substrate by a plurality of solder balls; an encapsulation layer overlying the plurality of dies, the plurality of first and second conductive pads, the first dielectric, the plurality of TMVs, the bridge, the hybrid layer, and the HDP substrate, the encapsulation layer having a top surface that is substantially coplanar with a top surface of the plurality of dies and a bottom surface that is substantially coplanar with a bottom surface of the plurality of first conductive pads; and an underfill material overlying the encapsulation layer and the package substrate, the underfill material being between the bottom surface of the encapsulation layer and the top surface of the package substrate, the underfill material enclosing the encapsulation layer and the plurality of solder balls.

[0083] In Example 8, the subject matter of Examples 1-7 may optionally include the following features: the plurality of TMVs includes a plurality of first TMVs and a plurality of second TMVs, the plurality of first TMVs having a width greater than a width of the plurality of second TMVs, the plurality of second conductive pads includes a plurality of third conductive pads and a plurality of fourth conductive pads, the plurality of third conductive pads having a width greater than a width of the plurality of fourth conductive pads, the plurality of first TMVs being directly coupled to the plurality of third conductive pads, and the plurality of second TMVs being directly coupled to the plurality of fourth conductive pads.

[0084] In Example 9, the subject matter of Examples 1-8 may optionally include the following features: the surface finish of the hybrid layer of the bridge is directly bonded to the fourth conductive pads of the two dies of the plurality of dies, and the surface finish is directly between the conductive pads of the hybrid layer of the bridge and the fourth conductive pads of the two dies of the plurality of dies.

[0085] In Example 10, the subject matter of Examples 1-9 can optionally include the following features: the bridge is a thin bridge, the thin bridge has a thickness of about 15 um or less, the thin bridge is directly coupled to two of the multiple dies and the HDP substrate without a solder material, and the thin bridge includes a plurality of TSVs coupling the HDP substrate and the multiple dies.

[0086] Example 11 is a method for forming a semiconductor package, the method including the steps of: disposing a plurality of dies on a carrier, the plurality of dies being bonded to the carrier by an adhesive layer; disposing a bridge over two of the plurality of dies, the bridge including a hybrid layer, the bridge being bonded directly to the two dies by the hybrid layer; disposing a plurality of TMVs on the plurality of dies, the plurality of TMVs surrounding the bridge; disposing an encapsulation layer on the plurality of dies, the bridge, the hybrid layer, the plurality of TMVs, and the adhesive layer; and disposing an HDP substrate on the encapsulation layer, the plurality of TMVs, the bridge, and the plurality of dies, the plurality of TMVs bonding the HDP substrate to the plurality of dies, the plurality of TMVs having a thickness substantially equal to a thickness of the bridge, the bridge being bonded between the plurality of dies and the HDP substrate, a top surface of the hybrid layer of the bridge directly contacting bottom surfaces of the plurality of dies, and a bottom surface of the bridge directly contacting a top surface of the HDP substrate.

[0087] In Example 12, the subject matter of Example 11 may optionally include the following features: the hybrid layer of the bridge includes a plurality of conductive pads and a dielectric, the dielectric surrounding the plurality of conductive pads.

[0088] In Example 13, the subject matter of Examples 11-12 may optionally include the following features: the hybrid layer of the bridge further includes a surface finish, the surface finish being in direct contact with the top surfaces of the plurality of conductive pads.

[0089] In Example 14, the subject matter of Examples 11-13 can optionally include the following features: the plurality of conductive pads are a plurality of copper pads, the dielectric includes a silicon dioxide material, and the surface finish includes a tin material.

[0090] In example 15, the subject matter of examples 11-14 can optionally include the following features: the bridge is an EMIB, the EMIB communicatively coupled to the plurality of dies.

[0091] In Example 16, the subject matter of Examples 11-15 can optionally include the following features: the HDP substrate includes a plurality of conductive interconnects, the plurality of dies include a plurality of second conductive pads and a first dielectric, the plurality of second conductive pads and the first dielectric are on the bottom surfaces of the plurality of dies, the first dielectric surrounds the plurality of second conductive pads, the plurality of TMVs extend vertically from the top surface of the HDP substrate to the bottom surfaces of the plurality of dies, and the plurality of TMVs conductively couple the plurality of conductive connections of the HDP substrate to the plurality of second conductive pads of the plurality of dies.

[0092] In example 17, the subject matter of examples 11-16 can optionally include the following features: disposing a plurality of first conductive pads on a bottom surface of the HDP substrate; disposing an encapsulating layer over the plurality of first conductive pads and the HDP substrate, the encapsulating layer enclosing the plurality of dies, the plurality of first and second conductive pads, the first dielectric, the plurality of TMVs, the bridge, the hybrid layer, and the HDP substrate, the encapsulating layer having a top surface that is substantially coplanar with top surfaces of the plurality of dies, and the encapsulating layer having a bottom surface that is substantially coplanar with bottom surfaces of the plurality of first conductive pads. removing the carrier to expose the top surface of the encapsulation layer and the top surfaces of the plurality of dies; disposing the bottom surface of the encapsulation layer and the HDP substrate on a carrier substrate, where the first conductive pads of the HDP substrate are conductively coupled to the package substrate by a plurality of solder balls; and disposing an underfill material over the encapsulation layer and the package substrate, where the underfill material is between the bottom surface of the encapsulation layer and the top surface of the package substrate, where the underfill material surrounds the encapsulation layer and the plurality of solder balls.

[0093] In Example 18, the subject matter of Examples 11-17 may optionally include the following features: the plurality of TMVs includes a plurality of first TMVs and a plurality of second TMVs, the plurality of first TMVs having a width greater than a width of the plurality of second TMVs, the plurality of second conductive pads includes a plurality of third conductive pads and a plurality of fourth conductive pads, the plurality of third conductive pads having a width greater than a width of the plurality of fourth conductive pads, the plurality of first TMVs being directly coupled to the plurality of third conductive pads, and the plurality of second TMVs being directly coupled to the plurality of fourth conductive pads.

[0094] In Example 19, the subject matter of Examples 11-18 may optionally include the following features: the surface finish of the hybrid layer of the bridge is directly bonded to the fourth conductive pads of the two dies of the plurality of dies, and the surface finish is directly between the conductive pads of the hybrid layer of the bridge and the fourth conductive pads of the two dies of the plurality of dies.

[0095] In Example 20, the subject matter of Examples 11-19 can optionally include the following features: the bridge is a thin bridge, the thin bridge has a thickness of about 15 um or less, the thin bridge is directly coupled to two of the multiple dies and the HDP substrate without a solder material, and the thin bridge includes a plurality of TSVs coupling the HDP substrate and the multiple dies.

[0096] Example 21 is a semiconductor package comprising: an HDP substrate overlying a package substrate; a bridge on the HDP substrate and including a hybrid layer, the hybrid layer including a plurality of conductive pads, a surface finish, and a dielectric; a plurality of dies overlying the bridge and the HDP substrate, the bridge being coupled between the plurality of dies and the HDP substrate, the bridge being directly coupled to two of the plurality of dies by the hybrid layer, a top surface of the hybrid layer of the bridge directly contacting the bottom surfaces of the plurality of dies, and a bottom surface of the bridge directly contacting the top surface of the HDP substrate; a plurality of TMVs on the HDP substrate, the plurality of TMVs coupling the HDP substrate to the plurality of dies, the plurality of TMVs having a thickness substantially equal to a thickness of the bridge; and an encapsulation layer overlying and surrounding the plurality of dies, the plurality of TMVs, the bridge, the hybrid layer, and the HDP substrate, the encapsulation layer having a top surface directly contacting the top surfaces of the plurality of dies.

[0097] In Example 22, the subject matter of Example 21 may optionally include the following features: the dielectric surrounds the plurality of conductive pads, the surface finish is in direct contact with top surfaces of the plurality of conductive pads, the plurality of conductive pads are a plurality of copper pads, the dielectric comprises a silicon dioxide material, the surface finish comprises a tin material, the bridge is an EMIB, and the EMIB is communicatively coupled to the plurality of dies.

[0098] In Example 23, the subject matter of Examples 21-22 may optionally include the following features: the HDP substrate includes a plurality of conductive interconnects, the plurality of dies include a plurality of second conductive pads and a first dielectric, the plurality of second conductive pads and the first dielectric are on the bottom surfaces of the plurality of dies, the first dielectric surrounds the plurality of second conductive pads, the plurality of TMVs extend vertically from the top surface of the HDP substrate to the bottom surfaces of the plurality of dies, and the plurality of TMVs conductively couple the plurality of conductive connections of the HDP substrate to the plurality of second conductive pads of the plurality of dies.

[0099] In Example 24, the subject matter of Examples 21-23 may optionally include the following features: a plurality of first conductive pads on a bottom surface of the HDP substrate, the plurality of first conductive pads of the HDP substrate conductively coupled to the package substrate by a plurality of solder balls, the encapsulation layer enclosing the plurality of dies, the plurality of first and second conductive pads, the first dielectric, the plurality of TMVs, the bridge, the hybrid layer, and the HDP substrate, the encapsulation layer having a bottom surface that is substantially coplanar with the bottom surfaces of the plurality of first conductive pads; an underfill material over the encapsulation layer and the package substrate, the underfill material being between the bottom surface of the encapsulation layer and a top surface of the package substrate, the underfill material enclosing the encapsulation layer and the plurality of solder balls; and one or more thermal devices over the top surfaces of the plurality of dies and the top surface of the encapsulation layer.

[0100] In example 25, the subject matter of examples 21-24 can optionally include the following features: the plurality of TMVs includes a plurality of first TMVs and a plurality of second TMVs, the plurality of first TMVs having a width greater than a width of the plurality of second TMVs, the plurality of second conductive pads includes a plurality of third conductive pads and a plurality of fourth conductive pads, the plurality of third conductive pads having a width greater than a width of the plurality of fourth conductive pads, the plurality of first TMVs are directly coupled to the plurality of third conductive pads, the plurality of second TMVs are directly coupled to the plurality of fourth conductive pads, and the hive of the bridge. the surface finish of the lid layer is directly bonded to the fourth conductive pads of the two dies of the plurality of dies, the surface finish being between the conductive pads of the hybrid layer of the bridge and the fourth conductive pads of the two dies of the plurality of dies, the bridge being a thin bridge, the thin bridge having a thickness of about 15 um or less, the thin bridge being directly bonded to the two dies of the plurality of dies and the HDP substrate without a solder material, and the thin bridge including a plurality of TSVs coupling the HDP substrate and the plurality of dies.

[0101] The method and apparatus have been described herein with reference to certain exemplary embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope thereof. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. 1. A semiconductor package comprising: A bridge in a high density package (HDP) substrate, the bridge including a hybrid layer; a plurality of dies on the bridge and the HDP substrate, the bridge being coupled between the plurality of dies and the HDP substrate, the bridge being coupled directly to two of the plurality of dies by the hybrid layer, a top surface of the hybrid layer of the bridge directly contacting bottom surfaces of the plurality of dies, and a bottom surface of the bridge directly contacting a top surface of the HDP substrate; and a plurality of through mold vias (TMVs) in the HDP substrate, the plurality of TMVs coupling the HDP substrate to the plurality of dies, the plurality of TMVs having a thickness substantially equal to a thickness of the bridge; A semiconductor package comprising:

2. 2. The semiconductor package of claim 1, wherein the hybrid layer of the bridge includes a plurality of conductive pads and a dielectric, the dielectric surrounding the plurality of conductive pads.

3. 3. The semiconductor package of claim 2, wherein the hybrid layer of the bridge further comprises a surface finish, the surface finish directly contacting a top surface of the plurality of conductive pads.

4. 4. The semiconductor package of claim 3, wherein the plurality of conductive pads are a plurality of copper pads, the dielectric comprises a silicon dioxide material, and the surface finish comprises a tin material or a copper material.

5. 5. The semiconductor package of claim 1, 2, 3 or 4, wherein the bridge is an embedded multi-die interconnect bridge (EMIB), the EMIB communicatively coupled to the multiple dies.

6. 5. The semiconductor package of claim 1, 2, 3 or 4, wherein the HDP substrate includes a plurality of conductive interconnects, the plurality of dies includes a plurality of second conductive pads and a first dielectric, the plurality of second conductive pads and the first dielectric are on the bottom surfaces of the plurality of dies, the first dielectric surrounds the plurality of second conductive pads, the plurality of TMVs extend vertically from the top surface of the HDP substrate to the bottom surfaces of the plurality of dies, and the plurality of TMVs conductively couple the plurality of conductive interconnects of the HDP substrate to the plurality of second conductive pads of the plurality of dies.

7. a plurality of first conductive pads on a bottom surface of the HDP substrate, the HDP substrate overlying a package substrate, the plurality of first conductive pads of the HDP substrate being conductively coupled to the package substrate by a plurality of solder balls; an encapsulation layer overlying and surrounding the plurality of dies, the plurality of first and second conductive pads, the first dielectric, the plurality of TMVs, the bridge, the hybrid layer, and the HDP substrate, the encapsulation layer having a top surface that is substantially coplanar with top surfaces of the plurality of dies and a bottom surface that is substantially coplanar with bottom surfaces of the plurality of first conductive pads; and an underfill material overlying the encapsulation layer and the package substrate, the underfill material being between the bottom surface of the encapsulation layer and the top surface of the package substrate, the underfill material surrounding the encapsulation layer and the plurality of solder balls; The semiconductor package of claim 6 further comprising:

8. 7. The semiconductor package of claim 6, wherein the plurality of TMVs includes a plurality of first TMVs and a plurality of second TMVs, the plurality of first TMVs having a width greater than a width of the plurality of second TMVs, the plurality of second conductive pads includes a plurality of third conductive pads and a plurality of fourth conductive pads, the plurality of third conductive pads having a width greater than a width of the plurality of fourth conductive pads, the plurality of first TMVs being directly coupled to the plurality of third conductive pads, and the plurality of second TMVs being directly coupled to the plurality of fourth conductive pads.

9. 9. The semiconductor package of claim 8, wherein the surface finish of the hybrid layer of the bridge is directly bonded to the fourth conductive pads of the two dies of the plurality of dies, and the surface finish is directly between the conductive pads of the hybrid layer of the bridge and the fourth conductive pads of the two dies of the plurality of dies.

10. 5. The semiconductor package of claim 1, 2, 3, or 4, wherein the bridge is a thin bridge, the thin bridge having a thickness of about 15 um or less, the thin bridge is directly coupled to the two dies of the plurality of dies and the HDP substrate without a solder material, and the thin bridge includes a plurality of through silicon vias (TSVs) coupling the HDP substrate and the plurality of dies.

11. 1. A method of forming a semiconductor package, comprising: disposing a plurality of dies on a carrier, the plurality of dies being bonded to the carrier by an adhesive layer; disposing a bridge over two of the plurality of dies, the bridge including a hybrid layer, the bridge being directly coupled to the two dies by the hybrid layer; disposing a plurality of TMVs on the plurality of dies, the plurality of TMVs surrounding the bridge; disposing an encapsulation layer over the dies, the bridge, the hybrid layer, the TMVs, and the adhesive layer; and disposing an HDP substrate over the encapsulation layer, the TMVs, the bridge, and the dies, the TMVs coupling the HDP substrate to the dies, the TMVs having a thickness substantially equal to a thickness of the bridge, the bridge coupled between the dies and the HDP substrate, a top surface of the hybrid layer of the bridge directly contacting bottom surfaces of the dies, and a bottom surface of the bridge directly contacting a top surface of the HDP substrate; The method according to claim 1,

12. The method of claim 11 , wherein the hybrid layer of the bridge includes a plurality of conductive pads and a dielectric, the dielectric surrounding the plurality of conductive pads.

13. The method of claim 12 , wherein the hybrid layer of the bridge further comprises a surface finish, the surface finish directly contacting a top surface of the plurality of conductive pads.

14. 14. The method of claim 13, wherein the plurality of conductive pads are a plurality of copper pads, the dielectric comprises a silicon dioxide material, and the surface finish comprises a tin material or a copper material.

15. 15. The method of claim 11, 12, 13 or 14, wherein the bridge is an EMIB, the EMIB being communicatively coupled to the plurality of dies.

16. 15. The method of claim 11, 12, 13 or 14, wherein the HDP substrate includes a plurality of conductive interconnects, the plurality of dies includes a plurality of second conductive pads and a first dielectric, the plurality of second conductive pads and the first dielectric are on the bottom surfaces of the plurality of dies, the first dielectric surrounds the plurality of second conductive pads, the plurality of TMVs extend vertically from the top surface of the HDP substrate to the bottom surfaces of the plurality of dies, and the plurality of TMVs conductively couple the plurality of conductive interconnects of the HDP substrate to the plurality of second conductive pads of the plurality of dies.

17. disposing a plurality of first conductive pads on a bottom surface of the HDP substrate; disposing the encapsulating layer over the plurality of first conductive pads and the HDP substrate, the encapsulating layer encapsulating the plurality of dies, the plurality of first and second conductive pads, the first dielectric, the plurality of TMVs, the bridge, the hybrid layer, and the HDP substrate, the encapsulating layer having a top surface that is substantially coplanar with top surfaces of the plurality of dies, and the encapsulating layer having a bottom surface that is substantially coplanar with bottom surfaces of the plurality of first conductive pads; removing the carrier to expose the top surface of the encapsulation layer and the top surfaces of the plurality of dies; disposing the bottom surface of the encapsulation layer and the HDP substrate over a package substrate, the first conductive pads of the HDP substrate being conductively coupled to the package substrate by a plurality of solder balls; disposing an underfill material over the encapsulation layer and the package substrate, the underfill material being between the bottom surface of the encapsulation layer and the top surface of the package substrate, the underfill material surrounding the encapsulation layer and the plurality of solder balls; 20. The method of claim 16 further comprising:

18. 17. The method of claim 16, wherein the plurality of TMVs includes a plurality of first TMVs and a plurality of second TMVs, the plurality of first TMVs having a width greater than a width of the plurality of second TMVs, the plurality of second conductive pads includes a plurality of third conductive pads and a plurality of fourth conductive pads, the plurality of third conductive pads having a width greater than a width of the plurality of fourth conductive pads, the plurality of first TMVs being directly coupled to the plurality of third conductive pads and the plurality of second TMVs being directly coupled to the plurality of fourth conductive pads.

19. 20. The method of claim 18, wherein the surface finish of the hybrid layer of the bridge is directly bonded to the fourth conductive pads of the two dies of the plurality of dies, and the surface finish is directly between the conductive pads of the hybrid layer of the bridge and the fourth conductive pads of the two dies of the plurality of dies.

20. 15. The method of claim 11, 12, 13, or 14, wherein the bridge is a thin bridge, the thin bridge having a thickness of about 15 um or less, the thin bridge is directly coupled to the two dies of the plurality of dies and the HDP substrate without a solder material, and the thin bridge includes a plurality of TSVs coupling the HDP substrate and the plurality of dies.

21. 1. A semiconductor package comprising: HDP substrate on top of the package substrate; a bridge on the HDP substrate, the bridge including a hybrid layer, the hybrid layer including a plurality of conductive pads, a surface finish, and a dielectric; a plurality of dies on the bridge and the HDP substrate, the bridge being coupled between the plurality of dies and the HDP substrate, the bridge being coupled directly to two of the plurality of dies by the hybrid layer, a top surface of the hybrid layer of the bridge directly contacting bottom surfaces of the plurality of dies, and a bottom surface of the bridge directly contacting a top surface of the HDP substrate; a plurality of TMVs on the HDP substrate, the plurality of TMVs coupling the HDP substrate to the plurality of dies, the plurality of TMVs having a thickness substantially equal to a thickness of the bridge; and an encapsulation layer overlying and surrounding the plurality of dies, the plurality of TMVs, the bridge, the hybrid layer, and the HDP substrate, the encapsulation layer having a top surface that is substantially coplanar with a top surface of the plurality of dies; A semiconductor package comprising:

22. 22. The semiconductor package of claim 21, wherein the dielectric surrounds the plurality of conductive pads, the surface finish is in direct contact with top surfaces of the plurality of conductive pads, the plurality of conductive pads are a plurality of copper pads, the dielectric comprises a silicon dioxide material, the surface finish comprises a tin material or a copper material, the bridge is an EMIB, and the EMIB is communicatively coupled to the plurality of dies.

23. 23. The semiconductor package of claim 21 or 22, wherein the HDP substrate includes a plurality of conductive interconnects, the plurality of dies includes a plurality of second conductive pads and a first dielectric, the plurality of second conductive pads and the first dielectric are on the bottom surfaces of the plurality of dies, the first dielectric surrounds the plurality of second conductive pads, the plurality of TMVs extend vertically from the top surface of the HDP substrate to the bottom surfaces of the plurality of dies, and the plurality of TMVs conductively couple the plurality of conductive interconnects of the HDP substrate to the plurality of second conductive pads of the plurality of dies.

24. a plurality of first conductive pads on a bottom surface of the HDP substrate, the plurality of first conductive pads of the HDP substrate being conductively coupled to the package substrate by a plurality of solder balls, the encapsulation layer enclosing the plurality of dies, the plurality of first and second conductive pads, the first dielectric, the plurality of TMVs, the bridge, the hybrid layer, and the HDP substrate, the encapsulation layer having a bottom surface that is substantially coplanar with the bottom surfaces of the plurality of first conductive pads; an underfill material overlying the encapsulation layer and the package substrate, the underfill material being between the bottom surface of the encapsulation layer and the top surface of the package substrate, the underfill material surrounding the encapsulation layer and the plurality of solder balls; and one or more thermal devices on the top surfaces of the plurality of dies and on the top surface of the encapsulation layer; 24. The semiconductor package of claim 23, further comprising:

25. the plurality of TMVs includes a plurality of first TMVs and a plurality of second TMVs, the plurality of first TMVs having a width greater than a width of the plurality of second TMVs, the plurality of second conductive pads includes a plurality of third conductive pads and a plurality of fourth conductive pads, the plurality of third conductive pads having a width greater than a width of the plurality of fourth conductive pads, the plurality of first TMVs are directly coupled to the plurality of third conductive pads, the plurality of second TMVs are directly coupled to the plurality of fourth conductive pads, and the surface finish of the hybrid layer of the bridge is preferably a surface finish of the two dies of the plurality of dies.

24. The semiconductor package of claim 23, wherein the surface finish is directly between the conductive pads of the hybrid layer of the bridge and the fourth conductive pads of the two dies of the plurality of dies, the bridge is a thin bridge, the thin bridge has a thickness of about 15 um or less, the thin bridge is directly coupled to the two dies of the plurality of dies and the HDP substrate without a solder material, and the thin bridge includes a plurality of TSVs coupling the HDP substrate and the plurality of dies.

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