Structure in which multiple components are embedded and packaged in layers and its manufacturing method

Abstract

To provide a structure obtained by embedding and packaging multiple components layer by layer, and a method for manufacturing the same.SOLUTION: A manufacturing method includes: preparing a polymer supporting frame; forming a first packaging layer 1015; forming a first circuit layer and a second circuit layer 3012, forming a second insulating layer 201 on the first circuit layer, and forming a third insulating layer 301 on the second circuit layer; forming a second component placement frame 2016 vertically overlapping a first component placement frame 1013; mounting a second component 1042 and a third component 1043 in the second component placement frame to form a second packaging layer 2018; and forming a third circuit layer 4012 on the second insulating layer. Respective terminals of the second and third components are in communication with the third circuit layer. The first conductive circuit layer 2012 and the third circuit layer are conductively connected through a second conductive copper pillar layer 2014.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a packaging structure for electronic components, and more particularly to a structure in which a plurality of components are embedded and packaged in separate layers, and a method for manufacturing the same. [Background technology]

[0002] At present, in the field of panel-level embedded packaging, although it has been possible to realize embedded packaging of multiple components, there are still certain limitations: multiple components are embedded packaged at the same level inside the board at one time, and the horizontal dimension is large, which cannot meet the development requirements for miniaturization of embedded packaging, and the most reasonable embedded packaging structure cannot be realized based on the actual product structure and wiring design, which increases the difficulty of wiring and the length of the conductor wires, affecting the electrical performance. Summary of the Invention [Problem to be solved by the invention]

[0003] In order to solve the above technical problems, the embodiment of the present invention provides a structure and a manufacturing method for embedding multiple components in layers. Based on the actual needs of the packaging module, the present invention can embed and package multiple components at different levels of the substrate, effectively reducing the dimensions in the XY direction, realizing higher density integrated packaging, while reducing the wiring difficulty, and realizing the shortest distance electrical connection between the components and the substrate, thereby improving the electrical performance of the packaging module. [Means for solving the problem]

[0004] A first aspect of the present invention relates to a method for manufacturing a multi-component embedded packaged structure in layers, comprising the steps of: (a) providing a polymer support frame, the polymer support frame including a first insulating layer, a first conductive copper pillar layer penetrating the first insulating layer, and a first component placement frame; (b) mounting a first component on a bottom of the first component frame, and forming a first packaging layer in a gap between the first component frame and the first component; (c) forming a first circuit layer and a second circuit layer on an upper surface and a lower surface of the first insulating layer, respectively, the first circuit layer including a first conductive circuit layer and a first sacrificial circuit layer, the first sacrificial circuit layer covering the first component placement frame, a terminal of the first component communicating with the second circuit layer, and the first conductive circuit layer and the second circuit layer being conductively connected via the first conductive copper pillar layer. (d) forming a second copper pillar layer on the first circuit layer, the second copper pillar layer including a second conductive copper pillar layer and a second sacrificial copper pillar layer, the second sacrificial copper pillar layer located on the first sacrificial circuit layer. (e) laminating an insulating material on the first circuit layer and the second copper pillar layer, thinning the insulating material to expose an end of the second copper pillar layer to form a second insulating layer, and laminating an insulating material on the second circuit layer to form a third insulating layer. (f) etching the first sacrificial circuit layer and the second sacrificial copper pillar layer to form a second component frame, the second component frame vertically overlapping the first component frame; (g) mounting a second component and a third component on the bottom of the second component frame, and forming a second packaging layer in a gap between the second component frame and the second component and the third component, the second component and the third component being layered and vertically overlapping the first component, respectively. (h) forming a third circuit layer on an upper surface of the second insulating layer, a terminal of the second component and a terminal of the third component each communicating with the third circuit layer, and the first conductive circuit layer and the third circuit layer being conductively connected via the second conductive copper pillar layer.

[0005] In some embodiments, the method further comprises: (i) Continuing after step (h), laminating an insulating material onto the third circuit layer to form a fourth insulating layer, and forming a first blind via and a second blind via in the third insulating layer and the fourth insulating layer, respectively. (j) forming a first conductive via and a fifth circuit layer within the first blind via and on the surface of the third insulating layer, respectively, and forming a second conductive via and a fourth circuit layer within the second blind via and on the surface of the fourth insulating layer, respectively, the second circuit layer and the fifth circuit layer being conductively connected via the first conductive via, and the third circuit layer and the fourth circuit layer being conductively connected via the second conductive via. (k) forming a first solder resist layer on the fourth circuit layer, forming a second solder resist layer on the fifth circuit layer, and treating the metal surfaces exposed in the first solder resist layer and the second solder resist layer, respectively, to form a first metal surface treatment layer and a second metal surface treatment layer.

[0006] In some embodiments, step (b) comprises: (b1) providing a first adhesive layer on a bottom portion of the first insulating layer; (b2) A terminal surface of the first component is attached to a first adhesive layer exposed within the first component arrangement frame. (b3) A packaging material is laminated on an upper surface of the first insulating layer and in a gap between the first component and the first component placement frame, and the packaging material is hardened to form a first packaging layer. (b4) thinning the first packaging layer to expose ends of the first conductive copper pillar layer. (b5) removing the first adhesive layer;

[0007] In some embodiments, the first adhesive layer comprises a single-sided tape.

[0008] In some embodiments, step (g) includes providing an adhesive material on a bottom of the second component frame, and then mounting a back surface of the second component and a back surface of the third component to the adhesive material, respectively, thereby achieving mounting of the second component and the third component to the bottom of the second component frame.

[0009] In some embodiments, step (g) includes providing an adhesive material on the back surface of the second component and the back surface of the third component, respectively, and then mounting the back surface of the second component and the back surface of the third component, respectively, to the bottom of the second component frame, thereby achieving mounting of the second component and the third component to the bottom of the second component frame.

[0010] In some embodiments, step (i) includes forming the blind vias by means of laser machining.

[0011] In some embodiments, the insulating material is selected from pure resin or resin containing glass fiber.

[0012] In some embodiments, the first packaging layer and the second packaging layer are each selected from a thermoset type media material or a photosensitive type media material.

[0013] In some embodiments, the first component, the second component, and the third component each include one or more of an active component and a passive component.

[0014] A second aspect of the present invention relates to a method for manufacturing a multi-component embedded packaged structure in layers, comprising: (a) providing a polymer support frame, the polymer support frame including a first insulating layer, a first conductive copper pillar layer penetrating the first insulating layer, and a first component placement frame; (b) mounting a first component on the top of the first component frame, and forming a first packaging layer in a gap between the first component frame and the first component; (c) forming a second circuit layer on a lower surface of the first insulating layer, and forming a fifth insulating layer on an upper surface of the first insulating layer, the fifth insulating layer including a sixth circuit layer located in the lower surface of the fifth insulating layer and a third conductive copper pillar layer located in the sixth circuit layer, a terminal of the first component communicating with the sixth circuit layer, and the sixth circuit layer and the second circuit layer being conductively connected via the first conductive copper pillar layer. (d) forming a first circuit layer on the upper surface of the fifth insulating layer, the first circuit layer including a first conductive circuit layer and a first sacrificial circuit layer, the first conductive circuit layer and the sixth circuit layer being conductively connected via the third conductive copper pillar layer, and the first sacrificial circuit layer and the first component placement frame being in the same vertical position. (e) forming a second copper pillar layer on the first circuit layer, the second copper pillar layer including a second conductive copper pillar layer and a second sacrificial copper pillar layer, the second sacrificial copper pillar layer located on the first sacrificial circuit layer. (f) laminating an insulating material on the first circuit layer and the second copper pillar layer, thinning the insulating material to expose an end of the second copper pillar layer to form a second insulating layer, and laminating an insulating material on the second circuit layer to form a third insulating layer. (g) etching the first sacrificial circuit layer and the second sacrificial copper pillar layer to form a second component frame, the second component frame vertically overlapping the first component frame; (h) mounting a second component and a third component on the bottom of the second component frame, and forming a second packaging layer on the top surface of the second insulating layer and in gaps between the second component frame and the second and third components, so that the first component is layered and vertically overlaps the second and third components. (i) forming a third blind via in the second packaging layer, forming a third conductive via in the third blind via, and forming a third circuit layer on a surface of the second packaging layer and the third conductive via, wherein a terminal of the second component and a terminal of the third component are each conductively connected to the third circuit layer through the third conductive via, and the first conductive circuit layer and the third circuit layer are conductively connected to the third conductive via through the second conductive copper pillar layer.

[0015] In some embodiments, the method further comprises: (j) continuing from step (i), laminating an insulating material onto the third circuit layer to form a fourth insulating layer, and forming a first blind via and a second blind via in the third insulating layer and the fourth insulating layer, respectively. (k) forming a first conductive via and a fifth circuit layer within the first blind via and on the surface of the third insulating layer, respectively, and forming a second conductive via and a fourth circuit layer within the second blind via and on the surface of the fourth insulating layer, respectively, the second circuit layer and the fifth circuit layer being conductively connected through the first conductive via, and the third circuit layer and the fourth circuit layer being conductively connected through the second conductive via. (l) forming a first solder resist layer on the fourth circuit layer, forming a second solder resist layer on the fifth circuit layer, and treating the metal surfaces exposed in the first solder resist layer and the second solder resist layer, respectively, to form a first metal surface treatment layer and a second metal surface treatment layer.

[0016] A third aspect of the present invention relates to a structure in which multiple components are embedded and packaged in layers, which is manufactured using the manufacturing method for a structure in which multiple components are embedded and packaged in layers described in the first aspect of the present invention.

[0017] In some embodiments, the semiconductor device includes a first insulating layer and a second insulating layer above the first insulating layer, the first insulating layer including a first conductive copper pillar layer penetrating the first insulating layer along a height direction and a first component frame, a first component is mounted on a bottom of the first component frame, a first packaging layer is provided in a gap between the first component frame and the first component, the second insulating layer includes the second component frame, a first conductive circuit layer located in a lower surface of the second insulating layer, and a second conductive copper pillar layer located on the first conductive circuit layer, a second component and a third component are mounted on a bottom of the second component frame, and a second packaging layer is provided in gaps between the second component frame and the second and third components, wherein the first component frame and the second component frame are vertically overlapped, and the first component is vertically overlapped with the second and third components in a layered manner.

[0018] In some embodiments, The semiconductor device further includes a third insulating layer located below the first insulating layer and a fourth insulating layer located above the second insulating layer, the third insulating layer including a second circuit layer located within an upper surface of the third insulating layer, a first conductive via in the second circuit layer, and a fifth circuit layer located on a lower surface of the third insulating layer, the second circuit layer and the fifth circuit layer being conductively connected through the first conductive via, the first conductive circuit layer and the second circuit layer being conductively connected through the first conductive copper pillar layer, and a terminal of the first component communicating with the second circuit layer. The fourth insulating layer includes a third circuit layer located within a lower surface of the fourth insulating layer, a second conductive via in the third circuit layer, and a fourth circuit layer located on an upper surface of the fourth insulating layer, a terminal of the second component and a terminal of the third component respectively communicate with the third circuit layer, the third circuit layer and the fourth circuit layer are conductively connected through the second conductive via, and the first conductive circuit layer and the third circuit layer are conductively connected through the second conductive copper pillar layer.

[0019] In some embodiments, the semiconductor device further includes a first solder resist layer and a second solder resist layer formed on the fourth circuit layer and the fifth circuit layer, respectively, a first metal surface treatment layer provided within the first solder resist layer, and a second metal surface treatment layer provided within the second solder resist layer.

[0020] A fourth aspect of the present invention relates to a structure in which multiple components are embedded and packaged in layers, which is manufactured using the manufacturing method for a structure in which multiple components are embedded and packaged in layers described in the second aspect of the present invention.

[0021] In some embodiments, the semiconductor device includes a first insulating layer, a fifth insulating layer above the first insulating layer, and a second insulating layer above the fifth insulating layer, the first insulating layer includes a first conductive copper pillar layer and a first component frame penetrating the first insulating layer along a height direction, a first component is mounted on a top of the first component frame, and a first packaging layer is provided in a gap between the first component frame and the first component, the fifth insulating layer includes a sixth circuit layer located in a lower surface of the fifth insulating layer and a third conductive copper pillar layer located in the sixth circuit layer, the second insulating layer includes a second component frame, a second component and a third component are mounted on a bottom of the second component placement frame; a second packaging layer is provided on an upper surface of the second insulating layer and in a gap between the second component placement frame and the second and third components, wherein the sixth circuit layer and the first conductive circuit layer are conductively connected via the third conductive copper pillar layer, a terminal of the first component is connected to the sixth circuit layer, the first component placement frame and the second component placement frame are vertically overlapped, and the first component is vertically overlapped with the second component and the third component in a layered manner.

[0022] In some embodiments, The semiconductor device further includes a third insulating layer located below the first insulating layer and a fourth insulating layer located above the second insulating layer, the third insulating layer including a second circuit layer located within an upper surface of the third insulating layer, a first conductive via in the second circuit layer, and a fifth circuit layer located on a lower surface of the third insulating layer, the second circuit layer and the fifth circuit layer being conductively connected through the first conductive via, and the sixth circuit layer and the second circuit layer being conductively connected through the first conductive copper pillar layer. the fourth insulating layer includes a third circuit layer located within a lower surface of the fourth insulating layer, a second conductive via in the third circuit layer, and a fourth circuit layer located on an upper surface of the fourth insulating layer, the third circuit layer and the fourth circuit layer being conductively connected through the second conductive via, a third conductive via is provided within the second packaging layer, a terminal of the second component and a terminal of the third component are each conductively connected to the third circuit layer through the third conductive via, and the first conductive circuit layer and the third circuit layer are conductively connected to the third conductive via through the second conductive copper pillar layer.

[0023] In some embodiments, the semiconductor device further includes a first solder resist layer and a second solder resist layer formed on the fourth circuit layer and the fifth circuit layer, respectively, a first metal surface treatment layer provided within the first solder resist layer, and a second metal surface treatment layer provided within the second solder resist layer. [Brief description of the drawings]

[0024] For a better understanding of the invention and to illustrate embodiments thereof, reference will now be made, purely by way of example, to the accompanying drawings, in which:

[0025] Specifically, when referring to the drawings, it should be emphasized that the particular drawings are exemplary, and the purpose is merely to descriptively discuss preferred embodiments of the present invention, and are presented on the basis of providing views that are believed to be most useful and most easily understood for explaining the principles and conceptual aspects of the present invention. It is not intended to illustrate the details of the configuration of the present invention beyond the details necessary for a basic understanding of the present invention. The description with reference to the drawings will allow those skilled in the art to recognize how some aspects of the present invention can be actually implemented. [Figure 1] FIG. 1 is a schematic cross-sectional view of a packaging method and structure for an integrated circuit according to the prior art. [Diagram 2] FIG. 2 is a cross-sectional schematic diagram of a multi-component embedded packaging structure according to one embodiment of the present invention. [Diagram 3]FIG. 3 is a cross-sectional schematic diagram of a multi-component embedded packaging structure according to one embodiment of the present invention. [Figure 4-1] 4(a) to 4(c) are schematic cross-sectional views showing intermediate structures at each step in a manufacturing method according to one embodiment of the present invention, in which a structure in which a plurality of components are embedded and packaged in layers is manufactured. [Figure 4-2] 4(d) to 4(f) are schematic cross-sectional views showing intermediate structures at each step in a manufacturing method according to one embodiment of the present invention, in which a structure in which a plurality of components are embedded and packaged in layers is manufactured. [Figure 4-3] 4(g) to 4(i) are schematic cross-sectional views showing intermediate structures at each step in a manufacturing method according to one embodiment of the present invention, in which a structure in which a plurality of components are embedded and packaged in layers is manufactured. [Figure 4-4] 4(j) to 4(l) are schematic cross-sectional views showing intermediate structures at each step in a manufacturing method according to one embodiment of the present invention, in which a structure in which a plurality of components are embedded and packaged in layers is manufactured. [Figure 4-5] FIG. 4(m) is a schematic cross-sectional view showing intermediate structures at various steps in a method for manufacturing a multi-component embedded packaged structure according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] With the development of electronic technology, electronic products are becoming more and more highly functional and highly integrated. As the miniaturization of components is approaching its limit, how to package multiple components rationally and achieve high functionality and high density integration has become an important issue being considered in the current industry. At the same time, in order to consider cost and efficiency, panel-level packaging has also become the current trend, in the process of manufacturing a substrate, components are embedded inside the substrate, which effectively reduces the packaging volume and at the same time improves the production efficiency, and at the same time significantly reduces the cost compared with wafer-level packaging. After continuous development and evolution, panel-level embedded packaging technology is increasingly applied and plays an increasingly important role in the semiconductor packaging field. At the same time, panel-level embedded packaging technology has also been developed, and currently in the panel-level embedded packaging field, it has already been possible to realize embedded packaging of multiple components, but there are still certain limitations.

[0027] Conventional panel-level embedded packaging solutions have already realized the embedded packaging of multiple chips and other components, such as the panel-level embedded packaging solution disclosed in the prior art CN109686669B, as shown in Figure 1, the packaging structure embeds multiple components 11 into the frame 10 of the substrate middle layer at one time, and after packaging, performs single-sided fan-out and then double-sided build-up. This solution has certain limitations, and the components must be embedded and packaged all at once in the initial layer, and cannot realize the embedded packaging of multiple chips and other components at different levels. Since multiple components can only be embedded and packaged at the same level inside the substrate at one time, the horizontal dimension is large, which cannot meet the development requirements for miniaturization of embedded packaging, and cannot realize the most reasonable embedded packaging structure based on the actual product structure and wiring design, which increases the wiring difficulty and wire length, and affects the electrical characteristics.

[0028] In order to solve the above problems, the present invention provides a structure and a manufacturing method for packaging multiple components embedded in layers, which will be described in detail below with reference to the accompanying drawings.

[0029] 2, a cross-sectional schematic diagram of a multi-component embedded packaging structure 100 is shown, the packaging structure 100 includes a first insulating layer 101 and a second insulating layer 201 above the first insulating layer 101. The first insulating layer 101 and the second insulating layer 201 may include the same material or different materials. The first insulating layer 101 and the second insulating layer 201 can be selected from pure resin or resin containing glass fiber, respectively, and preferably, the first insulating layer is selected from polyimide, epoxy resin, bismaleimide triazine resin (BT), ceramic filler, glass fiber or a combination thereof, and the second insulating layer is selected from resin containing glass fiber.

[0030] The first insulating layer 101 includes a first conductive copper pillar layer 1012 and a first component placement frame 1013 penetrating the first insulating layer 101 along the height direction, a first component 1041 is mounted on the bottom of the first component placement frame 1013, and a first packaging layer 1015 is provided in the gap between the first component placement frame 1013 and the first component 1041. Generally, the components referred to in this embodiment can include one or more of active components and passive components. The components may be bare chips, such as integrated circuit driver chips (IC drivers), field effect transistors (FETs), etc., or passive components, such as capacitors, resistors, or inductances, or may be a single initially packaged packaging body, such as ball grid arrays (BGA) / land grid arrays (LGA), etc., or a combination of multiple types of components therein. Preferably, the first component 1041 is a passive component.

[0031] The conductive copper pillar layer according to the present embodiment can include at least one copper via pillar as an IO channel to realize electrical conduction between layers, and the sizes and / or shapes of the multiple copper via pillars can be the same or different. The copper via pillar can be a solid copper pillar or a hollow pillar with surface copper plating. Preferably, the first conductive copper pillar layer 1012 includes multiple copper via pillars as IO channels, and the end of the first conductive copper pillar layer can be flush with the first insulating layer or higher than the first insulating layer.

[0032] The packaging layer referred to in this embodiment may be selected from a thermosetting medium material or a photosensitive medium material, and preferably, the first packaging layer 1015 is selected from a thermosetting resin material. The first packaging layer 1015 covers the first component 1041 and can fix the first component 1041, and can prevent the first component 1041 from being short-circuited with the second component 1042 or the third component 1043.

[0033] The second insulating layer 201 includes a second component placement frame 2016, a first conductive circuit layer 2012 located in the lower surface of the second insulating layer 201, and a second conductive copper pillar layer 2014 located in the first conductive circuit layer 2012, preferably the second conductive copper pillar layer 2014 includes a plurality of copper via columns as IO channels, and the end of the second conductive copper pillar layer 2014 may be flush with the second insulating layer 201 or may be higher than the second insulating layer 201. A second component 1042 and a third component 1043 are mounted on the bottom of the second component placement frame 2016, preferably the second component 1042 and the third component 1043 are both passive components. A second packaging layer 2018 is provided in the gap between the second component placement frame 2016 and the second component 1042 and the third component 1043, and preferably, the second packaging layer 2018 is selected from a thermosetting resin material, and the second packaging layer 2018 can fix the second component 1042 and the third component 1043. The first component placement frame 1013 and the second component placement frame 2016 are vertically overlapped, and the first component 1041, the second component 1042, and the third component 1043 are vertically overlapped in layers, which effectively reduces the dimensions of the board in the XY direction, realizes higher density integrated packaging, and at the same time reduces the wiring difficulty and realizes the shortest distance electrical connection between the components and the board, thereby improving the electrical performance of the packaging module.

[0034] The packaging structure 100 further includes a third insulating layer 301 below the first insulating layer 101 and a fourth insulating layer 401 above the second insulating layer 201, and preferably the third insulating layer 301 and the fourth insulating layer 401 are each selected from pure resin. The third insulating layer 301 includes a second circuit layer 3012 located in the upper surface of the third insulating layer 301, a first conductive via 3014 in the second circuit layer 3012, and a fifth circuit layer 3015 located on the lower surface of the third insulating layer 301, the second circuit layer 3012 and the fifth circuit layer 3015 are conductively connected through the first conductive via 3014, the first conductive circuit layer 2012 and the second circuit layer 3012 are conductively connected through the first conductive copper pillar layer 1012, and the terminal of the first component communicates with the second circuit layer.

[0035] The fourth insulating layer 401 includes a third circuit layer 4012 located on the lower surface of the fourth insulating layer 401, a second conductive via 4014 in the third circuit layer 4012, and a fourth circuit layer 4015 located on the upper surface of the fourth insulating layer 401, wherein the terminals of the second component 1042 and the terminals of the third component 1043 are respectively connected to the third circuit layer 4012, the third circuit layer 4012 and the fourth circuit layer 4015 are conductively connected through the second conductive via 4014, and the first conductive circuit layer 1012 and the third circuit layer 4012 are conductively connected through the second conductive copper pillar layer 2014.

[0036] Referring to FIG. 2, the packaging structure 100 further includes a first solder resist layer 601 and a second solder resist layer 701 formed on the fourth circuit layer 4015 and the fifth circuit layer 3015, respectively, wherein a first metal surface treatment layer 6011 is provided in the first solder resist layer 601, and a second metal surface treatment layer 7011 is provided in the second solder resist layer 701.

[0037] Referring to FIG. 3, a cross-sectional schematic diagram of a structure 200 in which multiple components are embedded and packaged in layers is shown. The differences between the packaging structure 200 and the packaging structure 100 are as follows. The packaging structure 200 includes a fifth insulating layer 501 located between the first insulating layer 101 and the second insulating layer 201, preferably the fifth insulating layer 501 is selected from a resin containing glass fiber, the fifth insulating layer 501 includes a sixth circuit layer 5012 located in the lower surface of the fifth insulating layer 501 and a third conductive copper pillar layer 5013 located in the sixth circuit layer 5012, preferably the third conductive copper pillar layer 5013 includes a plurality of copper via pillars as IO channels, and the end of the third conductive copper pillar layer 5013 may be flush with the fifth insulating layer 501 or higher than the fifth insulating layer 501. The first conductive circuit layer 2012 and the sixth circuit layer 5012 are conductively connected through the third conductive copper pillar layer 5013. The first component 1041 is mounted on the top of the first component placement frame 1013, and a terminal of the first component 1041 communicates with the sixth circuit layer 5012. A second packaging layer 2018 is provided on the upper surface of the second insulating layer 201 and in a gap between the second component placement frame 2016 and the second component 1042 and the third component 1043, and a third conductive via 2019 is provided in the second packaging layer 2018, and the terminal of the second component 1042 and the terminal of the third component 1043 respectively communicate with the third circuit layer 4012 through the third conductive via 2019, and the first conductive circuit layer 2012 and the third circuit layer 4012 are conductively connected to the third conductive via 2019 through the second conductive copper pillar layer 2014.

[0038] 4(a)-4(m), there are shown schematic cross-sectional views of intermediate structures at various steps in a method for fabricating a multi-component layered embedded packaging structure 100 according to one embodiment of the present invention.

[0039] The manufacturing method includes the following steps: As shown in Fig. 4(a), a polymer support frame is prepared. The polymer support frame includes a first insulating layer 101, a first conductive copper pillar layer 1012 penetrating the first insulating layer 101, and a first component placement frame 1013. Typically, the first component placement frame 1013 can penetrate the first insulating layer 101, and a plurality of first component placement frames 1013 can be provided for subsequent component mounting, and the sizes of the first component placement frames 1013 can be the same or different, and are determined according to the shapes and sizes of the components that need to be embedded.

[0040] Typically, the method of manufacturing the polymeric support frame includes the following sub-steps: Get a sacrifice career. A copper seed layer is applied to the sacrificial carrier. A resist layer is applied to a sacrificial carrier. Another copper seed layer is applied. A photoresist layer is applied. The patterned photoresist is a pattern having copper vias and ring strip vias. Copper is electroplated onto the pattern to form a first conductive copper pillar layer 1012 and a first ring-strip-shaped copper pillar layer. The photoresist layer is stripped. An insulating material is used to laminate the first conductive copper pillar layer 1012 and the first ring-strip-shaped copper pillar. The insulating material is thinned and planarized to expose the ends of the first conductive copper pillar 1012 and the first ring-strip-shaped copper pillar layer to form the first insulating layer 101 . Remove the sacrificial carrier. The resist layer is etched. An upper photoresist layer and a lower photoresist layer are applied to the upper and lower surfaces of the first insulating layer 101, respectively, and the upper photoresist layer and the lower photoresist layer are exposed and developed to expose the ring-strip-shaped copper pillars in the first ring-strip-shaped copper pillar layer. The ring-strip-like copper pillars may be etched and the dielectric material therein removed to form the first component placement frame 1013, and the top and bottom photoresist layers may be removed to fabricate the polymer support frame.

[0041] Next, as shown in FIG. 4(b), a first adhesive layer 1014 is provided on the bottom of the first insulating layer 101, and the terminal surface of the first component 1041 is attached to the first adhesive layer 1014 exposed in the first component placement frame 1013. Usually, the first adhesive layer 1014 may be a single-sided tape, and the single-sided tape is generally a commercially available transparent film that is thermally decomposable or decomposable by ultraviolet irradiation. The first adhesive layer 1014 can provide temporary support and fixation for the first component 1041. Preferably, the first component is a passive component.

[0042] Next, as shown in FIG. 4(c), a packaging material is laminated on the upper surface of the first insulating layer 101 and in the gap between the first component 1041 and the first component placement frame 1013, the packaging material is cured to form the first packaging layer 1015, the first packaging layer 1015 is thinned to expose the end of the first conductive copper pillar layer 1012, and the first adhesive layer 1014 is removed. Usually, the first adhesive layer 1014 can be removed by ultraviolet irradiation or thermal decomposition. The packaging material may be selected from thermosetting medium materials or photosensitive medium materials. Preferably, a thermosetting resin material is laminated, the thermosetting resin material is cured by heating to form the first packaging layer 1015, and the first packaging layer 1015 is thinned overall by plasma etching or grinding to expose the end of the first conductive copper pillar layer 1012.

[0043] 4(d), a first circuit layer and a second circuit layer 3012 are formed on the upper and lower surfaces of the first insulating layer 101, respectively, the first circuit layer includes a first conductive circuit layer 2012 and a first sacrificial circuit layer 2013, the first sacrificial circuit layer 2013 covers the first component placement frame 1013, the terminal of the first component 1041 communicates with the second circuit layer 3012, and the first conductive circuit layer 2012 and the second circuit layer 3012 are conductively connected via the first conductive copper pillar layer 1012. Generally, the method includes the following steps: A first metal seed layer 2011 and a second metal seed layer 3011 are formed on the upper and lower surfaces of the first insulating layer 101, respectively. A first photoresist layer is applied to the first metal seed layer 2011 and a second photoresist layer is applied to the second metal seed layer 3011 . The first photoresist layer and the second photoresist layer are exposed and developed to form a first feature pattern and a second feature pattern, respectively. A first circuit layer is formed on the first feature pattern by electroplating, and a second circuit layer 3012 is formed on the second feature pattern by electroplating. The first and second photoresist layers are removed.

[0044] Generally, the metal seed layer can be formed by electroless plating or sputtering, and the metal seed layer can include titanium, copper, titanium-tungsten alloy, or a combination thereof. Preferably, the first metal seed layer 2011 and the second metal seed layer 3011 are fabricated by sputtering titanium and copper. The first feature pattern and the second feature pattern are respectively electroplated with copper to form the first circuit layer and the second circuit layer 3012, and the thickness of the first circuit layer and the second circuit layer 3012 can be determined according to actual needs, and the number of sacrificial circuits included in the first sacrificial circuit layer 2013 in the first circuit layer can be determined according to the number of components that need to be actually embedded.

[0045] 4(e), a second copper pillar layer is formed on the first circuit layer, the second copper pillar layer includes a second conductive copper pillar layer 2014 and a second sacrificial copper pillar layer 2015, and the second sacrificial copper pillar layer 2015 is located on the first sacrificial circuit layer 2013. Generally, the method includes the following steps: A third photoresist layer is applied to the first circuit layer, and the third photoresist layer is exposed and developed to form a third feature pattern. Copper is electroplated in the third feature to form a second copper pillar layer. The third photoresist layer is removed, and the exposed first metal seed layer 2011 and second metal seed layer 3011 are etched.

[0046] Next, as shown in FIG. 4(f), an insulating material is laminated on the first circuit layer and the second copper pillar layer, and the insulating material is thinned to expose the end of the second copper pillar layer to form the second insulating layer 201, and an insulating material is laminated on the second circuit layer 3012 to form the third insulating layer 301. Preferably, the second insulating layer is selected from a resin containing glass fiber, and the third insulating layer is selected from a pure resin. In general, the insulating material can be thinned overall, for example, by grinding or plasma etching. Also, the insulating material can be thinned partially, for example, by partially thinning the insulating material in the second copper pillar layer by a laser or mechanical drill to expose the end of the second copper pillar layer. Preferably, the insulating material is thinned overall by grinding or plasma etching to expose the end of the second copper pillar layer.

[0047] 4(g), the first sacrificial circuit layer 2013 and the second sacrificial copper pillar layer 2015 are etched to form a second component placement frame 2016. The second component placement frame 2016 vertically overlaps with the first component placement frame 1013. Generally, the method includes the following steps: A fourth photoresist layer is applied on top of the second insulating layer 201 . A fourth feature pattern is formed by exposure and development, and the ends of the second sacrificial copper pillar layer 2015 are exposed. The second sacrificial copper pillar layer 2015 and the first sacrificial circuit layer 2013 are etched to form a second component placement frame 2016 . The fourth photoresist layer is stripped.

[0048] Next, as shown in FIG. 1(h), the second component 1042 and the third component 1043 are mounted on the bottom of the second component placement frame 2016, and the second component 1042 and the third component 1043 are each layered and vertically overlapped with the first component 1041. Typically, the mounting of the second component 1042 and the third component 1043 on the bottom of the second component placement frame 2016 is achieved by providing an adhesive material 2017 on the bottom of the second component placement frame 2016, and then mounting the back surface of the second component 1042 and the back surface of the third component 1043 on the adhesive material 2017, respectively. After providing adhesive material 2017 on the back surface of second component 1042 and the back surface of third component 1043, respectively, the back surfaces of second component 1042 and third component 1043 are mounted on the bottom of second component placement frame 2016, thereby achieving mounting of second component 1042 and third component 1043 on the bottom of second component placement frame 2016. Preferably, second component 1042 and third component 1043 are each passive components.

[0049] 4(i), a second packaging layer 2018 is formed in the gaps between the second component placement frame 2016 and the second and third components 1042 and 1043. Generally, the process includes the following steps. A packaging material is laminated on the upper surface of second insulating layer 201 and in the gaps between second component placement frame 2016 and second component 1042 and third component 1043 , and the packaging material is cured to form second packaging layer 2018 . The second packaging layer 2018 is thinned to expose the ends of the second conductive copper pillar layer 2014 , the terminals of the second component 1042 and the terminals of the third component 1043 .

[0050] Preferably, a thermosetting resin material is laminated and then cured by heating to form the second packaging layer 2018. The second packaging layer 2018 is entirely thinned by plasma etching or grinding to expose the ends of the second conductive copper pillar layer 2014, the second component 1042, and the third component 1043.

[0051] 4(j), a third circuit layer 4012 is formed on the upper surface of the second insulating layer 201, and the terminals of the second component 1042 and the third component 1043 are respectively connected to the third circuit layer 4012, and the first conductive circuit layer 2012 and the third circuit layer 4012 are conductively connected to each other via the second conductive copper pillar layer 2014. Generally, the method includes the following steps: A third metal seed layer 4011 is formed on the upper surface of the second insulating layer 201 . A fifth photoresist layer is applied to the third metal seed layer 4011, and is exposed and developed to form a fifth feature pattern. Copper is electroplated in the fifth feature pattern to form third circuit layer 4012. The fifth photoresist layer is stripped and the exposed third metal seed layer 4011 is etched.

[0052] Preferably, the third metal seed layer 4011 is fabricated by sputtering titanium and copper.

[0053] Next, as shown in Fig. 4(k), an insulating material is laminated on the third circuit layer 4012 to form a fourth insulating layer 401, and a first blind via 3017 and a second blind via 4017 are formed in the third insulating layer 301 and the fourth insulating layer 401, respectively. Usually, the blind vias can be formed by a means of laser processing. Preferably, the fourth insulating layer is selected from a pure resin.

[0054] 4(l), a first conductive via 3014 and a fifth circuit layer 3015 are formed in the first blind via 3017 and on the surface of the third insulating layer 301, a second conductive via 4014 and a fourth circuit layer 4015 are formed in the second blind via 4017 and on the surface of the fourth insulating layer 401, and the second circuit layer 3012 and the fifth circuit layer 3015 are conductively connected through the first conductive via 3014, and the third circuit layer 4012 and the fourth circuit layer 4015 are conductively connected through the second conductive via 4014. Generally, the method includes the following steps: A fifth metal seed layer 3013 is formed on the bottom and sidewalls of the first blind via 3017 and the surface of the third insulating layer 301 , and a fourth metal seed layer 4013 is formed on the bottom and sidewalls of the second blind via 4017 and the surface of the fourth insulating layer 401 . A sixth photoresist layer is applied to the fourth metal seed layer 4013, a seventh photoresist layer is applied to the fifth metal seed layer 3013, and the sixth and seventh photoresist layers are exposed and developed to form a sixth and seventh feature pattern, respectively. The sixth feature pattern is electroplated with copper to form second conductive vias 4014 and fourth circuit layer 4015 , and the seventh feature pattern is electroplated with copper to form first conductive vias 3014 and fifth circuit layer 3015 . The sixth and seventh photoresist layers are removed, and the exposed fourth and fifth metal seed layers 4013 and 3013 are etched.

[0055] The fourth metal seed layer 4013 and the fifth metal seed layer 3013 are preferably fabricated by sputtering titanium and copper.

[0056] 4(m), a first solder resist layer 601 is formed on the fourth circuit layer 4015, a second solder resist layer 701 is formed on the fifth circuit layer 3015, and the metal surfaces exposed in the first solder resist layer 601 and the second solder resist layer 701 are treated to form a first metal surface treatment layer 6011 and a second metal surface treatment layer 7011. Usually, the first metal surface treatment layer 6011 and the second metal surface treatment layer 7011 are formed by selecting oxidation prevention, nickel palladium gold plating, tin plating, silvering, etc.

[0057] The present invention further provides a method for manufacturing a structure 200 in which multiple components are embedded and packaged in layers, and the differences between the manufacturing method of the packaging structure 200 and the manufacturing method of the packaging structure 100 are as follows: 1. The first component 1041 is mounted on the top of the first component placement frame 1013. 2. After the first packaging layer 1015 is formed, a fifth insulating layer 501 is formed on the upper surface of the first insulating layer 101, and the fifth insulating layer 501 includes a sixth circuit layer 5012 located in the lower surface of the fifth insulating layer 501 and a third conductive copper pillar layer 5013 located on the sixth circuit layer 5012, and the terminal of the first component 1041 communicates with the sixth circuit layer 5012, and the sixth circuit layer 5012 and the second circuit layer 3012 are conductively connected through the first conductive copper pillar layer 1012. 3. A first circuit layer including a first conductive circuit layer 2012 and a first sacrificial circuit layer 2013 is formed on the fifth insulating layer 501, and the first conductive circuit layer 2012 and the sixth circuit layer 5012 are conductively connected through a third conductive copper pillar layer 5013. 4. A second packaging layer 2018 is formed on the upper surface of the second insulating layer 201 and in a gap between the second component arrangement frame 2016 and the second component 1042 and the third component 1043. 5. A third conductive via 2019 is formed in the second packaging layer 2018, and the terminal of the second component 1042 and the terminal of the third component 1043 are conductively connected to the third circuit layer 4012 through the third conductive via 2019, respectively, and the first conductive circuit layer 2012 and the third circuit layer 4012 are conductively connected to the third conductive via 2019 through the second conductive copper pillar layer 2014.

[0058] The other steps in the manufacturing method of the packaging structure 200 are the same as the corresponding steps in the manufacturing method of the packaging structure 100, so the description will be omitted here.

[0059] Those skilled in the art will understand that the present invention is not limited to the specific illustrations and description in the context, and the scope of the present invention is defined by the claims, including combinations and subcombinations of the technical features described above, and variations and improvements thereon, which may occur to those skilled in the art after reading the above description.

[0060] In the claims, the term "comprise" and similar terms such as "comprise," "contain," etc. mean the inclusion of the recited elements but not the exclusion of other elements. [Explanation of symbols]

[0061] 100: Packaging structure 101: First insulating layer 1012: First conductive copper pillar layer 1013: First component placement frame 1014: First adhesive layer 1015: First packaging layer 1041: First part 1042: 2nd part 1043: Third part 200: Packaging structure 201: Second insulating layer 2011: First metal seed layer 2012: 1st conductive circuit layer 2013: First sacrificial circuit layer 2014: Second conductive copper pillar layer 2015: Second sacrificial copper pillar layer 2016: 2nd component placement frame 2017: Adhesive materials 2018: Second packaging layer 2019: 3rd Conductive Via 301: Third insulating layer 3011: Second metal seed layer 3012: First circuit layer and second circuit layer 3012: 2nd circuit layer 3013: 5th metal seed layer 3014: First conductive via 3015: 5th circuit layer 3017: 1st blind via 401: Fourth insulating layer 4011: 3rd metal seed layer 4012: 3rd circuit layer 4013: 4th metal seed layer 4014: Second conductive via 4015: 4th circuit layer 4017: 2nd blind via 501: Fifth insulating layer 5012: 6th circuit layer 5013: Third conductive copper pillar layer 601: First solder resist layer 6011: First metal surface treatment layer 701: Second solder resist layer 7011: Second metal surface treatment layer

Claims

1. A method for manufacturing a structure in which a plurality of components are embedded and packaged in layers, comprising the steps of: (a) providing a polymer support frame, the polymer support frame including a first insulating layer, a first conductive copper pillar layer penetrating the first insulating layer, and a first component placement frame; (b) mounting a first component on a bottom of the first component frame, and forming a first packaging layer in a gap between the first component frame and the first component; (c) forming a first circuit layer and a second circuit layer on an upper surface and a lower surface of the first insulating layer, respectively, the first circuit layer including a first conductive circuit layer and a first sacrificial circuit layer, the first sacrificial circuit layer covers the first component placement frame, a terminal of the first component communicates with the second circuit layer, and the first conductive circuit layer and the second circuit layer are conductively connected via the first conductive copper pillar layer; (d) forming a second copper pillar layer on the first circuit layer, the second copper pillar layer including a second conductive copper pillar layer and a second sacrificial copper pillar layer, the second sacrificial copper pillar layer located on the first sacrificial circuit layer; (e) depositing an insulating material on the first circuit layer and the second copper pillar layer, thinning the insulating material to expose an end of the second copper pillar layer to form a second insulating layer, and depositing an insulating material on the second circuit layer to form a third insulating layer; (f) etching the first sacrificial circuit layer and the second sacrificial copper pillar layer to form a second component frame, the second component frame and the first component frame vertically overlapping; (g) mounting a second component and a third component on a bottom of the second component placement frame, and forming a second packaging layer in gaps between the second component placement frame and the second and third components, wherein the second and third components are layered and vertically overlap the first component, respectively; (h) forming a third circuit layer on an upper surface of the second insulating layer, wherein a terminal of the second component and a terminal of the third component are respectively connected to the third circuit layer, and the first conductive circuit layer and the third circuit layer are conductively connected via the second conductive copper pillar layer.

2. (i) continuing from step (h), depositing an insulating material onto the third circuit layer to form a fourth insulating layer, and forming a first blind via and a second blind via in the third insulating layer and the fourth insulating layer, respectively; (j) forming a first conductive via and a fifth circuit layer in the first blind via and on the surface of the third insulating layer, respectively, and forming a second conductive via and a fourth circuit layer in the second blind via and on the surface of the fourth insulating layer, respectively, wherein the second circuit layer and the fifth circuit layer are conductively connected through the first conductive via, and the third circuit layer and the fourth circuit layer are conductively connected through the second conductive via; 2. The manufacturing method of claim 1, further comprising: (k) forming a first solder resist layer on the fourth circuit layer, forming a second solder resist layer on the fifth circuit layer, and treating metal surfaces exposed in the first solder resist layer and the second solder resist layer, respectively, to form a first metal surface treatment layer and a second metal surface treatment layer.

3. Step (b) (b1) providing a first adhesive layer on a bottom of the first insulating layer; (b2) attaching a terminal surface of the first component to a first adhesive layer exposed within the first component arrangement frame; (b3) depositing a packaging material on an upper surface of the first insulating layer and in a gap between the first component and the first component placement frame, and hardening the packaging material to form a first packaging layer; (b4) thinning the first packaging layer to expose ends of the first conductive copper pillar layer; (b5) removing the first adhesive layer.

4. The method of claim 3 , wherein the first adhesive layer comprises a single-sided tape.

5. 2. The manufacturing method of claim 1, wherein step (g) includes providing an adhesive material on a bottom of the second component frame, and then mounting the back surfaces of the second component and the third component to the adhesive material, respectively, thereby achieving mounting the second component and the third component to the bottom of the second component frame.

6. 2. The manufacturing method of claim 1, wherein step (g) includes providing an adhesive material on the back surface of the second component and the back surface of the third component, respectively, and then mounting the back surface of the second component and the back surface of the third component, respectively, to the bottom of the second component frame, thereby achieving mounting of the second component and the third component to the bottom of the second component frame.

7. The method of claim 2 , wherein step (i) includes forming the blind vias by means of laser machining.

8. The method according to claim 2, wherein the insulating material is selected from the group consisting of pure resin and resin containing glass fiber.

9. The manufacturing method of claim 1 , wherein the first packaging layer and the second packaging layer are each selected from a thermosetting medium material or a photosensitive medium material.

10. The method of claim 1 , wherein the first component, the second component, and the third component each include one or more of an active component and a passive component.

11. A method for manufacturing a structure in which a plurality of components are embedded and packaged in layers, comprising the steps of: (a) providing a polymer support frame, the polymer support frame including a first insulating layer, a first conductive copper pillar layer penetrating the first insulating layer, and a first component placement frame; (b) mounting a first component on a top of the first component frame and forming a first packaging layer in a gap between the first component frame and the first component; (c) forming a second circuit layer on the lower surface of the first insulating layer, and forming a fifth insulating layer on the upper surface of the first insulating layer, the fifth insulating layer including a sixth circuit layer located in the lower surface of the fifth insulating layer and a third conductive copper pillar layer located in the sixth circuit layer, a terminal of the first component communicates with the sixth circuit layer, and the sixth circuit layer and the second circuit layer are conductively connected via the first conductive copper pillar layer; (d) forming a first circuit layer on an upper surface of the fifth insulating layer, the first circuit layer including a first conductive circuit layer and a first sacrificial circuit layer, the first conductive circuit layer and the sixth circuit layer being conductively connected via the third conductive copper pillar layer, and the first sacrificial circuit layer and the first component placement frame being in the same vertical position; (e) forming a second copper pillar layer on the first circuit layer, the second copper pillar layer including a second conductive copper pillar layer and a second sacrificial copper pillar layer, the second sacrificial copper pillar layer located on the first sacrificial circuit layer; (f) depositing an insulating material on the first circuit layer and the second copper pillar layer, thinning the insulating material to expose an end of the second copper pillar layer to form a second insulating layer, and depositing an insulating material on the second circuit layer to form a third insulating layer; (g) etching the first sacrificial circuit layer and the second sacrificial copper pillar layer to form a second component frame, the second component frame and the first component frame vertically overlapping; (h) mounting a second component and a third component on a bottom of the second component placement frame, and forming a second packaging layer on an upper surface of the second insulating layer and in a gap between the second component placement frame and the second and third components, the first component being layered and vertically overlapping the second and third components; (i) forming a third blind via in the second packaging layer, forming a third conductive via in the third blind via, and forming a third circuit layer on a surface of the second packaging layer and the third conductive via, wherein a terminal of the second component and a terminal of the third component are respectively conductively connected to the third circuit layer through the third conductive via, and the first conductive circuit layer and the third circuit layer are conductively connected to the third conductive via through the second conductive copper pillar layer.

12. (j) continuing from step (i), depositing an insulating material onto the third circuit layer to form a fourth insulating layer, and forming a first blind via and a second blind via in the third insulating layer and the fourth insulating layer, respectively; (k) forming a first conductive via and a fifth circuit layer in the first blind via and on the surface of the third insulating layer, respectively, and forming a second conductive via and a fourth circuit layer in the second blind via and on the surface of the fourth insulating layer, respectively, wherein the second circuit layer and the fifth circuit layer are conductively connected through the first conductive via, and the third circuit layer and the fourth circuit layer are conductively connected through the second conductive via; 12. The manufacturing method of claim 11, further comprising: (l) forming a first solder resist layer on the fourth circuit layer, forming a second solder resist layer on the fifth circuit layer, and treating metal surfaces exposed in the first solder resist layer and the second solder resist layer, respectively, to form a first metal surface treatment layer and a second metal surface treatment layer.

13. A structure in which a plurality of components are embedded and packaged in layers, the structure being manufactured by the manufacturing method of a structure in which a plurality of components are embedded and packaged in layers according to any one of claims 1 to 10.

14. 14. The structure of claim 13, in which a plurality of components are embedded and packaged in layers, comprising a first insulating layer and a second insulating layer above the first insulating layer, the first insulating layer including a first conductive copper pillar layer penetrating the first insulating layer along a height direction and a first component frame, a first component mounted on a bottom of the first component frame, a first packaging layer being provided in a gap between the first component frame and the first component, the second insulating layer including a second component frame, a first conductive circuit layer located in a lower surface of the second insulating layer, and a second conductive copper pillar layer located on the first conductive circuit layer, a second component and a third component mounted on a bottom of the second component frame, a second packaging layer being provided in a gap between the second component frame and the second and third components, wherein the first component frame and the second component frame are vertically overlapped, and the first component is vertically overlapped with the second and third components in a layered manner.

15. the third insulating layer is disposed below the first insulating layer and a fourth insulating layer is disposed above the second insulating layer, the third insulating layer includes a second circuit layer disposed within an upper surface of the third insulating layer, a first conductive via in the second circuit layer, and a fifth circuit layer disposed on a lower surface of the third insulating layer, the second circuit layer and the fifth circuit layer are conductively connected through the first conductive via, the first conductive circuit layer and the second circuit layer are conductively connected through the first conductive copper pillar layer, and a terminal of the first component communicates with the second circuit layer; 15. The structure of claim 14 in which multiple components are embedded in layers and packaged, wherein the fourth insulating layer includes a third circuit layer located in a lower surface of the fourth insulating layer, a second conductive via in the third circuit layer, and a fourth circuit layer located on an upper surface of the fourth insulating layer, a terminal of the second component and a terminal of the third component respectively communicate with the third circuit layer, the third circuit layer and the fourth circuit layer are conductively connected through the second conductive via, and the first conductive circuit layer and the third circuit layer are conductively connected through the second conductive copper pillar layer.

16. 16. The multi-component embedded packaging structure according to claim 15, further comprising a first solder resist layer and a second solder resist layer formed on the fourth circuit layer and the fifth circuit layer, respectively, a first metal surface treatment layer being provided within the first solder resist layer, and a second metal surface treatment layer being provided within the second solder resist layer.

17. A structure in which a plurality of components are embedded and packaged in layers, the structure being manufactured by the manufacturing method of a structure in which a plurality of components are embedded and packaged in layers according to any one of claims 11 to 12.

18. a first insulating layer, a fifth insulating layer above the first insulating layer, and a second insulating layer above the fifth insulating layer, the first insulating layer including a first conductive copper pillar layer penetrating the first insulating layer along a height direction and a first component placement frame, a first component is mounted on a top of the first component placement frame, and a first packaging layer is provided in a gap between the first component placement frame and the first component, the fifth insulating layer including a sixth circuit layer located within a lower surface of the fifth insulating layer and a third conductive copper pillar layer in the sixth circuit layer, the second insulating layer including a second component placement frame, a first conductive circuit layer located within a lower surface of the second insulating layer, and a second conductive copper pillar layer in the first conductive circuit layer.

18. The structure of claim 17 in which multiple components are embedded and packaged in layers, comprising a second conductive copper pillar layer positioned on a bottom of the second component placement frame, a second component and a third component are mounted on a bottom of the second component placement frame, a second packaging layer is provided on an upper surface of the second insulating layer and in a gap between the second component placement frame and the second component and the third component, wherein the sixth circuit layer and the first conductive circuit layer are conductively connected via the third conductive copper pillar layer, a terminal of the first component is connected to the sixth circuit layer, the first component placement frame and the second component placement frame are vertically overlapped, and the first component is vertically overlapped with the second component and the third component in a layered manner.

19. the third insulating layer is disposed below the first insulating layer and a fourth insulating layer is disposed above the second insulating layer, the third insulating layer includes a second circuit layer disposed within an upper surface of the third insulating layer, a first conductive via in the second circuit layer, and a fifth circuit layer disposed on a lower surface of the third insulating layer, the second circuit layer and the fifth circuit layer being conductively connected through the first conductive via, and the sixth circuit layer and the second circuit layer being conductively connected through the first conductive copper pillar layer; 20. The structure of claim 18 in which multiple components are embedded and packaged in layers, wherein the fourth insulating layer includes a third circuit layer located in a lower surface of the fourth insulating layer, a second conductive via in the third circuit layer, and a fourth circuit layer located on an upper surface of the fourth insulating layer, the third circuit layer and the fourth circuit layer being conductively connected through the second conductive via, a third conductive via is provided in the second packaging layer, a terminal of the second component and a terminal of the third component are respectively conductively connected to the third circuit layer through the third conductive via, and the first conductive circuit layer and the third circuit layer are conductively connected to the third conductive via through the second conductive copper pillar layer.

20. 20. The structure of claim 19, further comprising a first solder resist layer and a second solder resist layer formed on the fourth circuit layer and the fifth circuit layer, respectively, a first metal surface treatment layer being provided within the first solder resist layer, and a second metal surface treatment layer being provided within the second solder resist layer.

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